Semiconductor chip packaging body and semiconductor chip packaging method

Abstract

To provide a semiconductor chip packaging body and a semiconductor chip packaging method that can reduce adhesion of a foreign matter to semiconductor chips.SOLUTION: A semiconductor chip packaging body 1 includes an adhesive sheet 10, a plurality of semiconductor chips 100 arranged on the adhesive sheet 10, release paper 12 positioned on the adhesive sheet 10 and covering the plurality of semiconductor chips 100, and a frame-shaped spacer 11 arranged between the adhesive sheet 10 and the release paper 12 and surrounding the outside of the plurality of semiconductor chips 100.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor chip package and a method for packaging semiconductor chips. [Background technology]

[0002] In semiconductor chip packaging, it is known that shipping and transporting semiconductor chips in tape form results in smaller packaging compared to other forms such as tape frames, grip rings, or trays, leading to reduced transportation costs and reduced greenhouse gas emissions associated with transportation.

[0003] On the other hand, shipping and transporting semiconductor chips in tape form poses a problem in that when packaging semiconductor chips, the components of the release paper (release treatment agent) that improves the peelability from the adhesive film migrate to the surface or electrodes of the semiconductor chip.

[0004] For example, in Patent Document 1, multiple semiconductor chips are placed on an adhesive film, and then the multiple semiconductor chips are covered with a second protective sheet made of polyethylene or the like that is large enough to cover the entire multiple semiconductor chips. Patent Document 1 also discloses a method for preventing adhesion of a release agent to the surface of the semiconductor chips by bonding a chip protective sheet that has been treated with a release agent onto the second protective sheet. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 6-122412 Summary of the Invention [Problem to be solved by the invention]

[0006] In recent years, semiconductor chips themselves have become increasingly smaller due to the demand for smaller and lighter end products that use them. As a result, foreign particles of a few microns in size have become a problem, and appearance standards are becoming stricter than ever before. Furthermore, repeated unpacking and repacking operations during downstream processes such as inspection, packaging, and assembly, which are carried out after visual inspection, can cause the adhesive film to flex, causing the edges or corners of the semiconductor chip that come into contact with the release paper to rub against the release paper, potentially scraping off parts of the release paper or the semiconductor chip, resulting in the creation of foreign particles.

[0007] However, in Patent Document 1, removing the semiconductor chip requires a process of peeling off the release paper and then peeling off the second protective sheet, which has less releasability than the release paper, from the adhesive film. The second protective sheet is more prone to static electricity than the release paper and is difficult to peel off. Furthermore, the process does not take into consideration the generation of foreign matter caused by friction between the second protective sheet and the edges or corners of the semiconductor chip. Therefore, as the subsequent unpacking and packaging processes are repeated, portions of the material of the second protective sheet or the semiconductor chip may be scraped off and adhere to the semiconductor chip, or they may attract dust floating in the air, potentially increasing the rate of foreign matter adhesion as each process is repeated.

[0008] Foreign matter adhering to semiconductor chips can cause leakage paths, which can degrade reverse current and reverse voltage characteristics. Therefore, it is necessary to reduce the adhesion of all foreign matter.

[0009] An object of the present invention is to provide a semiconductor chip package and a method for packaging semiconductor chips that can reduce adhesion of foreign matter to semiconductor chips. [Means for solving the problem]

[0010] The present inventors have thoroughly investigated ways to solve the above problems and have come up with the idea that, during the opening and packaging process, the semiconductor chips arranged on the periphery of the array, particularly the semiconductor chips arranged on the periphery, come into contact with the release paper, which may cause some of the material of the release paper or the semiconductor chip to be scraped off and adhere to the semiconductor chip.The present inventors have discovered that by placing a frame-shaped spacer that surrounds the periphery of the array of semiconductor chips between the adhesive sheet on which the semiconductor chips are arranged and the release paper covering the adhesive sheet, it is possible to prevent the edges or corners of the semiconductor chips located on the outermost periphery of the array of semiconductor chips from coming into contact with the release paper, thereby reducing the rate of foreign matter adhesion, and have completed the present invention.That is, the gist of the present invention is as follows.

[0011] (1) an adhesive sheet; a plurality of semiconductor chips arranged on the adhesive sheet; a release paper positioned on the adhesive sheet and covering the semiconductor chips; a frame-shaped spacer disposed between the adhesive sheet and the release paper and surrounding the outer sides of the semiconductor chips; Equipped with Semiconductor chip packaging.

[0012] (2) The plurality of semiconductor chips are arranged in a closed space formed by the inner surface of the frame-shaped spacer, the adhesive sheet, and the release paper. The semiconductor chip package according to (1) above.

[0013] (3) The thickness of the frame-shaped spacer is 1.0 times or more and less than 20.0 times the thickness of the semiconductor chip. The semiconductor chip package according to (1) or (2) above.

[0014] (4) The material of the frame-shaped spacer is a resin material or the same material as the release paper. The semiconductor chip package according to any one of (1) to (3) above.

[0015] (5) The inner dimension of the frame-shaped spacer in the direction of the long side width of the arrangement range of the plurality of semiconductor chips is 1.1 times or more and less than 2.0 times the long side width of the arrangement range of the plurality of semiconductor chips. The semiconductor chip package according to any one of (1) to (4) above.

[0016] (6) The release paper is attached to the adhesive sheet on the outside of the frame-shaped spacer. The semiconductor chip package according to any one of (1) to (5) above.

[0017] (7) The thickness of the frame-shaped spacer makes it possible for the longest distance from the outer periphery of the frame-shaped spacer to where the adhesive sheet and the release paper are attached to each other to be equal to or less than half the shortest distance between the outer periphery of the frame-shaped spacer and the outer periphery of the adhesive sheet. The semiconductor chip package according to (6) above.

[0018] (8) an arrangement step of arranging a plurality of semiconductor chips on the adhesive sheet; a packaging step of placing a release paper covering the semiconductor chips on the adhesive sheet; Including, the packaging step includes a step of arranging a frame-shaped spacer that surrounds the outside of the plurality of semiconductor chips between the adhesive sheet and the release paper. Packaging methods for semiconductor chips.

[0019] (9) an arrangement step of arranging a plurality of semiconductor chips on the adhesive sheet; a packaging step of placing a release paper covering the semiconductor chips on the adhesive sheet; Including, the arranging step includes a step of arranging a frame-shaped spacer on the pressure-sensitive adhesive sheet in advance, In the packaging step, a frame-shaped spacer is disposed between the adhesive sheet and the release paper at a position surrounding the outside of the plurality of semiconductor chips. Packaging methods for semiconductor chips.

[0020] (10) The semiconductor chips are arranged in a closed space formed by the inner surface of the frame-shaped spacer, the adhesive sheet, and the release paper. The method for packaging semiconductor chips according to (8) or (9) above.

[0021] (11) The thickness of the frame-shaped spacer is 1.0 times or more and less than 20.0 times the thickness of the semiconductor chip. The method for packaging semiconductor chips according to any one of (8) to (10) above.

[0022] (12) The material of the frame-shaped spacer is a resin material or the same material as the release paper. The method for packaging semiconductor chips according to any one of (8) to (11) above.

[0023] (13) The inner dimension of the frame-shaped spacer in the direction of the long side width of the arrangement range of the plurality of semiconductor chips is 1.1 times or more and less than 2.0 times the long side width of the arrangement range of the plurality of semiconductor chips. The method for packaging semiconductor chips according to any one of (8) to (12) above.

[0024] (14) In the packaging step, the release paper and the adhesive sheet are attached to each other on the outside of the frame-shaped spacer. The method for packaging semiconductor chips according to any one of (8) to (13) above.

[0025] (15) The thickness of the frame-shaped spacer makes it possible for the longest distance from the outer periphery of the frame-shaped spacer to where the adhesive sheet and the release paper are attached to each other to be equal to or less than half the shortest distance between the outer periphery of the frame-shaped spacer and the outer periphery of the adhesive sheet. The method for packaging semiconductor chips according to (14) above. [Effects of the Invention]

[0026] According to the present invention, it is possible to provide a semiconductor chip package and a method for packaging semiconductor chips that can reduce adhesion of foreign matter to semiconductor chips. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 2 is a schematic diagram illustrating a plurality of arranged semiconductor chips. [Figure 2] FIG. 10 is a schematic diagram illustrating the appearance determination criteria. [Figure 3A] 1A to 1C are schematic top views illustrating a semiconductor chip arrangement process according to an embodiment of the present invention. [Figure 3B] 3B is a schematic top view illustrating a part of the packaging process of the semiconductor chip according to the embodiment of the present invention, following FIG. 3A. [Figure 3C] 3B, and a schematic top view illustrating a part of the packaging process for the semiconductor chip according to one embodiment of the present invention, as seen from the release paper side of the semiconductor chip package according to one embodiment of the present invention. [Figure 4A] 1 is a schematic bottom view of a semiconductor chip package according to one embodiment of the present invention as viewed from the adhesive sheet side. FIG. [Figure 4B] 4B is a schematic cross-sectional view taken along line AA of the semiconductor chip package according to the embodiment of the present invention shown in FIG. 4A. [Figure 4C] FIG. 1 is a schematic cross-sectional view of a conventional semiconductor chip package. [Figure 5] 10 is a graph showing the transition of the foreign matter adhesion rate of the semiconductor chip package according to the present invention. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0028] Prior to describing the embodiments according to the present invention, the following points will be explained in advance.

[0029] <Semiconductor chip arrangement> FIG. 1 illustrates a plurality of semiconductor chips 20, each of which has a plurality of semiconductor chips 100 arranged therein. As an example, FIG. 1 shows an arrangement of a plurality of semiconductor chips 20 in a 3-row, 4-column configuration. In FIG. 1, the semiconductor chips 100 located on the outermost periphery of the plurality of semiconductor chips 20 are designated by the symbol S. Among the plurality of semiconductor chips 20, the semiconductor chips 100 located inside the outermost periphery, other than the semiconductor chips 100 designated by the symbol S, are designated by the symbol T. The arrangement range R of the plurality of semiconductor chips 20 refers to the area occupied by a shape, such as a rectangle, formed by straight lines along the outer edges of the arrangement of the semiconductor chips S located on the outermost periphery of the plurality of arranged semiconductor chips 20. The long side width B of the arrangement range R of the plurality of semiconductor chips 20 is, for example, the long side width of the rectangle described above. The short side width C of the arrangement range R of the plurality of semiconductor chips 20 is, for example, the short side width of the rectangle described above. The arrangement pitch A is, for example, the sum of the horizontal length along the long side of the arrangement range R of the semiconductor chip 100 of the multiple semiconductor chips 20 and the distance between two adjacent semiconductor chips 100 of the multiple semiconductor chips 20. The arrangement range R of the multiple semiconductor chips 20, the long side width B and short side width C of the arrangement range R of the multiple semiconductor chips 20, and the arrangement pitch A are each illustrated within the arrangement of the multiple semiconductor chips 20 in FIG. 1 . Here, the shape of the arrangement range R of the multiple semiconductor chips 20 is not limited to a rectangle and may be a circle or other polygon. If the shape of the arrangement range R of the multiple semiconductor chips 20 is a shape other than a rectangle, the long side width B and short side width C are the long side width and short side width of a rectangle that circumscribes the arrangement range R so as to minimize the area. Here, the direction of each side of the rectangle is horizontal to the periphery of the multiple arranged semiconductor chips.

[0030] <Foreign object> In the present invention, the term "foreign matter" includes components contained in the material of the release paper, or pieces of the release paper and semiconductor chips that are generated when the release paper comes into contact with the semiconductor chip during the opening and packing operations.

[0031] <Foreign matter adhesion rate> In the present invention, the foreign matter adhesion rate refers to the ratio of the number of semiconductor chips S having foreign matter attached thereto among the semiconductor chips S located at the outermost periphery of the plurality of semiconductor chips 20. Since the number of foreign matters attached to the semiconductor chips T inside the arrangement of the plurality of semiconductor chips 20 is small, they are not included in the judgment. In other words, the foreign matter adhesion rate can be expressed by the following formula (1). Foreign matter adhesion rate (%) = (number of semiconductor chips S with foreign matter attached among semiconductor chips S) / (number of semiconductor chips S) × 100 (1)

[0032] <Appearance Judgment Criteria> The appearance judgment criteria of the present invention will be explained using FIG. 2. In the example, an automatic appearance inspection device (camera used: AP-3200T-PMCL manufactured by JAI Corporation, lens used: 2x lens, resolution: 1.7 μm) was used to capture a coaxial epi-illumination image of the surface of the semiconductor chip 100 opposite the adhesive surface with the adhesive sheet, on which the semiconductor layer or electrode pattern is formed, and image data was acquired. A semiconductor chip 100 having a foreign substance 13 attached thereto was determined to have the foreign substance 13 attached thereto when the foreign substance 13 was present within a range from the edge 101 of the semiconductor chip 100 to within 10 μm of the edge 101. In the three examples shown in FIG. 2, the leftmost image is determined to have no foreign substance 13 attached thereto because the foreign substance 13 was not present within a range from the edge 101 of the semiconductor chip 100 to within 10 μm of the edge 101 of the semiconductor chip 100. The central and rightmost images are determined to have the foreign substance 13 attached thereto because the foreign substance 13 was present within a range from the edge 101 of the semiconductor chip 100 to within 10 μm of the edge 101 of the semiconductor chip 100. The term "cross" means that the foreign matter is continuously present within a range of 10 μm from the edge 101 of the semiconductor chip 100 and is in contact with both the edge 101 and a point 10 μm from the edge 101.

[0033] An embodiment of the present invention will be described below.

[0034] (Semiconductor chip packaging method) A method for packaging semiconductor chips according to the present invention includes an arrangement step and a packaging step, and the packaging step includes a step of arranging a frame-shaped spacer. The method for packaging semiconductor chips according to an embodiment of the present invention will be described in detail below with reference to FIGS. 3A to 3C. In the arrangement step, a plurality of semiconductor chips 100 are arranged on an adhesive sheet 10 to form a plurality of semiconductor chips 20 (FIG. 3A). In the packaging step, a frame-shaped spacer 11 is first arranged on the adhesive sheet 10 so as to surround the plurality of semiconductor chips 20 arranged in the arrangement step (FIG. 3B). Next, a release paper 12 is arranged on the adhesive sheet 10 so as to cover the plurality of semiconductor chips 20 (FIG. 3C).

[0035] <Arrangement process> As described above, the arrangement step is a step of arranging multiple semiconductor chips 100 on the adhesive sheet 10 (FIG. 3A). The number of semiconductor chips 20 is not particularly limited, but can be, for example, 2 columns and 1 row to 200 columns and 200 rows. A soft, stretchable, single-sided adhesive sheet such as dicing tape or UV-curable tape can be used as the adhesive sheet 10. The dimensions of the adhesive sheet 10 can be, for example, 50 mm x 50 mm to 500 mm x 500 mm. The arrangement pitch A of the multiple semiconductor chips 20 is not particularly limited, but can be, for example, 0.3 mm to 3.0 mm. The long side width B of the arrangement range R of the multiple semiconductor chips 20 is not particularly limited as long as it is smaller than the dimensions of the adhesive sheet 10, but can be, for example, 0.5 mm to 200 mm. Similarly, the short side width C can be, for example, 0.3 mm to 200 mm. Between the adhesive sheet 10 and the semiconductor chip 100, there is an adhesive force to the extent that the semiconductor chip 100 will not shift position unless it is touched after being placed.

[0036] <Packing process> As described above, the packaging step first includes a step of arranging frame-shaped spacers 11 on adhesive sheet 10 so as to surround the plurality of semiconductor chips 20 arranged in the arrangement step (FIG. 3B). Next, the packaging step includes a step of arranging release paper 12 on adhesive sheet 10 so as to cover the plurality of semiconductor chips 20 (FIG. 3C). There is sufficient adhesive force between adhesive sheet 10 and frame-shaped spacer 11 that the frame-shaped spacer 11 will not shift position after arrangement unless it is touched.

[0037] The frame-shaped spacer 11 is preferably less prone to bending than the adhesive sheet 10. The material of the frame-shaped spacer 11 is preferably a material that does not emit gases that have a detrimental effect on the semiconductor chip. Therefore, the material of the frame-shaped spacer 11 is preferably the same as the resin material or the release paper 12, more preferably the same as the resin material or the release paper 12 used to package the semiconductor chip or semiconductor wafer, and even more preferably the same as the release paper 12. Here, examples of the resin material include polyethylene, polypropylene, polyvinyl chloride, PTFE, and PEEK resin, and examples of the material of the release paper include paper as a base material and polyethylene as a laminating material.

[0038] The shape of the inner periphery of the frame-shaped spacer 11 is preferably such that the adhesive sheet 10 and the release paper 12 do not come into contact with each other inside the frame-shaped spacer 11, and preferably there is a space between the adhesive sheet 10 and the release paper 12. That is, it is preferable that multiple semiconductor chips 20 are arranged in a closed space formed by the inner surface of the frame-shaped spacer 11, the adhesive sheet 10, and the release paper 12. It is more preferable that the adhesive sheet 10 has little deflection inside the frame-shaped spacer 11, and that the surface of the semiconductor chip 100 and the release paper 12 are approximately parallel when viewed from the side of the semiconductor chip 100. The shape of the inner periphery of the frame-shaped spacer 11 can be designed arbitrarily to match the shape of the multiple semiconductor chips 20, as long as it is possible to achieve a state in which the edges or corners of the semiconductor chip 100 do not come into contact with the release paper 12. The shapes of the multiple semiconductor chips 20 may be elliptical or circular, rectangular or square, or polygonal. The shape of the outer periphery of the frame-shaped spacer 11 can also be arbitrarily set to match the shape of the inner periphery, as long as it does not cause problems in bonding the adhesive sheet 10 to the frame-shaped spacer 11 and bonding the adhesive sheet 10 to the release paper 11. Regardless of the shapes of the multiple semiconductor chips 20 and the frame-shaped spacer 11, it is necessary that the frame-shaped spacer 11 not come into contact with the semiconductor chips 100 when arranging or peeling it off. Therefore, the shortest distance between the inside of the frame-shaped spacer 11 and the outside of the arrangement of the semiconductor chips 100 is preferably equal to or greater than the arrangement pitch A of the multiple semiconductor chips 20, and can be, for example, 1 mm or more, and preferably 2 mm to 50 mm. The longest distance between the inside of the frame-shaped spacer 11 and the outside of the arrangement of the semiconductor chips 100 depends on the thickness of the frame-shaped spacer 11, but as described above, it should be a length that prevents the adhesive sheet 10 and the release paper 11 from coming into contact inside the frame-shaped spacer 11 due to bending of the adhesive sheet 10.

[0039] For example, the inner dimension of the frame-shaped spacer 11 in the direction of the long side width B of the arrangement range R of the multiple semiconductor chips 20 is preferably 1.1 times or more and less than 2.0 times the long side width B of the arrangement range R of the multiple semiconductor chips 20, more preferably 1.2 times or more and less than 1.8 times, and even more preferably 1.4 times or more and less than 1.6 times. The value of the inner dimension of the frame-shaped spacer 11 / the outer dimension of the frame-shaped spacer 11 is preferably less than 0.8, and more preferably less than 0.7. If the ratio of the inner dimensions to the long side width B of the frame-shaped spacer 11 is smaller than the above range, the frame-shaped spacer 11 may come into contact with the semiconductor chip 100 when placed on the adhesive sheet 10, potentially damaging the semiconductor chip 100. If the ratio of the inner dimensions to the long side width B of the frame-shaped spacer 11 is larger than the above range, the adhesive sheet 10 may sag in the space surrounded by the inner periphery of the frame-shaped spacer 11, potentially causing the release paper 12 to come into contact with the semiconductor chip 100. However, by keeping the ratio within the above range, this possibility can be sufficiently reduced.

[0040] The thickness of the frame-shaped spacer 11 is preferably 1.0 to less than 20.0 times the thickness of the semiconductor chip 100, more preferably 1.1 to less than 4.0 times, and even more preferably 1.5 to less than 3.0 times. If the thickness of the frame-shaped spacer 11 is thinner than the thickness of the semiconductor chip 100, the release paper 12 is more likely to come into contact with the edges or corners of the multiple semiconductor chips 100, potentially reducing the effectiveness of the spacer. Furthermore, if the thickness of the frame-shaped spacer 11 is too thick relative to the thickness of the semiconductor chip 100, adhesion between the adhesive sheet 10 and the release paper 12 may become difficult, potentially resulting in peeling, or the thickness after packaging may increase, reducing transportation efficiency. However, by keeping the thickness within the above range, these possibilities can be sufficiently reduced. The 1.0-fold thickness, which is also used in Example 1 described below, is a relationship in which the surface of the semiconductor chip 100 and the release paper 12 are in parallel contact with each other. When the contact is parallel, there is less chance of rubbing between the release paper 12 and the edge or corner of the semiconductor chip 100 even when they are in contact, so even at a factor of 1.0, the possibility of foreign matter 13 being generated due to rubbing against the edge or corner of the semiconductor chip 100 is reduced, but the rate of adhesion of foreign matter 13 can be further reduced if there is nothing directly contacting the surface of the semiconductor chip 100, such as at a factor of 1.1 or more.

[0041] Next, release paper 12 is placed on adhesive sheet 10 so as to cover the plurality of semiconductor chips 20. There may or may not be adhesive force between release paper 12 and frame-shaped spacer 11, but if there is no adhesive force between release paper 12 and frame-shaped spacer 11, it is preferable that release paper 12 and adhesive sheet 10 stick to each other on the outside of frame-shaped spacer 11. Furthermore, it is preferable that release paper 12 covers the entire adhesive sheet 10 and is larger than adhesive sheet 10. This is to make the opening and packing operations easier.

[0042] When release paper 12 and adhesive sheet 10 are attached to each other outside frame-shaped spacer 11, as shown in Fig. 4A, the longest distance (distance 1) from the outer periphery of frame-shaped spacer 11 due to the thickness of frame-shaped spacer 11 to where adhesive sheet 10 and release paper 12 are attached to each other is preferably no more than half, more preferably no more than one-third, and even more preferably no more than one-quarter of the shortest distance (distance 2) between the outer periphery of frame-shaped spacer 11 and the outer periphery of adhesive sheet 10. This ensures a sufficient area for release paper 12 to adhere to adhesive sheet 10.

[0043] (Variation) In the above description, after the arrangement step in which multiple semiconductor chips 100 are arranged to form multiple semiconductor chips 20, the frame-shaped spacer 11 is arranged in alignment with the multiple semiconductor chips 20, and the packaging step includes the step of arranging the frame-shaped spacer 11. As a variation, the order may be changed so that the frame-shaped spacer 11 is arranged on the adhesive sheet 10 before arranging the multiple semiconductor chips 100, and then, in the arrangement step in which the multiple semiconductor chips 100 are arranged, the step of arranging the multiple semiconductor chips 100 by aligning them inside the frame-shaped spacer 11 may be performed. Even with this order, the semiconductor chip package described below can be formed in the same shape, and similar effects can be achieved. Note that this order of the variation is also expected to be effective in preventing contact between multiple semiconductor chips due to operational errors, such as curling of the soft adhesive sheet 10, during the arrangement step.

[0044] (Semiconductor chip packaging) The following describes the semiconductor chip packaging body 1 obtained through the process including the above-mentioned arrangement step and packaging step. As shown in Figures 3C and 4A, this semiconductor chip packaging body 1 includes an adhesive sheet 10, a plurality of semiconductor chips 20 arranged on the adhesive sheet 10, a release paper 12 located on the adhesive sheet 10 and covering the plurality of semiconductor chips 20, and a frame-shaped spacer 11 disposed between the adhesive sheet 10 and the release paper 12 and surrounding the outside of the plurality of semiconductor chips 20.

[0045] The significance of providing a frame-shaped spacer 11 in the semiconductor chip packaging 1 will now be described. FIG. 4A is a schematic bottom view of a semiconductor chip packaging 1 according to one embodiment of the present invention, as viewed from the adhesive sheet side (the surface opposite the adhesive surface of the adhesive sheet), and FIG. 4B is a cross-sectional view taken along line AA of the semiconductor chip packaging 1. FIG. 4C is a schematic cross-sectional view of a conventional semiconductor chip packaging in which the frame-shaped spacer 11 is not provided. When multiple semiconductor chips 100 are arranged on the adhesive sheet 10, the adhesive sheet 10 bends. If the frame-shaped spacer 11 is not used as shown in FIG. 4C, the edges or corners of the semiconductor chips 100 located at the outermost periphery of the multiple semiconductor chips 20 may come into contact with the release paper 12, potentially resulting in the generation of foreign matter 13.

[0046] In contrast, when the frame-shaped spacer 11 is disposed between the adhesive sheet 10 and the release paper 12 according to this embodiment, as shown in FIG. 4B , the edge or corner of the frame-shaped spacer 11 comes into contact with the release paper 12. Therefore, the edge or corner of the semiconductor chip 100 located at the outermost periphery of the plurality of semiconductor chips 20 is less likely to come into contact with the release paper 12. In other words, even if the semiconductor chip package 1 is repeatedly opened and packaged, the possibility of foreign matter 13 being generated is low. Thus, it is preferable to have a space between the adhesive sheet 10 and the release paper 12 inside the frame-shaped spacer 11. It is preferable that the plurality of semiconductor chips 20 are disposed within a closed space formed by the inner surface of the frame-shaped spacer 11, the adhesive sheet 10, and the release paper 12. Furthermore, it is more preferable that the adhesive sheet 10 bends little inside the frame-shaped spacer 11, and that the surfaces of the semiconductor chips 100 and the release paper 12 are substantially parallel to each other.

[0047] As described above, the thickness of the frame-shaped spacer 11 is preferably 1.0 to less than 20.0 times the thickness of the semiconductor chip 100, more preferably 1.1 to less than 4.0 times, and even more preferably 1.5 to less than 3.0 times. If the thickness of the frame-shaped spacer 11 is thinner than the thickness of the semiconductor chip 100, there is a high possibility that the release paper 12 will come into contact with the edges or corners of the multiple semiconductor chips 100, which may reduce its effectiveness as a spacer. Furthermore, if the thickness of the frame-shaped spacer 11 is too thick relative to the thickness of the semiconductor chip 100, it may be difficult for the adhesive sheet 10 and the release paper 12 to adhere to each other, which may lead to peeling, or the thickness after packaging may increase, which may reduce transportation efficiency.

[0048] Depending on the thickness of the frame-shaped spacer 11, the semiconductor chips 100 located at the outermost periphery of the plurality of semiconductor chips 20 may come into surface contact with the release paper 12, but this does not pose a problem in this embodiment. The possibility of foreign matter 13 occurring increases when the edges or corners of the semiconductor chips 100 come into contact with the release paper 12, and surface-to-surface contact is unlikely to be a cause of the occurrence of foreign matter 13.

[0049] As mentioned above, the material of the frame-shaped spacer 11 is preferably a resin material or the same material as the release paper 12 described below, more preferably a resin material for packaging semiconductor chips or semiconductor wafers or the same material as the release paper 12, and even more preferably the same material as the release paper 12. Examples of the resin material include polyethylene, polypropylene, polyvinyl chloride, PTFE, or PEEK resin. The reason that the material of the frame-shaped spacer 11 is preferably the same material as the release paper 12 is that it has high releasability from the pressure-sensitive adhesive sheet 10 and good releasability. It is also preferable that the frame-shaped spacer 11 be outgassing-suppressed.

[0050] As described above, the inner dimensions of the frame-shaped spacer 11 are preferably 1.1 times or more and less than 2.0 times the long side width B of the arrangement range R of the multiple semiconductor chips 20, more preferably 1.2 times or more and less than 1.8 times, and even more preferably 1.4 times or more and less than 1.6 times. The ratio of the inner dimensions of the frame-shaped spacer 11 to the outer dimensions of the frame-shaped spacer 11 is preferably less than 0.8, more preferably less than 0.7. If the inner dimensions of the frame-shaped spacer 11 are small, the frame-shaped spacer 11 may come into contact with the semiconductor chip 100 when placed on the adhesive sheet 10, potentially damaging the semiconductor chip 100. Furthermore, if the inner dimensions of the frame-shaped spacer 11 are large, the adhesive sheet 10 may sag, potentially causing the release paper 12 to come into contact with the semiconductor chip 100.

[0051] The width of the frame-shaped spacer 11 may be constant or may vary depending on the position. The shape of the inner and outer peripheries of the frame-shaped spacer 11 can be any shape, such as circular, rectangular, or polygonal, as long as the adhesive sheet 10 does not bend and come into contact with the release paper 12 described below in the space between the frame-shaped spacer 11 and the multiple semiconductor chips 20. The shapes of the inner and outer peripheries of the frame-shaped spacer 11 may be the same or different. When the release paper 12 described below is not bonded to the frame-shaped spacer 11, the area enclosed by the inner and outer peripheries of the frame-shaped spacer 11 can be set arbitrarily as long as it ensures an adhesion area between the release paper 12 and the adhesive sheet 10 on the outer adhesive surface of the frame-shaped spacer 11. On the other hand, when the release paper 12 is bonded to the frame-shaped spacer 11, it can be set arbitrarily as long as it ensures an adhesion area between the frame-shaped spacer 11 and the release paper 12 and between the frame-shaped spacer 11 and the adhesive sheet 10.

[0052] It is preferable that the release paper 12 sticks to the adhesive sheet 10 on the outside of the frame-shaped spacer 11. It is preferable that the release paper 12 covers the entire adhesive sheet 10 and is larger than the adhesive sheet 10. This makes it possible to carry out the opening and packing operations more smoothly. The material of the release paper 12 can be paper as the base material and polyethylene or the like as the laminating material.

[0053] As mentioned above, depending on the thickness of frame-shaped spacer 11, the longest distance from the outer periphery of frame-shaped spacer 11 to where adhesive sheet 10 and release paper 12 adhere to each other (distance 1 in FIG. 4A) is preferably no more than half, more preferably no more than one-third, and even more preferably no more than one-quarter of the shortest distance (distance 2 in FIG. 4A) between the outer periphery of frame-shaped spacer 11 and the outer periphery of adhesive sheet 10. This is to ensure a sufficient area where release paper 12 adheres to adhesive sheet 10. [Example]

[0054] The present invention will be described in more detail below using examples, but the present invention is not limited to the following examples. Reference numerals refer to Figures 1 to 4.

[0055] First, preparations for each example and comparative example will be described. Example 1 Semiconductor chips 100 (0.35 mm square, 0.15 mm thick) were arranged on the adhesive surface of Nitto Denko Corporation's dicing tape 10 (190 mm square, ELP V-8SR) in a rectangular array of 74 columns and 19 rows, with an array pitch of 0.55 mm, and left-justified, for a total of 1,400 chips (arrangement area: 40.5 mm x 10.5 mm). Murai Electric Co., Ltd.'s MT sheet (90 mm square, 0.15 mm thick) was cut into a 14 mm wide rectangular shape (external dimensions: 90 mm x 90 mm, internal dimensions: 62 mm x 62 mm) and attached to the outer periphery of the semiconductor chips 20, with the sides of the semiconductor chips 20 parallel to the internal sides of the frame-shaped spacer 11. The MT sheet used here is a release paper with a release surface on both sides. Furthermore, at this time, the inner dimension of the frame-shaped spacer 11 in the direction of the long side width was 1.53 times the long side width (40.5 mm) of the multiple semiconductor chips 20, and the frame-shaped spacer 11 was arranged so that the distance between the outer periphery of the multiple semiconductor chips 20 and the inner surface of the frame-shaped spacer 11 was uniform, and the shortest distance between the multiple semiconductor chips 20 and the frame-shaped spacer 11 was approximately 11 mm (10.7 mm). A release paper 12 made from a similar MT sheet processed to 310 mm x 320 mm was attached thereon. Then, the adhesive surface between the dicing tape 10 and the release paper 12 in the outer region of the frame-shaped spacer 11 was rubbed with a nonwoven fabric pallet to remove as much air as possible, and the multiple semiconductor chips 20 were packaged so that they were arranged within the closed space formed by the inner surface of the frame-shaped spacer 11, the dicing tape 10, and the release paper 12. Here, the release paper 12 was attached to the dicing tape 10 only on the outside of the frame-shaped spacer 11, and due to the thickness of the frame-shaped spacer 11, the longest distance (distance 1) from the outer periphery of the frame-shaped spacer 11 to where the dicing tape 10 and the release paper 12 were attached to each other was 5 mm. Also, the shortest distance (distance 2) between the outer periphery of the frame-shaped spacer 11 and the outer periphery of the dicing tape 10 was 39 mm. That is, the value of distance 1 / distance 2 was 0.13. In Example 1, the number of semiconductor chips 100 located on the outermost periphery of the multiple semiconductor chips 20 was 181.

[0056] Example 2 A total of 2,088 semiconductor chips 100 (0.35 mm square, 0.15 mm thick) were arranged on the adhesive surface of Nitto Denko dicing tape 10 (190 mm square, ELP V-8SR) in a rectangular array of 74 columns and 29 rows, with an array pitch of 0.55 mm and left-justified (arrangement area: 40.5 mm x 15.9 mm). A frame-shaped spacer 11, a Protos spacer (90 mm square, 1 mm thick) manufactured by Achilles Corporation, was cut into a 14 mm wide rectangular shape (external dimensions: 90 mm x 90 mm, internal dimensions: 62 mm x 62 mm), and attached to surround the periphery of multiple semiconductor chips 20. Each Protos spacer was a low-density polyethylene sheet. Also, at this time, the inner dimension of the frame-shaped spacer 11 was 1.53 times the long side width (40.5 mm) of the multiple semiconductor chips 20, and the frame-shaped spacer 11 was arranged so that the distance between the outer periphery of the multiple semiconductor chips 20 and the inner surface of the frame-shaped spacer 11 was not biased relative to the long side width, and the shortest distance between the multiple semiconductor chips 20 and the frame-shaped spacer 11 was approximately 11 mm (10.7 mm). On top of that, a release paper 12 made by processing the MT sheet used in Example 1 to 310 mm x 320 mm was attached. Then, the adhesive surface between the dicing tape 10 and the release paper 12 in the outer region of the frame-shaped spacer 11 was rubbed with a nonwoven fabric pallet to remove as much air as possible, and the multiple semiconductor chips 20 were packaged so that they were arranged in a closed space formed by the inner surface of the frame-shaped spacer 11, the dicing tape 10, and the release paper 12. Here, the release paper was attached to the dicing tape 10 only on the outside of the frame-shaped spacer 11, and distance 1 and distance 2, which were caused by the thickness of the frame-shaped spacer, were 10 mm and 40 mm, respectively. That is, the value of distance 1 / distance 2 was 0.25. In Example 2, the number of semiconductor chips 100 located on the outermost periphery of the multiple semiconductor chips 20 was 201.

[0057] Example 3 The frame-shaped spacer 11 used was a frame-shaped spacer 11 obtained by stacking two of the frame-shaped spacers 11 used in Example 1 and adhering them with double-sided tape (Nichiban Co., Ltd., Nicetack NW-10), and the same experiment as in Example 1 was carried out except that the number of semiconductor chips 100 arranged was 2037. Here, distance 1 was 7 mm and distance 2 was 40 mm. That is, the value of distance 1 / distance 2 was 0.18. In Example 3, the number of semiconductor chips 100 located on the outermost periphery of the plurality of semiconductor chips 20 was 199.

[0058] (Comparative Example) The same procedure as in Example 1 was carried out, except that no frame-shaped spacer 11 was used and the number of arranged semiconductor chips 100 was 1424. In the comparative example, the number of semiconductor chips 100 located on the outermost periphery of the plurality of semiconductor chips 20 was 183.

[0059] For each example, the state of adhesion of foreign matter 13 to the semiconductor chip 100 was observed. Specifically, the release paper 12 and frame-shaped spacer 11 were peeled off from the state shown in FIG. 3C to return to the state shown in FIG. 3A. Then, using an automated visual inspection device (camera used: AP-3200T-PMCL manufactured by JAI Corporation, lens used: 2x lens, resolution 1.7 μm), a coaxial epi-illumination image of the surface of the semiconductor chip 100 located at the outermost periphery of the multiple semiconductor chips 20 opposite to the adhesive surface with the dicing tape 10 was captured, and image data was obtained. After capturing the image, the frame-shaped spacer 11 and release paper 12 were attached from FIG. 3A to return to the state shown in FIG. 3C. The process of peeling off the release paper 12, taking the image, and attaching the release paper 12 constitutes one visual inspection step. The visual inspection in the comparative example was similar except that the frame-shaped spacer 11 was not used. According to the above-mentioned appearance inspection criteria, for each semiconductor chip 100 located at the outermost periphery of the plurality of semiconductor chips 20, if there was a foreign substance crossing the range from the edge 101 of the semiconductor chip 100 to 10 μm inward, it was determined to be a foreign substance-adhered chip. The number of foreign substance-adhered chips was counted, and the foreign substance adhesion rate was calculated. As mentioned above, the foreign substance adhesion rate was calculated using formula (1). As mentioned above, the criteria for determining foreign substance-adhered chips are shown in Figure 2. Of the three examples shown in Figure 2, the examples in the center and on the right are determined to be foreign substance-adhered chips. The above-mentioned appearance inspection was repeated until a total of 10 times, and the progress in the number of foreign substance-adhered chips was confirmed.

[0060] Table 1 shows the conditions of the frame-shaped spacer 11 according to each example and comparative example.

[0061] [Table 1]

[0062] Table 2 shows the conditions of the semiconductor chips 20 according to each of the examples and comparative examples.

[0063] [Table 2]

[0064] Table 3 shows the relationship between distance 1, distance 2, and distance 1 / distance 2 for each example and comparative example.

[0065] [Table 3]

[0066] Table 4 shows the results of repeated measurements for each of the Examples and Comparative Examples.

[0067] [Table 4]

[0068] FIG. 5 shows the transition of the foreign matter adhesion rate over time for each example and comparative example. Table 4 and FIG. 5 reveal that the semiconductor chip packages 1 of Examples 1 to 3, in which the frame-shaped spacer 11 was placed, had a lower foreign matter adhesion rate than the comparative example, in which the frame-shaped spacer 11 was not placed. This suggests that when using the semiconductor chip packages 1 obtained under the conditions of the present invention, the foreign matter adhesion rate can be kept low even when the unpacking and packing operations are repeated after packaging. The reason for the particularly low foreign matter adhesion rate in Example 3 is thought to be due to the optimal thickness ratio between the frame-shaped spacer 11 and the semiconductor chip 100. When the frame-shaped spacer 11 and the semiconductor chip 100 have the same thickness, they come into surface contact with each other during each unpacking and packing operation. This is thought to result in a higher foreign matter adhesion rate than in Examples 2 and 3, in which the frame-shaped spacer 11 is thicker and there is no surface contact. Furthermore, release paper is preferable for the frame-shaped spacer 11 material because it is easier to peel from the dicing tape 10 and causes less deflection of the adhesive sheet during peeling, making it easier to work with. In Example 2, the thickness of the frame-shaped spacer 11 was greater than that of the semiconductor chip 100, resulting in greater deflection, and the use of a protospacer resulted in unnecessary movement during the opening and packing operations, which is thought to have resulted in a higher rate of foreign matter adhesion than in Example 3.

[0069] Furthermore, even when the order was changed so that the frame-shaped spacer 11 in Example 1 was placed on the dicing tape 10 before the semiconductor chips 100 were arranged, the same results as in Example 1 were obtained. [Explanation of symbols]

[0070] 1 Semiconductor chip packaging 10 adhesive sheet 11 Frame-shaped spacer 12 Release paper 13 Foreign object 20 Multiple semiconductor chips 100 semiconductor chips 101 En S: semiconductor chips located on the outermost periphery of the plurality of semiconductor chips 20 T: a semiconductor chip located inside the plurality of semiconductor chips 20 (a semiconductor chip other than S) R: Arrangement range of the plurality of semiconductor chips 20 B: Long side width of the arrangement range R of the plurality of semiconductor chips 20 A 20-point arrangement pitch of multiple semiconductor chips

Claims

1. An adhesive sheet, a plurality of semiconductor chips arranged on the adhesive sheet; a release paper positioned on the adhesive sheet and covering the semiconductor chips; a frame-shaped spacer disposed between the adhesive sheet and the release paper and surrounding the outer sides of the semiconductor chips; Equipped with Semiconductor chip packaging.

2. The plurality of semiconductor chips are arranged in a closed space formed by the inner surface of the frame-shaped spacer, the adhesive sheet, and the release paper. The semiconductor chip package according to claim 1 .

3. The thickness of the frame-shaped spacer is 1.0 times or more and less than 20.0 times the thickness of the semiconductor chip. The semiconductor chip package according to claim 1 .

4. The material of the frame-shaped spacer is a resin material or the same material as the release paper. The semiconductor chip package according to claim 1 .

5. an inner dimension of the frame-shaped spacer in the direction of the long side width of the arrangement range of the plurality of semiconductor chips is 1.1 times or more and less than 2.0 times the long side width of the arrangement range of the plurality of semiconductor chips; The semiconductor chip package according to claim 1 .

6. the release paper is attached to the adhesive sheet on the outside of the frame-shaped spacer; The semiconductor chip package according to claim 1 .

7. the maximum distance from the outer periphery of the frame-shaped spacer to where the adhesive sheet and the release paper are attached to each other due to the thickness of the frame-shaped spacer is not more than half the minimum distance between the outer periphery of the frame-shaped spacer and the outer periphery of the adhesive sheet; The semiconductor chip package according to claim 6 .

8. an arrangement step of arranging a plurality of semiconductor chips on an adhesive sheet; a packaging step of placing a release paper covering the semiconductor chips on the adhesive sheet; Including, the packaging step includes a step of arranging a frame-shaped spacer that surrounds the outside of the plurality of semiconductor chips between the adhesive sheet and the release paper. Packaging methods for semiconductor chips.

9. an arrangement step of arranging a plurality of semiconductor chips on an adhesive sheet; a packaging step of placing a release paper covering the semiconductor chips on the adhesive sheet; Including, the arranging step includes a step of arranging a frame-shaped spacer on the pressure-sensitive adhesive sheet in advance, In the packaging step, a frame-shaped spacer is disposed between the adhesive sheet and the release paper at a position surrounding the outside of the plurality of semiconductor chips. Packaging methods for semiconductor chips.

10. The plurality of semiconductor chips are arranged in a closed space formed by the inner surface of the frame-shaped spacer, the adhesive sheet, and the release paper.

10. The method for packaging semiconductor chips according to claim 8 or 9.

11. The thickness of the frame-shaped spacer is 1.0 times or more and less than 20.0 times the thickness of the semiconductor chip.

10. The method for packaging semiconductor chips according to claim 8 or 9.

12. The material of the frame-shaped spacer is a resin material or the same material as the release paper.

10. The method for packaging semiconductor chips according to claim 8 or 9.

13. an inner dimension of the frame-shaped spacer in the direction of the long side width of the arrangement range of the plurality of semiconductor chips is 1.1 times or more and less than 2.0 times the long side width of the arrangement range of the plurality of semiconductor chips; 10. The method for packaging semiconductor chips according to claim 8 or 9.

14. In the packaging step, the release paper and the adhesive sheet are attached to each other on the outside of the frame-shaped spacer.

10. The method for packaging semiconductor chips according to claim 8 or 9.

15. the maximum distance from the outer periphery of the frame-shaped spacer to where the adhesive sheet and the release paper are attached to each other due to the thickness of the frame-shaped spacer is not more than half the minimum distance between the outer periphery of the frame-shaped spacer and the outer periphery of the adhesive sheet; The method for packaging semiconductor chips according to claim 14.

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