Error correction management for data storage system

Abstract

To provide a system, method and device for managing error corrections for a data storage system.SOLUTION: A data storage system 400 includes a data storage device 410 comprising at least one memory 412 and a memory controller including at least one first error correction code (ECC) decoder 414. The memory controller reads data from the at least one memory, executes an ECC test on the read-out data using the at least one first ECC decoder, and transmits the read-out data to an external device having at least one second ECC decoder for decoding the read-out data in response to a determination that the read-out data has not passed the ECC test. The external device 420 is located external of the data storage device. A second ECC decoder 422 has an ECC function stronger than the first ECC decoder.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to data storage systems, for example, error correction for data storage systems. [Background technology]

[0002] Once storage cells in a data storage device, e.g., a memory device, are programmed, data can be read from the storage cells by sensing the programming state of each memory cell by comparing the cell threshold voltage to one or more read voltages. However, the cell threshold voltage can change due to one or more factors, e.g., read disturb or data retention, which can cause the sensed programming state to differ from the written programming state, resulting in a fail bit in the data read output. Summary of the Invention

[0003] This disclosure describes systems, devices, methods, and techniques for managing error correction for data storage systems, such as data storage systems that include multiple data storage devices, such as solid-state drives (SSDs), high-density drives (HDDs), NAND flash modules, and combinations thereof.

[0004] One aspect of the present disclosure features a data storage system including one or more data storage devices and a system controller coupled to the one or more data storage devices. The one or more data storage devices include a data storage device having at least one memory and a memory controller coupled to the at least one memory, the memory controller including at least one first error correction code (ECC) decoder. The memory controller is configured to read data from the at least one memory, perform a first ECC test on the read data using the at least one first ECC decoder, and, in response to determining that the read data fails the first ECC test, transmit the read data to an external device having at least one second ECC decoder for decoding the read data. The external device is external to the data storage device, and the at least one second ECC decoder has stronger ECC capabilities than the at least one first ECC decoder.

[0005] In some implementations, the at least one memory includes one or more memory chips.

[0006] In some implementations, in response to determining that the read data fails the first ECC test and before transmitting the read data to the external device, the memory controller is configured to: determine whether the number of times the read data fails the first ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, modify one or more read parameters to re-read the data from the at least one memory or perform soft decoding on the data; and if the number has reached the predetermined threshold, transmit the read data to an external device including at least one second ECC decoder for decoding the read data.

[0007] In some implementations, in response to determining that the read data does not pass the first ECC test, and based on a result of the first ECC test before transmitting the read data to the at least one second ECC decoder, the memory controller is configured to do one of: i) modify one or more parameters for reading the data from the at least one memory or perform soft decoding on the data and perform the first ECC test again using the at least one first ECC decoder; or ii) transmit the read data to an external device including at least one second ECC decoder for decoding the read data.

[0008] In some implementations, the external device is configured to perform a second ECC test on the read data using at least one second ECC decoder, and in response to determining that the read data passes the second ECC test, transmit the corrected read data to the system controller.

[0009] In some implementations, in response to determining that the read data fails the second ECC test, the external device is configured to determine whether the number of times the read data fails the second ECC test is less than a predetermined threshold, and if the number is less than the predetermined threshold, transmit a notification to the memory controller to i) modify one or more parameters for reading the data from the at least one memory, or ii) perform soft decoding on the data, and if the number reaches the predetermined threshold, trigger a redundant array of independent disks (RAID) circuitry to perform error correction on the read data.

[0010] In some implementations, in response to determining that the read data fails the second ECC test and before triggering the RAID circuitry, the external device is configured to, based on the results of the second ECC test, do one of the following: i) modify one or more parameters for reading the data from the at least one memory or perform soft decoding on the data and re-run at least one of the first ECC test using the at least one first ECC decoder or the second ECC test using the at least one second ECC decoder; or ii) trigger the RAID circuitry to perform error correction on the read data.

[0011] In some implementations, the RAID circuitry is included in the memory controller and is configured to perform error correction on data read from the data storage device.

[0012] In some implementations, the RAID circuitry is included in the system controller and is configured to perform error correction on data read in one or more data storage devices.

[0013] In some implementations, the memory controller is configured to: perform an ECC decoding operation on the read data using at least one first ECC decoder; determine whether a number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold; determine that the read data passes the first ECC test if the number of error bits is less than the predetermined threshold; and determine that the read data fails to pass the first ECC test if the number of error bits is equal to or greater than the predetermined threshold.

[0014] In some implementations, the system controller is configured to receive commands from a host device external to the data storage system directing the reading of data from one or more data storage devices, send commands to the data storage devices to read the data, and transmit the corrected read data to the host device in response to receiving the corrected read data from the data storage devices or the external device.

[0015] In some implementations, the external device is separate from the one or more data storage devices and is coupled to the one or more data storage devices and the system controller.

[0016] In some implementations, the data storage device includes only at least one first ECC decoder without a second ECC decoder.

[0017] In some implementations, the external device includes only at least one second ECC decoder, without the first ECC decoder.

[0018] In some implementations, a second data storage device of the one or more data storage devices includes an external device, and the second data storage device includes one or more first ECC decoders and at least one second ECC decoder.

[0019] In some implementations, the one or more data storage devices include one or more first data storage devices each including only one or more first ECC decoders, and the one or more second data storage devices each including one or more first ECC decoders and one or more second ECC decoders.

[0020] In some implementations, the system controller is configured to store a first type of data in one or more first data storage devices and to store a second type of data in one or more second data storage devices, the first type of data being configured to be read more frequently than the second type of data.

[0021] In some implementations, the one or more first data storage devices and the one or more second data storage devices are configured to operate based on a protocol. Each of the one or more first data storage devices is configured to transmit the read first data to one of the one or more second data storage devices in response to determining that one or more first ECC decoders in the first data storage device fail to correct the first data read from a corresponding first memory. Each of the one or more second data storage devices is configured to decode the corresponding read data using one or more second ECC decoders in the second data storage device in response to receiving the corresponding read data from one of the one or more first data storage devices.

[0022] In some implementations, the external device is contained within the system controller.

[0023] In some implementations, the data storage system further includes one or more external devices, each of the one or more external devices including one or more second ECC decoders.

[0024] In some implementations, the system controller is configured to generate an alert message to discard the data storage device based on at least one of a result of the first ECC test using the at least one first ECC decoder or a result of the second ECC test using the at least one second ECC decoder.

[0025] In some implementations, the memory controller includes a first ECC encoder configured to encode data to generate first ECC data, the memory controller is configured to store the data together with the first ECC data in the at least one memory, the at least one first ECC decoder is configured to decode the read data based on the first ECC data, and the at least one second ECC decoder is configured to decode the read data based on the first ECC data.

[0026] In some implementations, the memory controller includes a first ECC encoder configured to encode data to generate first ECC data, and the external device includes a second ECC encoder configured to encode data to generate second ECC data. The memory controller is configured to store data with the first ECC data and the second ECC data in at least one memory, read data with the first ECC data and the second ECC data from the at least one memory, and, in response to determining that the read data fails the first ECC test, transmit the read data and the second ECC data to an external device having at least one second ECC decoder. The at least one first ECC decoder is configured to decode the read data based on the first ECC data, and the at least one second ECC decoder is configured to decode the read data based on the second ECC data received from the memory controller.

[0027] In some implementations, the memory controller is configured to store the first ECC data and the second ECC data as a concatenated code of data in the at least one memory.

[0028] In some implementations, the system controller is configured to transmit multiple portions of specific data to multiple data storage devices of one or more data storage devices, respectively. Each of the multiple data storage devices includes a first ECC encoder and one or more first ECC decoders, where the first ECC encoder is configured to encode a corresponding portion of the specific data to generate corresponding first ECC data. The external device includes a second ECC encoder configured to encode a corresponding portion of the specific data to generate second ECC data. Each of the multiple data storage devices includes a memory controller configured to store the corresponding portion of the specific data together with the corresponding first ECC data and second ECC data in a corresponding memory. For each of the multiple data storage devices, the one or more first ECC decoders are configured to decode the corresponding portion of the specific data from the corresponding memory based on the corresponding first ECC data. At least a second ECC decoder in the external device is configured to decode the portion of the specific data based on the second ECC data in response to receiving the portion of the specific data and the second ECC data from one of the multiple data storage devices.

[0029] In some implementations, the at least one first ECC decoder and the at least one second ECC decoder include the same type of decoder with different ECC functions.

[0030] In some implementations, the at least one first ECC decoder and the at least one second ECC decoder include different types of decoders having different ECC capabilities.

[0031] In some implementations, the at least one first ECC decoder includes a low-power (LP) low-density parity-check (LDPC) decoder, and the at least one second ECC decoder includes a min-sum (MS) LDPC decoder.

[0032] In some implementations, at least one of the at least one first ECC decoder or the at least one second ECC decoder is configured to perform Bose-Chaudhuri-Hocquenghem (BCH) decoding or LDPC decoding.

[0033] In some implementations, the first ECC decoder has lower power consumption than the second ECC decoder.

[0034] Another aspect of the present disclosure features a data storage device including at least one memory and a memory controller coupled to the at least one memory. The memory controller includes at least one first error correction code (ECC) decoder. The memory controller is configured to read data from the at least one memory, perform a first error correction code (ECC) test on the read data using the at least one first ECC decoder, and, in response to determining that the read data fails the first ECC test, transmit the read data to an external device having at least one second ECC decoder for decoding the read data. The external device is external to the data storage device, and the at least one second ECC decoder has stronger ECC capabilities than the at least one first ECC decoder.

[0035] In some implementations, the memory controller includes only at least one first ECC decoder without a second ECC decoder.

[0036] In some implementations, in response to determining that the read data fails the first ECC test and before transmitting the read data to the external device, the memory controller is configured to: determine whether the number of times the read data fails the first ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, modify one or more read parameters to re-read the data from the at least one memory or perform soft decoding on the data; and if the number has reached the predetermined threshold, transmit the read data to an external device including at least one second ECC decoder for decoding the read data.

[0037] Another aspect of the present disclosure features a device including at least one first error correction code (ECC) decoder externally coupled to at least one data storage device including at least one memory configured to store data. The at least one data storage device includes at least one second ECC decoder, the at least one first ECC decoder having stronger ECC capabilities than the at least one second ECC decoder. The at least one first ECC decoder is configured to: responsive to receiving read data from the at least one data storage device, perform an ECC test on the read data using the at least one first ECC decoder; and responsive to determining that the read data passes the ECC test, generate corrected read data for the at least one data storage device.

[0038] In some implementations, the device is configured, in response to determining that the read data fails the ECC test, to determine whether the number of times the read data fails the ECC test is less than a predetermined threshold, and if the number is less than the predetermined threshold, to transmit a notification to the at least one data storage device to i) modify one or more parameters for reading the data from the at least one memory or ii) perform soft decoding on the data, and if the number has reached the predetermined threshold, to trigger a redundant array of independent disks (RAID) circuitry to perform error correction on the read data.

[0039] In some implementations, the at least one second ECC decoder is configured to decode the read data based on ECC data associated with the data stored in the at least one memory, and the at least one first ECC decoder is configured to decode the read data based on the ECC data.

[0040] In some implementations, the device further includes a first ECC encoder configured to encode data to generate first ECC data and transmit the first ECC data to at least one data storage device. The at least one data storage device includes a second ECC encoder configured to encode data to generate second ECC data. The at least one data storage device is configured to store data with the first ECC data and the second ECC data in at least one memory, read data with the first ECC data and the second ECC data from the at least one memory, and transmit the read data and the first ECC data to the at least one first ECC decoder in response to determining that the at least one second ECC decoder is unable to decode the read data based on the second ECC data. The at least one first ECC decoder is configured to decode the read data based on the first ECC data in response to receiving the read data and the first ECC data from the at least one data storage device.

[0041] In some implementations, the data includes multiple portions, and the at least one data storage device includes multiple data storage devices configured to respectively store the multiple portions. The device further includes a first ECC encoder configured to encode the multiple portions of the data to generate first ECC data and transmit the first ECC data to each of the multiple data storage devices. Each of the multiple data storage devices includes a second ECC encoder configured to encode a corresponding portion of the data to generate corresponding second ECC data. Each of the multiple data storage devices is configured to store the corresponding portion of the data along with the corresponding second ECC data and first ECC data in a corresponding memory. The at least first ECC decoder is configured to decode the portion of the data based on the first ECC data in response to receiving the portion of the data and the first ECC data from one of the multiple data storage devices.

[0042] Implementations of the above technology include methods, systems, computer program products, and computer-readable media. In one example, the method may be performed by a data storage system including multiple data storage devices and a system controller coupled to the multiple data storage devices, and the method may include the above-described operations performed by the system controller and the data storage devices, such as operations for managing error correction for the data storage devices. In another example, one such computer program product is suitably embodied in a non-transitory machine-readable medium that stores instructions executable by one or more processors. The instructions are configured to cause the one or more processors to perform the above-described operations. One such computer-readable medium stores instructions configured, when executed by the one or more processors, to cause the one or more processors to perform the above-described operations.

[0043] The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0044] [Figure 1A] FIG. 1 is a schematic diagram of an example system including a data storage system.

[0045] [Figure 1B] 1 is a schematic diagram of an example of a first data storage device including both a weaker ECC decoder and a stronger ECC decoder.

[0046] [Figure 1C] FIG. 10 is a schematic diagram of an example of a second data storage device that includes only a weaker ECC decoder.

[0047] [Figure 1D] FIG. 1 is a schematic diagram of an example of an external device that includes only a stronger ECC decoder.

[0048] [Figure 2] 1 is a schematic diagram of an example of a data storage system including one or more external devices having a stronger ECC decoder for a data storage device having only a weaker ECC decoder.

[0049] [Figure 3] 1 is a schematic diagram of another example of a data storage system including a data storage device having a stronger ECC decoder for a data storage device having only a weaker ECC decoder.

[0050] [Figure 4] FIG. 10 is a schematic diagram of another example of a data storage system including a system controller that includes one or more external devices with stronger ECC decoders for the data storage devices.

[0051] [Figure 5] 1 is a flowchart of an exemplary process for managing error correction in a data storage system.

[0052] [Figure 6A] FIG. 2 is a schematic diagram of an exemplary process for encoding data and decoding data in a data storage system.

[0053] [Figure 6B] FIG. 2 is a schematic diagram of another exemplary process for encoding data and decoding data in a data storage system.

[0054] [Figure 6C] FIG. 2 is a schematic diagram of another exemplary process for encoding data and decoding data in a data storage system.

[0055] Like reference numbers and designations in the various drawings indicate like elements. It should also be understood that the various exemplary implementations shown in the figures are illustrative representations only and are not necessarily drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0056] Due to frequent read operations or long retention times, data stored in a memory may suffer from read disturbance or data retention, in which the states of memory cells in the memory, such as an erased state and one or more programmed states, may have changed their threshold voltages. The read disturbance or data retention may result in fail bits (or error bits) in the read output of the data. These problems become more severe in data storage systems that include multiple data storage devices, such as SSDs, HDDs, flash modules, or a combination thereof.

[0057] To ensure data accuracy, multiple approaches can be implemented. In some cases, read optimization (or calibration) approaches, such as read retries, valley tracking reads, and machine learning-based reads, can be employed to reduce error bits. In some cases, an error correction code (ECC) decoder can be configured to decode data read from the memory to detect and correct any bit errors that may exist in the data up to the error correction capability of the ECC scheme.

[0058] In some cases, erasure coding is implemented in storage systems to enhance fault tolerance and recover data from memory chip and / or storage device failures. In storage systems using erasure coding, data can be reconstructed even if a certain number of storage nodes become unavailable or experience data loss. This makes erasure coding valuable in distributed storage environments where hardware failures or network issues are common. While erasure coding offers attractive benefits, it also increases computational requirements. The encoding and decoding process involves complex mathematical calculations, potentially impacting system performance. In some cases, RAID (Redundant Array of Independent Disks) is a data storage virtualization technology that combines multiple physical disk drive components into one or more logical units for data redundancy, performance improvement, or both. Unlike ECC data, which is stored in the same page as user data, RAID redundant data is stored across different physical disk drive components. Therefore, RAID can provide inter-page RAID or inter-disk RAID protection to recover ECC-uncorrectable data as additional protection. However, to perform page-to-page or disk-to-disk RAID protection, every page is read for failed data, which takes much longer than ECC to recover the data. The probability of triggering RAID can be configured to be very low due to the performance requirements of the data storage system.

[0059] To avoid long recovery times for RAID procedures and / or high computational requirements for erasure coding, the error handling process of a data storage system may iteratively repeat read optimization and ECC decoding procedures with different parameter settings. To efficiently reduce the trigger rate of RAID and / or erasure coding, the error correction of read optimization and ECC decoding may also be improved. Generally, read optimization and ECC decoding approaches are implemented in a device controller (e.g., an SSD controller) of a data storage device (e.g., an SSD). However, achieving high ECC functionality requires significant hardware resources (e.g., the gate count of an ASIC in the SSD controller). In some cases, a data storage device may include a dual-mode ECC decoder, e.g., both a weaker ECC decoder and a stronger ECC decoder, to reduce the overall hardware cost and power consumption of the ECC decoder. However, the hardware overhead of the stronger ECC decoder remains a major part of the device controller. Furthermore, the power consumption of the stronger ECC decoder dominates the power consumption of the data storage device.

[0060] Implementations of the present disclosure provide techniques for managing error correction for data storage systems, for example, by providing i) a cost-effective data storage device with a weaker built-in ECC decoder for most read requests, and ii) one or more external devices with stronger ECC decoders that ensure the reliability of the entire data storage system. These techniques may be implemented with new error correction architectures for data storage systems, thereby enabling the cost of data storage devices (e.g., SSDs) to be effectively reduced with the same (or similar) reliability for the entire data storage system.

[0061] In some examples, the data storage system includes a rack cabinet or rack mount of a storage system that may include multiple data storage devices (e.g., SSDs or HDDs). In some examples, the data storage system is an all-flash array. A processing unit (e.g., FPGA or DPU) can function as a controller for multiple memory chips (e.g., NAND flash memory chips), and the combination of the processing unit and the multiple memory chips may be considered a storage module (or flash module). The all-flash array may include multiple storage modules. The data storage system may include a system controller configured to manage data allocation among the multiple data storage devices or multiple storage modules, which may improve read / write performance and storage lifespan.

[0062] A data storage device (or a single storage module) may include a built-in (or local) ECC decoder for detecting and correcting error bits in one or more memories (e.g., NAND flash memory chips). The built-in (or local) ECC decoder may be implemented with only a weaker ECC decoder, which may be inexpensive, low-power, and small in area. If the weaker ECC decoder is unable to decode data read from one or more memories, the data storage device may transmit the read data to an external device within the data storage system. The external device may be considered a guaranteed-reliability device or accelerator. The external device may be external to the data storage device and include a stronger ECC decoder for decoding the read data. The stronger ECC decoder has stronger ECC capabilities than the built-in (or local) ECC decoder. The built-in (or local) ECC decoder can process most read requests with low power consumption, while the stronger ECC decoder ensures the reliability of the entire data storage system. The number of stronger ECC decoders may be scalable to improve the end-of-life (EOL) performance of the entire data storage system. The data storage system may include one or more external devices that each include one or more stronger ECC decoders.

[0063] The external device can be implemented by a field programmable gate array (FPGA) device or any processing unit, such as a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), or a full SSD. In a data storage system, a data storage device or flash module (e.g., an SSD or a NAND flash module) is a consumable item due to its limited lifespan (e.g., endurance, maximum total bytes written (TBW)). Therefore, by implementing a data storage device or flash module with a lower-cost, weaker ECC decoder, the cost of the data storage device or flash module can be reduced, thereby effectively reducing the total cost of ownership (TCO) of the data storage system. These techniques enable the SSD / flash module to offload its primary burden (e.g., a stronger ECC decoder) and rely on the external device to maintain the reliability of the entire data storage system. This significantly reduces the cost of consumables for the entire data storage system. Also, improving the read performance of end-of-life devices can be achieved by adding a stronger ECC decoder to the external device. Furthermore, the read optimization approach can be performed locally or globally with the assistance of an external device with a stronger ECC decoder, such as machine learning based read optimization, which is online inference by the external device.

[0064] In some implementations, the external device is external to, but coupled to, the data storage device and the system controller, for example, as shown in further detail in Figure 2. In some implementations, the external device is included within the system controller, for example, as shown in further detail in Figure 4.

[0065] In some implementations, for example, as shown in further detail in FIG. 3 , the external device has its own memory chip and is integrated with a data storage device that provides the functionality of a typical data storage device (e.g., a typical SSD, HDD, or NAND flash module). The data storage device may include only a stronger ECC decoder or may include a dual-mode ECC decoder (e.g., both a weaker ECC decoder and a stronger ECC decoder). The data storage device may help decode faulty data in other data storage devices that have only weaker ECC decoders. In some instances, a data storage system includes one or more first data storage devices that have only weaker ECC decoders and one or more second data storage devices that have stronger ECC decoders and optionally weaker ECC decoders. The data storage system may store hot data (e.g., more data reads) with more frequent exchange in one or more first data storage devices and cold data (e.g., less frequent data reads) with less frequent exchange in one or more second data storage devices, which may reduce the total cost of ownership (TCO) of the data storage system. The data storage system may include a protocol between one or more first data storage devices and one or more second data storage devices to enable a stronger ECC decoder in the one or more second data storage devices to help decode failed data in the one or more first data storage devices.

[0066] In this disclosure, a weaker ECC decoder refers to an ECC decoder having a weaker ECC function that has lower power consumption and lower cost compared to a stronger ECC decoder having a stronger ECC function that has higher power consumption and higher cost. In some examples, the weaker ECC decoder is an ECC decoder having an ECC function lower than a threshold specified for the data storage device, and the stronger ECC decoder is an ECC decoder having an ECC function that is the same as or higher than the specified threshold. In some examples, the weaker ECC decoder and the stronger ECC decoder are the same type of decoder but with different ECC functions. For example, the weaker ECC decoder may be a low-power (LP) low-density parity-check (LDPC) decoder, and the stronger ECC decoder may be a min-sum (MS) LDPC decoder. In some examples, the weaker ECC decoder and the stronger ECC decoder are different types of decoders with different ECC functions. For example, the weaker ECC decoder may be a Bose-Chaudhuri-Hocquenghem (BCH) decoder, and the stronger ECC decoder may be an LDPC decoder. The ECC code is not limited to an LDPC code, and any linear block ECC may be used in the present disclosure, such as an algebraic code, a concatenated code, a product code, etc.

[0067] In some examples, the same ECC decoder (e.g., an LDPC decoder) may be configured to be a weaker ECC decoder or a stronger ECC decoder. For example, an ECC encoder is configured to encode data having a predetermined length or size (e.g., 4 KB) to generate ECC data having a predetermined size (e.g., 512 B). The ECC data may include ECC parity bits. An ECC decoder is configured to decode data having a predetermined length or size (e.g., 4 KB) using ECC data having a predetermined size (e.g., 512 B). For data of the same size, ECC data of a larger size may provide a higher error correction capability (or ECC function) than ECC data of a smaller size. For ECC data of the same size, ECC data may provide a higher error correction capability for data of a smaller size than for data of a larger size. For example, a 4 KB ECC encoder generates ECC data of 512 B. When an ECC encoder is used to encode 2 KB of data and 2 KB of predetermined (or fixed) values ​​(e.g., 1 or 0) to generate 512 B of ECC data, when an ECC decoder decodes the data using the ECC data, the 512 B of ECC data generated based on the 2 KB of data can provide higher error correction capability than the 512 B of ECC data generated based on 4 KB of data.

[0068] These techniques can be applied to various types of semiconductor devices, volatile memory devices, or nonvolatile memory (NVM) devices, including NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change memory (PCM) such as phase change random access memory (PCRAM), and spin-transfer torque (STT) magnetoresistive random access memory (MRAM), among others. These techniques can also be applied to charge trapping memory devices, such as silicon oxide nitride silicon oxide (SONOS) memory devices and floating gate memory devices. These techniques can be applied to two-dimensional (2D) or three-dimensional (3D) memory devices. These techniques can be applied to various memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices such as two-level cell devices, triple-level cell (TLC) devices, quad-level cell (QLC) devices, or penta-level cell (PLC) devices. Additionally or alternatively, these techniques may be applied to various types of devices and systems, such as Secure Digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, among others. These techniques may be applied to SSD- or HDD-based storage systems or all-flash arrays.

[0069] 1A is a schematic diagram of an example system 100 including a data storage system 110 and a host device 120. The data storage system 110 may include a system controller 112 and multiple data storage devices 130-1, 130-2, ..., 130-n (collectively and individually referred to as data storage devices 130), where n is an integer equal to or greater than 1. The system controller 112 and the data storage devices 130 may be coupled to a communication bus 115 through which the system controller 112 can communicate with each of the data storage devices 130 and the data storage devices 130 themselves can communicate with each other. In some examples, the communication bus 115 includes a Peripheral Component Interconnect Express (PCIe)-based bus or interface. In some implementations, the system controller 112 and the data storage devices 130 communicate wirelessly or via wires.

[0070] The system controller 112 is configured to manage data allocation among the data storage devices 130. For example, the system controller 112 can receive data and write commands from the host device 120 and store this data in one or more data storage devices 130. The system controller can also receive read commands from the host device 120 and read data from one or more data storage devices 130.

[0071] The host device 120 includes a host controller that may include at least one processor and at least one memory, the at least one memory coupled to the at least one processor and storing program instructions for execution by the at least one processor to perform one or more corresponding operations. The system controller 112 may include at least one memory and at least one processor configured to execute instructions and process data in the at least one memory. The instructions may include firmware instructions and / or other program instructions stored as firmware code and / or other program code, respectively. The data includes program data corresponding to firmware and / or other programs executed by the at least one processor, among other suitable data. In some implementations, the at least one processor is a general-purpose microprocessor or an application-specific microcontroller, such as a CPU, GPU, or DPU.

[0072] The data storage devices 130 may be solid-state drives (SSDs), embedded multimedia cards (eMMCs), secure digital (SD) cards, flash modules (e.g., NAND flash memory modules), or any other suitable storage devices. As described in further detail below, the data storage devices 130 may be the same as or different from one another, for example, as shown in FIG. 3.

[0073] In some implementations, data storage device 130 includes a memory controller and one or more memories. Each memory may include one or more memory chips (e.g., NAND flash memory chips). The memory controller is configured to receive data and instructions from system controller 112 and send data to system controller 112. The memory controller may be further configured to send data and commands to one or more memories and receive data from one or more memories. For example, the memory controller may be configured to send data and write commands to instruct one or more memories to store data at specified addresses. As another example, the memory controller may be configured to receive read requests (or read commands) from system controller 112 and send corresponding read commands to one or more memories to read data from specified addresses in the one or more memories.

[0074] In some implementations, the memory controller includes one or more ECC encoders and one or more ECC decoders. In some implementations, one or more ECC encoders and one or more ECC decoders may also be externally coupled to the memory controller. The ECC encoder may be configured to receive data to be stored in the memory and generate check bits by encoding the data, for example, using an ECC encoding scheme. The check bits may be referred to as ECC data. The ECC encoder may include a Reed-Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity check (LDPC) encoder, or any combination thereof. The ECC decoder may be configured to decode data read from the memory to detect and correct any bit errors that may be present in the data, up to the error correction capability of the ECC scheme. The ECC decoder may perform BCH decoding or LDPC decoding. The ECC decoder may be a BCH decoder, a low-power (LP) LDPC decoder, or a min-sum (MS) LDPC decoder. The ECC decoder may use any linear block ECC, for example, an algebraic code, a concatenated code, a product code, etc.

[0075] In some implementations, data storage system 110 includes RAID circuitry (or RAID circuitry) configured to protect data using RAID techniques. The RAID circuitry can distribute data across different disk drives within data storage device 130 or among multiple data storage devices 130. The RAID circuitry can be configured to provide additional phase error protection in the absence of read optimization and ECC protection within data storage system 110.

[0076] 1B is a schematic diagram of an example of a first data storage device 150 that includes both a weaker ECC decoder and a stronger ECC decoder. The first data storage device 150 may be an SSD, HDD, or NAND flash module.

[0077] The first data storage device 150 may be implemented as the data storage device 130 of FIG. 1A. The first data storage device 150 may include one or more memories 152 and a memory controller 151. Each of the one or more memories 152 may include one or more memory chips 153, such as NAND flash memory chips. The memory controller 151 may include one or more first ECC decoders 154 (e.g., weaker ECC decoders) and one or more second ECC decoders 156 (e.g., stronger ECC decoders). The second ECC decoders may have stronger ECC capabilities than the first ECC decoders. If the one or more first ECC decoders 154 fail to decode data read from the one or more memories 152, the memory controller 151 may control the one or more second ECC decoders 156 within the first data storage device 150 to decode the read data.

[0078] 1C is a schematic diagram of an example of a second data storage device 160 that includes only a weaker ECC decoder. The second data storage device 160 may be an SSD, HDD, or NAND flash module. The second data storage device 160 may be implemented as the data storage device 130 of FIG. 1A.

[0079] Similar to the first data storage device 150 of FIG. 1B, the second data storage device 160 may include a memory controller 161 and one or more memories 152. Unlike the memory controller 151 of FIG. 1B, the memory controller 161 may include only one or more first ECC decoders 154 (e.g., weaker ECC decoders) without any other ECC decoders, such as the second ECC decoder 156. As described in further detail in FIGS. 2 through 5, if the one or more first ECC decoders 154 are unable to decode data read from the one or more memories 152, the memory controller 161 may transmit the read data to an external device that includes a stronger ECC decoder (e.g., the second ECC decoder 156). The external device is external to the second data storage device 160.

[0080] FIG. 1D is a schematic diagram of an example of an external device 170 that includes only a stronger ECC decoder. The external device 170 may be considered a guaranteed-reliability device or an accelerator. The external device 170 may include only a stronger ECC decoder for decoding read data. The external device 170 may include a controller configured to control the stronger ECC decoder. The stronger ECC decoder may be a second ECC decoder 156, which may be the same as the second ECC decoder 156 of FIG. 1B. The stronger ECC decoder has stronger ECC capabilities than an internal (or local) ECC decoder, for example, the first ECC decoder 154 in the data storage device 150 of FIG. 1B or the data storage device 160 of FIG. 1C. The external device 170 may be implemented by a field-programmable gate array (FPGA) device or any processing unit, for example, a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), or a full SSD.

[0081] In some implementations, external device 170 may be external to data storage devices 130 (e.g., second data storage device 160 of FIG. 1C ) and system controller 112, as described in further detail, for example, in FIG. 2. In some implementations, external device 170 may be one of data storage devices 130 or may be included in one of data storage devices 130 (e.g., first data storage device 150 of FIG. 1B ), as described in further detail, for example, in FIG. 3. In some implementations, external device 170 may be included within system controller 112, as described in further detail, for example, in FIG. 4.

[0082] 1A, data storage system 110 may include one or more accessory devices 140, which may be coupled to data storage device 130 and system controller 112 via bus 115. In some implementations, one or more accessory devices 140 include one or more external devices 170 of FIG. 1D, which may each include one or more stronger ECC decoders (e.g., second ECC decoder 156 of FIG. 1B or FIG. 1D). If data storage device 130 (e.g., data storage device 160 of FIG. 1C) is unable to decode the read data using an internal ECC decoder within data storage system 110 (e.g., first ECC decoder 154 of FIG. 1C), data storage device 130 may transmit the read data to one or more accessory devices 140 that can decode the read data using the one or more stronger ECC decoders.

[0083] 2 is a schematic diagram of an example of a data storage system 200 including one or more external devices 220 having a stronger ECC decoder 222 for a data storage device 210 having only a weaker ECC decoder 214. Data storage system 200 may be implemented as data storage system 110 of FIG. 1A. Data storage system 200 includes a system controller 202 (e.g., system controller 112 of FIG. 1A) in communication with data storage device 210 over a bus 204 (e.g., communication bus 115 of FIG. 1A). Data storage device 210 and one or more external devices 220 can also communicate with each other over bus 204.

[0084] Each of the data storage devices 210 may be the data storage device 160 of FIG. 1C that includes only one or more weaker ECC decoders 214 (e.g., the first ECC decoder 154 of FIG. 1B or 1C). Each of the one or more external devices 220 may be the external device 170 of FIG. 1D and may include only one or more stronger ECC decoders 222 (e.g., the second ECC decoder 156 of FIG. 1B or 1D). If the one or more weaker ECC decoders 214 are unable to decode data read from the one or more memories 212, the data storage device 210 may transmit the read data to the one or more external devices 220 for decoding the read data up to the ECC capabilities using the one or more stronger ECC decoders 222.

[0085] 1B , data storage system 200 includes data storage devices 210 that have lower cost and lower power consumption due to having only weaker ECC decoders 214 and one or more external devices 220 with stronger ECC decoders 222. Weaker ECC decoder 214 is configured to process most read requests in data storage device 210 with low power consumption, and one or more external devices 220 are configured to ensure the reliability of the entire data storage system 200 through stronger ECC decoders 222. The number of stronger ECC decoders 222 and / or the number of external devices 220 may be scalable to improve end-of-life (EOL) performance of data storage system 200.

[0086] 3 is a schematic diagram of another example of a data storage system 300 including a data storage device having a stronger ECC decoder for a data storage device having only a weaker ECC decoder. Data storage system 300 may be implemented as data storage system 110 of FIG. 1A. Data storage system 300 includes a system controller 302 (e.g., system controller 112 of FIG. 1A) in communication with a first data storage device 310 and a second data storage device 320 over a bus 304 (e.g., communication bus 115 of FIG. 1A). First data storage device 310 and second data storage device 320 can also communicate with each other over bus 304.

[0087] Each of the second data storage devices 320 may be the first data storage device 150 of FIG. 1B and may include both a weaker ECC decoder 324 (e.g., the first ECC decoder 154 of FIG. 1B or 1C) and a stronger ECC decoder 326 (e.g., the second ECC decoder 156 of FIG. 1B or 1D). If the weaker ECC decoder 324 is unable to decode data read from one or more memories 322 (e.g., one or more memories 152 of FIG. 1B or 1C), the stronger ECC decoder 326 in the second data storage device 320 can decode the read data within the second data storage device 320.

[0088] Each of the first data storage devices 310 may be the data storage device 160 of FIG. 1C that includes only one or more weaker ECC decoders 314 (e.g., the first ECC decoder 154 of FIG. 1B or 1C). If the weaker ECC decoder 314 is unable to decode data read from one or more memories 312 (e.g., one or more memories 152 of FIG. 1B or 1C) in the first data storage device 310, the first data storage device 310 may be configured to transmit the read data to one or more second data storage devices 320 for decoding using a stronger ECC decoder 326 in the one or more second data storage devices 320.

[0089] The data storage system 300 may include a protocol between the one or more first data storage devices 310 and the one or more second data storage devices 320 to enable a stronger ECC decoder 326 in the one or more second data storage devices 320 to assist in decoding failed data in the one or more first data storage devices 310. For example, each of the one or more first data storage devices 310 is configured, in response to determining that the weaker ECC decoder 314 in the first data storage device 310 is unable to correct first data read from the corresponding first memory 312, to transmit the read first data to one of the one or more second data storage devices 320 for decoding. Each of the one or more second data storage devices 320 is configured, in response to receiving the corresponding read data from one of the one or more first data storage devices 310, to decode the corresponding read data using the one or more stronger ECC decoders 326 in the second data storage device 320.

[0090] In some implementations, the system controller 302 may be configured to store a first type of data (e.g., hot data) in one or more first data storage devices 310 and a second type of data (e.g., cold data) in one or more second data storage devices 320. The first type of data may be data that is read more frequently than the second type of data. In that way, the data storage system 300 may reduce total cost of ownership (TCO) because the first data storage devices 310 are much less expensive than the second data storage devices 320 and may be replaced more frequently than the second data storage devices 320.

[0091] 4 is a schematic diagram of another example of a data storage system 400 including a system controller 402 that includes one or more external devices 420 with stronger ECC decoders 422 for data storage devices 410. Data storage system 400 may be implemented as data storage system 110 of FIG. 1A.

[0092] Similar to data storage system 200 of FIG. 2, each of data storage devices 410 may be data storage device 160 of FIG. 1C, data storage device 210 of FIG. 2, or first data storage device 310 of FIG. 3. Data storage device 410 may include only one or more weaker ECC decoders 414 (e.g., first ECC decoder 154 of FIG. 1B or FIG. 1C, 214 of FIG. 2, or 314 of FIG. 3). Each of one or more external devices 420 may be external device 170 of FIG. 1D or 220 of FIG. 2 and may include only one or more stronger ECC decoders 422 (e.g., second ECC decoder 156 of FIG. 1B or FIG. 1D, 222 of FIG. 2, 326 of FIG. 3). If the weaker ECC decoder 414 in the data storage device 410 is unable to decode data read from one or more memories 412 (e.g., memory 152 in FIG. 1B or FIG. 1C, 212 in FIG. 2, or 312 or 322 in FIG. 3), the data storage device 410 can transmit the read data to one or more external devices 420 for decoding the read data up to the ECC capabilities using one or more stronger ECC decoders 422.

[0093] 2, in which one or more external devices 220 are external to the system controller 202, in the data storage system 400, one or more external devices 420 may be included within the system controller 402. The number of one or more external devices 420 may be increased to improve the overall read performance of the data storage system 400.

[0094] FIG. 5 is a flowchart of an example process 500 for managing error correction in a data storage system. The data storage system may be data storage system 110 of FIG. 1A , data storage system 200 of FIG. 2 , data storage system 300 of FIG. 3 , or data storage system 400 of FIG. 4 . The data storage system may include a system controller and one or more data storage devices. The system controller may be, for example, system controller 112 of FIG. 1A , system controller 202 of FIG. 2 , system controller 302 of FIG. 3 , or system controller 402 of FIG. 4 . The data storage device may be, for example, data storage device 130 of FIG. 1A , data storage device 150 of FIG. 1B , data storage device 160 of FIG. 1C , data storage device 210 of FIG. 2 , first data storage device 310 of FIG. 3 , second data storage device 320 of FIG. 3 , or data storage device 410 of FIG. 4 .

[0095] In step 502, the system controller receives a read request from a host device (e.g., host device 120 of FIG. 1A). The read request may be a read command to read data from one or more data storage devices in the data storage system. The system controller may transmit the read command to the one or more data storage devices.

[0096] In stage 504, in response to the data storage device receiving a read command from the system controller, a memory controller (e.g., memory controller 161 of FIG. 1C) in the data storage device reads data from at least one memory (e.g., memory 152 of FIG. 1C, memory 212 of FIG. 2, memory 312 of FIG. 3, or memory 412 of FIG. 4) in the data storage device. The memory controller may include at least one first ECC decoder, which may be a weaker ECC decoder (e.g., ECC decoder 154 of FIG. 1B or FIG. 1C, ECC decoder 214 of FIG. 2, ECC decoder 314 of FIG. 3, or ECC decoder 414 of FIG. 1C).

[0097] The memory controller performs weaker ECC decoding in the data storage device using at least one first ECC decoder in step 506 and determines whether the read data passes the first ECC test in step 508. In some implementations, the memory controller performs an ECC decoding operation on the read data using the at least one first ECC decoder. In some implementations, the memory controller includes a first ECC encoder configured to encode data to generate first ECC data (e.g., ECC parity bits), and the memory controller can store data with the first ECC data in the at least one memory and read data with the first ECC data from the at least one memory. The at least one first ECC decoder can decode the data read from the at least one memory using the first ECC data.

[0098] The memory controller can determine whether the read data passes the first ECC test by determining whether the number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold. If the number of error bits is less than the predetermined threshold, the memory controller can determine that the read data passes the first ECC test. If the number of error bits is equal to or greater than the predetermined threshold, the memory controller determines that the read data fails to pass the first ECC test.

[0099] If the memory controller determines that the read data passes the first ECC test, then in step 510 the memory controller returns the corrected read data to the system controller, which transmits the corrected read data to the host device.

[0100] If the memory controller determines that the read data fails the first ECC test, then in step 512, the memory controller determines whether the number of times the read data fails the first ECC test is less than a predetermined threshold, for example, by comparing a counter of the number of times to a predetermined number. If the number is less than the predetermined threshold, then in step 514, the memory controller changes one or more read parameters to re-read the data from the at least one memory or performs soft decoding on the data (in step 504). The counter may be incremented by one accordingly.

[0101] If the number of times reaches a predetermined threshold, the memory controller transmits the read data to an external device including at least one second ECC decoder for stronger ECC decoding. The external device may be, for example, external device 170 of FIG. 1D , external device 220 of FIG. 2 , second data storage device 320 of FIG. 3 , or external device 420 of FIG. 4 within the system controller. The at least one second ECC decoder may be, for example, second ECC decoder 156 of FIG. 1B , second ECC decoder 156 of FIG. 1D , stronger ECC decoder 222 of FIG. 2 , stronger ECC decoder 326 of FIG. 3 , or stronger ECC decoder 422 of FIG. 4 . The at least one second ECC decoder in the external device may have stronger ECC capabilities than the at least one first ECC decoder in the data storage device.

[0102] In some implementations, additionally or alternatively to step 512, in response to determining that the read data fails the first ECC test and before transmitting the read data to the at least one second ECC decoder, the memory controller may, based on the results of the first ECC test, perform one of the following: i) modify one or more parameters for reading the data from the at least one memory or perform soft decoding on the data and perform the first ECC test again using the at least one first ECC decoder; or ii) transmit the read data to an external device including at least one second ECC decoder for decoding the read data. For example, if the results of the first ECC test indicate that the error bits in the read data are slightly above the capability of the first ECC decoder, the memory controller may decide to proceed with option i). If the results of the first ECC test indicate that the error bits are far above the capability of the first ECC decoder, the memory controller may decide to proceed with option ii).

[0103] The external device performs stronger ECC decoding on the read data using at least one second ECC decoder in step 518 and determines whether the read data passes the second ECC test in step 520. In some implementations, the external device performs ECC decoding operations on the read data using at least one second ECC decoder. As described in further detail in FIG. 6A, 6B, or 6C, the at least one second ECC decoder can perform ECC decoding operations based on first ECC data generated by at least one first ECC decoder (e.g., shown in FIG. 6A), or second ECC data generated based on data read using a second ECC encoder in the external device or in a data storage device (e.g., shown in FIG. 6B), or second ECC data generated based on multiple data portions of data read from multiple data storage devices using a second ECC decoder in the external device (e.g., shown in FIG. 6C).

[0104] The external device can determine whether the read data passes the second ECC test by determining whether the number of error bits in the read data after the ECC decoding operation is smaller than a predetermined threshold. If the number of error bits is smaller than the predetermined threshold, the external device can determine that the read data passes the second ECC test. If the number of error bits is equal to or larger than the predetermined threshold, the external device determines that the read data fails to pass the second ECC test.

[0105] If the external device determines that the read data passes the second ECC test, the external device returns the corrected read data to the system controller, which transmits the corrected read data to the host device, in step 510. In some implementations, the external device transmits the corrected read data back to the data storage device.

[0106] If the external device determines that the read data fails the second ECC test, then in step 522, the external device determines whether the number of times the read data fails the second ECC test is less than a predetermined threshold, for example, by comparing a counter of the number of times to a predetermined number. If the number is less than the predetermined threshold, the external device can transmit a notification to the memory controller to either i) change one or more parameters to re-read the data from the at least one memory, or ii) perform soft decoding on the data, as shown in step 514. The counter can be incremented by one.

[0107] If the number of times reaches a predetermined threshold, the external device can trigger 524 a redundant array of independent disks (RAID) circuit to perform error correction on the read data for data recovery. For example, the external device can send a message to the system controller instructing it to trigger the RAID circuit, and the system controller can trigger the RAID circuit in response. In some implementations, the RAID circuit can be included in a memory controller and configured to perform error correction on the read data in the data storage device. In some implementations, the RAID circuit can be included in a system controller and configured to perform error correction on the read data in one or more data storage devices. The RAID circuit can be in an accessory device (e.g., accessory device 140 of FIG. 1A) that is external to the data storage device and the system controller.

[0108] In some implementations, additionally or alternatively to step 522, in response to determining that the read data fails the second ECC test and before triggering the RAID circuitry, the external device may, based on the results of the second ECC test, either: i) modify one or more parameters for reading data from the at least one memory or perform soft decoding on the data and re-run at least one of the first ECC test with the at least one first ECC decoder or the second ECC test with the at least one second ECC decoder; or ii) trigger the RAID circuitry to perform error correction on the read data. For example, if the results of the second ECC test indicate that the number of error bits in the read data is slightly above the capability of the second ECC decoder, the external device may decide to proceed with option i). If the results of the second ECC test indicate that the number of error bits in the read data is much higher than the capability of the second ECC decoder, the external device may decide to proceed with option ii).

[0109] In some implementations, the system controller is configured to generate an alert message to discard the data storage device based on at least one of the results of the first ECC test using the at least one first ECC decoder or the results of the second ECC test using the at least one second ECC decoder. For example, the data storage device may be designed to be inexpensive and discardable if the error bits are difficult to correct by the first ECC decoder and / or the second ECC decoder.

[0110] 6A to 6C show different examples of data encoding and decoding in a data storage system implemented in the present disclosure. The data storage system may be data storage system 110 of FIG. 1A, data storage system 200 of FIG. 2, data storage system 300 of FIG. 3, or data storage system 400 of FIG. 4. The data storage system may include a system controller and one or more data storage devices. The system controller may be, for example, system controller 112 of FIG. 1A, system controller 202 of FIG. 2, system controller 302 of FIG. 3, or system controller 402 of FIG. 4. The data storage device may be, for example, data storage device 130 of FIG. 1A, data storage device 150 of FIG. 1B, data storage device 160 of FIG. 1C, data storage device 210 of FIG. 2, first data storage device 310 of FIG. 3, second data storage device 320 of FIG. 3, or data storage device 410 of FIG. 4.

[0111] 6A is a schematic diagram of an example process 600 for encoding and decoding data 601 in a data storage system, for example, using the same ECC data for a weaker ECC decoder and a stronger ECC decoder. The data storage device may include a memory controller and memory 604. The memory controller may be, for example, memory controller 161 of FIG. 1C. The memory controller may include an ECC encoder 602 and a weaker ECC decoder 606. The weaker ECC decoder 606 may be, for example, ECC decoder 154 of FIG. 1B or 1C, ECC decoder 214 of FIG. 2, ECC decoder 314 of FIG. 3, or ECC decoder 414 of FIG. 1C.

[0112] An ECC encoder 602 can encode data 601 to generate ECC data 603 (e.g., ECC parity bits). A memory controller can write the data 601 along with the ECC data 603 to memory 604. The data 601 along with the ECC data 603 can be read from memory 604, for example, in response to a read command from a system controller. The read data 605 can have error bits.

[0113] As described above, the weaker ECC decoder 606 in the data storage device can first decode the read data 605 based on the ECC data 603. If the weaker ECC decoder 606 is unable to decode the read data 605, the memory controller can transmit the read data 605 and the ECC data 603 to an external device including a stronger ECC decoder 608 having stronger ECC capabilities than the weaker ECC decoder 606. The external device can be, for example, the external device 170 in FIG. 1D , the external device 220 in FIG. 2 , the second data storage device 320 in FIG. 3 , or the external device 420 in FIG. 4 within the system controller. The stronger ECC decoder 608 can be, for example, the second ECC decoder 156 in FIG. 1B , the second ECC decoder 156 in FIG. 1D , the stronger ECC decoder 222 in FIG. 2 , the stronger ECC decoder 326 in FIG. 3 , or the stronger ECC decoder 422 in FIG. 4 . A stronger ECC decoder 608 can decode the read data 605 based on the ECC data 603 to generate corrected read data 609 .

[0114] In some implementations, a bit-flip based LDPC decoder (as a low-power decoding mode) and a min-sum LDPC decoder (as a stronger decoding mode) are implemented as a pair of a weaker ECC decoder 606 and a stronger ECC decoder 608. As shown in Figure 6A, only one ECC encoder 602 is used for both modes, and ECC data 603 (e.g., ECC parity bits) is shared for both the weaker ECC decoder 606 and the stronger ECC decoder 608.

[0115] 6B is a schematic diagram of another exemplary process 630 for encoding and decoding data in a data storage system. Unlike process 610 in FIG. 6A, process 630 involves two different ECC data. In some implementations, a memory controller in a data storage device may include an internal ECC encoder 634 and an internal ECC decoder 638. An external device may include an external ECC encoder 632 and an external ECC decoder 640. In some implementations, the memory controller includes the internal ECC encoder 634, the external ECC encoder 632, and the internal ECC decoder 638, while the external device includes only the external ECC decoder 640. The internal ECC encoder 634 may correspond to the internal ECC decoder 638, while the external ECC encoder 632 may correspond to the external ECC decoder 640. The inner ECC decoder 638 is configured to decode data using the ECC data generated by the inner ECC encoder 634, and the outer ECC decoder 640 is configured to decode data using the ECC data generated by the outer ECC encoder 632.

[0116] The external device may be, for example, external device 170 of FIG. 1D , external device 220 of FIG. 2 , second data storage device 320 of FIG. 3 , or external device 420 of FIG. 4 within a system controller. External ECC decoder 640 may have higher ECC capabilities than internal ECC decoder 638. Internal ECC decoder 638 may be a weaker decoder, such as ECC decoder 154 of FIG. 1B or 1C , ECC decoder 214 of FIG. 2 , ECC decoder 314 of FIG. 3 , or ECC decoder 414 of FIG. 1C . External ECC decoder 640 may be a stronger decoder, such as second ECC decoder 156 of FIG. 1B , second ECC decoder 156 of FIG. 1D , stronger ECC decoder 222 of FIG. 2 , stronger ECC decoder 326 of FIG. 3 , or stronger ECC decoder 422 of FIG. 4 .

[0117] Data 631 to be stored in memory 636 of the data storage device may first be encoded by external ECC encoder 632 to generate external ECC data 633 (e.g., external ECC parity bits). Then, the external device may transmit the data 631 along with the ECC data 633 to the data storage device. An internal ECC encoder 634 may encode the data 631 to generate internal ECC data 635 (e.g., internal ECC parity bits). A memory controller may store the data 631 along with the external ECC data 633 and the internal ECC data 635 in memory 636 of the data storage device. The memory controller may store the internal ECC data 635 and the external ECC data in memory 636 as a concatenated code of the data 631. The internal ECC decoder 638 may cover most read requests, and the stronger external ECC decoder 640 may be executed rarely, at the cost of longer latency and higher power consumption.

[0118] The memory controller may read data 631, along with external ECC data 633 and internal ECC data 635, from memory 636 to obtain read data 637, which may include error bits. The memory controller may decode the read data 637 using an internal ECC decoder 638, for example, as described in FIG. 5 . If the internal ECC decoder 638 successfully decodes the read data 637 using the internal ECC data 635, the memory controller generates corrected read data 639. If the internal ECC decoder 638 fails to decode the read data 637 using the internal ECC data 635, the memory controller may transmit the read data 637 and the external ECC data 633 to an external device. An external ECC decoder 640 in the external device may then decode the read data 637 based on the external ECC data 633 to generate corrected read data 639.

[0119] 6C is a schematic diagram of another exemplary process 650 for encoding data and decoding data in a data storage system. Unlike process 630 in FIG. 6B, process 650 involves storing multiple data portions of data on multiple data storage devices in the data storage system.

[0120] In some implementations, each of the multiple data storage devices includes a memory controller (e.g., memory controller 161 of FIG. 1C ) and corresponding memory 656. The memory controller in the data storage device may include an internal ECC encoder 654 and an internal ECC decoder 658. The external device may include an external ECC encoder 652 and an external ECC decoder 660. The internal ECC encoder 654 may correspond to the internal ECC decoder 658, while the external ECC encoder 652 may correspond to the external ECC decoder 660. The internal ECC decoder 658 is configured to decode data using ECC data generated by the internal ECC encoder 654, and the external ECC decoder 660 is configured to decode data using the ECC data generated by the external ECC encoder 652.

[0121] The external device may be, for example, external device 170 of FIG. 1D , external device 220 of FIG. 2 , second data storage device 320 of FIG. 3 , or external device 420 of FIG. 4 within a system controller. External ECC decoder 660 may have stronger ECC capabilities than internal ECC decoder 658. Internal ECC decoder 658 may be a weaker decoder, such as ECC decoder 154 of FIG. 1B or 1C , ECC decoder 214 of FIG. 2 , ECC decoder 314 of FIG. 3 , or ECC decoder 414 of FIG. 1C . External ECC decoder 660 may be a stronger ECC decoder, such as second ECC decoder 156 of FIG. 1B , second ECC decoder 156 of FIG. 1D , stronger ECC decoder 222 of FIG. 2 , stronger ECC decoder 326 of FIG. 3 , or stronger ECC decoder 422 of FIG. 4 .

[0122] Multiple data portions 651 of data to be stored in multiple data storage devices may first be encoded by an external ECC encoder 652 in the external device to generate external ECC data 653 (e.g., external ECC parity bits) for the multiple data portions 651 of data. Each data portion 651 and external ECC data 653 may then be transmitted to a corresponding one of the multiple data storage devices, for example, by the external device or by a system controller. An internal ECC encoder 654 in the corresponding data storage device may encode the data portion 651 to generate internal ECC data 655 (e.g., internal ECC parity bits) for the data portion 651. A memory controller in the corresponding data storage device may store the data portion 651 of data, along with the internal ECC data 655 and external ECC data 653, in memory 656 of the corresponding data storage device.

[0123] In response to receiving a read request from a host device (e.g., host device 120 of FIG. 1A ), the system controller can transmit a read command to each of the multiple data storage devices. For each of the multiple data storage devices, the memory controller can read a corresponding data portion 651 of data along with corresponding internal ECC data 655 and external ECC data 653 from memory 656. An internal ECC decoder 658 first decodes the corresponding read data portion 657 based on the corresponding internal ECC data 655. If the internal ECC decoder 655 successfully decodes the corresponding read data portion 657 using the internal ECC data 655, the memory controller generates a corrected read data portion 659. If the internal ECC decoder 658 fails to decode the corresponding read data portion 657 using the internal ECC data 655, the memory controller can transmit the corresponding read data portion 657 and the external ECC data 653 to the external device. An external ECC decoder 660 in the external device may then decode the read corresponding data portion 657 based on the external ECC data 653 to generate a corrected read corresponding data portion 659 .

[0124] In the process 650, a product code may be implemented using a pair of weaker and stronger ECC encoders and decoders. Two types of ECC encoders 652, 654 generate two types of party bits, e.g., internal ECC data for corresponding data portions and external ECC data for multiple data portions or the entire data. Both encoding and decoding of the external (stronger) ECC are performed by an external device. Both encoding and decoding of the internal (weaker or low-power) ECC are performed internally within a single data storage device. The internal ECC decoder can cover most read requests, and the stronger external ECC decoder may be rarely executed, at the cost of longer latency and higher power consumption.

[0125] The disclosed examples and other examples may be implemented as one or more computer program products, e.g., one or more modules of computer program instructions encoded on a computer-readable medium for execution by or to control the operation of a data processing apparatus. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or one or more combinations thereof. The term "data processing apparatus" encompasses all apparatuses, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, an apparatus may include code that creates an execution environment for the computer program, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations of these.

[0126] A system may encompass all apparatus, devices, and machines that process data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, a system may include code that creates an execution environment for the computer program, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these.

[0127] A computer program (also known as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any form including a stand-alone program or modules, components, subroutines, or other units suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated files (e.g., files storing one or more modules, subprograms, or code portions). A computer program can be deployed for execution on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0128] The processes and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The processes and logic flows may also be performed by, and apparatus may be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0129] Processors suitable for executing a computer program include, by way of example, both general-purpose and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor receives instructions and data from a read-only memory or a random-access memory, or both. The essential elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer may include one or more mass storage devices, such as magnetic, magneto-optical, or optical disks, for storing data, or may be operatively coupled to receive data from or transfer data to them, or both. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data may include all types of non-volatile memory, media, and memory devices, including, by way of example, semiconductor memory devices, such as EPROMs, EEPROMs, flash memory devices, and magnetic disks. The processor and memory may be supplemented by, or incorporated in, special-purpose logic circuitry.

[0130] While the specification may describe many specific examples, these should not be construed as limitations on the scope of the claimed invention or what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Also, while features may be described above as operating in a particular combination and even initially claimed as such, in some cases, one or more features from a claimed combination can be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of a subcombination. Similarly, although the figures may show operations in a particular order, this should not be understood as requiring such operations to be performed in the particular order or sequential order shown, or to perform all of the shown operations, to achieve desired results.

[0131] Only a few examples and implementations are disclosed. Variations, modifications, and enhancements to the described examples and implementations and other implementations may be made based on what is disclosed.

Claims

1. one or more data storage devices; and a system controller coupled to the one or more data storage devices; Equipped with the one or more data storage devices include a data storage device including at least one memory and a memory controller coupled to the at least one memory, the memory controller including at least one first error correction code (ECC) decoder; Here, the memory controller reading data from said at least one memory; performing a first ECC test on the read data using the at least one first ECC decoder; and In response to determining that the read data fails the first ECC test, transmitting the read data to an external device including at least one second ECC decoder for decoding the read data. and wherein the external device is external to the data storage device, and the at least one second ECC decoder has stronger ECC capabilities than the at least one first ECC decoder. Data storage system.

2. The memory controller in response to determining that the read data fails the first ECC test and prior to transmitting the read data to the external device, determining whether the number of times the read data fails the first ECC test is less than a predetermined threshold; If the number of times is less than the predetermined threshold, modifying one or more read parameters to re-read the data from the at least one memory or performing soft decoding on the data; and transmitting the read data to the external device including the at least one second ECC decoder for decoding the read data if the number of times has reached the predetermined threshold. configured to: The data storage system of claim 1 .

3. The memory controller in response to determining that the read data fails the first ECC test and prior to transmitting the read data to the at least one second ECC decoder; and Based on the results of the first ECC test, i) changing one or more parameters for reading the data from the at least one memory or performing soft decoding on the data and performing the first ECC test again using the at least one first ECC decoder; or ii) transmitting the read data to the external device including the at least one second ECC decoder for decoding the read data. one of configured to run The data storage system of claim 1 .

4. The external device performing a second ECC test on the read data using the at least one second ECC decoder; and transmitting the corrected read data to the system controller in response to determining that the read data passes the second ECC test. configured to: The data storage system of claim 1 .

5. The external device responsive to determining that the read data fails the second ECC test, determining whether the number of times the read data fails the second ECC test is less than a predetermined threshold; If the number is less than the predetermined threshold, transmitting a notification to the memory controller to: i) modify one or more parameters for reading the data from the at least one memory; or ii) perform soft decoding on the data; and triggering a RAID (Redundant Array of Independent Disks) circuit to perform error correction on the read data if the number of times reaches the predetermined threshold. configured to: The data storage system of claim 4 .

6. The external device in response to determining that the read data fails the second ECC test and prior to triggering a RAID circuit; and Based on the results of the second ECC test, i) changing one or more parameters for reading the data from the at least one memory or performing soft decoding on the data, and re-running at least one of the first ECC test with the at least one first ECC decoder or the second ECC test with the at least one second ECC decoder; or ii) triggering the RAID circuitry to perform error correction on the read data. one of configured to run The data storage system of claim 4 .

7. The memory controller performing an ECC decoding operation on the read data using the at least one first ECC decoder; determining whether a number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold; determining that the read data passes the first ECC test if the number of error bits is less than the predetermined threshold; and determining that the read data fails the first ECC test if the number of error bits is equal to or greater than the predetermined threshold; configured to: The data storage system of claim 1 .

8. the one or more data storage devices; one or more first data storage devices, each including only one or more first ECC decoders; and one or more second data storage devices each including one or more first ECC decoders and one or more second ECC decoders having The data storage system of claim 1 .

9. The system controller storing data of a first type in said one or more first data storage devices; and Storing data of a second type on said one or more second data storage devices. and wherein the first type of data is configured to be read more frequently than the second type of data.

9. The data storage system of claim 8.

10. the one or more first data storage devices and the one or more second data storage devices are configured to operate based on a protocol; each of the one or more first data storage devices is configured to transmit the read first data to one of the one or more second data storage devices in response to determining that the one or more first ECC decoders in the first data storage device are unable to correct the first data read from a corresponding first memory; each of the one or more second data storage devices is configured, in response to receiving corresponding read data from one of the one or more first data storage devices, to decode the corresponding read data using the one or more second ECC decoders in the second data storage device; 9. The data storage system of claim 8.

11. The data storage system of claim 1 , wherein the external device is included within the system controller.

12. the memory controller includes a first ECC encoder configured to encode the data to generate first ECC data, and the memory controller is configured to store the data along with the first ECC data in the at least one memory; the at least one first ECC decoder is configured to decode the read data based on the first ECC data, and the at least one second ECC decoder is configured to decode the read data based on the first ECC data. The data storage system of claim 1 .

13. the memory controller includes a first ECC encoder configured to encode the data to generate first ECC data, and the external device includes a second ECC encoder configured to encode the data to generate second ECC data; The memory controller storing the data along with the first ECC data and the second ECC data in the at least one memory; reading the data along with the first ECC data and the second ECC data from the at least one memory; and transmitting the read data and the second ECC data to the external device including at least one second ECC decoder in response to determining that the read data fails the first ECC test. and the at least one first ECC decoder is configured to decode the read data based on the first ECC data, and the at least one second ECC decoder is configured to decode the read data based on the second ECC data received from the memory controller. The data storage system of claim 1 .

14. the system controller is configured to transmit a plurality of portions of a particular data to a plurality of data storage devices of the one or more data storage devices, respectively; each of the plurality of data storage devices includes a first ECC encoder and one or more first ECC decoders, the first ECC encoders configured to encode corresponding portions of the particular data to generate corresponding first ECC data; the external device includes a second ECC encoder configured to encode the portions of the particular data to generate second ECC data; each of the plurality of data storage devices includes a memory controller configured to store the corresponding portion of the particular data along with the corresponding first ECC data and the second ECC data in a corresponding memory; for each of the plurality of data storage devices, the one or more first ECC decoders are configured to decode the corresponding portion of the particular data from the corresponding memory based on the corresponding first ECC data; the at least one second ECC decoder in the external device is configured to, in response to receiving the portion of the particular data and the second ECC data from one of the plurality of data storage devices, decode the portion of the particular data based on the second ECC data. The data storage system of claim 1 .

15. at least one memory; and a memory controller coupled to the at least one memory; 1. A data storage device comprising: the memory controller having at least one first error correction code (ECC) decoder; Here, the memory controller reading data from said at least one memory; performing a first error correction code (ECC) test on the read data using the at least one first ECC decoder; and In response to determining that the read data fails the first ECC test, transmitting the read data to an external device including at least one second ECC decoder for decoding the read data. and wherein the external device is external to the data storage device, and the at least one second ECC decoder has stronger ECC capabilities than the at least one first ECC decoder. Data storage device.

16. The memory controller in response to determining that the read data fails the first ECC test and prior to transmitting the read data to the external device, determining whether the number of times the read data fails the first ECC test is less than a predetermined threshold; If the number of times is less than the predetermined threshold, modifying one or more read parameters to re-read the data from the at least one memory or performing soft decoding on the data; and transmitting the read data to the external device including the at least one second ECC decoder for decoding the read data if the number of times has reached the predetermined threshold. configured to:

16. The data storage device of claim 15.

17. at least one first error correction code (ECC) decoder externally coupled to at least one data storage device including at least one memory configured to store data; A device comprising: the at least one data storage device includes at least one second ECC decoder, the at least one first ECC decoder having stronger ECC capabilities than the at least one second ECC decoder; wherein the at least one first ECC decoder: responsive to receiving read data from the at least one data storage device, performing an ECC test on the read data with the at least one first ECC decoder; and generating corrected read data for the at least one data storage device in response to determining that the read data passes the ECC test; configured to: device.

18. the at least one second ECC decoder configured to decode the read data based on ECC data associated with the data stored in the at least one memory; the at least one first ECC decoder is configured to decode the read data based on the ECC data; 18. The device of claim 17.

19. a first ECC encoder configured to encode the data to generate first ECC data and transmit the first ECC data to the at least one data storage device; the at least one data storage device includes a second ECC encoder configured to encode the data to generate second ECC data; wherein the at least one data storage device is: storing the data along with the first ECC data and the second ECC data in the at least one memory; reading the data along with the first ECC data and the second ECC data from the at least one memory; and transmitting the read data and the first ECC data to the at least one first ECC decoder in response to determining that the at least one second ECC decoder is unable to decode the read data based on the second ECC data. and The at least one first ECC decoder responsive to receiving the read data and the first ECC data from the at least one data storage device, decoding the read data based on the first ECC data. configured to:

18. The device of claim 17.

20. the data includes a plurality of portions, and the at least one data storage device includes a plurality of data storage devices configured to store the plurality of portions respectively; the device further comprising a first ECC encoder configured to encode the plurality of portions of the data to generate first ECC data and transmit the first ECC data to each of the plurality of data storage devices; each of the plurality of data storage devices includes a second ECC encoder configured to encode a corresponding portion of the data to generate corresponding second ECC data; each of the plurality of data storage devices configured to store the corresponding portion of the data along with the corresponding second ECC data and the first ECC data in a corresponding memory; the at least one first ECC decoder is configured to, in response to receiving the portion of the data and the first ECC data from one of the plurality of data storage devices, decode the portion of the data based on the first ECC data.

18. The device of claim 17.

Images