Calibration of signal current in radio frequency signal generators

Abstract

A technique for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system, is provided. The device includes a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured to measure a first current in a first signal path of a radio frequency signal generator and a second current in a second signal path of the radio frequency signal generator during a calibration process. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to compensate for an imbalance between the measured first current and the measured second current.

Description

[Background technology]

[0001] The present disclosure generally relates to techniques for calibrating RF signal generators, such as radio frequency (RF) signal generators and arbitrary waveform generator (AWG) systems. For various applications, RF signal generators have a quadrature architecture in which a baseband signal is upconverted to an RF signal using a single-sideband (SSB) modulation system in which a quadrature baseband signal is used to modulate a quadrature local oscillator (LO) signal. For SSB modulation, generating a high-fidelity RF signal without LO leakage or sideband image spurs (or significantly suppressed spurs) requires precise amplitude and phase balance between in-phase (I) and quadrature-phase (Q) signal components. More specifically, amplitude and phase imbalance between the quadrature I / Q signal components can lead to degraded image rejection performance, which results in the presence of undesired sideband spurs. Furthermore, positive and negative components in the same phase (e.g., I + and I - ) can result in LO leakage spurs. Measuring and calibrating I / Q imbalance is particularly important when the signal paths for the I and Q channels are implemented using single-ended baseband filter structures. Due to device mismatch, single-ended filter elements can exhibit inherent amplitude imbalance that impairs RF performance.

[0002] Conventional techniques for detecting and calibrating amplitude and phase imbalance of I / Q signals in RF signal generators typically utilize on-chip or off-chip calibration equipment configured to perform RF measurements that analyze the RF output signal generated by the RF signal generator. For example, conventional on-chip calibration equipment implements an RF downconversion receiver, which is disposed in a feedback path of a transmitter and configured to extract baseband signal components from the RF output signal. The on-chip calibration equipment compensates for imbalances detected in the extracted baseband signal components. In addition, conventional on-chip and off-chip calibration equipment can be implemented using complex spectrum analyzer systems and circuits. Conventional calibration systems that perform RF measurements are significantly costly in terms of hardware complexity, resource usage, and area overhead required for on-chip implementation. In addition, conventional calibration systems that perform RF measurements consume a significant amount of power that is prohibitive at cryogenic temperatures. Summary of the Invention

[0003] Exemplary embodiments of the present disclosure include techniques for calibrating signal current in an RF signal generator system, such as an AWG system.

[0004] In an exemplary embodiment, a device includes a current measurement circuit and a current imbalance correction circuit, the current measurement circuit configured to measure a first current in a first signal path of a radio frequency signal generator and a second current in a second signal path of the radio frequency signal generator during a calibration process, and the current imbalance correction circuit configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.

[0005] Advantageously, in contrast to conventional calibration techniques that perform RF measurements that analyze an RF output signal generated by an RF signal generator, a calibration technique according to exemplary embodiments of the present disclosure implements a current measurement circuit that measures a signal current (e.g., a DC baseband current) generated in the signal path of the RF signal generator during the calibration process, and such baseband signal current measurements are significantly less costly in terms of hardware complexity and computing resources required for calibration compared to calibration systems that analyze an RF output signal generated by an RF signal generator. In addition, the current measurement circuit can operate at very low power (e.g., on the order of milliwatts or less) and have a relatively small footprint (occupying a small chip area), which is advantageous for on-chip implementation and cryogenic control electronics for quantum computing applications.

[0006] Another advantage is that for quadrature RF signal generator architectures utilizing I / Q signals, all components of the I / Q baseband signal (e.g., I + , I - , Q + , Q - ) is utilized to measure the current measurement. In this regard, the current measurement is insensitive to inherent offsets in the current measurement circuit, such that inaccuracies in the current measurement circuit will not adversely affect the accuracy of the measurement because any inherent offset in the current measurement circuit will be applied to all signal current measurements, thereby effectively canceling out such inherent errors when the difference between the measured currents is determined.

[0007] Another exemplary embodiment includes a system including a radio frequency signal generator and a calibration system. The radio frequency signal generator is configured to convert a baseband signal to a radio frequency signal. The radio frequency signal generator has a first signal path for processing a first signal component of the baseband signal and a second signal path for processing a second signal component of the baseband signal. The calibration system is configured to perform a calibration process to calibrate the radio frequency signal generator. The calibration system includes a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured to measure a first current in the first signal path of the radio frequency signal generator and a second current in the second signal path of the radio frequency signal generator during the calibration process. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to compensate for an imbalance between the measured first current and the measured second current.

[0008] Another exemplary embodiment includes a system comprising a quantum processor, an arbitrary waveform generator system, and a calibration system. The quantum processor includes at least one superconducting qubit. The arbitrary waveform generator system includes at least one arbitrary waveform generator channel configured to convert a baseband signal into radio frequency control pulses that control the at least one superconducting qubit. The at least one arbitrary waveform generator channel includes a first signal path for processing a first signal component of the baseband signal and a second signal path for processing a second signal component of the baseband signal. The calibration system is configured to perform a calibration process to calibrate the at least one arbitrary waveform generator channel. The calibration system includes a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured to measure a first current in the first signal path of the at least one arbitrary waveform generator channel and a second current in the second signal path of the at least one arbitrary waveform generator channel during the calibration process. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the at least one arbitrary waveform generator channel to correct for an imbalance between the measured first current and the measured second current.

[0009] Another exemplary embodiment that may be combined with the preceding paragraph includes a control circuit configured to determine a difference between the measured first current and the measured second current, generate a control signal based on the determined difference between the measured first current and the measured second current, and output the control signal to the current imbalance correction circuit, wherein in response to the control signal, the current imbalance correction circuit is configured to inject a current into at least one of the first signal path and the second signal path of the radio frequency signal generator to compensate for the determined difference between the measured first current and the measured second current.

[0010] In another exemplary embodiment that may be combined with the preceding paragraph, the current measurement circuit includes a current-mode digital-to-analog converter circuit and a current comparator circuit. The current-mode digital-to-analog converter circuit is configured to generate a reference current. The current comparator circuit is configured to receive one of the first current and the second current as an input current to be measured, compare the reference current to the input current, and generate a comparison output signal. The current-mode digital-to-analog converter circuit is configured to one of increase and decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the input current.

[0011] In another exemplary embodiment that may be combined with the preceding paragraph, the current comparator circuit includes a first transistor, a second transistor, a first switch, a second switch, and a voltage comparator. The first transistor has a drain terminal coupled to an input node of the comparator circuit, a source terminal coupled to a power supply node, and a gate terminal coupled to a first node. The first switch is coupled between the input node and the first node. The second switch is coupled between the first node and the power supply node. The second transistor has a gate terminal coupled to the first node, a source terminal coupled to the power supply node, and a drain terminal coupled to a second node. The voltage comparator has a first input terminal coupled to a threshold voltage node and a second input terminal coupled to the second node. An output of the current-mode digital-to-analog converter circuit is coupled to the second node. During the calibration process, the first switch is enabled to configure the first transistor as a diode-connected transistor by coupling the gate terminal and the drain terminal of the first transistor, and the second switch is disabled to allow the input current to flow to the current measurement circuit.

[0012] In another exemplary embodiment that may be combined with the preceding paragraph, the current comparator circuit further includes a low-pass filter circuit configured to enable the current comparator circuit to measure a direct current (DC) offset component of an alternating current (AC) input current, the low-pass filter circuit being one of (i) coupled between the first node and the gate terminal of the second transistor and (ii) coupled to the second input terminal of the voltage comparator.

[0013] Another exemplary embodiment includes a computer program product for executing a calibration process for calibrating a radio frequency signal generator, the computer program product comprising one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media, the program instructions including: program instructions for configuring a current measurement circuit to measure a first current in a first signal path of the radio frequency signal generator and a second current in a second signal path of the radio frequency signal generator during the calibration process; and program instructions for configuring a current imbalance correction circuit to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.

[0014] Another exemplary embodiment includes a method comprising: measuring a first current in a first signal path of a radio frequency signal generator; measuring a second current in a second signal path of the radio frequency signal generator; and adjusting a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.

[0015] Other embodiments will be described in the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying figures. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram illustrating a schematic diagram of a radio frequency signal generator system and a calibration system configured to calibrate a baseband signal in the radio frequency signal generator system according to an exemplary embodiment of the present disclosure.

[0017] [Figure 2] FIG. 10 is a diagram illustrating a schematic diagram of a radio frequency signal generator system and a calibration system configured to calibrate a baseband signal in the radio frequency signal generator system according to another exemplary embodiment of the present disclosure.

[0018] [Figure 3] FIG. 2 illustrates a schematic diagram of a current measurement circuit implemented by a calibration system for measuring baseband current, according to an exemplary embodiment of the present disclosure.

[0019] [Figure 4A] FIG. 4 is a schematic diagram of a current-mode digital-to-analog converter circuit that can be implemented in the current measurement circuit of FIG. 3, according to an exemplary embodiment of the present disclosure. [Figure 4B] FIG. 4 is a schematic diagram of a current-mode digital-to-analog converter circuit that can be implemented in the current measurement circuit of FIG. 3, according to an exemplary embodiment of the present disclosure. [Figure 4C] FIG. 4 is a schematic diagram of a current-mode digital-to-analog converter circuit that can be implemented in the current measurement circuit of FIG. 3, according to an exemplary embodiment of the present disclosure.

[0020] [Figure 5] FIG. 2 is a schematic diagram of a local oscillator signal output configuration circuit according to an exemplary embodiment of the present disclosure.

[0021] [Figure 6]FIG. 10 illustrates a table of settings for configuring a radio frequency signal generator system and a calibration system in calibration mode to measure individual baseband currents, according to an exemplary embodiment of the present disclosure.

[0022] [Figure 7A] FIG. 1 illustrates a process for calibrating baseband current in a radio frequency signal generator system according to an exemplary embodiment of the present disclosure. [Figure 7B] FIG. 1 illustrates a process for calibrating baseband current in a radio frequency signal generator system according to an exemplary embodiment of the present disclosure.

[0023] [Figure 8] FIG. 2 is a diagram illustrating a schematic of a current measurement circuit implemented by a calibration system to measure the DC component of an upconverted radio frequency current signal, according to an exemplary embodiment of the present disclosure.

[0024] [Figure 9] FIG. 10 is a diagram illustrating a schematic of a current measurement circuit implemented by a calibration system to measure the DC component of an upconverted radio frequency current signal, according to another exemplary embodiment of the present disclosure.

[0025] [Figure 10] FIG. 1 illustrates a schematic diagram of a quantum computing system implementing an arbitrary waveform generator system and a calibration circuit, according to an exemplary embodiment of the present disclosure.

[0026] [Figure 11] FIG. 1 is a schematic diagram of a quantum computing system according to another exemplary embodiment of the present disclosure.

[0027] [Figure 12] FIG. 2 is a diagram illustrating a schematic diagram of an exemplary computing environment configured to execute program instructions for controlling a calibration process of a calibration system, according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0028] Exemplary embodiments of the present disclosure will now be described in further detail with respect to systems and methods for calibrating signal current in an RF signal generator system, such as an AWG system. It should be understood that the various features shown in the accompanying drawings are schematic illustrations that are not drawn to scale. Moreover, the same or similar reference numerals are used throughout the drawings to indicate the same or similar features, elements, or structures, and therefore, a detailed description of the same or similar features, elements, or structures will not be repeated for each of the drawings. Furthermore, the term "exemplary," as used herein, means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" should not be construed as preferred or advantageous over other embodiments or designs.

[0029] Furthermore, it should be understood that the phrase "configured to," when used in connection with a circuit, structure, element, component, or the like that performs one or more functions or otherwise provides some functionality, is intended to encompass embodiments in which the circuit, structure, element, component, or the like is implemented in hardware, software, and / or combinations thereof, and in implementations that include hardware, the hardware may include discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application specific integrated circuit (ASIC) chips, field-programmable gate array (FPGA) chips, etc.), processing devices (e.g., central processing units (CPUs), graphics processing units (GPUs), etc.), one or more integrated circuits, and / or combinations thereof. Thus, by way of example only, when a circuit, structure, element, component, etc. is defined as being configured to provide a particular functionality, it is intended to encompass, without limitation, embodiments in which the circuit, structure, element, component, etc. is comprised of an element, processing device, and / or integrated circuit that enables the circuit, structure, element, component, etc. to perform the particular functionality when it is in an operational state (e.g., connected or otherwise deployed in a system, powered on, receiving input, and / or generating output), as well as embodiments in which the circuit, structure, element, component, etc. is in a non-operational state (e.g., not connected or otherwise deployed in a system, not powered on, not receiving input, and / or not generating output) or in a partially operational state.

[0030]

[0013] Figure 1 schematically illustrates a radio frequency signal generator system according to an exemplary embodiment of the present disclosure, and a calibration system configured to calibrate baseband currents in a signal path of the radio frequency signal generator system. In particular, Figure 1 schematically illustrates an RF signal generator system 100 including a baseband I / Q signal generator 110, a digital-to-analog converter stage 120 (or DAC stage 120), a baseband filter stage 130, a mixer stage 140, an amplifier stage 150, an impedance matching network 160, a local oscillator (LO) signal generator circuit 170, and an LO signal output configuration circuit 180, the functions of which will be described in further detail below. A calibration system 190 includes a current measurement circuit 192, a current imbalance correction circuit 194, and a calibration control circuit 196, the functions of which will be described in further detail below.

[0031] 1, DAC stage 120 has an input coupled to the output of baseband I / Q signal generator 110. Baseband filter stage 130 has an input coupled to the output of DAC stage 120. Mixer stage 140 has an input coupled to the output of baseband filter stage 130. Amplifier stage 150 has an input coupled to the output of mixer stage 140 and an output coupled to the input of impedance matching network 160, the output of which is coupled to an output node (RF_OUT) of RF signal generator system 100. LO signal generator circuit 170 is configured to generate an LO signal (e.g., a quadrature LO signal) utilized by mixer stage 140 to perform amplitude modulation of the in-phase LO signal (LO_I) and quadrature-phase LO signal (LO_Q). The LO signal output configuration circuit 180 is configured to control the input of the LO signal to the mixer stage 140 for different operating modes of the RF signal generator system 100 (e.g., a real-time operating mode and a calibration mode), as will be discussed in more detail below.

[0032] It should be appreciated that the RF signal generator system 100 can be implemented for a variety of applications. For example, in some embodiments, the RF signal generator system 100 comprises an RF transmitter for wireless applications, where the output of the RF signal generator system 100 is coupled to an antenna system configured to transmit an RF output signal generated by the RF signal generator system 100. In other embodiments, the RF signal generator system 100 comprises a waveform generator (e.g., an arbitrary waveform generator (AWG) or a function generator) where the output of the RF signal generator system 100 is coupled to the input of a sensor device, where the RF output signal generated by the RF signal generator system 100 is configured to excite the sensor device. In other embodiments, the RF signal generator system 100 comprises an AWG system implemented for quantum computing applications, where the RF signal generator system 100 is configured to generate RF control pulses to control the operation of, for example, a superconducting quantum bit (qubit), an active superconducting coupler circuit coupling two superconducting qubits, or other superconducting quantum devices.

[0033] In the context of the exemplary embodiments discussed herein, RF signals include signals having frequencies ranging, for example, from about 20 kHz to about 300 GHz. In some embodiments, RF signal generator system 100 comprises an analog quadrature system configured to generate quadrature (I / Q) signals (e.g., baseband I / Q signals and LO I / Q signals) and perform quadrature modulation (or I / Q signal modulation) to generate RF signals for a given application. As is known in the art, quadrature signals include an in-phase (I) signal component and a quadrature-phase (Q) signal component. A pair of signals in quadrature have the same frequency but differ in phase by 90 degrees. For example, by convention, the I signal is a cosine waveform and the Q signal is a sinusoidal waveform. For illustrative purposes, exemplary embodiments of the present disclosure will be described in the context of a quadrature RF signal generator system, although the exemplary signal processing circuits and methods as discussed herein can be implemented with other types of RF signal generator systems and modulation techniques.

[0034] 1 , baseband I / Q signal generator 110 is configured to generate digital quadrature signals I and Q that represent input baseband data for a given application. For example, for quantum computing applications, baseband I / Q signal generator 110 is configured to implement pulse shaping techniques to generate RF control pulses having desired envelope shapes (e.g., Gaussian pulses, cosine pulses (e.g., sums of half cosines), hyperbolic secant pulses, etc.) that are applied to superconducting qubit or active qubit coupler circuits to perform single-qubit gate operations, entanglement gate operations, etc. In some embodiments, baseband I / Q signal generator 110 implements digital signal processing techniques based on a combination of hardware and software to generate digital quadrature baseband signals I and Q.

[0035] The DAC stage 120 is configured to convert the digital quadrature signals I and Q into analog baseband signals I'(t) and Q'(t) having a target baseband frequency. In particular, the DAC stage 120 comprises a multi-bit DAC circuit including a first DAC circuit 121 and a second DAC circuit 122. The first DAC circuit 121 is configured to convert the digital baseband component I into an analog baseband component I'(t) having the baseband frequency, and the second DAC circuit 122 is configured to convert the digital baseband component Q into an analog baseband component Q'(t) having the same baseband frequency but shifted in phase by 90 degrees with respect to I'(t). The DAC stage 120 is configured to convert the digital baseband component I into an analog baseband component Q'(t) having the same baseband frequency but shifted in phase by 90 degrees with respect to I'(t). S) or sampling frequency, e.g., at a baseband frequency ranging from about 100 kHz to about 1 GHz depending on a given application. In some embodiments, first and second DAC circuits 121 and 122 implement a configurable hardware framework that allows various operating parameters of DAC stage 120 to be adjusted by digital control signals input to DAC stage 120. For example, in some embodiments, digital control can be utilized to adjust DAC operating parameters including, but not limited to, sampling rate, analog output gain, etc.

[0036] Based on the Nyquist sampling theory, the highest fundamental output frequency f that a DAC can generate at a sampling frequency fs. O The signal is sampled at half the sampling rate, i.e., f s / 2 (called the first Nyquist zone). In the frequency domain, the frequency f O When generating a sinusoidal waveform of the fundamental baseband frequency f O is f O , there will be additional higher order frequency components generated at the output of DAC stage 120, which are called "images" and appear as spectral components at f S and f O For example, the high-order frequency components are functions of |(n×f S )±f O |, where n=1, 2, 3, .... Images have the same information content as the fundamental spectral components, but at higher frequencies and lower amplitudes. Unwanted images are suppressed / removed, for example, using a baseband filter stage 130.

[0037] The baseband filter stage 130 is configured to filter the analog baseband signals I'(t) and Q'(t) output from the DAC stage 120, thereby generating filtered analog baseband signals I(t) and Q(t). The baseband filter stage 130 comprises a first filter circuit 131 and a second filter circuit 132. The first filter circuit 131 is configured to filter the in-phase analog signal I'(t) output from the first DAC circuit 121, and the second filter circuit 132 is configured to filter the quadrature-phase analog signal Q'(t) output from the second DAC circuit 122. In some embodiments, the first and second filter circuits 131 and 132 comprise low-pass filters configured to pass fundamental spectral components of the respective analog signals I'(t) and Q'(t) while suppressing image components of the respective analog signals I'(t) and Q'(t). In other embodiments, the first and second filter circuits 131 and 132 can be configured as bandpass filters that pass a desired band of high-frequency image components of the respective analog signals I'(t) and Q'(t) while suppressing the fundamental spectral component and other image components of the respective analog signals I'(t) and Q'(t). In other embodiments, the first and second filter circuits 131 and 132 can be configured as highpass filters as may be desired for a given application.

[0038] In some embodiments, baseband filter stage 130 comprises configurable filter circuits, e.g., that can adjust the cutoff frequencies of first and second filter circuits 131 and 132, or that can configure first and second filter circuits 131 and 132 to have different filter types (e.g., low-pass, band-pass, etc.) as desired for a given application. For example, in some embodiments, a band-pass filter can be configured using two low-pass filters using known signal filtering techniques and architectures. In some embodiments, the filter configuration is digitally controlled by a digital control signal input to baseband filter stage 130.

[0039] For example, a higher DAC sampling frequency may be utilized as needed to transmit baseband data and / or to soften the filter response of downstream filters in baseband filter stage 130. In practice, increasing the DAC sampling frequency provides the possibility of accommodating higher baseband transmission frequencies (i.e., analog signals I'(t) and Q'(t) having higher baseband frequencies). Additionally, increasing the DAC sampling frequency increases the center frequency f of the baseband components. O and the center frequency of the higher frequency image, n×f S ±f O , which results in an increase in the separation between the DAC sampling frequency and the filter cutoff sharpness required at the filter corner frequency. However, a higher DAC sampling rate results in an increase in power consumption. Therefore, the trade-off between power consumption and the DAC sampling frequency and the filter cutoff sharpness at the filter corner frequency are factors that should be considered.

[0040] In some embodiments, the mixer stage 140 is configured to perform analog I / Q signal modulation, e.g., single-sideband (SSB) modulation, by mixing the filtered analog signals I(t) and Q(t) output from the baseband filter stage 130 with quadrature LO signals (e.g., an in-phase LO signal (LO_I) and a quadrature-phase LO signal (LO_Q)) to generate and output an analog RF signal (e.g., a single-sideband modulated RF output signal). The local oscillator signals LO_I and LO_Q each have the same LO frequency, except that the LO_Q signal is phase-shifted by 90 degrees relative to the LO_I signal. In the case of amplitude modulation, the filtered analog signals I(t) and Q(t) amplitude modulate the LO_I and LO_Q signals. It is desirable to ensure that the amplitude modulation level applied to the LO_I signal closely matches the amplitude modulation level applied to the LO_Q signal. Otherwise, the in-phase (I) and quadrature-phase (Q) signal components of the RF output generated by RF signal generator system 100 will be unbalanced, resulting in degraded image rejection performance and the presence of undesirable sideband spurs.

[0041] More specifically, the mixer stage 140 includes a first mixer circuit 141 (e.g., an I mixer circuit), a second mixer circuit 142 (e.g., a Q mixer circuit), and a signal combiner circuit 143. The first mixer circuit 141 is configured to mix the filtered analog signal I(t) with the LO_I signal to generate a first RF signal output. The second mixer circuit 142 is configured to mix the filtered analog signal Q(t) with the LO_Q signal to generate a second RF signal output. The first and second RF signals output from the first and second mixer circuits 141 and 142 are input to the signal combiner circuit 143 and combined (e.g., added) to generate a single-sideband RF signal output.

[0042] In some embodiments, a quadrature phase shifter circuit is implemented to generate quadrature LO signals LO_I and LO_Q. For example, the quadrature phase shifter circuit is configured to receive an LO signal as an input and output quadrature LO signals LO_I and LO_Q based on the LO input signal. In this configuration, the LO_I signal has the same frequency and phase as the input LO signal, and the LO_Q signal has the same frequency as the input LO signal but with a 90-degree phase shift. The quadrature phase shifter circuit can be implemented using one of a variety of quadrature phase shifting techniques known to those skilled in the art.

[0043] Mixer stage 140 performs an upconversion mixing process configured to generate an RF analog signal having a center frequency higher than the baseband frequency of the baseband signal output from DAC stage 120. In some embodiments, the LO frequency of mixer stage 140 is in the range of 100 MHz to approximately 10 GHz, depending on the application. More specifically, as will be appreciated by those skilled in the art, as a result of the mixing operations of first and second mixer circuits 141 and 142, the first and second RF signals output from the respective first and second mixer circuits 141 and 142 each comprise a double-sideband RF signal. The double-sideband signal comprises an upper sideband (USB) and a lower sideband (LSB) disposed at equal distances above and below the LO frequency. The upper sideband comprises a spectral band at frequencies higher than the LO frequency, and the lower sideband comprises a spectral band at frequencies lower than the LO frequency. The upper and lower sidebands each carry the same information content of the IQ signal. For example, if the filtered analog signals I(t) and Q(t) (i.e., the modulating signals) have a center frequency f M (intermediate frequency), and the LO signal has a frequency f LO The first and second RF signals output from the first and second mixer circuits 141 and 142 are respectively (i)(f LO +f M ), and (ii) the upper sideband of the spectral component, which is a frequency band centered at the frequency of (f LO -f M) frequency band centered at the frequency of the lower sideband of the spectral component.

[0044] In some embodiments, the signal combiner circuit 143 is configured to sum the first and second RF signals output from the first and second mixer circuits 141 and 142, in which case the signal combiner circuit 143 combines the first and second RF signals output from the first and second mixer circuits 141 and 142 at frequencies f M to the center frequency of the lower sideband (f LO -f M ) and outputs the "useful" lower sideband signal as a single-sideband modulated RF signal (with a suppressed carrier frequency) having a center frequency upconverted to the frequency f of the modulated signals I(t) and Q(t). In another embodiment, the signal combiner circuit 143 is configured to subtract the first and second RF signals output from the first and second mixer circuits 141 and 142, in which case the signal combiner circuit 143 subtracts ... frequency f of the modulated signals I(t) and Q(t). M to the center frequency of the upper sideband (f LO +f M ) and outputs the “effective” upper sideband signal as a single-sideband modulated RF signal (with a suppressed carrier) having a center frequency upconverted to LO_Q. In other embodiments, mixer stage 140 is configured as a double-sideband modulator (with a suppressed carrier frequency). More specifically, mixer stage 140 can be configured to provide double-sideband modulation by maintaining the LO_Q input to second mixer 142 at a constant zero voltage level (i.e., LO_Q=0). In this case, second mixer circuit 142 will have zero output (i.e., no RF signal is output from second mixer circuit 142), and the output of signal combiner circuit 143 will be the double-sideband RF signal output from first mixer circuit 141.

[0045] Amplifier stage 150 is configured to receive the modulated RF signal output from mixer stage 140, amplify or attenuate the modulated RF signal to a desired power level, and drive the output of RF signal generator system 100 (e.g., drive an antenna, sensor device, qubit, etc. coupled to the output of RF signal generator system 100). In some embodiments, amplifier stage 150 includes programmable gain, which can be expressed as the difference between the input power level (at the input of amplifier stage 150) and the output power level (at the output of amplifier stage 150), or more specifically, the ratio of the output power to the input power. In some embodiments, amplifier stage 150 is utilized to increase the power level of the RF output signal to a level that is sufficient for transmitting the modulated RF signal (wirelessly or via wire) at a given power level and over a required transmission distance. In other embodiments, amplifier stage 150 comprises a programmable gain attenuation stage. The programmable gain attenuation stage comprises a programmable amplifier configured to amplify the modulated RF signal by a gain factor of 1 or less. In this manner, the programmable gain attenuator stage can attenuate the power level of the modulated RF signal output from mixer stage 140 as desired for a given application.

[0046] The impedance matching network 160 is configured to match the source impedance or load impedance of the output of the amplifier stage 150 to the characteristic impedance of the output load (e.g., antenna input, diplexer, etc.) of the RF signal generator system 100. In some embodiments, the impedance matching network 160 comprises a balun that converts the differential / balanced output of the amplifier stage 150 to a single-ended / unbalanced output. In some embodiments, the resonant parameters (e.g., impedance and bandwidth) of the impedance matching network 160 remain substantially unchanged, and the impedance matching network 160 is designed with a center frequency corresponding to the desired operating frequency of the load. In other embodiments, the impedance matching network 160 is configured with multiple injection points to provide different impedance matching and filtering characteristics. Different injection points can be selected by a digital control signal applied to the impedance matching network 160. The impedance matching network 160 can have high-pass and low-pass characteristics, and different injection points can be selected to provide different impedance matching and response characteristics. In some embodiments, the impedance matching network 160 is designed with a high Q factor, and the center frequency of the impedance matching network 160 can be adjusted to provide sufficient impedance matching for different occurring transmit frequencies, depending on a given application, for example, by changing the sampling frequency of the DAC stage 120 and / or by changing the LO frequency of the mixer stage 140.

[0047] In some embodiments, the LO signal generator circuit 170 is configured to generate quadrature LO signals LO_I and LO_Q at a target center frequency, which are utilized by the mixer stage 140 to perform I / Q modulation and upconversion. In some embodiments, in the case of a differential signaling framework, the LO signal generator circuit 170 generates complementary in-phase LO signals LO_I and

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[0048] LO signal generator circuit 170 is implemented using known circuit architectures and LO signal generation techniques. For example, in some embodiments, LO signal generator circuit 170 includes a phase-locked loop (PLL) system configured to generate an LO signal at a target center frequency, and a phase shifter circuit that converts the LO signal generated by the PLL system into quadrature LO signals LO_I and LO_Q. In the case of differential quadrature LO signals, in some embodiments, LO signal generator circuit 170 receives as input a complementary pair of LO signals, LO_I and LO_Q.

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[0049] The LO signal output configuration circuit 180 comprises an LO signal driver stage configured to drive the LO inputs of the first and second mixer circuits 141 and 142 in the mixer stage 140 with the quadrature LO signals generated and output from the LO signal generator circuit 170. As will be described in further detail below, in a normal operation mode of the RF signal generator system 100, the LO signal output configuration circuit 180 is configured to drive the LO inputs of the first and second mixer circuits 141 and 142 with the quadrature LO signals LO_I and LO_Q (or complementary quadrature LO signals) to perform normal I / Q modulation. In a calibration mode of the RF signal generator system 100, the LO signal output configuration circuit 180 is configured to selectively drive the LO inputs of the first and second mixer circuits 141 and 142 with DC voltages that are configured to selectively enable and disable the switching transistors of the first and second mixer circuits 141 and 142 to perform DC measurements of baseband currents, details of which will be described in further detail below. An exemplary embodiment of the LO signal output configuration circuit 180 will be discussed in further detail below in conjunction with FIG. 5.

[0050] 1 , the various signal processing stages 110, 120, 130, 140, 150, 160, 170, and 180 of RF signal generator system 100 include control signal input ports that receive digital control signals from either a calibration system 190 or any processor or microcontroller configured to control the operation of RF signal generator system 100. Calibration system 190 can generate the digital control signals to configure RF signal generator system 100 to operate in a calibration mode and can control the execution of a calibration process performed in the calibration mode to calibrate the I / Q signals of RF signal generator system 100. Furthermore, in some embodiments, some or all of stages 110, 120, 130, 140, 150, 160, 170, and 180 include a configurable hardware framework that can adjust various operating parameters of the stages via digital control signals to adjust normal mode operation of RF signal generator system 100.

[0051] In the exemplary I / Q modulation architecture of the RF signal generator system 100 shown in FIG. 1, it is desirable to eliminate or otherwise substantially minimize imbalance between the baseband I and Q signals for image rejection purposes. In practice, I / Q imbalance can result in undesired spectral components at the image frequency. As described above, the SSB mixer mixes the intermediate frequency (IF) of the baseband signal at f LO -f IF or f IF +f LO to only one of the sideband signal center frequencies without creating an image of the other sideband signal, which is particularly useful when using low IF frequencies, since pre-selection filtering is difficult in that case. For example, if the desired RF signal is at frequency f RF =f LO -f IF If it occurs at f IF +f LO The sideband signal (image signal) at will be suppressed by the sideband suppression provided by the SSB mixer. However, the amplitude imbalance of the baseband I and Q signals can result in the presence of relatively high spectral power for undesired spectral components at the image frequency.

[0052] In addition, the differential analog I signal

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[0053] The calibration system 190 is configured to perform functions such as (i) generating control signals that configure the RF signal generator system 100 to operate in a calibration mode, (ii) detecting imbalances between the baseband I and Q signals in the I / Q signal paths of the RF signal generator system 100 using DC measurement techniques, and (iii) generating DC correction signals in the I / Q signal paths to compensate for the detected imbalances between the baseband I and Q signals in the I / Q signal paths of the RF signal generator system 100, as well as other functions, as discussed in more detail below.

[0054] In some embodiments, the current measurement circuit 192 is configured to measure the I / Q baseband currents in the I / Q signal paths of the RF signal generator system 100 and detect the amount of imbalance, if any, in the I / Q baseband currents when the RF signal generator system 100 is configured in a calibration mode of operation. For example, in some embodiments, the current measurement circuit 192 is configured to measure the I and Q baseband currents and detect any imbalance between the I and Q baseband signals. Furthermore, in some embodiments, for a differential I / Q system, the current measurement circuit 192 measures (i) the complementary I(t) and

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[0055] The current imbalance correction circuit 194 is configured to generate a DC correction signal in the I / Q signal path to compensate for detected imbalances between the baseband I and Q signals in the I / Q baseband signal paths of the RF signal generator system 100. In some embodiments, as discussed in further detail below, the current imbalance correction circuit 194 injects DC currents into the I / Q baseband signal paths of the RF signal generator system 100 to correct (i) the I and Q baseband currents, (ii) the complementary I(t) and

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[0056] The calibration control circuit 196 is configured to perform various functions of the calibration system 190 for calibrating the baseband I / Q signals of the RF signal generator system 100. For example, the calibration control circuit 196 generates various control signals for configuring the RF signal generator system 100 to operate in a calibration mode to perform a calibration process. In addition, the calibration control circuit 196 generates control signals that control the operation of the current measurement circuit 192 and the current imbalance correction circuit 194. Moreover, in some embodiments, the calibration control circuit 196 includes control logic configured to, for example, (i) process the I / Q baseband current measurement data generated by and output from the current measurement circuit 192 during the calibration process and generate digital control signals that control the operation of the current imbalance correction circuit 194 to generate a target DC current correction signal based on the results of processing the I / Q baseband current measurements. In some embodiments, the control logic implements a finite state machine to process the current measurement data output from the current measurement circuit 192 and generate the digital control signals that control the operation of the current imbalance correction circuit 194.

[0057]

[0023] Figure 2 schematically illustrates a radio frequency signal generator system and a calibration system configured to calibrate a baseband current in a signal path of the radio frequency signal generator system according to another exemplary embodiment of the present disclosure. More specifically, Figure 2 schematically illustrates an RF signal generator system 200 including a baseband signal input stage 210, a current-commutating mixer stage 220, a signal attenuation stage 230, and a transformer circuit 240 (alternatively, an output transformer stage 240). In addition, Figure 2 schematically illustrates a calibration system including a current measurement circuit 250, a control logic circuit 260, a first DC offset compensation DAC 270, and a second DC offset compensation DAC 272.

[0058] In some embodiments, the RF signal generator system 200 generates complementary in-phase baseband signals I(t) and

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[0059] The baseband signal input stage 210 comprises a plurality of baseband input transistors 211, 212, 213, and 214. In some embodiments, the baseband input transistors 211, 212, 213, and 214 are p-type metal-oxide-semiconductor (PMOS) transistors. The transistors 211 and 212 comprise a first differential transistor pair 210-1, with source terminals commonly connected to a positive power supply voltage node VDD (e.g., VDD_RF, where VDD_RF is approximately 900 mV or less) and complementary in-phase baseband signals I(t) and I(t) as inputs, respectively.

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[0060] In some embodiments, transistors 211, 212, 213, and 214 of baseband signal input stage 210 comprise variable gain elements (as indicated schematically by the diagonal arrows across the transistors) that are configurable to adjust the baseband signal gain in the I / Q signal paths. For example, in some embodiments, each baseband input transistor 211, 212, 213, and 214 varies the effective gate width of the transistor structure, and thus the drain current I that flows through the respective transistor 211, 212, 213, and 214 when operating in saturation mode. D_1 , I D_2 , I D_3 , and I D_4 The variable width transistor is structurally configured and controlled using known techniques to adjust the maximum amount of

[0061] For example, in some embodiments, each baseband input transistor 211, 212, 213, and 214 can be structurally configured to include multiple transistor segments coupled in parallel, and the number of segments that are enabled / disabled at a given time can be adjusted (via a digital switching control system) to change the effective gate width of a given baseband input transistor. In this regard, the effective widths of transistors 211, 212, 213, and 214 in baseband signal input stage 210 can be configured to adjust the baseband signal gain in the I / Q signal path over a target gain range (e.g., a 20 dB gain range) with multiple gain step settings within the gain range. For example, in some embodiments, the DC baseband current can be adjusted to one of various target current levels over a given range (e.g., a range from about 35 μA to about 350 μA) with the highest baseband current level approximately 10× higher than the lowest baseband current level.

[0062] Current-commutating mixer stage 220 includes a differential I mixer 220-1 and a differential Q mixer 220-2. Differential I mixer 220-1 includes a plurality of mixing transistors 221, 222, 223, and 224 (alternatively, I mixer switching transistors 221, 222, 223, and 224). Differential Q mixer 220-2 includes mixing transistors 225, 226, 227, and 228 (alternatively, Q mixer switching transistors 225, 226, 227, and 228). In some embodiments, as shown in FIG. 2, mixing transistors 221, 222, 223, 224, 225, 226, 227, and 228 are PMOS transistors.

[0063] In the differential I mixer 220-1, the mixing transistors 221 and 222 have their source terminals commonly connected to the drain terminal of the transistor 211 in the baseband signal input stage 210, and complementary in-phase LO signals LO_I and LO_I as inputs, respectively.

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[0064] In the differential Q mixer 220-2, the mixing transistors 225 and 226 have their source terminals commonly connected to the drain terminal of the transistor 213 in the baseband signal input stage 210, and complementary quadrature-phase LO signals LO_Q and LO_Q as inputs, respectively.

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[0065] 2, mixing transistors 221, 223, 225, and 227 have their drain terminals commonly coupled to the output node INT_1 of current-commutating mixer stage 220, and mixing transistors 222, 224, 226, and 228 have their drain terminals commonly coupled to the output node INT_0 of current-commutating mixer stage 220. Differential I mixer 220-1 and differential Q mixer 220-2 are configured to provide analog I / Q modulation and upconversion, where the connections of the mixing transistors of differential I and Q mixers 220-1 and 220-2 (where the mixing transistors operate in triode mode) enable summation / subtraction of the output currents of mixing transistors 221, 222, 223, 224, 225, 226, 227, and 228 to achieve SSB I / Q modulation, as will be understood by those skilled in the art. As described in more detail below, in some embodiments, output nodes INT_0 and INT_1 comprise intermediate nodes in the baseband I and Q signal paths that are tapped by a calibration system to measure the I / Q baseband currents of RF signal generator system 200 during a calibration process.

[0066] Signal attenuation stage 230 is configured to adjust the signal strength of the RF output signal. More specifically, in the exemplary embodiment of FIG. 2, signal attenuation stage 230 is configured to adjust the amount of differential current flowing from output nodes INT_0 and INT_1 to output transformer stage 240. In this regard, signal attenuation stage 230 functions to adjust the signal level of the signal output from current-commutating mixer stage 220. Signal attenuation stage 230 adjusts the signal strength of each pair of differential control signals.

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[0067] In the first attenuation segment 230-1, a first differential pair of transistors 231 and 232 have their source terminals commonly connected to the mixer output node INT_1 and a differential control signal V as inputs, respectively. ATTN_1 and

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[0068] Similarly, in attenuation segment 230-s, a first differential pair of transistors 235 and 236 have their source terminals commonly connected to mixer output node INT_1 and a differential control signal V as inputs, respectively. ATTN_S and

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[0069] In operation, the amount of differential current flowing from output nodes INT_0 and INT_1 to output transformer stage 240 can be adjusted based on the number of attenuation segments 230-1, ..., 230-s that are enabled. A given attenuation segment is adjusted based on the corresponding differential control signal V ATTN and

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[0070] In this configuration, the amount of differential current flowing from output nodes INT_0 and INT_1 to output transformer stage 240 can be increased (i) by increasing the number of "disabled" attenuation segments (thereby increasing the RF output signal level), or (ii) by increasing the number of "enabled" attenuation segments (thereby decreasing the RF output signal level). The number of attenuation segments 230-1, ..., 230-s implemented will depend on the desired resolution of the gain adjustment.

[0071] As described above, in the baseband signal input stage 210, the first differential transistor pair 210-1 receives the complementary in-phase baseband signal I(t) and

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[0072] As described above, amplitude or phase imbalance between the I and Q signals can cause degradation in image rejection performance, leading to the presence of unwanted spur sidebands. Furthermore, positive and negative components in the same phase (I phase) (e.g., I + and I - ) leads to LO leakage spurs. In a current-mode RF signal generator system architecture (e.g., an AWG system) such as that shown in FIG. 2, (i) the I and Q baseband currents, (ii) the I + and I - current, and / or (iii) Q + and Q - An imbalance between the currents can lead to degraded performance in terms of LO leakage and unwanted spurious sideband signals.

[0073] The exemplary calibration system shown in FIG. 2 is configured to correct imbalances in the I / Q baseband currents. As described above, in some embodiments, output nodes INT_0 and INT_1 comprise intermediate nodes in the baseband I and Q signal paths that are tapped by the calibration system to measure the I / Q baseband currents in RF signal generator system 200 during the calibration process. In the exemplary embodiment of FIG. 2, current measurement circuit 250 comprises first and second inputs selectively coupled (via switches) to respective output nodes INT_0 and INT_1 of current-commutating mixer stage 220. During the calibration process, current measurement circuit 250 is enabled and measures the respective I-phase and Q-phase current signal components I at output nodes INT_0 and INT_1. + , I - , Q + , and Q - The device is configured to perform a DC measurement to detect

[0074] More specifically, in some embodiments, calibration is performed as follows: RF signal generator system 200 is configured to operate in a calibration mode. In calibration mode, baseband input transistors 211, 212, 213, and 214 of baseband signal input stage 210 are biased at their normal current levels (i.e., the same as those used in normal operation mode). Upstream circuitry (such as first and second DAC circuits 121 and 122 in FIG. 1) ensures that zero differential voltage is applied to the common-mode input.

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[0075] Additionally, in calibration mode, current commutating mixer stage 220 outputs the baseband current I of a given baseband phase on one of nodes INT_0 and INT_1 for input to current measurement circuit 250. + , I - , Q + , or Q - In particular, the baseband current I can be selected at a given time for measurement. + , I - , Q + , or Q - To selectively output one of the I and Q mixer switching transistors, the I and Q mixer switching transistors are configured by applying a DC voltage of logic "1" or a DC voltage of logic "0" to the gate terminals of the I and Q mixer switching transistors, as needed, to selectively turn on one mixing transistor while turning off the other mixing transistor.

[0076] For example, the baseband current I on node INT_1 + To output the baseband current I on node INT_1, the mixing transistor 221 of the I mixer 220-1 is turned on, while all other mixing transistors 222, 223, 224, 225, 226, 227, and 228 are turned off. -To output a baseband current Q on node INT_1, mixing transistor 223 of I mixer 220-1 is turned on, while all other mixing transistors 221, 222, 224, 225, 226, 227, and 228 are turned off. + In order to output a baseband current Q on node INT_1, mixing transistor 225 of Q mixer 220-2 is turned on, while all other mixing transistors 221, 222, 223, 224, 226, 227, and 228 are turned off. - To output I, mixing transistor 227 of Q mixer 220-2 is turned on, while all other mixing transistors 221, 222, 223, 224, 225, 226, and 228 are turned off. In other embodiments, the individual I-phase and Q-phase current signal components I + , I - , Q + and Q - Note that can be selectively output on node INT_0 by selectively enabling only one of the mixing transistors 222, 224, 226, or 228 at a given time.

[0077] In some embodiments, the current measurement circuit 250 measures the DC baseband current I + , I - , Q + , and Q - and the control logic circuit 260 is configured to measure / estimate the coherent {I + ,I -} and {Q + ,Q -}. For example, the measured I + and I - Difference (imbalance) between baseband currents and / or measured Q + and Q - The difference (imbalance) between the baseband currents represents the DC offset that leads to the LO leakage. + and Q +It is configured to determine the difference (imbalance) between the baseband currents, I + and Q + Imbalances between the baseband currents can degrade image rejection, which results in the presence of unwanted sideband spurs.

[0078] The control logic circuit 260 is configured to generate respective first and second digital control signals (e.g., n-bit control signals [n-1:0]) that are applied to the first and second DC offset compensation DACs 270 and 272, respectively. In some embodiments, the first control signal input to the first DC offset compensation DAC 270 is a signal that is a function of the measured I + and I - A second control signal that provides an indication of the determined difference between the baseband currents and is input to the second DC offset compensation DAC 272 is + and Q - An indication of the determined difference between the baseband currents is provided.

[0079] 2, the first DC offset compensation DAC 270 has a first output terminal coupled to the drain terminal of the baseband input transistor 211 and a second output terminal coupled to the drain terminal of the baseband input transistor 212. The second DC offset compensation DAC 272 has a first output terminal coupled to the drain terminal of the baseband input transistor 213 and a second output terminal coupled to the drain terminal of the baseband input transistor 214.

[0080] In this exemplary configuration, in response to a control signal received from control logic circuit 260, first DC offset compensation DAC 270 generates additional current I as needed. C_1 and I C_2 I + and I - It is configured to inject an additional current I into the baseband signal path. C_1 and I C_2is the drain current I of each of the baseband input transistors 211 and 212. D_1 and I D_2 is added to, thereby, I + and I - The baseband current is equalized and thus the I applied to the input of I mixer 220-1 + and I - The DC offset between the baseband currents is significantly reduced or eliminated. Similarly, in response to a control signal received from the control logic circuit 260, the second DC offset compensation DAC 272 generates an additional current I as needed. C_3 and I C_4 Q + and Q - It is configured to inject an additional current I into the baseband signal path. C_3 and I C_4 is the drain current I of each of the baseband input transistors 213 and 214. D_3 and I D_4 is added to, thereby Q + and Q - The baseband currents are equalized and thus the Q + and Q - The DC offset between the baseband currents is significantly reduced or eliminated.

[0081] It should be noted that the imbalance between the baseband currents can be adjusted via the first and second DC offset compensation DACs 270 and 272 and / or the first and second DAC circuits 121 and 122 in FIG. 1. For example, by utilizing the first and second DC offset compensation DACs 270 and 272, it is possible to adjust the imbalance between the baseband currents for a given phase, e.g., {I + and I -}, and {Q + and Q -} is minimized. On the other hand, the first and second DAC circuits 121 and 122 (FIG. 1) preferably provide a baseband current I + and Q +Therefore, the use of first and second DC offset compensation DACs 270 and 272, along with first and second DAC circuits 121 and 122, provides the ability to correct for imbalances and compensates for all baseband currents I + , I - , Q + , and Q - are guaranteed to be essentially equal in magnitude.

[0082] The current measurement circuit 250 of FIG. 2 (and the current measurement circuit 192 of FIG. 1) can be implemented using exemplary techniques and circuit architectures as described herein. For example, FIG. 3 schematically illustrates a current measurement circuit 300 implemented by a calibration system for measuring baseband currents according to an exemplary embodiment of the present disclosure. The current measurement circuit 300 includes a first current sink circuit 310, a second current sink circuit 320, a transistor 330 (alternatively, a mirror transistor 330), a current DAC circuit 340, a comparator 350, and a switch SW2. The first current sink circuit 310 includes a first transistor 312 and a switch SW0. The second current sink circuit 320 includes a second transistor 322 and a switch SW1. In some embodiments, the transistors 312, 322, and 330 are n-type MOS (NMOS) field-effect transistors.

[0083] In the first current sink circuit 310, a first transistor 312 has a drain terminal coupled to a first current sensing node INT_0 (e.g., intermediate node INT_0 in FIG. 2), a source terminal coupled to a negative power supply node VSS, and a gate terminal coupled to a first node N1. A switch SW0 is coupled to and between the drain and gate terminals of the first transistor 312. Furthermore, in the second current sink circuit 320, a second transistor 322 has a drain terminal coupled to a second current sensing node INT_1 (e.g., intermediate node INT_1 in FIG. 2), a source terminal coupled to the negative power supply node VSS, and a gate terminal coupled to the first node N1. A switch SW1 is coupled to and between the drain and gate terminals of the second transistor 322.

[0084] Mirror transistor 330 has a gate terminal coupled to a first node N1, a drain terminal coupled to a second node N2, and a source terminal coupled to a negative power supply node VSS. Current DAC circuit 340 has an output terminal coupled to the second node N2. Comparator 350 (e.g., a voltage comparator circuit) has a non-inverting input terminal (+) coupled to the second node N2, a voltage reference node VSS, and a non-inverting input terminal (-) coupled to the second node N2. REF and an output terminal coupled to an input terminal of a calibration control circuit (e.g., block 260, FIG. 2; block 196, FIG. 1). The switch SW2 is coupled to and between the first node N1 and the negative power supply node VSS.

[0085] The current DAC circuit 340 generates a reference current I with a magnitude that can be adjusted under digital control by a calibration control circuit (e.g., block 260, FIG. 2; block 196, FIG. 1, etc.). REF4A, 4B, and 4C.

[0086] The circuit components 310, 320, 330, and 350 of current measurement circuit 300 essentially receive an input baseband current to be measured (from one of nodes INT_0 or INT_1) and convert the input current into a reference current I (generated and output from current DAC circuit 340). REF Note that the current DAC circuit 340 includes a current comparator circuit configured to compare the reference current I REF The reference current I is fed to the current comparator circuit until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current I is substantially equal to the magnitude of the input current. REF is configured to increase or decrease the

[0087] More specifically, during normal operation of the RF signal generator system, the current measurement circuit 300 is configured in a disabled state in which switches SW0 and SW1 are open (disabled) and switch SW2 is closed (enabled). In the disabled state of the current measurement circuit 300, the first node N1 is coupled to the negative power supply voltage node VSS (e.g., ground). Because the gate terminals of transistors 312, 322, and 330 are commonly coupled to the first node N1, the transistors 312, 322, and 330 are in cutoff mode and therefore turned off. Furthermore, when switches SW0 and SW1 are disabled, the first and second nodes INT_0 and INT_1 are disconnected from the first node N1. In the disabled state, the current measurement circuit 300 provides a relatively small capacitive load (e.g., the small parasitic capacitance of the first and second transistors 312 and 322 in cutoff mode) to the first and second nodes INT_0 and INT_1 of the current-commutating mixer stage 220 to avoid RF signal attenuation.

[0088] During the calibration mode, the current measurement circuit 300 measures the DC current (e.g., I + , I - , Q + , Q -) is configured to measure the input current. For example, to measure the baseband current on the first node INT_0, switch SW0 is enabled (closed), switch SW1 remains disabled (open), and switch SW2 is disabled (open). In this configuration, the first current sink circuit 310 is enabled, where the first transistor 312 is a diode-connected MOSFET with its drain and gate terminals both coupled to the first node N1. Additionally, the first transistor 312 (in a diode-connected MOSFET configuration) and the mirror transistor 330 form a current mirror circuit. In some embodiments, the current mirror circuit formed by the first transistor 312 (in a diode-connected configuration) and the mirror transistor 330 is configured to provide a 1:1 current mirror ratio (or current transfer ratio). In other embodiments, the current mirror circuit is configured to scale the input current by a factor of M, where M<1 or where M>1.

[0089] In calibration mode, the RF signal generator system + , I - , Q + , or Q - A DC current corresponding to one of the baseband currents is configured to flow from the first node INT_0 to the first current sink circuit 310 and through the first transistor 312. The current DAC circuit 340 is configured to receive a reference current I that flows through the mirror transistor 330. REF and the voltage (V IN ) is generated on the second node N2. In some embodiments, a reference voltage V REF =0.5*VDD is applied to the inverting input (-) terminal of the comparator 350. The voltage V on the second node N2 IN V REF If the voltage V on the second node N2 is higher than IN V REFIf it is less than 1, the output of comparator 350 will be at a logic '0' level. In this exemplary configuration, the high output impedance of node N2 is well suited to perform the comparison operation.

[0090] In operation, the DC baseband current being measured flows from the first node INT_0 to the first current sink circuit 310, which generates a DAC reference current (I REF ) is output from the current DAC circuit 340. When the DAC reference current is higher than the DC baseband current, a voltage V IN is V REF , causing the output of comparator 350 to go to a logic "1" level. In response to the logic "1" output from comparator 350, the calibration control logic will determine that the DC baseband current being measured is less than the DAC reference current, and in response will generate a control code to cause current DAC circuit 340 to decrease the DAC reference current.

[0091] On the other hand, if the DAC reference current is less than the DC baseband current, the voltage V developed on the second node N2 IN is V REF will be less than the DAC reference current, causing the output of comparator 350 to go to a logic '0' level. In response to the logic '0' output from comparator 350, the calibration control logic will determine that the DC baseband current being measured is higher than the DAC reference current, and in response will generate control code to current DAC circuit 340 to increase the DAC reference current.

[0092] In the exemplary configuration, the comparison result at the output of comparator 350 is the DAC reference current I REF is adjusted (either increasing or decreasing), this is tracked by the calibration control logic. When the output of comparator 350 toggles from 0 to 1 or 1 to 0, this indicates that the most recent DAC code is equal to or substantially equal to the DAC reference current IREF In other words, the current DAC circuit 340 provides an indication that the DAC reference current I REF is adjusted to find a DAC code that makes the DC baseband current being measured as close as possible to the DC baseband current being measured, and the final code setting of current DAC circuit 340 will provide an estimate of the magnitude of the DC baseband current.

[0093] Similarly, to measure the baseband current on the second node INT_1, switch SW1 is enabled (closed), switch SW0 is disabled (open), and switch SW2 is disabled (open). In this configuration, the second current sink circuit 320 is enabled, where the second transistor 322 is a diode-connected MOSFET with its drain and gate terminals both coupled to the first node N1. Additionally, the second transistor 322 (in a diode-connected MOSFET configuration) and the mirror transistor 330 form a current mirror circuit. In some embodiments, the current mirror circuit formed by the second transistor 322 (in a diode-connected configuration) and the mirror transistor 330 is configured to provide a 1:1 current mirror ratio. In other embodiments, the current mirror circuit is configured to scale the input current by a factor of M, where M<1 or where M>1. In some embodiments, the current mirror circuit formed by the second transistor 322 (in a diode-connected configuration) and mirror transistor 330 is configured to provide the same current mirror ratio as the current mirror circuit formed by the first transistor 312 (in a diode-connected configuration) and mirror transistor 330.

[0094] In calibration mode, the RF signal generator system + , I - , Q + , or Q -A DC current corresponding to one of the baseband currents is configured to flow from the second node INT_1 to the second current sink circuit 320 and through the second transistor 322. The current measurement circuit 300 generates a DAC reference current I that is equal to or substantially equal to the DC baseband current being measured. REF The same process as discussed above is used to compare the (measured) DC baseband current with different DAC reference currents to determine . An exemplary calibration process will be discussed in more detail below, e.g., in conjunction with Figures 5, 6, 7A, and 7B.

[0095] Current DAC circuit 340 may be implemented using any high-resolution current-output DAC architecture that is suitable for a given application. The general function of current DAC circuit 340 is to convert a digital input code (provided by calibration control logic) into an analog current (e.g., a DAC reference current I) that is output from current DAC circuit 340. REF ) As is known in the art, a current-mode DAC architecture replicates a reference current source in each branch of the DAC, with the current sources connected in parallel with each other. In addition, the current sources are connected to the output node through respective MOSFET switches controlled by a digital input code. Each branch current is switched off or on based on the digital input code, and the currents output from each enabled branch of the DAC are summed to generate an analog output current.

[0096] In some embodiments, as described above, current DAC circuit 340 comprises a segmented DAC framework including a coarse binary-weighted DAC segment and a fine thermometer-coded DAC segment, which allows the analog output current of current DAC circuit 340 to be digitally programmed using coarse and fine bits. The coarse binary-weighted DAC segment is utilized to generate an output current close to a target current level (e.g., the baseband current being measured), while the fine thermometer-coded DAC segment is utilized for fine-tuning the output current to converge closer to the target current level. Note that current DAC circuit 340 can be designed with relaxed requirements, for example, in that the least significant bit (LSB) size of the fine thermometer-coded DAC segment does not have to be strictly related to the LSB size of the coarse binary-weighted DAC segment.

[0097] More specifically, current measurement circuit 300 converts the input baseband current to be measured into a DAC reference current I REF Compared with the DAC reference current I REF is determined to be equal to or substantially equal to the magnitude of the input baseband current being measured. REF There is no requirement to correct / calibrate the LSB size of the coarse and fine DAC segments because the coarse DAC segment is configured as a current comparator circuit that adjusts the magnitude of the DAC reference current I within the tuning range of the fine DAC segment. REF while the fine DAC segment adjusts the DAC reference current I to converge as close as possible to the magnitude of the baseband current being measured. REF The coarse DAC segment is used to fine-tune the magnitude of the DAC reference current I within the tuning range of the fine DAC segment. REF As long as it can be used to set the magnitude of the DC baseband current (e.g., I + , I - , Q+ , Q - ) can be compared against each other with high precision (resolution) by the current measurement circuit 300.

[0098] Furthermore, in some embodiments, the current DAC circuit 340 is configured to have a programmable range control that is equivalent to the range of the gain settings of the baseband signal input stage 210 (FIG. 2). As described above, in the exemplary embodiment of FIG. 2, the effective widths of the transistors 211, 212, 213, and 214 of the baseband signal input stage 210 can be adjusted to increase or decrease the baseband current levels in the I / Q signal paths over a given range, where the highest baseband current level (e.g., 350 μA) is approximately 10× higher than the lowest baseband current level (e.g., 35 μA). In this regard, the current measurement range of the current measurement circuit 300 can be scaled to match the baseband current levels generated by the baseband signal input stage 210.

[0099] For example, in some embodiments, current DAC circuit 340 is configured to operate over the full range of baseband current levels that can be generated by baseband signal input stage 210. Current DAC circuit 340 includes a scaling adjustment knob (e.g., a prescaler adjustment knob) that scales current DAC circuit 340 to generate output current levels that are equivalent to the baseband current levels in the I / Q signal paths that are generated for a given gain stage setting of baseband signal input stage 210. In some embodiments, the scaling of current DAC circuit 340 is configured to track the scaling of baseband signal input stage 210 using control signals that are “ganged” together so that when the gain of baseband signal input stage 210 is adjusted, the DAC current output range of current DAC circuit 340 is automatically scaled, thereby causing the current measurement range of current measurement circuit 300 to be equivalent to the adjusted I / Q baseband current levels.

[0100] In some embodiments, the current DAC circuit 340 can be configured to allow scaling of the LSB size of the coarse DAC segment and / or the fine DAC segment. For example, if the baseband current level increases or decreases by a given amount due to a change in the baseband gain setting, the LSB current can be adjusted by the same amount to scale the current output range of the current DAC circuit 340. The LSB size can be scaled using known techniques. For example, in an embodiment in which the DAC segment comprises an array of current sources biased using current mirrors with diode-connected transistors coupled to mirror transistors (current sources) in various DAC cells, the effective width of the diode-connected transistors can be scaled (increased or decreased) to change the current mirror ratio and, therefore, the amount of current generated by the mirror transistors. For example, if the effective width of the diode-connected transistors of the current mirror increases by a factor of two (2X), the amount of current generated by the mirror transistors (current sources) decreases by 2X.

[0101] 4A, 4B, and 4C schematically illustrate a current-mode DAC 400 that can be implemented in the current measurement circuit 300 of FIG. 3 according to an exemplary embodiment of the present disclosure. As shown in FIG. 4A, the current-mode DAC 400 comprises a segmented DAC architecture including a prescaler DAC segment 410, a coarse DAC segment 420, a fine DAC segment 430, and a current source 435. The prescaler DAC segment 410 comprises a plurality (e.g., three) of adjustable (i.e., selectable) diode-connected transistors 410-1, 410-2, and 410-3. The coarse DAC segment 420 comprises a plurality (e.g., seven) of current sources 420-1, 420-2, 420-3, 420-4, 420-5, 420-6, and 420-7. Fine DAC segment 430 includes multiple (e.g., 31) current sources 430-1, ..., 430-31. Current source 435 provides an input current (I REF_Cal ) is generated.

[0102] The prescaler DAC segment 410 operates as a diode-connected transistor used to develop bias voltages for the DAC cells, with a width that is programmable with M-bit (e.g., M=3) resolution. The programmable width can be used to prescale the current output level of the current-mode DAC 400 based on the gain setting of the baseband signal input stage 210. In some embodiments, the coarse DAC segment 420 comprises an N-bit (e.g., N=7) binary-weighted current DAC, and the fine DAC segment 430 comprises a P-bit (e.g., P=5) thermometer-coded current DAC (also referred to as unary weighted). The output current of the current-mode DAC 400 is the sum of the current outputs from the coarse DAC segment 420 and the fine DAC segment 430. For a given baseband gain setting, the setting of the prescaler DAC segment 410 remains fixed, while the current outputs of the coarse DAC segment 420 and the fine DAC segment 430 are adjusted to match the magnitude of the baseband current being measured. REF The size of the slit is dynamically adjusted via digital control to adjust the size of the slit (Figure 3).

[0103] In some embodiments, DAC segments 410, 420, and 430 utilize the same unit current cell to reduce mismatch between the currents in DAC segments 410, 420, and 430. FIG. 4B schematically illustrates a unit current cell (1U) 440, according to an exemplary embodiment of the present disclosure, utilized to implement each unit cell of DAC segments 410, 420, and 430. Unit current cell 440 includes PMOS transistors 442, 444, and 446. PMOS transistor 442 has a gate terminal coupled to a first control node Ctrl, a source terminal coupled to a positive power supply node VDD, and a drain terminal coupled to a gate terminal of PMOS transistor 446. PMOS transistor 444 has a gate terminal coupled to a second control node Ctrlb, a source terminal coupled to a gate terminal of PMOS transistor 446, and a drain terminal coupled to node G, which is a gate bias voltage node for current-mode DAC 400. PMOS transistor 446 has its source terminal coupled to the positive power supply node VDD and its drain terminal coupled to the current output node D. Control terminals Ctrl and Ctrlb receive complementary controls that enable or disable the unit cell.

[0104] As shown in FIG. 4A, the prescaler DAC segment 410 is configured to provide an adjustable reference current mirror circuit, with the gate (G) and drain (D) terminals supplying a reference current I REFIt is connected to form an adjustable diode-connected transistor biased by _Cal. In some embodiments, each adjustable diode-connected transistor 410-1, 410-2, and 410-3 of the prescaler DAC segment 410 comprises a plurality of unit current cells 440 of FIG. 4B connected in parallel. For example, in some embodiments, the smallest (e.g., least significant bit, 8X) adjustable diode-connected transistor 410-1 of the prescaler DAC segment 410 comprises eight unit current cells 440 connected in parallel, and the remaining adjustable diode-connected transistors 410-2 and 410-3 are weighted by having an increased number of unit current cells 440. For example, the adjustable diode-connected transistor 410-2 (16X) comprises 16 unit current cells 440 connected in parallel, and so on.

[0105] Furthermore, each current source 420-1, 420-2, 420-3, 420-4, 420-5, 420-6, and 420-7 of the coarse DAC segment 420 comprises a plurality of unit current cells 440 of FIG. 4B connected in parallel. For example, in some embodiments, the smallest (e.g., least significant bit, 1X) current source 420-1 of the coarse DAC segment 420 comprises eight unit current cells 440 connected in parallel, and the remaining binary weighted current sources 420-2, 420-3, 420-4, 420-5, 420-6, and 420-7 have an increased amount of unit current cells 440. For example, the current source 420-2 (with a weight of 2X) comprises 16 unit current cells 440 connected in parallel, and so on.

[0106] Moreover, in some embodiments, each current source 430-1, ..., 430-31 of fine DAC segment 430 comprises a single unit current cell 440 (1U). This configuration provides 4X overlap (2 bits) between binary-weighted coarse DAC segment 420 and thermometer-coded fine DAC segment 430, allowing for 10-bit resolution for current-mode DAC 400, e.g., 7 bits (coarse DAC) + 5 bits (fine DAC) - 2 bits (overlap) = 10 bits. In this exemplary configuration, 10-bit resolution is achieved while a 12-bit control signal is applied to current-mode DAC 400 to take advantage of the 4X overlap and not rely on matching the LSB sizes of coarse and fine DAC segments 420 and 430. As shown in FIG. 4C, the 5-bit digital control signals for the fine DAC segment 430 are input to a decoder 450 to generate a 31-bit control signal Ctrl[30:0] and a 31-bit complementary control signal Ctrlb[30:0] to selectively enable the respective current sources 430-1, ..., 430-31 of the thermometer-coded fine DAC segment 430.

[0107] As described above, LO signal output configuration circuit 180 (FIG. 1) comprises an LO signal driver stage configured to drive the LO inputs of first and second mixer circuits 141 and 142 in mixer stage 140 with either (i) quadrature LO signals for performing I / Q modulation (in normal mode) or (ii) DC voltages configured to selectively enable and disable switching transistors of first and second mixer circuits 141 and 142 for performing DC measurements of baseband currents (in calibration mode). An exemplary embodiment of LO signal output configuration circuit 180 is shown in FIG.

[0108] 5 is a schematic diagram of an LO signal output configuration circuit 500 according to an exemplary embodiment of the present disclosure. The LO signal output configuration circuit 500 generates quadrature LO signals for I / Q modulation when operating in normal mode.

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[0109] More specifically, as shown in FIG. 5, the first LO driver stage 501 includes a buffer stage 510 and an output formation stage 520. The buffer stage 510 includes a CMOS inverter including a PMOS transistor 512 and an NMOS transistor 514 connected in series between a positive power supply voltage node VDD_LO and a negative power supply voltage node VSS. The source terminal of the PMOS transistor 512 is selectively connected to the positive power supply voltage node VDD_LO through a first switch 514-1. The source terminal of the NMOS transistor 514 is selectively connected to the negative power supply voltage node VSS through a second switch 514-2. The PMOS and NMOS transistors 512 and 514 have commonly connected gate terminals coupled to an input node N10 of the first LO driver stage 501. The PMOS and NMOS transistors 512 and 514 have commonly connected drain terminals connected to an output node N11 of the CMOS inverter.

[0110] In some embodiments, the first switch 514-1 has a switch control signal applied to its gate terminal.

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[0111] 5, buffer stage 510 comprises a single CMOS inverter stage, with the output node N11 of the CMOS inverter coupled to or comprising the output node OUT of first LO driver stage 501. In other embodiments, buffer stage 510 is implemented by cascading two CMOS inverters, with the output node N11 of the CMOS inverter connected to the input node of a second CMOS inverter, with the output node of the second CMOS inverter coupled to or comprising the output node OUT of first LO driver stage 501. As is known in the art, the cascaded combination of two CMOS inverters restores the input LO signal to its original phase.

[0112] Output forming stage 520 comprises a first switch 522-1 and a second switch 522-2. The first switch 522-1 is coupled between a positive power supply node VDD_LO and an output node OUT of first LO driver stage 501. The second switch 522-2 is coupled between a negative power supply node VSS and an output node OUT of first LO driver stage 501. In some embodiments, the first switch 522-1 comprises a PMOS transistor controlled by a switch control signal PU1 (or pull-up control signal) applied to its gate terminal, and the second switch 522-2 comprises an NMOS transistor controlled by a switch control signal PD1 (or pull-down control signal) applied to its gate terminal.

[0113] In normal operation, the first LO driver stage 501 generates a quadrature LO signal

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[0114] On the other hand, in the calibration mode of operation, first LO driver stage 501 is configured to output a DC LO signal at a logic "0" level or a logic "1" level. In particular, in the calibration mode, buffer stage 510 controls switch control signals S1 and S2 to disable (open) first switch 514-1 and second switch 514-2.

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[0115] Although FIG. 5 shows an exemplary circuit configuration of first LO driver stage 501 for ease of illustration, second LO driver stage 502, third LO driver stage 503, and fourth LO driver stage 504 have the same circuit configuration and operate similarly to first LO driver stage 501, where in the exemplary embodiment, first LO driver stage 501 is configured to drive LO_I, and second LO driver stage 502 is configured to drive

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[0116] 6 illustrates a table 600 of settings for configuring an RF signal generator system and a calibration system in a calibration mode to measure individual baseband currents, according to an exemplary embodiment of the present disclosure. In particular, FIG. 6 illustrates a table 600 of settings for configuring an RF signal generator system and a calibration system in a calibration mode to measure individual baseband currents, I, generated on first and second output nodes INT_0 and INT_1 of current-commutating mixer stage 220 (FIG. 2), according to an exemplary embodiment of the present disclosure. + , I - , Q + , and Q - 5. How to measure the current by controlling the different states of the first and second switches SW0 and SW1 (of the current measurement circuit 300, FIG. 3) and the quadrature LO signals (generated by programming the LO signal output configuration circuit 500, FIG. 5)

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[0117] As collectively shown in Figures 2, 3, and 5, in calibration mode, the baseband current I + (i) The LO_I signal having a DC voltage of logic "0" (Low) is

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[0118] Additionally, in calibration mode, the baseband current Q + (i) LO_Q signal with a DC voltage of logic "0" (

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[0119] The exemplary table 600 shown in FIG. 6 provides the individual DC baseband currents I + , I - , Q + , and Q - Note that the diagram illustrates different switch configurations in a calibration mode for measuring two DC baseband currents (e.g., I and Q) at a given time by simultaneously enabling the mixer transistors in I mixer 220-1 and Q mixer 220-2 at a given time. + +Q + ) can be measured. It is further noted that the current measurement circuit 300 of FIG. 3, coupled to both output nodes INT_0 and INT_1 of the current commutating mixer stage 220, provides equalized loads on both output nodes INT_0 and INT_1 during normal operation of the RF signal generator system (when the calibration circuit is disabled). Furthermore, the same baseband current (e.g., I + ), while in some embodiments, the calibration process measures the same baseband current on both nodes INT_0 and INT_1 individually for better accuracy, e.g., the baseband current I on node INT_0. + Measure the baseband current I on node INT_1. + and calculating the average of the two baseband current measurements.

[0120] 7A and 7B illustrate a process for calibrating baseband currents in an RF signal generator system according to an exemplary embodiment of the present disclosure. More specifically, FIG. 7A illustrates a flow diagram of an exemplary signal calibration process, and FIG. 7B illustrates waveform diagrams illustrating exemplary modes of operation of a current measurement circuit. For illustrative purposes, FIGS. 7A and 7B may be described in the context of the exemplary embodiments of the RF signal generator and calibration system shown in FIGS. 2 and 3. Referring to FIG. 7A, the calibration process is initiated by the calibration system to calibrate baseband signals (e.g., I / Q signals) of the RF signal generator system (block 700). Depending on a given application of the RF signal generator system, the calibration process may be initiated automatically by the calibration system upon powering up the RF signal generator system. Furthermore, in some embodiments, the calibration process may be performed automatically or manually during an idle operating mode of the RF signal generator system.

[0121] The calibration process includes an initialization phase in which various settings are applied to configure the RF signal generator system and the calibration mode of the calibration system. For example, a digital control signal is applied to the amplifier / attenuator stage at the output of the mixer stage to turn off all transistors in the amplifier / attenuator stage, thus shutting down the amplifier / attenuator stage (step 701). In particular, in the exemplary embodiment of FIG. 2, as discussed above, a logic "1" DC voltage is applied to the gate terminals of all transistors in the signal attenuator stage 230 to turn off all transistors, resulting in a complete turn-off of the signal attenuator stage 230 and thereby reducing the DC baseband current I to be measured. + , I - , Q + , and Q - is routed from the output of the current commutating mixer stage 220 to the current measurement circuit 250 .

[0122] The initialization phase further includes setting the baseband gain of the baseband input stage to a desired level (block 702). As described above, in the exemplary embodiment of FIG. 2, baseband signal input stage 210 includes variable-width transistors 211, 212, 213, and 214 that can be configured to adjust the baseband signal gain in the I / Q signal path. For example, as described above, in some embodiments, the DC baseband current can be adjusted to one of various target current levels over a given range (e.g., a range of about 35 μA to about 350 μA) in which the highest baseband current level is about 10× higher than the lowest baseband current level to provide a 20 dB gain variation. For initialization and baseband signal measurements, transistors 211, 212, 213, and 214 of baseband signal input stage 210 can be set to the lowest gain setting (e.g., the smallest width setting for the lowest baseband current).

[0123] Additionally, the initialization phase includes adjusting the current DAC segments of the current measurement circuit 250 based on the current gain setting of the baseband signal input stage 210 and setting the initial code of the current-mode DAC to a midpoint level (block 703). As described above, in some embodiments, the current-mode DAC (implemented in the current measurement circuit) is configured to operate over the full range of current levels of the DC baseband signal (which depends on the baseband signal gain) to be measured. In this regard, depending on the gain setting of the baseband signal input stage 210, the current sources of the coarse and fine segments of the current DAC can be scaled (e.g., increased or decreased) according to the baseband gain setting to enable proper and accurate measurement of the DC baseband current.

[0124] Next, the calibration process configures the current measurement circuit to allow a target baseband current input to be measured from a given output node of the mixer stage (block 704). For example, in the exemplary embodiment shown in FIG. 3, the current measurement circuit 300 can be configured to input the baseband current on the output node INT_0 by enabling switch SW0 and disabling switch SW2 of the first current sink circuit 310 (while keeping switch SW1 turned off), thereby configuring an active current mirror circuit comprising transistor 312 (in a diode-connected transistor configuration) and mirror transistor 330. Alternatively, the current measurement circuit 300 can be configured to input the baseband current on the output node INT_1 by enabling switch SW1 and disabling switch SW2 of the second current sink circuit 320 (while keeping switch SW0 turned off), thereby configuring an active current mirror circuit comprising transistor 322 and mirror transistor 330 (in a diode-connected transistor configuration).

[0125] Additionally, the LO signal input applied to the mixer in the mixer stage is configured with an appropriate DC voltage such that the mixer stage outputs a target DC baseband current to be measured on a target output node (block 705). For example, as described above, in some embodiments, the mixing transistors of differential I and Q mixers 220-1 and 220-2 in current-commutating mixer stage 220 (FIG. 2) are selectively enabled / disabled by applying a DC LO voltage (logic high or logic low) to the gate terminals of the mixing transistors as needed to output a target DC baseband current to be measured on one of output nodes INT_0 or INT_1 of current-commutating mixer stage 220. For example, as shown in table 600 of FIG. 6, the DC baseband current I + applies a DC LO voltage of logic "0" (low) to the LO_I input of differential I mixer 220-1 and a DC LO voltage of logic "1" to the LO_I input of differential I and Q mixers 220-1 and 220-2.

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[0126] When a DC baseband current flows through current measurement circuit 300, comparator 350 detects the voltage (V IN ) with the reference voltage V REF (e.g., 1 / 2VDD), and the control process will determine (block 706) the initial logic level to be generated at the output of comparator 350. If it is determined (at block 706) that the comparator output is at an initial logic "0" level, this indicates that the DC baseband current (at the midpoint code setting) is equal to the DAC reference current I REF In response, the control process generates and outputs a reference current I from the current DAC circuit 340. REF The control process then adjusts (e.g., increments) the code setting of the current DAC circuit 340 to increase the level of current DAC circuit 340 (block 707). In some embodiments, the DAC code is adjusted using a suitable binary search process to select the next code setting of the current DAC circuit 340. After incrementing the code setting of the current DAC circuit 340, the control process determines whether the comparator output is still at the initial logic "0" level (block 708).

[0127] The code setting of current DAC circuit 340 is incrementally adjusted while the comparator output remains at the initial logic "0" level (repeating blocks 707 and 708) until the output of comparator 350 switches from the initial logic "0" level to a logic "1" level. If the control process determines that the output of comparator 350 is no longer at the initial logic "0" level (a negative decision at block 708), the control process adjusts the reference current I output from current DAC circuit 340 to a logic "1" level. REF is equal to, or at least substantially equal to, the DC baseband current being measured, and the control process will record (e.g., store) the current DAC code setting (block 709), the recorded code setting representing the measurement for the DC baseband current.

[0128] On the other hand, if it is determined (at block 706) that the comparator output is at the initial logic "1" level, this indicates that the DC baseband current is being output from the current DAC circuit 340 (at the midpoint code setting) as the DAC reference current I REF In response, the control process generates and outputs a reference current I from the current DAC circuit 340. REF The control process then adjusts (e.g., decrements) the code setting of the current DAC circuit 340 to decrease the level of current DAC circuit 340 (block 710). In some embodiments, the DAC code is adjusted using a suitable binary search process to select the next code setting of the current DAC circuit 340. After decrementing the code setting of the current DAC circuit 340, the control process determines whether the comparator output is still at the initial logic "1" level (block 711).

[0129] The code setting of current DAC circuit 340 is adjusted by decrementing while the comparator output remains at the initial logic "1" level (repeating blocks 710 and 711) until the output of comparator 350 switches from the initial logic "1" level to a logic "0" level. In particular, if the control process determines that the output of comparator 350 is no longer at the initial logic "1" level (a negative decision at block 711), the control process adjusts the reference current I output from current DAC circuit 340 by REF is equal to, or at least substantially equal to, the DC baseband current being measured, and the control process will record (e.g., store) the current DAC code setting (block 709), the recorded code setting representing the measurement for the DC baseband current.

[0130] Once the code setting is recorded for the measured DC baseband current, the control process determines whether the baseband current measurement is correct for all individual I-phase and Q-phase baseband components I for a given baseband gain setting. + , I - , Q + , and Q - If there are one or more additional DC baseband currents to be measured (a negative determination at block 712), the calibration process flow returns to block 703, where current DAC circuit 340, current sink circuits 310 and 320, and the DC LO input to the mixer stage are initialized and configured, as necessary, to measure the next selected DC baseband current using the same measurement process (blocks 706-711) discussed above.

[0131] DC baseband current measurements are performed on all individual I-phase and Q-phase baseband components I for a given baseband gain setting. + , I - , Q + , and Q -Once completed for (a positive decision at block 712), the control process (for all individual I-phase and Q-phase baseband components I + , I - , Q + , and Q - The next step is to determine whether DC baseband current measurements (for all baseband gain stage settings) have been completed for all baseband gain stage settings (block 713). If there are one or more additional baseband gain stage settings for which DC baseband current needs to be measured (a negative determination at block 713), the calibration process flow returns to block 702, where the baseband gain setting is set to the next gain stage setting, and current DAC circuit 340, current sink circuits 310 and 320, and the DC LO input to the mixer stage are initialized and configured, as necessary, to measure the first selected DC baseband current for the new baseband gain setting using the same measurement process (blocks 706-711) discussed above.

[0132] (All individual I-phase and Q-phase baseband components I + , I - , Q + , and Q - Once DC baseband current measurements (for + , I - , Q + , and Q - The control process then determines, for the selected baseband gain setting, (i) the DC baseband current I + and I - , (ii) DC baseband current Q + and Q - , and (iii) DC baseband current I + and Q +, and proceeds to adjust the code settings of the first and second DC offset compensation DACs 270 and 272 (FIG. 2) as needed to minimize the offset (imbalance) between them (block 714), at which point the calibration process ends (block 715). If the baseband gain setting is subsequently adjusted (increased or decreased), the calibration system will adjust the measured DC baseband current I for the newly adjusted baseband gain setting. + , I - , Q + , and Q - A calibration database can be accessed to determine the most recently recorded current DAC code for

[0133] After the measurement, four digital codes representing the individual DC baseband currents for the four I-phase and Q-phase baseband components (I+, I-, Q+, Q-) are obtained, and the difference between the codes represents the imbalance contributing to the spur (e.g., the offset between I+ and I- represents the DC offset that leads to LO leakage, and the offset between I+ and Q+ represents the amplitude imbalance that degrades the image rejection). In this way, both the image rejection and the LO leakage can be improved through calibration to provide better spur performance for the RF signal generator system.

[0134] 7B is a diagram 720 illustrating an exemplary mode of operation of a current measurement circuit when performing a comparison process to measure a DC baseband current. For illustrative purposes, FIG. 7B will be described in the context of an exemplary comparison process performed by current measurement circuit 300 of FIG. 3. In FIG. 7B, the Y-axis represents voltage in millivolts (mV) ranging from 0 V (e.g., VSS) to 900 mV (e.g., VDD), and the X-axis represents the digital code (e.g., ranging from 0 to 100) of a current DAC for generating a reference current.

[0135] 7B further illustrates exemplary voltage waveforms 722, 724, and 726. The exemplary voltage waveform 722 is a DC reference voltage V applied to the inverting (-) input terminal of the comparator 350.REF For example, the reference voltage V REF is shown to be 450 mV (½VDD). An exemplary voltage waveform 724 is generated on high impedance node N2 and is a function of the input voltage V IN Furthermore, the example voltage waveform 726 represents the input voltage V IN Waveform 724 is a DC reference voltage V REF represents the comparator output voltage generated by comparator 350 by comparing it to

[0136] The comparison process of FIG. 7B compares the reference current I generated by current DAC circuit 340 for a given DC baseband current being measured. REF As the digital code for Δt increases, the DC baseband current being measured and the reference current I output from the current DAC circuit 340 REF The difference between the input voltage V IN The waveform 724 shows an increase in the input voltage V IN Waveform 724 is the DC reference voltage V REF When the comparator output voltage waveform 726 toggles from 0 V (VSS) to 900 mV (VDD), the measurement ends. The reference current I generated by the current DAC circuit 340 toggles the comparator output voltage waveform 726 from logic "0" to logic "1." REF 7B, the digital code value of 70 of current DAC circuit 340 corresponds to the estimated measurement of the DC baseband current.

[0137] The calibration techniques described above, for example, (i) compensate for mismatch between the baseband input transistors 211 and 212 for the I phase (I + and I - (ii) compensate for mismatch between the baseband input transistors 213 and 214 for the Q phase (Q + and Q -(iii) compensate for mismatch between the differential input transistor pair 210-1 and 210-2 (I + and Q + and a static current measurement technique configured to compensate for imbalances between the baseband DC currents, and such calibration is performed such that zero differential voltage is present at the common mode input.

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[0138] However, in real-time operation of an RF signal generator system, there may be a duty-cycle-induced DC offset resulting from a quadrature-phase LO signal that does not have a 50% duty cycle. More specifically, if the LO_I signal and / or the LO_Q signal have a duty cycle less than or higher than 50%, the LO signal may introduce undesired LO tones in the RF output signal of the RF signal generator system due to a non-zero differential average LO current that is inherently injected into the I / Q signal paths, which may result in LO leakage and / or degraded image rejection.

[0139] In this regard, exemplary embodiments of the present disclosure further include calibration circuits and methods for calibrating duty-cycle-induced DC offsets resulting from quadrature-phase LO signals that do not have a 50% duty cycle. In particular, in some embodiments, the calibration system is configured to perform dynamic current measurements by applying a switching LO signal to one of the LO inputs of differential I and Q mixers 220-1 and 220-2 of current-commutating mixer stage 220 of FIG. 2 to generate an upconverted RF current signal by one mixer transistor being driven by the switching LO signal, while applying a static DC voltage of logic “1” to the other LO input of differential I and Q mixers 220-1 and 220-2 of current-commutating mixer stage 220 to turn off the other mixer transistor. For dynamic measurements, as described in further detail below in conjunction with FIGS. 8 and 9, the current measurement circuit is configured to receive as an input the upconverted RF current signal output from current commutating mixer stage 220 and extract and measure the DC component of the upconverted RF current signal.

[0140] 8, for example, schematically illustrates a current measurement circuit 800 implemented by a calibration system to measure the DC component of an upconverted RF current signal, according to an exemplary embodiment of the present disclosure. The current measurement circuit 800 is similar to the current measurement circuit 300 of FIG. 3, except that the current measurement circuit 800 includes a filter circuit 810 configured to remove high frequency components of the upconverted RF current signal output from the mixer stage as a result of applying an AC switching LO input signal (being tested for duty cycle error) to the mixer stage in calibration mode, and input to the current measurement circuit 800 to measure the DC offset of the upconverted RF current signal. The presence of a non-zero DC offset current induced by the switching LO signal is an indication of a duty cycle error in the switching LO signal.

[0141] 8, filter circuit 810 comprises a low-pass RC filter circuit comprising a resistor 812 coupled between nodes N1 and N3, and a capacitor 814 coupled to and between node N3 and a negative power supply node VSS. The gate terminal of mirror transistor 330 is coupled to node N3 (which is the output node of filter circuit 810). In some embodiments, current measurement circuit 250 in FIG. 2 is implemented using current measurement circuit 800 of FIG. 8. In such embodiments, current measurement circuit 800 operates in the same or similar manner as current measurement circuit 300 as discussed above, except that current measurement circuit 800 can be utilized to measure the DC baseband current or the DC offset of the upconverted RF current signal depending on a given calibration mode of operation.

[0142] It should be noted that dynamic baseband current measurements using a switching LO signal can be performed using the same or similar techniques as those discussed above for performing static baseband current measurements. For example, in some embodiments, the parameters shown in table 600 of FIG. 6 can be utilized to perform dynamic current measurements by controlling LO signal output configuration circuit 500 (FIG. 5) and configuring current measurement circuit 800 for a calibration mode, except that a switching LO signal (rather than a static LO voltage) is applied to a given input of the mixing transistor to generate an upconverted RF current signal on one of output nodes INT_0 or INT_1 for input to current measurement circuit 800.

[0143] For example, in calibration mode, the switching LO_I signal (

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[0144] In this example, the DC voltage output from filter circuit 810 on node N3 is equal to the upconverted RF current signal (RF_I + ) time-averaged current (DC offset current), which provides information about the duty cycle of the switching LO_I signal. Current measurement circuit 800 measures the upconverted RF current signal (RF_I) using the same current measurement techniques as discussed above (e.g., FIGS. 7A and 7B). + ) to determine the DC offset of the upconverted RF current signal (RF_I + ) is recorded in the calibration database. In this case, the measured DC offset current will include (i) the DC baseband current (bias current) originating from the baseband signal input stage 210 and (ii) the DC offset current (if any) resulting from the duty cycle error (if any) of the switching LO signal.

[0145] Other upconverted RF current signals (e.g., RF_I, LO_Q) are generated as a result of the associated switching LO_I and LO_Q signals applied to current commutating mixer stage 220. - , RF_Q + , and RF_Q - Similar dynamic baseband current measurements can be performed separately to determine the DC offset of each upconverted RF current signal (e.g., RF_I - , RF_Q + , and RF_Q - The digital codes of the current DAC circuit 340, which represent the measured DC offset currents of the LO duty cycle error, are recorded in a calibration database. These digital codes can be used to obtain information about the DC offset currents that occur as a result of the LO duty cycle error. For example, (i) the measured DC baseband current I + and (ii) a digital DAC code representing the upconverted RF current signal RF_I + The difference between the digital DAC codes representing the measured DC offset currents for LO_I and LO_I can provide relevant information regarding the amount of LO_I duty cycle error. In some embodiments, the duty cycle induced imbalance is resolved by using first and second DAC circuits 121 and 122 (FIG. 1) to calculate the fundamental baseband signal component I + and Q + Note that this can be corrected by adjusting

[0146] 9, which schematically illustrates a current measurement circuit implemented by a calibration system to measure the DC component of an upconverted RF current signal according to another exemplary embodiment of the present disclosure. Current measurement circuit 900 is similar to current measurement circuit 800 of FIG. 8 , except that current measurement circuit 900 includes a filter circuit 910 coupled to high-impedance node N2 to remove high-frequency components. In some embodiments, filter circuit 910 includes a low-pass filter including a capacitor 912 coupled to and between node N2 and negative power supply node VSS. Current measurement circuit 900 operates in a manner similar to current measurement circuits 300 and 800 as discussed above. The implementation of filter circuit 910 at high-impedance node N2 serves to reduce swing and improve measurement accuracy.

[0147] It should be appreciated that the exemplary calibration systems, circuits, and methods discussed herein offer significant advantages over conventional techniques commonly utilized for calibrating RF signal generators and the like. For example, as described above, conventional techniques include RF measurement techniques that utilize on-chip or off-chip equipment configured to analyze an RF signal generated by an RF signal generator using, for example, a complex spectrum analyzer or a downconversion receiver (in a feedback loop) to extract baseband signal components from the RF signal and calibrate a DAC to compensate for imbalances detected in the extracted baseband signal components. Conventional RF measurement techniques are costly in terms of complexity, resource usage, and area overhead required for on-chip implementation. Additionally, such conventional RF techniques consume a significant amount of power that is prohibitive at cryogenic temperatures.

[0148] In contrast to conventional calibration techniques that perform RF measurements, the exemplary calibration techniques as disclosed herein utilize DC baseband current measurements, which are much easier and less time-consuming to perform than RF measurements. In addition, the exemplary DC baseband current measurement techniques as discussed herein are significantly less costly in terms of hardware complexity and resources compared to using on-chip spectrum analyzers or loopback receivers to detect signal imbalance. In addition, the DC current measurement hardware and other calibration-related hardware can operate at very low power (e.g., on the order of milliwatts), and such hardware has a relatively low footprint (occupies a small chip area), which is advantageous for on-chip implementation.

[0149] Another advantage that should be noted is that the same current measurement hardware (e.g., current measurement circuits such as those shown in FIGS. 3, 8, and 9) can measure all I-phase and Q-phase baseband components I + , I - , Q + , Q - In this regard, the current measurement is insensitive to the inherent offset of the current measurement equipment, so that inaccuracies in the current measurement hardware do not adversely affect the accuracy of the measurement. For example, the same current measurement hardware can measure all I-phase and Q-phase baseband components I + , I - , Q + , Q - Because the baseband currents are utilized to measure DC currents for {I}, in the absence of drift, any inherent offset in the circuit, e.g., comparator offset, will be applied to all DC current measurements, thereby effectively canceling out such inherent errors in the DC current measurements. In this regard, the measurement equipment does not need high absolute accuracy to ensure that all baseband currents are equal to one another, since any inherent errors in the measurements will be offset by {I}. + ,I -}, {Q + ,Q -}, and {I+ ,Q +}, so as not to affect the ability of the calibration process to correct for imbalances in the I / Q baseband currents by equalizing the baseband currents.

[0150] Moreover, the same calibration hardware is utilized to calibrate both the LO leakage and the image rejection. In addition, all I-phase and Q-phase baseband components I + , I - , Q + , Q - Since the same hardware is utilized to measure the DC current for and correct the imbalance for, the overall area required for the calibration instrument is significantly reduced. For example, in the case of an on-chip instrument, all I-phase and Q-phase baseband components I + , I - , Q + , Q - Utilizing the same calibration hardware to measure σ allows for a reduced area overhead, eg, less than 10%, required for on-chip devices.

[0151] Another advantage that should be noted is that the baseband signal is sensed at a low impedance node (e.g., nodes INT_0 and INT_1, FIG. 2) at the output of the current-mode stage of the RF signal generator system, which helps to minimize the loading effect of the current measurement circuitry and therefore minimize any reduction in bandwidth during normal mode operation of the RF signal generator system.

[0152] 2, in which a current measurement circuit is coupled to the output node of current-commutating mixer stage 220, the voltage headroom across the transistors in baseband signal input stage 210 and current-commutating mixer stage 220 can be maintained roughly the same, ensuring that in calibration mode, DC baseband currents are measured under conditions that match those under normal operating mode. In other words, the architecture shown in FIG. 2 maintains similar voltage headroom across the baseband and mixer transistors in both normal and calibration modes.

[0153] Another advantage that should be noted is that the current measurement circuitry can accommodate a wide range of reference currents I in order to perform a highly accurate current comparison between the baseband current being measured and the reference current. REF the reference current I with the desired resolution over a REF The advantage of this approach is that it utilizes a wide-range, high-resolution current-mode DAC having coarse and fine DAC segments to generate the output reference current I. Additionally, as described above, to support wide-range scaling, the current-mode DAC implements a prescaler DAC segment that is used to scale the output range of the current-mode DAC, thereby reducing the output reference current I generated by the current-mode DAC. REF can be scaled to be equivalent to the amplitude level of the baseband current to be measured, thereby allowing DC measurements to be performed at higher and lower amplitude levels (e.g., variations can be performed over a 10X range, such as 35 μA to 350 μA).

[0154] Another advantage to note is that current imbalances detected by the calibration system are corrected using a current imbalance correction circuit configured to inject additional current into the baseband signal path. For example, LO leakage calibration control is provided by adjusting the digital code of an offset control DAC located at the output of the baseband stage. The same offset control DAC can be used to equalize the I and Q currents. If gain adjustment is required between channels, the reference currents for the I and Q DACs can be adjusted.

[0155] Another advantage that should be noted is that exemplary calibration circuits as described herein are configured to operate at low power (e.g., in the milliwatt range) and with low area overhead, thereby enabling such calibration circuits to be easily implemented as on-chip calibration equipment for calibrating cryoelectronics used for quantum computing applications and other applications or systems operating at cryogenic temperatures. For example, in the context of a quantum computing system implementing superconducting qubits and other components, exemplary calibration circuits as described herein can be easily implemented on-chip with an AWG system. In such embodiments, the on-chip calibration equipment is utilized to calibrate the AWG system to generate high-fidelity RF control pulses that control the superconducting qubits and thereby achieve high-fidelity qubit gate operations (e.g., single-qubit gate operations, entanglement gate operations, etc.). In particular, exemplary calibration techniques as discussed herein can be utilized to generate high-fidelity RF control pulses that are free of or significantly suppressed from LO leakage and sideband image spurs that would otherwise lead to lower-fidelity gate operations.

[0156] 10 schematically illustrates a quantum computing system 1000 implementing an arbitrary waveform generator system and calibration circuitry according to an exemplary embodiment of the present disclosure. Quantum computing system 1000 includes an arbitrary waveform generator system 1002 (or AWG system 1002) and a quantum processor 1004. Quantum processor 1004 includes a plurality (n) of superconducting qubits 1006-1, ..., 1006-n. Superconducting qubits 1006-1, ..., 1006-n may include superconducting transmon qubits, superconducting fluxonium qubits, superconducting multimode qubits, and other types, or combinations of different types, of superconducting qubits suitable for a given application. Additionally, in some embodiments, quantum processor 1004 includes coupler circuits (e.g., passive coupler circuits and / or active coupler circuits), where a given coupler circuit is configured to couple pairs of superconducting qubits to implement an entanglement gate operation (e.g., a two-qubit gate operation).

[0157] Quantum processor 1004 further comprises a plurality of control lines (e.g., transmission line resonators), including, but not limited to, qubit drive lines, flux bias lines, state readout lines, and active coupler drive lines. In some embodiments, a qubit drive line is coupled (e.g., capacitively coupled) to each of superconducting qubits 1006-1, ..., 1006-n. The qubit drive lines are configured to apply RF control pulses (generated by AWG system 1002) to each superconducting qubit 1006-1, ..., 1006-n to independently alter the state of each superconducting qubit (e.g., single-qubit gate operation), e.g., to alter the state of a given superconducting qubit, e.g., to be in a ground state |0>, an excited state |1>, or a superposition state. As is known in the art, the state of a superconducting qubit can be determined by a qubit transition frequency (f 01 The transition frequency f can be changed by applying an RF control pulse with a center frequency equal to 01corresponds to the energy difference between the ground state |0> and the excited state |1> of the qubit. In some embodiments, superconducting qubits 1006-1, ..., 1006-n are configured to have different operating frequencies (transition frequencies) such that the transition frequencies of neighboring qubits are detuned.

[0158] A state readout line is coupled to each of the superconducting qubits 1006-1, ..., 1006-n to read out the state of the superconducting qubit using known techniques (e.g., distributed readout). In embodiments in which the superconducting qubits include frequency-tunable qubits (e.g., flux-tunable transmon qubits or fluxonium qubits, etc.), a flux bias control line would be coupled (e.g., inductively coupled) to each superconducting qubit to apply a flux bias control signal to the tuning structure of the superconducting qubit to tune the operating frequency of the tunable qubit, as needed for a given application. Additionally, in the case of active coupler circuits, a coupler drive line would be coupled (e.g., capacitively coupled) to each coupler circuit, and each coupler circuit would have an operating frequency or transition frequency. A given coupler circuit enables exchange coupling between superconducting qubits coupled through the given coupler circuit and is driven by RF control pulses generated by AWG system 1002, or some other pulse signal generator, to implement two-qubit gate operations.

[0159] 10, AWG system 1002 comprises a multi-channel AWG framework comprising a plurality of AWG channels 1002-1, ..., 1002-c. AWG channels 1002-1, ..., 1002-c are configured to generate RF control pulses that are applied onto qubit drive lines to control respective ones of superconducting qubits 1006-1, ..., 1006-n. Although not specifically shown in FIG. 10, in some embodiments, AWG system 1002 will include an AWG channel for generating control signals that are applied to coupler drive lines to control active coupler devices of quantum processor 1004.

[0160] AWG channels 1002-1, ..., 1002-c each include a respective control pulse envelope generator 1010, a DAC stage 1020, a baseband filter stage 1030, an I / Q mixer stage 1040, an amplifier / attenuator stage 1050, a matching network 1060, an LO signal generator circuit 1070, and an LO signal output configuration circuit 1080. Control pulse envelope generator 1010 is configured to implement a pulse shaping technique to generate RF control pulses with a desired control pulse envelope shape (e.g., Gaussian pulse, cosine pulse (e.g., sum of half cosines), hyperbolic secant pulse, etc.) that are applied to superconducting qubits or active qubit coupler circuits to perform single-qubit gate operations, entanglement gate operations, etc. The shaped control pulses are used to generate RF control pulses with a desired control pulse envelope shape (e.g., Gaussian pulse, cosine pulse (e.g., sum of half cosines), hyperbolic secant pulse, etc.) that are applied to superconducting qubits or active qubit coupler circuits to perform single-qubit gate operations, entanglement gate operations, etc. 01 driving the transition, while f 12 and higher order transitions. Essentially, such pulse shaping techniques suppress / reduce transients associated with turning on and off control pulses. Additionally, pulse shaping techniques include DRAG (derivative removal by adiabatic gate) correction pulses, which can be used in conjunction with shaped pulses (such as Gaussian, cosine, or hyperbolic secant pulses) to further suppress undesired state transitions while maintaining the same pulse envelope area (or integral of the pulse envelope).

[0161] In each AWG channel of AWG system 1002, the digital control pulse envelope signal (digital I and Q components) is converted to an analog control pulse envelope signal (analog baseband I / Q signal), and I / Q mixer stage 1040 modulates a quadrature LO signal using the baseband I / Q signal, e.g., by performing SSB modulation as discussed above, to generate a modulated signal in the form of an RF control pulse that is applied onto a qubit drive line to control a given qubit. The functionality of the various stages 1020, 1030, 1050, 1060, 1070, and 1080 is the same as or similar to the corresponding stages in Figures 1, 2, etc., and these details will not be repeated.

[0162] 10 , in some embodiments, each AWG channel 1002-1, ..., 1002-c of the AWG system 1002 comprises dedicated calibration circuitry 1090-1, ..., 1090-c implemented on-chip with the AWG system 1002. The calibration circuitry 1090-1, ..., 1090-c is configured to calibrate the I / Q signal currents for each AWG channel 1002-1, ..., 1002-c of the AWG system 1002 when the AWG channels 1002-1, ..., 1002-c are configured in calibration mode, as discussed above. The calibration circuitry 1090-1, ..., 1090-c comprises hardware control and logic circuitry (e.g., current measurement circuitry, current-mode DACs, control logic circuitry, current imbalance correction circuitry, etc.), as discussed above. In some embodiments, calibration circuits 1090-1, . . . , 1090-c are controlled by software running on a computing platform that controls quantum computing system 1000.

[0163] For example, Figure 11 schematically illustrates a quantum computing system according to another exemplary embodiment of the present disclosure. In particular, Figure 11 schematically illustrates a quantum computing system 1100 comprising a quantum computing platform 1110, a control system 1120, and a quantum processor 1130. In some embodiments, the quantum computing platform 1110 implements a software control program, such as a calibration control process 1112, that performs functions such as configuring the AWG system and calibration circuitry to enter a calibration mode, controlling the execution of high-level functions of the calibration process, etc.

[0164] Additionally, quantum computing platform 1110 performs calibration procedures that are periodically performed on quantum systems such as quantum processors to calibrate various quantum elements such as readout resonators, data qubits, and coupler circuits to enable high-fidelity gate operations (e.g., single-qubit gate operations and entangled gate operations). For example, various types of in-situ calibration procedures are periodically performed to, e.g., determine the resonant frequency of a readout resonator, determine the transition frequency of a qubit, determine the coherence time (T) of a qubit (the coherence time T of a given qubit indicates the time it takes for a qubit state to decay from an excited state to a ground state), determine the transverse relaxation time (T) (or phase relaxation time) of a qubit, calibrate RF control pulses applied to a qubit to perform single-qubit gate operations, calibrate RF control pulses applied to active coupler circuits to perform entangled gate operations, etc. The calibration procedure results in the determination of various control parameters that are maintained in a calibration database and updated periodically, on the order of seconds, minutes, hours, days, etc., as needed, depending on the type of quantum device and the operating characteristics of the quantum computing system, and other factors as will be understood by those skilled in the art.

[0165] In some embodiments, control system 1120 comprises a multi-channel arbitrary waveform generator 1122 and a qubit readout control system 1124. (FIG. 10 schematically illustrates an exemplary AWG system 1002 that may be implemented in control system 1120.) Quantum processor 1130 comprises a solid-state semiconductor chip having a superconducting qubit array 1132 and a network of qubit drive lines, coupler drive lines, and qubit state readout lines 1134, as well as other circuit QED components that may be required for a given application or quantum system configuration.

[0166] In some embodiments, control system 1120 and quantum processor 1130 are disposed in a dilution refrigeration system 1140 that can generate cryogenic temperatures sufficient to operate the components of control system 1120 for quantum computing applications. For example, quantum processor 1130 may need to be cooled near absolute zero, e.g., 10-15 millikelvin (mK), to enable superconducting qubits to exhibit quantum behavior. In some embodiments, dilution refrigeration system 1140 includes a multi-stage dilution refrigerator that can maintain the components of control system 1120 at different cryogenic temperatures as needed. For example, quantum processor 1130 may need to be cooled to, e.g., 10-15 mK, while circuit components of control system 1120 may operate at cryogenic temperatures higher than 10-15 mK (e.g., cryogenic temperatures in the range of 3 K to 4 K), depending on the configuration of the quantum computing system.

[0167] In some embodiments, superconducting qubit array 1132 includes a plurality of superconducting transmon qubits and superconducting tunable coupler qubits, where each pair of superconducting qubits is connected by a respective superconducting qubit coupler using techniques as discussed herein. A network 1134 of qubit drive lines, flux bias lines, coupler drive lines, and qubit state readout lines, etc., is configured to apply microwave control signals to the superconducting qubit and coupler circuits in superconducting qubit array 1132 to perform various types of gate operations, e.g., single gate operations, entanglement gate operations, etc., and to read out the quantum states of the superconducting qubits. Network 1134 of qubit drive lines, flux bias lines, coupler drive lines, and qubit state readout lines, etc., is coupled to control system 1120 via a suitable hardware input / output (I / O) interface that couples I / O signals between control system 1120 and quantum processor 1130. For example, the hardware I / O interface may include various types of hardware and components such as RF cables, wiring, RF elements, optical fibers, heat exchangers, filters, amplifiers, isolators, and the like.

[0168] Quantum computing platform 1110 includes a software and hardware platform including various software layers configured to perform various functions, including, but not limited to, creating and implementing various quantum applications using a suitable quantum programming language, configuring and implementing various quantum gate operations, compiling quantum programs into quantum assembly language, implementing and utilizing a suitable quantum instruction set architecture (ISA), performing calibration operations to calibrate quantum circuit elements and gate operations, etc. In addition, quantum computing platform 1110 includes a hardware architecture, such as a processor, memory, etc., configured to control the execution of quantum applications and interface with control system 1120 to (i) generate digital control signals that are converted to analog microwave control signals by control system 1120 to control the operation of quantum processor 1130 when executing a given quantum application, and (ii) acquire and process digital signals received from control system 1120 that represent processing results generated by quantum processor 1130 when performing the various gate operations for the given quantum application. In some demonstrative embodiments, quantum computing platform 1110 of quantum computing system 1100 may be implemented using any suitable computing system architecture (e.g., as shown in FIG. 12 ) configured to implement methods for supporting quantum computing operations by executing computer-readable program instructions embodied on a computer program product including a computer-readable storage medium (or media) having such computer-readable program instructions for causing a processor to perform control methods as discussed herein.

[0169] Various aspects of the present disclosure are described through text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. For any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in successive flowchart blocks may be performed in reverse order, as a single integrated step, simultaneously, or in an at least partially overlapping manner.

[0170] A computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media (also referred to as "media") collectively included in a set of one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. The computer-readable storage medium may be, but is not limited to, an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random-access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (e.g., punch cards or pits / lands formed on a major surface of a disk), or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, is not to be construed as storage in the form of a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through fiber optic cables, electrical signals communicated through wires, and / or other transmission media.As will be appreciated by those skilled in the art, data is typically moved at some infrequent time during the normal operation of a storage device, such as during access, defragmentation, or garbage collection, but the above does not make the storage device temporary, as the data is not temporary while it is stored.

[0171] The computing environment 1200 includes an example of an environment for executing at least a portion of the computer code involved in performing the methods of the present invention, such as the calibration process control code 1226 for controlling the calibration process as shown in FIG. 7A. In addition to block 1226, computing environment 1200 includes, for example, a computer 1201, a wide area network (WAN) 1202, an end user device (EUD) 1203, a remote server 1204, a public cloud 1205, and a private cloud 1206. In this embodiment, computer 1201 includes a processor set 1210 (including processing circuitry 1220 and cache 1221), a communications fabric 1211, volatile memory 1212, persistent storage 1213 (including an operating system 1222 and block 1226 as identified above), a peripheral device set 1214 (including a user interface (UI), a device set 1223, storage 1224, and an Internet of Things (IoT) sensor set 1225), and a network module 1215. Remote server 1204 includes a remote database 1230. The public cloud 1205 includes a gateway 1240, a cloud orchestration module 1241, a set of host physical machines 1242, a set of virtual machines 1243, and a set of containers 1244.

[0172] Computer 1201 may take the form of a desktop computer, a laptop computer, a tablet computer, a smartphone, a smartwatch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database, such as remote database 1230. As is well understood in the art of computer technology, and depending on the technology, execution of a computer-implemented method may be distributed among multiple computers and / or among multiple locations. While in this presentation of computing environment 1200, to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 1201. Although computer 1201 is not depicted in the cloud of FIG. 12, it may be located in a cloud. However, computer 1201 is not required to reside within a cloud except to any extent that may be expressly indicated.

[0173] Processor set 1210 includes one or more computer processors of any type now known or later developed. Processing circuitry 1220 may be distributed across multiple packages, e.g., multiple coordinated integrated circuit chips. Processing circuitry 1220 may implement multiple processor threads and / or multiple processor cores. Cache 1221 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on processor set 1210. Cache memory is typically organized into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all caches for a processor set may be located “off-chip.” In some computing environments, processor set 1210 may be designed to operate with qubits and perform quantum computing.

[0174] Computer-readable program instructions are typically loaded onto computer 1201 to cause a series of operational steps to be performed by processor set 1210 of computer 1201, thereby implementing a computer-implemented method, whereby the instructions so executed instantiate the method specified in the flowcharts and / or descriptions of the computer-implemented method contained herein (collectively referred to as the "methods of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 1221 and other storage media discussed below. The program instructions and associated data are accessed by processor set 1210 to control and direct the execution of the methods of the present invention. In computing environment 1200, at least some of the instructions for implementing the methods of the present invention may be stored in block 1226 within persistent storage 1213.

[0175] Communications fabric 1211 is the signal-conducting pathway that allows various components of computer 1201 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as buses, bridges, switches and conductive pathways that make up physical input / output ports, etc. Other types of signal communication pathways, such as fiber optic and / or wireless communication pathways, may also be used.

[0176] Volatile memory 1212 may be any type of volatile memory now known or later developed. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory is characterized by random access, although this is not required unless expressly stated. In computer 1201, volatile memory 1212 is located in a single package and is internal to computer 1201, although alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 1201.

[0177] Persistent storage 1213 is any form of non-volatile storage for a computer, now known or developed in the future. The non-volatility of this storage means that stored data remains whether or not power is supplied to computer 1201 and / or to persistent storage 1213 directly. Persistent storage 1213 may be read-only memory (ROM), but typically at least a portion of persistent storage allows data to be written, data to be erased, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 1222 may take several forms, such as various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems that utilize a kernel. The code contained in block 1226 typically includes at least a portion of the computer code involved in performing the methods of the present invention.

[0178] Peripheral device set 1214 includes a set of peripheral devices of computer 1201. Data communication connections between peripheral devices and other components of computer 1201 may be implemented in various ways, such as Bluetooth connections, Near-Field Communication (NFC) connections, connections made by cable (such as a universal serial bus (USB)-type cable), insertion-type connections (e.g., a secure digital (SD) card), connections made over a local area communication network, and even connections made over a wide area network such as the Internet. In various embodiments, UI device set 1223 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage 1224 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. Storage 1224 may be persistent and / or volatile. In some embodiments, storage 1224 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 1201 is required to have a large amount of storage (e.g., computer 1201 stores and manages large databases locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. IoT sensor set 1225 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another sensor may be a motion detector.

[0179] Network module 1215 is a collection of computer software, hardware, and firmware that enables computer 1201 to communicate with other computers over WAN 1202. Network module 1215 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of network module 1215 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of network module 1215 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for implementing the methods of the present invention can typically be downloaded to computer 1201 from an external computer or external storage device through a network adapter card or network interface included in network module 1215.

[0180] WAN 1202 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances by any technology for communicating computer data, now known or later developed. In some embodiments, a WAN may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0181] End-user device (EUD) 1203 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 1201) and may take any of the forms discussed above in connection with computer 1201. EUD 1203 typically receives useful and useful data from the operation of computer 1201. For example, in the hypothetical case where computer 1201 is designed to provide recommendations to the end user, the recommendations would typically be communicated from network module 1215 of computer 1201 over WAN 1202 to EUD 1203. In this manner, EUD 1203 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 1203 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0182] Remote server 1204 is any computer system that provides at least some data and / or functionality to computer 1201. Remote server 1204 may be controlled and used by the same entity that operates computer 1201. Remote server 1204 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 1201. For example, in the hypothetical case where computer 1201 is designed and programmed to provide recommendations based on historical data, this historical data may be provided to computer 1201 from remote database 1230 of remote server 1204.

[0183] Public cloud 1205 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer functionality, particularly data storage (cloud storage) and computing power, without direct active management by users. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct active management of public cloud 1205's computing resources is performed by computer hardware and / or software in cloud orchestration module 1241. Computing resources provided by public cloud 1205 are typically implemented by virtual computing environments running on various computers that comprise host physical machine set 1242, which is the universe of physical computers in and / or available to public cloud 1205. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 1243 and / or containers from container set 1244. It is understood that these VCEs may be stored as images and may be transferred among and between various physical machine hosts as images or after instantiation of the VCE. Cloud orchestration module 1241 manages the transfer and storage of images, deploys new instantiations of VCEs, and manages active instantiations of VCE deployments. Gateway 1240 is a collection of computer software, hardware, and firmware that enables public cloud 1205 to communicate over WAN 1202.

[0184] Some further explanation of virtualized computing environments (VCEs) will now be provided. A VCE can be stored as an "image." A new, active instance of a VCE can be instantiated from the image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to a feature of an operating system in which the kernel allows the existence of multiple isolated user space instances called containers. These isolated user space instances typically behave as actual computers from the perspective of programs running in them. A computer program running on a normal operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and of the devices assigned to the container; this feature is known as containerization.

[0185] Private cloud 1206 is similar to public cloud 1205, except that the computing resources are available only for use by a single enterprise. While private cloud 1206 is shown as communicating with WAN 1202, in other embodiments, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often each implemented by a different vendor. While each of the multiple clouds remains a separate, discrete entity, the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both public cloud 1205 and private cloud 1206 are part of a larger hybrid cloud.

[0186] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a current measurement circuit configured to measure a first current in a first signal path of the radio frequency signal generator and to measure a second current in a second signal path of the radio frequency signal generator during a calibration process; and a current imbalance correction circuit configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current. A device comprising:

2. a control circuit configured to determine a difference between the measured first current and the measured second current, generate a control signal based on the determined difference between the measured first current and the measured second current, and output the control signal to the current imbalance correction circuit; 10. The device of claim 9, wherein in response to the control signal, the current imbalance correction circuit is configured to inject a current into at least one of the first signal path and the second signal path of the radio frequency signal generator to compensate for the determined difference between the measured first current and the measured second current.

3. 10. The device of claim 1, wherein the first current and the second current comprise one of an in-phase baseband current and a quadrature-phase baseband current, a pair of complementary in-phase baseband currents, and a pair of complementary quadrature-phase baseband currents.

4. The current measurement circuit a current-mode digital-to-analog converter circuit configured to generate a reference current; and a current comparator circuit configured to receive one of the first current and the second current as an input current to be measured, compare the reference current with the input current, and generate a comparison output signal; having 10. The device of claim 1, wherein the current-mode digital-to-analog converter circuit is configured to one of increase and decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the input current.

5. The current measurement circuit a current-mode digital-to-analog converter circuit configured to generate a reference current; and a current comparator circuit including a current mirror circuit configured to receive one of the first current and the second current as an input current to be measured and to generate a mirrored version of the input current; having the current comparator circuit is configured to compare the reference current with the mirrored version of the input current and generate a comparison output signal; 10. The device of claim 1, wherein the current-mode digital-to-analog converter circuit is configured to one of increase and decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the mirrored version of the input current.

6. The current comparator circuit a first transistor having a drain terminal coupled to an input node of the current comparator circuit, a source terminal coupled to a power supply node, and a gate terminal coupled to a first node; a first switch coupled between the input node and the first node; a second switch coupled between the first node and the power supply node; a second transistor including a gate terminal coupled to the first node, a source terminal coupled to the power supply node, and a drain terminal coupled to a second node; and a voltage comparator including a first input terminal coupled to a threshold voltage node and a second input terminal coupled to the second node; Including; an output of the current-mode digital-to-analog converter circuit coupled to the second node; 10. The device of claim 9, wherein during the calibration process, the first switch is enabled to configure the first transistor as a diode-connected transistor by coupling the gate terminal and the drain terminal of the first transistor, and the second switch is disabled to allow the input current to flow to the current measurement circuit.

7. the current comparator circuit further includes a low pass filter circuit configured to enable the current comparator circuit to measure a direct current (DC) offset component of an alternating current (AC) input current; 10. The device of claim 9, wherein the low pass filter circuit is one of: (i) coupled between the first node and the gate terminal of the second transistor; and (ii) coupled to the second input terminal of the voltage comparator.

8. a radio frequency signal generator configured to convert a baseband signal to a radio frequency signal, the radio frequency signal generator having a first signal path for processing a first signal component of the baseband signal and a second signal path for processing a second signal component of the baseband signal; and a calibration system configured to perform a calibration process to calibrate the radio frequency signal generator; A system comprising: The calibration system comprises: a current measurement circuit configured to measure a first current in the first signal path of the radio frequency signal generator and to measure a second current in the second signal path of the radio frequency signal generator during the calibration process; and a current imbalance correction circuit configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current. A system having:

9. the calibration system further comprising a control circuit configured to determine a difference between the measured first current and the measured second current, generate a control signal based on the determined difference between the measured first current and the measured second current, and output the control signal to the current imbalance correction circuit; 10. The system of claim 9, wherein in response to the control signal, the current imbalance correction circuit is configured to inject a current into at least one of the first signal path and the second signal path of the radio frequency signal generator to compensate for the determined difference between the measured first current and the measured second current.

10. The current imbalance correction circuit a first current-mode digital-to-analog converter circuit configured to output a first current in the first signal path; and a second current-mode digital-to-analog converter circuit configured to output a second current in the second signal path; 10. A system according to any one of the two preceding claims, comprising:

11. the baseband signal is a quadrature baseband signal including an in-phase signal component and a quadrature-phase signal component; the first signal path is configured to process the in-phase signal component; 10. A system according to any one of the three preceding claims, wherein the second signal path is configured to process the quadrature signal component.

12. the radio frequency signal generator having a plurality of current-mode stages including a baseband input stage, a mixer stage coupled to an output node of the baseband input stage, and an attenuation stage coupled to an output node of the mixer stage; the current measurement circuit is coupled to the output node of the mixer stage; 10. The system of claim 9, wherein during the calibration process, the baseband input stage is configured to output static baseband currents in the first signal path and the second signal path, and the attenuation stage is turned off to allow the first current and the second current to flow from at least one output node of the mixer stage to an input of the current measurement circuit.

13. the baseband input stage is configured to include a variable gain that can be adjusted to a target gain setting over a range of gain settings; 10. The system of claim 9, wherein the current measurement circuitry includes a current measurement range that is scalable to match full-scale current levels of the first current and the second current, the full-scale current being a function of the target gain setting.

14. 10. The system of claim 9, wherein during the calibration process, the mixer stage is configured by applying a static voltage to a local oscillator input of the mixer stage to selectively enable one transistor in the mixer stage at a given time to output one of the first current and the second current on the at least one output node of the mixer stage at the given time.

15. 10. The system of claim 9, wherein during the calibration process, the mixer stage is configured by applying a switching local oscillator signal to at least one local oscillator input of the mixer stage to selectively enable one transistor in the mixer stage at a given time, applying a static voltage to another local oscillator input of the mixer stage to selectively disable another transistor in the mixer stage at the given time, and outputting one of the first current and the second current on the at least one output node of the mixer stage at the given time.

16. The current measurement circuit a current-mode digital-to-analog converter circuit configured to generate a reference current; and a current comparator circuit configured to receive one of the first current and the second current as an input current to be measured, compare the reference current with the input current, and generate a comparison output signal; having 10. The system of claim 8, wherein the current-mode digital-to-analog converter circuit is configured to one of increase and decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the input current.

17. The current measurement circuit a current-mode digital-to-analog converter circuit configured to generate a reference current; and a current comparator circuit including a current mirror circuit configured to receive one of the first current and the second current as an input current to be measured and to generate a mirrored version of the input current; having the current comparator circuit is configured to compare the reference current with the mirrored version of the input current and generate a comparison output signal; 10. The system of any one of the nine preceding claims, wherein the current-mode digital-to-analog converter circuit is configured to one of increase and decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the mirrored version of the input current.

18. a quantum processor having at least one superconducting qubit; an arbitrary waveform generator system having at least one arbitrary waveform generator channel configured to convert a baseband signal into radio frequency control pulses that control the at least one superconducting qubit, the at least one arbitrary waveform generator channel including a first signal path for processing a first signal component of the baseband signal and a second signal path for processing a second signal component of the baseband signal; and a calibration system configured to perform a calibration process to calibrate the at least one arbitrary waveform generator channel; A system comprising: The calibration system comprises: a current measurement circuit configured to measure a first current in the first signal path of the at least one arbitrary waveform generator channel and to measure a second current in the second signal path of the at least one arbitrary waveform generator channel during the calibration process; and a current imbalance correction circuit configured to adjust a current level in at least one of the first signal path and the second signal path of the at least one arbitrary waveform generator channel to correct for an imbalance between the measured first current and the measured second current. A system having:

19. the calibration system further comprising a control circuit configured to determine a difference between the measured first current and the measured second current, generate a control signal based on the determined difference between the measured first current and the measured second current, and output the control signal to the current imbalance correction circuit; 10. The system of claim 9, wherein in response to the control signal, the current imbalance correction circuit is configured to inject a current into at least one of the first signal path and the second signal path of the at least one arbitrary waveform generator channel to compensate for the determined difference between the measured first current and the measured second current.

20. The current measurement circuit a current-mode digital-to-analog converter circuit configured to generate a reference current; and a current comparator circuit configured to receive one of the first current and the second current as an input current to be measured, compare the reference current with the input current, and generate a comparison output signal; having 10. The system of claim 9, wherein the current-mode digital-to-analog converter circuit is configured to one of increase and decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the input current.

21. the at least one arbitrary waveform generator channel having a plurality of current-mode stages including a baseband input stage, a mixer stage coupled to an output node of the baseband input stage, and an attenuation stage coupled to an output node of the mixer stage; the current measurement circuit is coupled to the output node of the mixer stage; 10. The system of claim 9, wherein during the calibration process, the baseband input stage is configured to output static baseband currents in the first signal path and the second signal path, and the attenuation stage is turned off to allow the first current and the second current to flow from at least one output node of the mixer stage to an input of the current measurement circuit.

22. 1. A computer program product for executing a calibration process for calibrating a radio frequency signal generator, the computer program product comprising: One or more computer-readable storage media and program instructions collectively stored on said one or more computer-readable storage media wherein the program instructions include: program instructions that configure a current measurement circuit to measure a first current in a first signal path of the radio frequency signal generator and to measure a second current in a second signal path of the radio frequency signal generator during a calibration process; and program instructions for configuring a current imbalance correction circuit to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current; 1. A computer program product comprising:

23. determining a difference between the measured first current and the measured second current; generating a control signal based on the determined difference between the measured first current and the measured second current; and outputting the control signal to the current imbalance correction circuit; 10. The computer program product of claim 9, wherein in response to the control signal, the current imbalance correction circuit is configured to inject a current into at least one of the first signal path and the second signal path of the radio frequency signal generator to compensate for the determined difference between the measured first current and the measured second current.

24. measuring a first current in a first signal path of the radio frequency signal generator; measuring a second current in a second signal path of the radio frequency signal generator; and adjusting a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current. A method comprising:

25. determining a difference between the measured first current and the measured second current; and generating a control signal based on the determined difference between the measured first current and the measured second current. Provided with:

10. The method of claim 9, wherein adjusting the current level in at least one of the first signal path and the second signal path of the radio frequency signal generator is performed in response to the control signal to compensate for the determined difference between the measured first current and the measured second current.

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