Compute near memory with backend memory

Abstract

Examples herein provide a memory device comprising an eDRAM memory cell.SOLUTION: The memory device includes a write circuit formed at least partially above the storage capacitor and a read circuit formed at least partially below the storage capacitor, a computational near memory device bonded to the memory device, a processor, and an interface from the memory device to the processor. In some examples, a circuit comprising one or more of a controller, a multiplexer, or a register for providing an output of a memory device is included to emulate an output read rate of an SRAM memory device. The bonding of the surface of the memory device can be to a computational near memory device or other circuitry.SELECTED DRAWING: Figure 4

Description

[Background technology]

[0001] Cutting-edge data-intensive applications such as artificial intelligence (AI) workloads, machine learning, deep learning, and graph processing process large amounts of data. For example, deep learning (DL) workloads can involve performing matrix operations on a large number of neural network (NN) parameters for both training and inference tasks. These data-intensive applications require large storage capacities to hold vast amounts of data and enormous computational power to process the data quickly and efficiently. Addressing both the storage and computational efficiency aspects for data-intensive workloads is a challenge. [Brief explanation of the drawings]

[0002] [Figure 1] FIG. 1 depicts an example of a memory device.

[0003] [Figure 2] FIG. 1 depicts an example of an embodiment.

[0004] [Figure 3A] FIG. 1 is a cross-sectional view of a gain cell eDRAM structure. [Figure 3B] FIG. 1 is a cross-sectional view of a gain cell eDRAM structure. [Figure 3C] FIG. 1 is a cross-sectional view of a gain cell eDRAM structure. [Figure 3D] FIG. 1 is a cross-sectional view of a gain cell eDRAM structure.

[0005] [Figure 4] FIG. 1 depicts an example of a parallel gain cell device with a shared layer.

[0006] [Figure 5] FIG. 5 depicts an example of a top-down view of the structure of FIG. 4.

[0007] [Figure 6]1 is a cross-sectional view of a gain cell eDRAM structure according to some embodiments.

[0008] [Figure 7A] 1A-1C depict various examples of top and bottom gate structures. [Figure 7B] 1A-1C depict various examples of top and bottom gate structures. [Figure 7C] 1A-1C depict various examples of top and bottom gate structures.

[0009] [Figure 8] 1 is a cross-sectional view of a memory device having multiple gain cell eDRAM devices.

[0010] [Figure 9] 1A-1C are circuit diagrams of several embodiments of gain cell transistors.

[0011] [Figure 10A] FIG. 1 depicts an example of forming a memory device. [Figure 10B] FIG. 1 depicts an example of forming a memory device. [Figure 10C] FIG. 1 depicts an example of forming a memory device. [Figure 10D] FIG. 1 depicts an example of forming a memory device. [Figure 10E] FIG. 1 depicts an example of forming a memory device. [Figure 10F] FIG. 1 depicts an example of forming a memory device.

[0012] [Figure 11] FIG. 1 depicts the process.

[0013] [Figure 12A] FIG. 1 is a cross-sectional view of a gain cell memory device. [Figure 12B] FIG. 1 is a cross-sectional view of a gain cell memory device. [Figure 12C] FIG. 1 is a cross-sectional view of a gain cell memory device.

[0014] [Figure 13] FIG. 2 is another cross-sectional view of a gain cell memory device.

[0015] [Figure 14] FIG. 1 depicts an example of a top-down view of various devices.

[0016] [Figure 15] FIG. 1 is an exemplary logical block diagram of a system having near memory and near memory computation blocks.

[0017] [Figure 16] FIG. 1 depicts an exemplary system in which circuitry can be used in a memory of a first memory type to emulate the output of another memory type.

[0018] [Figure 17] FIG. 10 depicts an example of signals that may be forwarded for access to multiple banks.

[0019] [Figure 18] FIG. 1 illustrates an exemplary system in which multiple SRAM banks are accessed and data from the banks is concatenated or combined to provide data to a computational engine.

[0020] [Figure 19] 1 depicts an example of an embedded DRAM memory whereby data output from the embedded DRAM memory is split and provided to multiple processing elements (PEs).

[0021] [Figure 20] FIG. 1 depicts an exemplary process for reading data from a memory device at a speed that emulates a faster memory device.

[0022] [Figure 21] 1A-1C depict an example of various systems.

[0023] [Figure 22] FIG. 1 depicts a system.

[0024] [Figure 23] A diagram depicting the environment. DETAILED DESCRIPTION OF THE INVENTION

[0025] Computer systems include random access memory (RAM) integrated within the same die or multi-chip module (MCM) to provide rapid access to data. Dynamic random access memory (DRAM) is commonly used as the random access memory within computer systems. However, if DRAM uses capacitors to store data, the use of DRAM may require refreshing the stored data and corresponding circuitry and timing devices. DRAM-based memories may experience read and write latency due to the time it takes to charge the bit lines. For example, a capacitor on a bit line (COB) is a capacitor that provides charge to the bit line. In some cases, for read operations, the time to charge the bit line may be longer than desired given the resistance-capacitance (RC) time constant delay from the use of a capacitor.

[0026] Static random access memory (SRAM) is an alternative to DRAM. SRAM does not use capacitors to store data and does not require refreshing. SRAM can achieve faster read and write times than DRAM. SRAM is commonly used for high-speed registers or caches.

[0027] Computational near-memory applications can utilize embedded DRAM (eDRAM) memory to enable high-density computational near-memory (CNM) circuits. For back-end eDRAM devices implemented in the back-end metal layer, the CNM realizes computational circuits opportunistically located below the back-end eDRAM array on the active silicon. In this way, the CNM circuit localizes computation directly below the eDRAM array to minimize wasted energy and latency during data movement and maximize available on-die memory bandwidth for meaningful computation. eDRAM-based CNM circuits achieve higher memory density (e.g., more data stored per unit area) compared to SRAM-based CNM implementations. For example, eDRAM-based CNM circuits achieve high storage capacity and acceptable computational efficiency for data-intensive workloads such as artificial intelligence (AI) tasks, machine learning, deep learning, graph processing, decryption, encryption, decompression, or compression.

[0028] Gain-cell embedded DRAM (eDRAM) arrays can achieve faster read and write times than DRAM or eDRAM with one-transistor-one-capacitor (1T1C) cells. Gain-cell eDRAMs are sometimes considered alternatives to SRAM. Some Gain-cell eDRAMs use bit cells and dynamic storage nodes that use several transistors (e.g., five or fewer). For example, a two-transistor (2T) Gain-cell topology includes a write transistor (MW) and a storage and read coupling transistor (MR). In some cases, Gain-cell eDRAM technology can achieve lower row-to-column delay (tRCD) and faster read times using the read transistor (MR). For a description of Gain-cell eDRAMs, see, for example, P. Meinerzhagen et al., "Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip" (2018).

[0029] One measure of read time is the ratio of tRCD / tRC. tRC and tRCD refer to the timing associated with two subsequent row accesses in a DRAM. tRC can represent the row cycle time and the minimum time interval between successive active commands to the same bank. tRCD can represent the row address to column address delay, which can be the number of clock cycles taken between issuing the active command and the read / write command. In some cases, GainCell eDRAM achieves a substantially lower tRCD than eDRAM's 1T1C technology.

[0030] FIG. 1 depicts an exemplary high-level block diagram of a memory device. The memory device 100 may include an SRAM memory array intellectual property (IP) 106 and peripherals 108 with mid-logic and input / output (I / O) connections. The memory array 106 and peripherals 108 with mid-logic and input / output (I / O) connections may be formed on a silicon (Si) substrate 104. The back-end interconnect 102 may be formed on the memory array 106 and peripherals 108 with mid-logic and input / output (I / O) connections. In contrast, compared to the use of SRAM in the memory device 100, the use of DRAM technology can achieve significantly higher density (e.g., more data stored per area). However, DRAM can be substantially slower than SRAM in read-intensive applications because every read has a writeback operation. As such, slow speeds and long read times may make DRAM a poor alternative to SRAM. To make DRAM competitive with high-speed memories such as SRAM, faster time to charge the capacitor on the bit line (COB) of a DRAM memory cell can reduce read time.

[0031] FIG. 2 depicts a high-level overview of one embodiment. The memory device 200 can include gain cell eDRAM memory array technology with stacked memory between back-end interconnects. The memory array 202 can include an array of write transistors (MW) and capacitor storage. The read circuit 204 can include one or more transistors used to read the contents of the capacitor storage. The gain cell eDRAM configuration can be used with high-speed silicon to mitigate issues associated with slow read operations involving capacitor storage. To further improve the speed of read operations involving the memory array 202, layer transfer silicon can be used to provide faster read transistor technology while freeing up the silicon substrate 212 beneath the memory array 202 for other uses. The peripherals / mid-logic / I / O 206 can include sense amplifiers (SAs), word line drivers, silicon transistors used with the memory array 202, and bit line signal routing to the read circuit 204 for reads, write circuits, multiplexing circuits, decoding circuits, etc.

[0032] According to some embodiments, materials can be bonded using an interface layer that contacts each other. Metal-metal bonds can be formed to achieve direct contact of metals etched opposite each other. For example, regions can be bonded together if the regions perform different functions (e.g., write circuitry, storage, read circuitry, I / O circuitry, sense amplifiers, etc.), are formed using different materials, or are formed at different temperatures. As described in more detail below, two or more layers of a device can be bonded together.

[0033] In some implementations of gain cells for DRAM memory devices, multiple transistors are used, and the transistors are arranged in the same plane (e.g., the XY plane). Arranging the transistors in the same plane can use die space and reduce the amount of die space available for other uses. Various embodiments provide a write device formed in the top layer above the read device (e.g., along the Z direction) using a bonding process and sequential three-dimensional channel processing. Thus, it is possible to provide DRAM-level data storage density with SRAM-level read speeds while saving area in the XY plane for circuitry other than the write or read circuit.

[0034] 3A depicts a cross-sectional view of a gain cell eDRAM structure according to some embodiments. Various embodiments provide a memory device including a write circuit 300, a storage capacitor 320, a dielectric 322, a storage capacitor 324, and a read circuit 330. Along the Z direction, the write circuit 300 is at least partially disposed above the read circuit 330 and may be disposed in a plane different from the plane of the read circuit 330. The write circuit 300 may be conductively coupled to the storage capacitor 320, and the read circuit 330 may be conductively coupled to the storage capacitor 320. In some embodiments, the layer 308 (in contact with the write circuit 300) may be bonded to the storage capacitor 320 in a manner described herein.

[0035] In some examples, the write circuit 300 can include a metal gate 302, a gate oxide 304, a channel 306, and source (S) and drain (D) regions. The metal gate 302 can include one or more of titanium nitride (TiN), tungsten, copper, tantalum nitride (TaN), ruthenium (Ru), copper oxide, nickel, carbon, titanium, tantalum, poly-Si, poly-Ge, iridium, iridium oxide, hafnium nitride, etc. The gate oxide 304 can include one or more of hafnium oxide, silicon oxide, aluminum oxide, silicon nitride, silicon carbide, h-BN, carbon, lanthanum oxide, or any combination or multilayer thereof. The channel 306 can comprise one or more of poly-Si / Ge / III-V / GaN, single crystal layer transferred Si / Ge / III-V / GaN, IGZO (indium gallium zinc oxide), indium oxide, zinc oxide, WSe2, WS2, MoSe2, black phosphorus, SnO, HfSnO, Cu2O, CoO, IZO, AZO, indium tungsten oxide, indium tin oxide (ITO), or any combination thereof, or doping with SiO2, HfO2, Al2O3, or other electrical insulators.

[0036] Source and drain regions can be formed in the substrate adjacent to the gate stack of each transistor. The source and drain regions can be formed using either an implantation or diffusion process or an etching or deposition process. In the case of implantation or diffusion, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the substrate to form the source and drain regions. An annealing process, which activates the dopants and further diffuses them into the substrate, typically follows the ion-implantation process. In an etching or deposition process, the substrate can first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process can then be performed to fill the recesses with the material used to fabricate the source and drain regions. In some implementations, the source and drain regions can be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy can be doped in situ with a dopant, such as boron, arsenic, or phosphorus. In further embodiments, the source and drain regions may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy, and in further embodiments, one or more layers of metal and / or metal alloy may be used to form the source and drain regions.

[0037] In some examples, the metal gate 302 can completely cover the gate oxide 304 or can cover only a portion of the gate oxide 304 along the XY plane. In some examples, the gate oxide 304 can cover only a portion of the channel 306 along the XY plane. A source region (S) can be formed in contact with the channel 306. A write bit line (WBL) (not shown) can be coupled to the source region (S). A drain region (D) can be formed in the channel through a layer 308. The layer 308 can include one or more of a silicon nitride (SiN) etch stop, an oxide layer (e.g., SiO, AlO), a nitride layer, or a carbide layer. The drain region (D) can be coupled to the channel 306 and the storage capacitor 320. Various exemplary configurations of the write circuit 300 are described herein, for example, with reference to FIG. 7A.

[0038] Write circuit 300 and layer 308 may be formed in region 307 using any semiconductor processing technique, including one or more of etching, chemical vapor deposition (CVD), polishing, doping, electron implantation, ion implantation, epitaxial growth, etc. Region 307 may be any type of insulating or semiconducting material, such as, but not limited to, oxide, field oxide, nitride, silicon nitride, etc.

[0039] According to some embodiments, the bonding interface 338 can be used to bond the bottom surface of the layer 308 in the first region 350 to the top surface of the second region 352, including region 326, and conductively couple the drain region (D) to the storage capacitor 320. In some examples, the bonding interface 338 can include one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC). Application of the bonding material onto the surface can be performed by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), spin-on, wet deposition process, or other similar process.

[0040] To bond the bottom surface of the first region 350 to the top surface of the second region 352, a bonding interface 338 can be applied to the bottom surface of the first region 350 and to the top surface of the second region 352. The bond can be activated by preparing the surfaces with a plasma treatment (e.g., exposure to high-energy ions of nitrogen, argon, oxygen, NH3, Cl, F2, etc.) to create broken or unbonded bonds. These dangling bonds can improve adhesion of the wafer used to form the first region 350 to the wafer used to form the second region 352. The wafers are aligned to each other using alignment marks and pressed together, for example, at a temperature ranging from room temperature to 400°C.

[0041] The storage capacitor and dielectric (e.g., 320, 322, and 324) can include an inner electrode material (320) such as titanium nitride, tantalum nitride, W, Ru, Ir, Cu, Ta, Ti, or a combination or multilayer structure thereof. The dielectric 322 can include silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, hafnium zirconium oxide, aluminum oxide, STO (e.g., SrTiO) material, BTO (e.g., BaTiO) material, or piezoelectric (PZT) material. The dielectric 322 can include a plate formed around the inner electrode material 320 (e.g., a coated surface of the cylindrical inner electrode material 320) and disposed between the inner electrode material 320 and the outer electrode 324.

[0042] The readout circuit 330 can be formed in the (-Z) direction below the storage capacitor 320. In some examples, the readout circuit 330 can include a metal gate 332, a gate oxide 334, and a channel 336. The metal gate 332 can include one or more of titanium nitride (TiN), tungsten, copper, tantalum nitride (TaN), ruthenium (Ru), copper oxide, nickel, carbon, titanium, tantalum, poly-Si, poly-Ge, iridium, iridium oxide, hafnium nitride, etc. The gate oxide 334 can include one or more of hafnium oxide, silicon oxide, aluminum oxide, silicon nitride, silicon carbide, h-BN, carbon, lanthanum oxide, or any combination or multilayer thereof. The channel 336 can comprise one or more of poly-Si / Ge / III-V / GaN, single crystal layer transferred Si / Ge / III-V / GaN, IGZO (indium gallium zinc oxide), indium oxide, zinc oxide, WSe2, WS2, MoSe2, black phosphorus, SnO, HfSnO, Cu2O, CoO, IZO, AZO, indium tungsten oxide, indium tin oxide (ITO), or any combination thereof, or doping with SiO2, HfO2, Al2O3, or other electrical insulators.

[0043] In some examples, the metal gate 332 can completely cover the gate oxide 334 or can cover only a portion of the gate oxide 334 along the XY plane. In some examples, the gate oxide 334 can cover only a portion of the channel 336 along the XY plane. A source region (S) can be formed in contact with the gate oxide 334 and the channel 336. The source region (S) can be coupled to receive a signal from a read bit line (RBL) (not shown). A drain region (D) can be formed in contact with the channel 336 and the gate oxide 334. The drain region (D) can be coupled to receive a signal from a read word line (RWL) (not shown).

[0044] The storage capacitor 320, the dielectric 322, the storage capacitor 324, and the readout circuit 330 may be formed in the region 326 using any semiconductor processing technique, including one or more of etching, chemical vapor deposition (CVD), polishing, doping, electron implantation, ion mounting, epitaxial growth, etc. The region 326 may be any type of insulating or semiconducting material, such as, but not limited to, oxide, field oxide, nitride, silicon nitride, aluminum oxide, etc.

[0045] In some embodiments, first region 350 can include write circuit 300, layer 308, and region 307 formed at a first temperature or temperature range, such as, but not limited to, 100°C to 2000°C. Second region 352 can include storage capacitor 320, dielectric 322, storage capacitor 324, read circuit 330, and region 326 formed at a second temperature or temperature range, such as, but not limited to, 100°C to 2000°C. The second temperature or temperature range can be different from, or at least partially overlap with, the first temperature or temperature range. Thus, first region 350 and second region 352 can be fabricated at different temperatures and bonded together using bonding interface 338.

[0046] 3B depicts an exemplary cross-sectional view of a gain cell eDRAM structure according to some embodiments. In some embodiments, first region 360 may include write circuit 300, layer 308, and region 307 formed together with storage capacitor 320, dielectric 322, storage capacitor 324, read circuit 330, and region 326 at a first temperature or temperature range. In this example, layer 308 and drain (D) region are formed over region 326 and storage capacitor 320, rather than bonding layer 308 and drain region to region 326 and a portion of storage capacitor 320, as in the example of FIG. 3A.

[0047] The second region 362 may include a readout circuit 330 formed in the region 340 at a second temperature or temperature range. The second temperature or temperature range may be different from or at least partially overlap with the first temperature or temperature range. The readout circuit 330 may be formed in the region 340 using any semiconductor processing technique, including one or more of etching, chemical vapor deposition (CVD), polishing, doping, electron implantation, ion mounting, epitaxial growth, etc. The region 340 may be any type of insulating or semiconducting material, such as, but not limited to, oxide, field oxide, nitride, silicon nitride, aluminum oxide, etc.

[0048] In some embodiments, the first region 360 and the second region 362 can be fabricated at different or overlapping temperatures and bonded together using a bond interface 342. In this example, the bond interface 342 can be used to bond the readout circuit 330 to the region 326 and to conductively couple the metal gate 332 to the storage capacitor 320. In this example, the lower portion of the first region 360 can be covered with the material of the bond interface 342, and the opposing portion of the second region 362 can be covered with the material of the bond interface 342 to form the bond interface 342. The bond interface 342 can include one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC). The techniques described above for the bond interface 338 can be used to bond the first region 360 to the second region 362.

[0049] It should be noted that in some cases, the formation of the storage capacitors and dielectrics (e.g., 320, 322, and 324) is performed at a higher or different temperature than that used to fabricate the write circuit 300 or read circuit 330, and the fabrication of such storage capacitors and dielectrics (e.g., 320, 322, and 324) is incompatible with the fabrication of the write circuit 300 or read circuit 330. Bonding provides a manner of coupling the write circuit 300 or read circuit 330 with the storage capacitors and dielectrics (e.g., 320, 322, and 324).

[0050] 3C depicts an exemplary cross-sectional view of a gain cell eDRAM structure according to some embodiments. In this example, a first region 350 is bonded to a second region 352 using a bonding interface 338. The second region 352 is bonded to a circuit 354 using a bonding interface 370. In this example, a lower portion of the second region 352 can be covered with the material of the bonding interface 370, and an opposing portion of the circuit 354 can be covered with the material of the bonding interface 370 to form the bonding interface 370. The bonding interface 370 can include one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC). The techniques described above for the bonding interface 370 can be used to bond the first region 350 to the second region 352. Circuitry 354 may include, among other circuits, Vcc, Vss terminals for sensing circuitry, computational near memory (CNM) circuitry, SRAM emulation circuitry (as described herein), vias, bit line drivers, or word line drivers.

[0051] 3D depicts an exemplary cross-sectional view of a gain cell eDRAM structure according to some embodiments. In this example, a first region 360 is bonded to a second region 362 using a bonding interface 342. The second region 362 can also be bonded to a circuit 354 using a bonding interface 370 in a manner similar to that described above. Thus, a bonding interface can be used to bond any structure and provide a conductive bond.

[0052] FIG. 4 depicts an example of a parallel gain cell device having a shared layer. The shared layer can be layer 308. Bonding between different structures can be performed as described above. For example, one or more of bonding interfaces 402, 404, and / or 406 can be used to bond the different structures to each other while allowing conductive coupling as needed. Bonding interfaces 402, 404, and / or 406 can include one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbonitride (SiCN), or silicon oxycarbide (SiOC). The techniques described above with respect to bonding interface 338 can be used to bond the different regions to each other.

[0053] FIG. 5 depicts an example of a top-down view of the structure of FIG. 4. Diagram 502 provides a top-down view of a write circuit according to some embodiments. Cell 504 can include a write circuit according to some embodiments. In some examples, top-down view 502 of cell 504 shows a bit line (BL) formed above cell 504, the bit line (BL) contacting at least one other copy of cell 504. In addition, word line WL0 is coupled to the gate oxide of cell 504 and can contact at least one other copy of cell 504. A capacitive contact (cap contact) can be disposed below cell 504 for connection to capacitive storage (not shown).

[0054] 6 depicts a cross-sectional view of a gain cell eDRAM structure according to some embodiments. Various embodiments provide a memory device including a write circuit 600, a storage capacitor 320, a dielectric 322, a storage capacitor 324, and a read circuit 330. The write circuit 600 is disposed at least partially above the read circuit 330 in the Z direction and may be disposed in an XY plane different from the plane of the read circuit 330. The write circuit 600 may be conductively coupled to the storage capacitor 320, and the read circuit 330 may be conductively coupled to the storage capacitor 320.

[0055] Write circuit 600 may include a metal gate 602, a gate oxide 604, a channel 606, and a layer 608. The metal gate 602 may include one or more of titanium nitride (TiN), tungsten, copper, tantalum nitride (TaN), ruthenium (Ru), copper oxide, nickel, carbon, titanium, tantalum, poly-Si, poly-Ge, iridium, iridium oxide, hafnium nitride, etc. The gate oxide 604 may include one or more of hafnium oxide, silicon oxide, aluminum oxide, silicon nitride, silicon carbide, h-BN, carbon, lanthanum oxide, or any combination or multilayer thereof. Channel 606 can include one or more of poly-Si / Ge / III-V / GaN, single-crystal layer-transferred Si / Ge / III-V / GaN, IGZO (indium gallium zinc oxide), indium oxide, zinc oxide, WSe2, WS2, MoSe2, black phosphorus, SnO, HfSnO, Cu2O, CoO, IZO, AZO, indium tungsten oxide, indium tin oxide (ITO), or any combination thereof, or doped with SiO2, HfO2, Al2O3, or other electrical insulators. Layer 608 can be formed to include silicon einsteinium (SiNEs).

[0056] In some examples, the metal gate 602 can completely cover the gate oxide 604 or can cover only a portion of the gate oxide 604 along the XY plane. The gate oxide 604 can cover a portion of the channel 606. A source region (S) can be formed in contact with the channel 606. A write bit line (WBL) signal can be coupled to the source region (S) (not shown). A drain region (D) can be formed in contact with the channel 606. A connection 610 can couple the drain region (D) to the storage capacitor 320. In some examples, the connection 610 can be formed from one or more of Cu, Ru, TiN, W, or Co. The connection 610 can be formed through a portion of the layer 608. In this example, the connection 610 is an inverted L-shaped structure, but any shape can be used.

[0057] In this example, one or more of bond interfaces 618 or bond interfaces 620 may be formed and used in a manner similar to that described with respect to the structures of Figures 3A-3D. Bond interfaces 618 and / or 620 may include one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbonitride (SiCN), or silicon oxycarbide (SiOC).

[0058] FIG. 7A depicts cross-sectional views of various examples of top-gate and bottom-gate structures. In this example, structures 700, 710, 720, and 730 are shown and can be used in write or read circuits. In some examples, a thin-film transistor configuration can be used without a sidewall gate in the case of a top-gate-top contact. In some examples, a FinFET configuration can be used for at least the gate structures. Materials used to form the write (top) and read (bottom) transistors can include one or more of poly-Si, Si, Ge, poly-Ge, III-V, GaN, transition metal dichalcogenides (TMDs) (e.g., MoS2, WSe2, MoSe2, WSe2), InS, HfS, ZnS, ZnSe, In2O3, ZnO, AZO, IGZO, IZO, and other back-end compatible materials. The back-end can include processing of layers subsequent to the formation of the bulk silicon transistor. Back-end compatible materials can include metals and dielectrics with a temperature budget of ≦approximately 500°C. Various embodiments provide back-end compatible transistors as described herein.

[0059] FIG. 7B depicts an example cross-section of a top-gate-top-contact structure of some embodiments. In this example, structure 710A is a cross-sectional view of structure 710. A fin field-effect transistor (FinFET) implementation is used for the gate structure, and a sidewall gate is present. According to some embodiments, the fin (e.g., narrow channel) provides improved gate control, improved sub-threshold swing, and improved leakage over planar implementations. The improved gate control can improve drive current (performance) at a given voltage while maintaining a low Ioff (off-state leakage) at negative or 0 volts. The read transistor and / or write transistor can be turned off abruptly, thereby allowing for abrupt or slower sub-threshold swing (e.g., rate of current reduction with decreasing gate voltage).

[0060] Figure 7C depicts an example of an upper gate alternating contact where the gate overlaps the capacitor contact. Structure 730 includes overlap between the gate and contact in the Z direction, but does not include overlap or contact with the contact adjacent to the bit line. The overlap between the gate and contact in the Z direction results in extra charge in the channel under the gate, which induces electrostatic doping (due to the gate electric field). This electrostatic doping improves contact resistance and increases drive current (performance). Improving drive current performance reduces the time it takes to charge the storage capacitor, thereby reducing latency (e.g., read / write time). When the gate overlaps the contact adjacent to the bit line contact, the signal-to-noise ratio (SNR) for identifying a 0 or 1 value stored in the storage capacitor is reduced due to the capacitance formed between the gate and the contact. However, because the capacitance is instead formed at the capacitor contact, the SNR may not be adversely affected, resulting in improved data retention in the capacitor storage.

[0061] FIG. 8 depicts a cross-sectional view of a memory device having multiple gain cell eDRAM devices. According to various embodiments, a memory cell 802 includes multiple bit cells, and a back-end write circuit 804 (MW) is disposed above a read circuit 806 (MR) in the Z direction, as opposed to being in the XY plane with the read circuit 806. In some examples, the back-end write circuit 804 is connected to a storage cell 808, and the read circuit 806 is connected to the storage cell, along the Z direction. In this example, the write circuit 804 is implemented as a FinFET transistor with a gate wrapping around the channel. The write circuit 804 can write bits to the storage cell 808. In this example, the storage cell 808 can be implemented as a capacitor on a bit line (COB) device. The read circuit 806 can read one or more bits stored in the storage cell 808 and the C of the storage cell 808. SN The MR transistors used to sense the state can be pre-amplified. The array of MR transistors can be used to amplify the stored C SN The status can be read.

[0062] As described in more detail herein, multiple layers of a device can be bonded and stacked on top of each other. For example, one layer can include only N-type metal oxide semiconductor (MOS) (NMOS) transistors or only P-type MOS transistors (PMOS) transistors, while another layer above or below it can include complementary metal oxide semiconductor (CMOS) transistors (having NMOS and PMOS transistors).

[0063] 9 shows circuit diagrams of some embodiments of gain cell transistors. Exemplary read and write operations for the devices of at least FIGS. 3A-3D, 4, 6, and 8 are now described. The read transistor (MR) and write transistor (MW) are connected to the capacitor C of the memory circuit. SNFor example, in an implementation with all NMOS read (MR) and write (MW) transistors, a DRAM bitcell consists of a MW transistor and a capacitor C SN For a write operation, when WBL is turned on, the capacitor C SN The charge stored in is transferred to node SN, which is connected to the gate of read transistor MR. To write a logic 1, read transistor MR is activated. To write a logic 0, read transistor MR is an open circuit.

[0064] Capacitor C SN To read data from the WBL, the WBL is kept off and the charge is transferred to the capacitor C SN The capacitor C is discharged to the line WBL, but is subject to an RC time constant delay. SN When a 1 is stored in the capacitor C, the gate of the MR has a voltage and its channel resistance is low. SN When MR stores a value of 0, its resistance becomes high. The change in resistance between RWL and RBL occurs because the gate of MR is at a specific potential (0 or 1). By applying a constant voltage difference between RWL and RBL, the capacitor C SN It is now possible to read the contents of the capacitor C SN stores a 1, the current through the read transistor is high.

[0065] However, connecting the SN node to the gate of the read transistor MR consumes area if the MR transistor is adjacent to the MW transistor in the XY plane. If the write circuit is a back-end transistor, the write circuit does not consume additional XY plane space in addition to the read circuit at the front end. The back-end transistor can have contacts underneath it (the gate and contacts are not in the same plane). As described herein, various embodiments provide the MW transistor in a plane above the MR transistor.

[0066] 10A-10F depict an example of forming a memory device. For example, the memory device may be a gain cell eDRAM device. FIG. 10A shows a cross-sectional view of a silicon substrate 1010. In an embodiment, the substrate 1010 may be a silicon substrate, a glass substrate such as soda-lime glass or borosilicate glass, a metal substrate, a plastic substrate, a substrate comprising SiO2, or another suitable substrate. A structure 1020 may be formed in or on the silicon substrate 1010. The structure 1020 may include read (MR) transistors, vias, redistribution lines, metal routing, word line (WL) drivers, power supplies, a memory controller, a memory management unit, row decoders and drivers, and logic and processing circuits. The structure 1020 may be formed on or in the silicon substrate 1010 by depositing various materials, etching, polishing, etc. The structure 1020 may include any type of active circuitry using planar or FinFET technology.

[0067] FIG. 10B depicts an example of interlayer dielectric (ILD) deposition on structure 1020. The ILD layer may be formed using a dielectric material known to be applicable to integrated circuit structures, such as a low-k material. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO), carbon-doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layer may contain pores or voids to further lower its dielectric constant. The ILD layer may include a silicon oxide (SiO) film, a silicon nitride (SiN) film, O3-tetraethylorthosilicate (TEOS), O3-hexamethyldisiloxane (HMDS), a plasma-TEOS oxide layer, or other suitable materials.

[0068] 10C depicts an example of forming a second layer of a transistor. The second layer of the transistor can be formed in a structure 1020. The structure 1020 can be modified to include a non-silicon-based transistor, such as a write (MW) circuit 1032 formed from the channel materials described above with respect to the metal gate 302, gate oxide 304, channel 306, source (S) region, and drain (D) region. The write circuit 1032 can be formed above and in contact with the storage cell, as described above. Signal or voltage transfer vias 1033 can also be formed in the structure 1030. Sequential three-dimensional channel processing can be used to deposit or form the transistors and vias in the structure 1030 (e.g., at low temperatures).

[0069] In some examples, a bonding layer 1034 can be used to attach structure 1036 to structure 1030. Various examples of bonding processes are described herein. Structure 1036 can include word line (WL) straps and vias to WL drivers.

[0070] 10D depicts an example of bonding a surface 1052 of a second substrate 1050 to a surface 1040 of a structure 1036. In some examples, the surface 1040 can be covered with a bonding material, and the surface 1052 can be covered with a bonding material. Bonding of the surface 1040 to the surface 1052 can be performed by contacting a bonding material covering both surfaces 1040 and 1052. In some examples, the bonding material can include one or more of SiO, SiON, SiOCN, SiCN, or SiOC. Various examples of bonding surfaces are described herein. For example, the second substrate 1050 can be a carrier wafer, and after bonding the second substrate 1050 to the surface 1040, the resulting structure can be flipped over and patterned.

[0071] 10E depicts the resulting structure after polishing the substrate 1010 to expose the surface 1060, particularly the active fin (e.g., channel region) of the readout transistor from the backside. Other techniques for removing the substrate 1010 can be used, such as etching or polishing or grinding.

[0072] 10F depicts the resulting structure after processing the backside metal using sequential processing (instead of bonding) to create layer-by-layer (e.g., via etching oxide and metal) in structure 1070. Formation of structure 1070 can be performed by flipping the wafer over so that structure 1070 is on top and exposed. However, in some examples, structure 1070 can be bonded to surface 1060 ( FIG. 10E ) according to techniques described herein.

[0073] 11 depicts a process for forming a gain cell memory device. At 1102, a first structure can be formed. For example, the first structure can include transistors of the same type (e.g., PMOS, NMOS) or CMOS transistors, etc. The first structure can achieve a particular operation. For example, the first structure can perform an operation using one or more of a write circuit, a read circuit, a storage capacitor, a sensing circuit and peripheral logic, an SRAM emulation circuit, etc. The first structure can be formed using a particular material group at a particular first temperature or temperature range.

[0074] At 1104, a second structure may be formed. For example, the second structure may include the same type of transistor (e.g., PMOS, NMOS) or CMOS transistor, etc. The second structure may achieve an operation different from that of the first structure. For example, the second structure may perform an operation using one or more of a write circuit, a read circuit, a storage capacitor, a sensing circuit and peripheral logic, an SRAM emulation circuit, etc. The second structure may be formed using a particular material group at a particular second temperature or temperature range, which may be different from (or partially overlap with) the first temperature or temperature range.

[0075] At 1106, a surface of the first structure can be partially or entirely covered with a bonding material. For example, the surface can be a surface of the first structure to be bonded to a second structure. Application of the bonding material onto the surface of the first structure can be performed by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), spin-on, wet deposition process, or other similar process. The bonding material can include one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

[0076] At 1108, a surface of the second structure can be partially or entirely covered with a bonding material. For example, the surface can be a surface of the second structure to be bonded to the first structure. Application of the bonding material onto the surface of the second structure can be performed by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), spin-on, wet deposition process, or other similar process. The bonding material can include one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

[0077] At 1110, a bonding material portion on a first structure can be bonded to a bonding material portion on a second structure. For example, a bond can be formed between a bonding material on a first structure and a bonding material on a second structure. For example, to form a bond between bonding materials on different surfaces, the bonding material can be formed by (1) preparing the surfaces with a plasma treatment (e.g., exposure to high-energy ions of nitrogen, argon, oxygen, NH3, Cl, F2, etc.) that creates broken or unbonded bonds, (2) aligning the surfaces, and (3) pressing the surfaces together at a temperature ranging from room temperature to 400°C.

[0078] 12A depicts another cross-sectional view of a gain cell memory device. In this example, a bonding interface using techniques described herein is used to bond and conductively couple a capacitor storage device of structure 1202 to a readout transistor of structure 1204. In this example, structure 1202 can be formed at a relatively higher temperature than the temperature used to form structure 1204, although the opposite may also be true.

[0079] 12B depicts another cross-sectional view of a gain cell memory device. In this example, a bonding interface using the techniques described herein is used to bond structure 1212 to structure 1214. For example, structure 1212 can include a gain cell eDRAM memory device including write and read circuits, and structure 1214 can include various circuits described herein. In this example, structure 1212 can be formed at a relatively lower temperature than the temperature used to form structure 1214, although the opposite may also be true.

[0080] 12C depicts another cross-sectional view of a gain cell memory device. In this example, a bonding interface using the techniques described herein is used to bond structure 1222 to structure 1224. For example, structure 1222 can include a gain cell eDRAM memory device, and structure 1224 can include readout circuitry and various circuits described herein. In this example, structure 1222 can be formed at a relatively higher temperature than the temperature used to form structure 1224, although the opposite may also be true.

[0081] Figure 13 depicts another cross-sectional view of a gain cell memory device. The eDRAM memory can be implemented in a back-end metallization layer and stacked above the memory access circuitry, control logic circuitry, and CNM circuitry. Through-silicon vias (TSVs) can be formed next to the memory stack. A hermetic enclosure can be formed around the memory stack to isolate the memory stack from the TSVs.

[0082] 14 depicts an example of a top-down view of various devices. In system 1402, SRAM memory is used to store data used by or generated by the CNM. System 1404 is a top-down view of a CNM floorplan with eDRAM tightly coupled to the processing elements (PEs) and TSVs for power delivery. In system 1404, a back-end gain cell eDRAM device can be used instead of SRAM to store data read and written by the CNM.

[0083] In some examples, to use GainCell eDRAM devices instead of SRAM devices, circuitry is added to enable the GainCell eDRAM devices to emulate at least the output of an SRAM device. GainCell eDRAM devices can have much slower read access times than SRAM devices, but offer higher memory cell density, allowing them to store more data for the same XY-planar footprint as an SRAM device. In some examples, GainCell eDRAM devices can include multiple memory banks and store data across multiple memory banks, so that data reads can begin on consecutive clock cycles, and despite the slower read times of eDRAM devices compared to SRAM devices, data can be available at or near the throughput of an SRAM device. In some examples, time-interleaved access circuitry is implemented on the active silicon, as shown in the "lgc" (logic) section.

[0084] The circuitry that enables the eDRAM to emulate an SRAM device can be placed below the back-end memory in the Z direction to save on XY plane footprint, or next to the eDRAM device, using additional XY plane footprint.

[0085] FIG. 14 illustrates an exemplary implementation of a CNM circuit module that uses back-end embedded DRAM memory partitions instead of, or in addition to, SRAM devices. Various embodiments provide eDRAM devices that achieve the same operations per second (OPS), throughput, and near-memory bandwidth as SRAM. To match the same throughput and performance (in terms of OPS), eDRAM banks provide the same on-die bandwidth to the processing engine as SRAM memory banks. However, because eDRAM uses capacitors to access data much slower than SRAM, DRAM row accesses can have slower latency than SRAM row accesses. Various embodiments enable time-multiplexed memory bank accesses to be performed.

[0086] FIG. 15 depicts an example logical block diagram of a system having near memory and a computation block. In this example, the near memory 1502 is an SRAM device that receives a memory access command and a clock signal (e.g., 1 GHz or other frequency). In this example, the memory access command is a read command that causes 128 bits of data to be read, but data of any size can be read. The SRAM outputs the 128 bits of data timed with clock edges of the clock signal. A processing element (PE) 1506 in the computation block 1504 receives the data from the SRAM device and performs a computation using an input vector. For example, the data can be weights, and the PE 1506 can perform a multiplication of the weights with the input vector as part of a matrix multiplication as part of a neural network used in machine learning (ML) or artificial intelligence (AI) applications for training or inference.

[0087] In some cases, a DRAM bank can provide more data storage than an SRAM device for the same XY plane footprint. Various embodiments provide emulator circuits for DRAM devices such that the DRAM devices can provide output data at the same throughput as SRAM devices.

[0088] FIG. 16 depicts an exemplary system in which circuitry can be used with a memory of a first memory type to emulate the output of another memory type. For example, memory 1604 can include multiple banks of eDRAM devices. The eDRAM device banks are addressable as rows and columns and can include storage units that may reside in one or more devices. The control circuit 1602 can time-interleave data access requests made to the eDRAM banks to achieve similar output (read) bandwidth compared to SRAM embodiments. The control circuit 1602 can control the transfer of memory access signals (e.g., read or write) to memory banks eDRAM#0 through eDRAM#7 over successive clock cycles. Other numbers of memory banks can also be used. For example, during a first clock cycle, memory access can be transferred to eDRAM#0, and during a second clock cycle (e.g., next or subsequent), memory access can be transferred to eDRAM#1, and so on.

[0089] In some examples, the control circuit 1602 can forward memory access commands to the gating circuit 1608. The gating circuit 1608 can receive the same clock signal as that provided to different types of memory devices (e.g., SRAMs) and can also receive memory access commands. The gating circuit 1608 can forward the memory access commands on an edge (e.g., rising or falling) of the clock signal, allowing the memory access commands to be forwarded to any of the eDRAMs #0 to #7 in an interleaved manner to be accessed.

[0090] For example, in the case of reading addresses 0 and 1 in an SRAM, the data stored at address 0 can be accessed in clock cycle 0, and the data at address 1 can be accessed during the next clock cycle 1, even though they are from the same memory bank. However, eDRAM can only achieve slower read times (e.g., higher read latency) compared to SRAM read times. Storing data at addresses 0 and 1 in the eDRAM #0 bank may require multiple clock cycles to retrieve data from both addresses. In some examples, data to be accessed consecutively can be stored in different eDRAM banks. Thus, data at address 0 can be stored in the eDRAM #0 bank, and data at address 1 can be stored in the eDRAM #1 bank. For example, if weight values ​​are to be retrieved consecutively, the weight values ​​can be stored in different memory banks. For faster access, data can be striped across multiple DRAMs for parallel access. However, if slower access is permitted, the data can be stored in a single bank and accessed consecutively. Thus, to access data at a rate commensurate with SRAM speed (i.e., with a matching throughput), data can be accessed from the eDRAM banks in parallel or in consecutive clock cycles. If a read from a memory bank takes several clock cycles to complete, an access of address 0 from eDRAM #0 can precede an access of address 1 from eDRAM #1. In some examples, the control circuit 1602 can use the most significant bit of the memory address to select which DRAM bank is accessed.

[0091] In some examples, the control circuitry 1602 can alternate requests forwarded to the memory 1604 to reduce the amount of buffering of received data from the memory banks and reduce the size of the memory buffer used to buffer read data. The memory banks of the memory 1604 can provide data to the multiplexer 1606, and the control circuitry 1602 can control from which bank data is forwarded to the processing elements 1506 of the computation block 1504.

[0092] FIG. 17 depicts an example of signals that may be routed for accessing multiple banks. In this example, memory banks 0-7 are to be accessed to read data from those banks. To read data from banks 0-7, gating circuit 1608 may route a read enable signal to memory bank 0 on the rising edge of clock cycle 0, a read enable signal to memory bank 1 on the rising edge of clock cycle 1, and so on. While this example shows the routing of read requests to all memory banks, not all available memory banks are accessed for every read request. The memory bank to be accessed depends on which memory bank stores the data to be accessed. Data may be stored in multiple memory banks to allow for time-interleaved access, in which multiple read operations partially overlap in time.

[0093] 16, PE 1506 performs dot product operations by performing vector-vector multiplication and receives data from near memory having binary or multi-bit elements at a 1 GHz clock frequency. Other examples of operations of CNM circuitry include multiply and accumulate (MAC), binary operations (AND, OR, XOR, NOT) (e.g., for binary operations, bit-serial operations, bit-blt, or hyperdimensional computing), single-batch or multi-batch matrix-matrix or matrix-vector dot product operations, neural network activation functions such as ReLu, tanh, sigmoid, soft-max exponentiation, data compression, encryption, media accelerator, string matching or regular expression accelerator, or pointer tracking circuitry. PE 1506 can be any type of fixed or configurable function device.

[0094] FIG. 18 illustrates an exemplary system whereby multiple SRAM banks are accessed and data from the banks is concatenated or combined to provide data to a computation engine. In this example, the computation engine performs a batch 2 vector-vector dot product operation. For example, on one or more clock edges (e.g., rising or falling), SRAM Bank #0 and SRAM Bank #1 can provide data that is combined to provide a concatenated data segment. The data concatenation can be performed using a memory buffer (not shown). In this example, SRAM Bank #0 and SRAM Bank #1 can both provide 32b data, which is combined and provided as a 64b (64-bit) value. The 64b value can be a single element of 64b bit width (e.g., integer or floating-point representation), or it can be a vector of multiple elements of 1-bit (e.g., binary representation), 2-bit (e.g., ternary representation of {-1, 0, +1} values), or multi-bit (e.g., multi-bit integer or floating-point representation) element size. Data of other sizes can be used or combined. The binding value can be provided to one or more processing elements (PEs) for parallel processing.

[0095] In some examples, data output from the SRAM can be combined or concatenated with data from an eDRAM bank. For example, in Figure 18, SRAM#0 can be replaced with a DRAM bank having circuitry that emulates operation as an SRAM device, and SRAM#1 can be an SRAM device.

[0096] 19 depicts an example of an embedded DRAM memory whereby data output from the embedded DRAM memory is provided to multiple processing elements (PEs). For example, a 128-bit value provided by multiplexer 1606 can be stored in buffer 1902 as W0 and W1. In this example, W0 and W1 can both be 64 bits in size or other sizes. Multiplexer 1904 can forward either W0 or W1 to PEs 1906-0 and 1906-1 on a clock edge. For example, the output from multiplexer 1904 can be controlled by the least significant bit of the accessed address.

[0097] In some examples, one or more of the control 1602, multiplexer 1606, circuit 1608, multiplexer 1904, and signal conductive paths can be located below the eDRAM memory device in the Z direction to conserve XY footprint. In some examples, one or more of the control 1602, multiplexer 1606, circuit 1608, multiplexer 1904, and signal conductive paths can be located to the side of the eDRAM memory device in the XY plane.

[0098] 20 depicts an exemplary process for reading data from a memory device at a speed that emulates a faster memory device. At 2002, data to be accessed in successive read accesses is stored in different memory banks of the memory device. The data can be stored in different eDRAM memory banks, and the different eDRAM memory banks can be accessed so that they can be read in the same or different clock cycles.

[0099] At 2004, read requests are provided to different memory banks of a memory device to achieve at least partially overlapping read operations in time. For example, the read request can propagate to a memory bank on a first clock edge, and the read request can propagate to a different memory bank on a subsequent clock edge.

[0100] In 2006, data from different memory banks can be output at least partially in parallel. The data output rate from the different memory banks can emulate the data output rate of a second memory device. For example, data can be multiplexed after output from eDRAM memory banks to a computation block in a manner that emulates the speed of data output to a processor element (e.g., SRAM) to match the throughput of the SRAM.

[0101] Various embodiments are applicable to any process technology and any number of memory partitions. A batch 2 dot product engine is given as an example, and the back-end eDRAM memory access techniques presented herein are applicable to any type of computation block, bit width, number of elements, etc. The access circuitry can be physically located directly below the back-end eDRAM array to save area and wiring resources.

[0102] 21 depicts one example of various systems. System 2102 includes memory 2104 connected to a processor or accelerator 2106 using a connection 2108. The back-end DRAM memory 2104 can be formed using techniques described herein and can provide data to or receive data from the processor or accelerator 2106 using a bus or other interconnect. Connection 2108 can be an embedded multi-die interconnect bridge (EMIB) or a chip-to-chip interconnect.

[0103] System 2150 is another configuration whereby back-end memory 2152 can include memory banks with processing elements formed within the same silicon die. For example, the memory banks can be coupled to the processing elements in accordance with the techniques described herein. Multiple memory bank and processing element pairs can be formed within the back-end memory device, whereby multiple memory banks can be coupled to multiple processing elements in accordance with the techniques described herein.

[0104] The processing element may be a CNM circuit that processes content from the memory bank and provides output to a process or accelerator, or stores the results in memory. In some examples, multiple DRAM memory systems may be connected via a bus, interconnect, network, or fabric for service chain processing, whereby one device processes data and provides data to another device for storage and processing. Various embodiments of the memory bank and PE may be eDRAM and CNM constructed in the manner described herein. Various embodiments of the memory bank may be eDRAM having circuitry that enables the eDRAM to emulate the operation of an SRAM device.

[0105] The back-end memory 2152 can be connected to the processor or accelerator device 2154 using a connection 2156. The connection 2156 can be an embedded multi-die interconnect bridge (EMIB) or a chip-to-chip interconnect. The processor or accelerator device 2106 can be any type of device, such as a general-purpose or special-purpose microprocessor, CPU, GPU, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), etc., or a combination of such devices.

[0106] 22 depicts a system. The system can use embodiments described herein, whereby a memory device includes a CNM mechanism formed in the manner described herein or using an SRAM emulation circuit. System 2100 includes a processor 2110 that provides processing, operation management, and execution of instructions for system 2100. Processor 2110 can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware that provides processing for system 2100, or a combination of processors. Processor 2110 controls the overall operation of system 2100 and can be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or a combination of such devices.

[0107] In one example, system 2200 includes an interface 2212 coupled to processor 2210, which may represent a high-speed or high-throughput interface for system components requiring a higher bandwidth connection, such as memory subsystem 2220 or graphics interface component 2240, or accelerator 2242. Interface 2212 represents interface circuitry, which may be a standalone component or may be integrated on the processor die. If present, graphics interface 2240 interfaces to a graphics component for providing a visual display to a user of system 2200. In one example, graphics interface 2240 may drive a high-definition (HD) display that provides output to the user. High resolution may refer to a display having a pixel density of approximately 100 PPI (pixels per inch) or greater and may include formats such as Full HD (e.g., 1080p), Retina display, 4K (ultra-high definition or UHD), etc. In one example, the display may include a touchscreen display. In one example, the graphics interface 2240 generates a display based on data stored in the memory 2230, or based on operations performed by the processor 2210, or both. In one example, the graphics interface 2240 generates a display based on data stored in the memory 2230, or based on operations performed by the processor 2210, or both.

[0108] Accelerator 2242 may be a programmable or fixed function offload engine that can be accessed or used by processor 2210. For example, an accelerator within accelerator 2242 may provide cryptographic services, such as compression (DC) functions, public key encryption (PKE), ciphers, hash / authentication functions, decryption, or other functions or services. In some embodiments, an accelerator within accelerator 2242 additionally or alternatively provides the field selection controller functionality described herein. In some cases, accelerator 2242 may be integrated into a CPU socket (e.g., a connector to a motherboard or circuit board that contains a CPU and provides an electrical interface with the CPU). For example, accelerator 2242 may include programmable processing elements such as single or multi-core processors, graphics processing units, logic execution units, single or multi-level caches, functional units usable to independently execute programs or threads, application specific integrated circuits (ASICs), neural network processors (NNPs), programmable control logic, and field programmable gate arrays (FPGAs). The accelerator 2242 may provide multiple neural networks, CPUs, processor cores, general-purpose graphics processing units, or graphics processing units may be made available for use by artificial intelligence (AI) or machine learning (ML) models. For example, the AI ​​models may use or include reinforcement learning methods, Q-learning methods, deep Q-learning, or asynchronous advantage actor-critic (A3C), combinational neural networks, recurrent combinatorial neural networks, or other AI or ML models, or any combination thereof. The multiple neural networks, processor cores, or graphics processing units may be made available for use by the AI ​​or ML models.

[0109] Memory subsystem 2220 represents the main memory of system 2200 and provides storage for code to be executed by processor 2210 or data values ​​to be used in executing routines. Memory subsystem 2220 may include one or more memory devices 2230, such as read-only memory (ROM), flash memory, one or more types of random access memory (RAM), such as DRAM, or other memory devices, or a combination of such devices. Memory 2230 stores and hosts, among other things, an operating system (OS) 2232 to provide a software platform for the execution of instructions in system 2200. Additionally, applications 2234 may execute on the OS 2232 software platform from memory 2230. Applications 2234 and OS 2232 may execute within a virtual machine or container environment having separate allocated memory regions. Applications 2234 represent programs having their own operating logic to implement the execution of one or more functions. Processes 2236 represent agents or routines that provide auxiliary functionality to OS 2232 or one or more applications 2234, or a combination. OS 2232, applications 2234, and processes 2236 implement software logic that provides functionality to system 2200. In one example, memory subsystem 2220 includes memory controller 2222, which is a memory controller that generates and issues commands to memory 2230. It will be appreciated that memory controller 2222 may be a physical part of processor 2210 or a physical part of interface 2212. For example, memory controller 2222 may be an integrated memory controller integrated on circuitry with processor 2210.

[0110] Although not specifically shown, it will be understood that system 2200 can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, etc. A bus or other signal line can communicatively or electrically couple components to each other, or can couple components both communicatively and electrically. A bus can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits, or a combination. A bus can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) Standard 1394 bus (Firewire®).

[0111] In one example, system 2200 includes interface 2214, which can be coupled to interface 2212. In one example, interface 2214 represents an interface circuit, which can include standalone components and integrated circuits. In one example, multiple user interface components and / or peripheral components are coupled to interface 2214. Network interface 2250 provides system 2200 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 2250 can include Ethernet adapters, wireless interconnection components, cellular network interconnection components, USB (Universal Serial Bus), or other wired or wireless, standards-based or proprietary interfaces. Network interface 2250 can transmit data to devices in the same data center or rack or to remote devices, which can include transmitting data stored in memory. Network interface 2250 can receive data from remote devices, which can include storing the received data in memory. Various embodiments can be used with network interface 2250, processor 2210, and memory subsystem 2220.

[0112] In one example, system 2200 includes one or more input / output (I / O) interfaces 2260. I / O interface 2260 can include one or more interface components (e.g., audio, alphanumeric, haptic / touch, or other interfaces) through which a user interacts with system 2200. Peripheral interface 2270 can include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that connect dependently to system 2200. A dependent connection is one in which system 2200 provides a software or hardware platform on which operations are executed and with which a user interacts.

[0113] In one example, system 2200 includes a storage subsystem 2280 that stores data in a nonvolatile manner. In one example, in some system implementations, at least some components of storage subsystem 2280 can overlap with components of memory subsystem 2220. Storage subsystem 2280 includes a storage device 2284, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid-state, or optical-based disks, or a combination thereof. Storage 2284 holds code or instructions and data 2286 in a persistent state (i.e., values ​​are retained despite interruptions in power to system 2200). Storage 2284 can generally be considered to be “memory,” while memory 2230 is typically the execution or operating memory that provides instructions to processor 2210. While storage 2284 is nonvolatile, memory 2230 can include volatile memory (i.e., data values ​​or states are indeterminate when power is interrupted to system 2200). In one example, storage subsystem 2280 includes a controller 2282 that interfaces with storage 2284. In one example, controller 2282 can be a physical part of interface 2214 or processor 2210, or can include circuitry or logic in both processor 2210 and interface 2214.

[0114] Volatile memory is memory whose state (and therefore the data stored in it) is indeterminate when power to the device is interrupted. Dynamic volatile memory requires refreshing the data stored in the device to maintain its state. An example of dynamic volatile memory includes DRAM (Dynamic Random Access Memory), or some variant thereof, such as Synchronous DRAM (SDRAM). The memory subsystem described herein may be implemented using DDR3 (Double Data Rate Version 3, first released by JEDEC (Joint Electron Devices Engineering Council) on June 27, 2007), DDR4 (DDR Version 4, initial specification published by JEDEC in September 2012), DDR4E (DDR Version 4), LPDDR3 (Low Power DDR Version 3, JESD209-3B, August 2013, by JEDEC), LPDDR4 (LPDDR Version 4, JESD209-4, August 2014, by JEDEC), or similar memory specifications. The interface may be compatible with several memory technologies, such as JEDEC standards such as WIO2 (Wide Input / Output Version 2, JESD229-2, first published by JEDEC in August 2014), HBM (High Bandwidth Memory, JESD325, first published by JEDEC in October 2013), LPDDR5 (currently under consideration by JEDEC), HBM2 (HBM Version 2, currently under consideration by JEDEC), etc., or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications. JEDEC standards are available at www.jedec.org.

[0115] A non-volatile memory (NVM) device is memory whose state is determinable even when power to the device is interrupted. In one embodiment, the NVM device may include a block-addressable memory device such as NAND technology, and more specifically, a multi-threshold level NAND flash memory (e.g., single-level cell ("SLC"), multi-level cell ("MLC"), quad-level cell ("QLC"), tri-level cell ("TLC"), or some other NAND). NVM devices may also include single-level or multi-level phase change memory (PCM) or switched phase change memory (PCMS), byte-addressable write-in-place three-dimensional cross-point memory devices such as Intel® Optane™ memory, or other byte-addressable write-in-place NVM devices (also called persistent memory), NVM devices using chalcogenide phase change materials (e.g., chalcogenide glasses), resistive memories including metal oxide-based, oxygen vacancy-based and conductive bridge random access memories (CB-RAM), nanowire memories, ferroelectric random access memories (FeRAM, FRAM®), magnetoresistive random access memories (MRAM) incorporating memristor technology, spin-transfer torque (STT)-MRAM, spintronic magnetic junction memory-based devices, magnetic tunnel junction (MTJ)-based devices, DW (domain wall) and SOT (spin-orbit transfer)-based devices, thyristor-based memory devices, or any combination of the above or other memories.

[0116] A power source (not shown) provides power to the components of system 2200. More specifically, the power source typically interfaces with one or more power supplies in system 2200 to provide power to the components of system 2200. In one example, the power supply includes an AC-DC (alternating current-direct current) adapter that plugs into a wall outlet. Such AC power can be a renewable energy (e.g., solar-powered) source. In one example, the power source includes a DC power source, such as an external AC / DC converter. In one example, the power source or power supply includes wireless charging hardware that charges in proximity to a charging field. In one example, the power source can include an internal battery, an AC source, a motion-based power supply, a solar power supply, or a fuel cell source.

[0117] In one example, system 2200 can be implemented using interconnected processors, memory, storage, network interfaces, and other components. The high-speed interconnect can be Ethernet (IEEE 802.3), Remote Direct Memory Access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Quick UDP Internet Connection (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect Express (PCIe), Intel QuickPath Interconnect (QPI), Intel UltraPath Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omnipath, Compute Express Link (CXL), HyperTransport, High-Speed ​​Fabric, NVLink, Advanced Microcontroller Bus Architecture (AMBA) Interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP® Long Term Evolution (LTE) (4G), 3GPP 5G, and variations thereof. Data can be copied or stored on virtualized storage nodes using protocols such as NVMe over Fabric (NVMe-oF) or NVMe.

[0118] Embodiments herein may be implemented in various types of computing and networking equipment, such as switches, routers, racks, and blade servers, such as those utilized in data center and / or server farm environments. Servers used in data centers and server farms comprise arrayed server configurations, such as rack-based servers or blade servers. These servers are communicatively interconnected via various network facilities, such as dividing sets of servers into local area networks (LANs) with appropriate switching and routing facilities between LANs to form private intranets. For example, cloud hosting facilities may typically utilize large data centers with numerous servers. Blades comprise separate computing platforms configured to perform server-type functions, i.e., "servers on a card." Thus, blades include components common to traditional servers, including a main printed circuit board (main board) providing internal wiring (i.e., buses) for coupling appropriate integrated circuits (ICs) and other components mounted on the board.

[0119] Various embodiments can be used in data centers, including memory pools, storage pools, or accelerators, to scale out storage or memory transactions using NVMe-oF. Various embodiments can be used by cloud service providers using distributed resources (e.g., compute, memory, storage, accelerators, storage). The distributed resources can be located among one or more of base stations, fog data centers, edge data centers, or remote data centers. Various embodiments can be used in base stations, on-premises data centers, off-premises data centers, edge network elements, fog network elements, and / or hybrid data centers (e.g., data centers that use virtualization, cloud, and software-defined networking to distribute application workloads across physical data centers and distributed multicloud environments) that support communications using wired or wireless protocols (e.g., 3GPP Long Term Evolution (LTE) (4G) or 3GPP 5G)).

[0120] FIG. 23 depicts an environment 2300 including multiple computing racks 2302, each including a top-of-rack (ToR) switch 2304, a pod manager 2306, and multiple pool system drawers. Various embodiments can be used for the switch. Generally, a pool system drawer may include a pool compute drawer and a pool storage drawer. Generally, a pool system drawer may also include a pool memory drawer and a pool input / output (I / O) drawer. In the illustrated embodiment, the pool system drawer includes an Intel® XEON® pool computer drawer 2308, an Intel® ATOM™ pool computer drawer 2310, a pool storage drawer 2312, a pool memory drawer 2314, and a pool I / O drawer 2316. Each of the pool system drawers is connected to the ToR switch 2304 via a high-speed link 2318, such as a 40 gigabit per second (Gb / s) or 100 Gb / s Ethernet link or a 100+ Gb / s silicon photonics (SiPh) optical link.

[0121] Multiple computing racks 2302 may be interconnected via their ToR switches 2304 (e.g., pod-level switches or data center switches), as shown by their connections to network 2320. In some embodiments, groups of computing racks 2302 are managed as separate pods via pod manager 2306. In one embodiment, a single pod manager is used to manage all racks in a pod. Alternatively, a distributed pod manager may be used for pod management operations.

[0122] Environment 2300 further includes a management interface 2322 that is used to manage various aspects of the environment, including managing rack configuration with corresponding parameters stored as rack configuration data 2324. Environment 2300 can be used for computing racks.

[0123] Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The determination of whether an example is implemented using hardware and / or software elements may vary according to any number of factors, such as desired computation rates, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints, as desired for a given implementation. It should be noted that hardware elements, firmware elements, and / or software elements may be collectively or individually referred to herein as “modules,” “logic,” “circuitry,” or “circuitry.” A processor may be a hardware state machine, digital control logic, a central processing unit, or a combination of one or more of any hardware, firmware, and / or software elements.

[0124] Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. The computer-readable medium may include a non-transitory storage medium that stores logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. In some examples, the logic may include various software elements such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0125] According to some examples, a computer-readable medium may include a non-transitory storage medium that stores or maintains instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform methods and / or operations according to described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. The instructions may be implemented according to a predetermined computer language, style, or syntax to instruct the machine, computing device, or system to perform a particular function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0126] One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium that represent various logic within a processor, which, when read by a machine, computing device, or system, causes the logic to be assembled into the machine, computing device, or system to perform the techniques described herein. Such representations, known as "IP cores," may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually produce the logic or processor.

[0127] Appearances of the phrase "one example" or "example" do not necessarily all refer to the same example or embodiment. Any aspect described herein can be combined with any other aspect or similar aspect described herein, regardless of whether the aspects are described with reference to the same figure or element. The division, omission, or inclusion of block functions depicted in the accompanying figures does not necessarily imply that hardware components, circuits, software, and / or elements for implementing those functions are necessarily divided, omitted, or included in the embodiment.

[0128] Some examples may be described using the terms "coupled" and "connected," along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other.

[0129] The terms "first," "second," and the like, used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms "a" and "an" used herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term "asserted," as used herein with respect to a signal, means that the signal is active and the state of the signal may be achieved by applying any logic level, either logic 0 or logic 1, to the signal. The terms "following" or "after" may refer to immediately following or after some other event or events. Other sequences of steps may also be performed according to alternative embodiments. Furthermore, additional steps may be added or deleted depending on the particular application. Any combination of modifications may be used, and those skilled in the art having the benefit of this disclosure will recognize numerous variations, modifications, and alternative embodiments thereof.

[0130] Disjunctive language, such as the phrase "at least one of X, Y, or Z," is understood to be generally used to indicate that, within context, an item, term, etc., can be either X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z), unless otherwise indicated. Thus, such disjunctive language generally does not and should not imply that a particular embodiment requires at least one X, at least one Y, or at least one Z to each be present. Furthermore, disjunctive language, such as the phrase "at least one of X, Y, or Z," should also be understood to mean X, Y, Z, or any combination thereof, including "X, Y, and / or Z," unless otherwise indicated.

[0131] Illustrative examples of the devices, systems, and methods disclosed herein are provided below. An embodiment of the devices, systems, and methods may include any one or more, and any combination, of the examples described below.

[0132] Example 1 includes an apparatus including a gain cell embedded dynamic random access memory (eDRAM) device including a write circuit, a storage device, and a read circuit, wherein the read circuit is disposed at least partially below the write circuit and in a plane different from the plane of the write circuit, the storage device coupling the write circuit to the read circuit, and one or more of the write circuit or the read circuit being bonded to the storage device.

[0133] Example 2 can be combined with any example, where the write circuit comprises a layer having a drain region, a channel layer, a gate oxide layer, a gate layer having a write word line interface, and a source region having a write bit line interface.

[0134] Example 3 can be combined with any example, where the read circuit comprises a channel region, a gate oxide layer, a gate layer, a source region having a read bit line interface, and a drain region having a read word line interface.

[0135] Example 4 can be combined with any example, where the write circuit comprises a layer, a drain region, a conductive region coupling the drain region to the storage device through the layer, a channel layer, a gate oxide layer, a gate layer, and a source region having a write bitline interface.

[0136] Example 5 can be combined with any example, wherein the readout circuit comprises a gate region, a gate oxide region at least partially formed on the gate region, a channel region at least partially formed on the gate oxide region, a source region formed on a portion of the channel region, and a drain region formed on a portion of the channel region.

[0137] Example 6 can be combined with any example, wherein the write circuit comprises a channel region, a gate oxide region at least partially formed over the channel region, a gate region at least partially formed over the gate oxide region, a source region formed over a portion of the channel region, and a drain region formed over a portion of the channel region.

[0138] Example 7 can be combined with any example, wherein the write circuit comprises a channel region, a source region formed below a portion of the channel region, a drain region formed below a portion of the channel region, a gate oxide region formed at least partially over the channel region, and a gate region formed at least partially over the gate oxide region.

[0139] Example 8 can be combined with any example, wherein the storage device comprises at least one capacitor and a dielectric in contact with the at least one capacitor.

[0140] Example 9 can be combined with any example, wherein the storage device comprises a capacitor on a bit line (COB).

[0141] Example 10 can be combined with any example, wherein the write circuit includes one or more of poly-Si, Si, Ge, poly-Ge, III-V, GaN, MoS2, WSe2, MoSe2, WSe2, InS, HfS, ZnS, ZnSe, In2O3, ZnO, AZO, IGZO, or IZO.

[0142] Example 11 can be combined with any example, wherein the write circuitry is bonded to the storage device using a bonding material.

[0143] Example 12 can be combined with any example, wherein the bonding material includes one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

[0144] Example 13 can be combined with any example, wherein the readout circuit is bonded to the storage device using a bonding material.

[0145] Example 14 can be combined with any example, wherein the bonding material includes one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

[0146] Example 15 can be combined with any example, including a computational near memory (CNM) circuit, the CNM circuit coupled to a read circuit or a write circuit.

[0147] Example 16 can be combined with any example and includes a memory emulation circuit that provides output from a GainCell eDRAM device at different effective output rates.

[0148] Example 17 may be combined with any example and includes an apparatus comprising: a memory device comprising a gain cell embedded dynamic random access memory (eDRAM) memory cell, the gain cell eDRAM memory cell comprising write circuitry formed at least partially above the memory cell and read circuitry formed at least partially below the memory cell; and a computational near-memory device coupled to the memory device.

[0149] Example 18 can be combined with any example, where the computational near memory device performs one or more of vector-vector multiplication, multiplication and accumulation (MAC), a dot product engine that performs AND, OR, XOR, NOT, neural network activation operations, softmax exponentiation, data compression, encryption, a media accelerator, a string matching or regular expression accelerator, or pointer chasing.

[0150] Example 19 can be combined with any example and includes an emulation circuit that provides an output of a memory device to emulate an output of a second memory device.

[0151] Example 20 can be combined with any example, wherein the emulation circuit comprises one or more of a controller, a multiplexer, or a register.

[0152] Example 21 can be combined with any example and includes a processor coupled to a memory device and a computational near-memory device.

[0153] Example 22 can be combined with any example, wherein the computational near-memory device is bonded to the memory device using a bonding material, and the bonding material includes one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

[0154] Example 23 may be combined with any example and includes a method of forming a gain cell memory device, including forming a first region on a first substrate, the first region comprising a word line driver, a read circuit, and an active fin; forming a dielectric region on the first region; forming at least one storage region in the dielectric region; forming a layer of non-silicon-based write circuitry on the dielectric region; bonding a second substrate to the layer of non-silicon-based write circuitry; and removing the first substrate to expose the active fin.

[0155] Example 24 may be combined with any example, wherein bonding the second substrate to the layer of non-silicon-based write circuitry includes applying a bonding material to opposing surfaces of the second substrate and the layer of non-silicon-based write circuitry, wherein the bonding material includes one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

[0156] Example 25 may be combined with any example, and wherein bonding the second substrate to the layer of non-silicon-based write circuitry includes applying a bonding material using one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC), and pressing the bonding materials on opposing surfaces together.

[0157] Example 26 can be combined with any example, wherein forming a layer of write circuitry over the dielectric region includes bonding the layer of write circuitry to a surface of the dielectric region.

[0158] Example 27 can be combined with any example and includes forming circuitry in a second substrate.

[0159] Example 28 may be combined with any example and includes a system comprising: a memory device comprising gain cell-embedded dynamic random access memory (eDRAM) memory cells, the eDRAM memory cells comprising write circuitry formed at least partially above the memory cells and read circuitry formed at least partially below the memory cells; a computational near-memory device coupled to the memory device; a processor; and an interface from the memory device to the processor.

[0160] Example 29 can be combined with any example, where the computational near memory device performs one or more of vector-vector multiplication, multiplication and accumulation (MAC), a dot product engine that performs AND, OR, XOR, NOT, neural network activation operations, softmax exponentiation, data compression, encryption, a media accelerator, a string matching or regular expression accelerator, or pointer chasing.

[0161] Example 30 can be combined with any of the examples and includes an emulation circuit that provides an output of a memory device to emulate the output read rate of an SRAM memory device.

[0162] Example 31 can be combined with any example, wherein the emulation circuit comprises one or more of a controller, a multiplexer, or a register.

[0163] Example 32 can be combined with any example, wherein the controller controls the forwarding of memory access requests to multiple banks of the memory device, and according to a selection by the controller, the multiplexer sends data from the memory device to the computational near memory device, or the multiplexer receives data from the computational near memory device and provides it to the memory device.

[0164] Example 33 can be combined with any of the examples, where the register buffers data output from the memory device prior to output to the computational near memory device.

[0165] Example 34 can be combined with any example, wherein the computational near-memory device is bonded to the memory device using a bonding material including one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

[0166] Example 35 can be combined with any example, and includes a network interface communicatively coupled to the processor.

[0167] Example 36 may be combined with any example and includes a system comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one memory comprises a gain cell embedded dynamic random access memory (eDRAM) device comprising a write circuit, a storage device, and a read circuit, wherein the read circuit is disposed at least partially below the write circuit and in a plane different from the plane of the write circuit, wherein the storage device couples the write circuit to the read circuit, and wherein one or more of the write circuit or the read circuit are bonded to the storage device.

[0168] Example 37 can be combined with any example, wherein the storage device comprises at least one capacitor and a dielectric in contact with the at least one capacitor.

[0169] Example 38 can be combined with any example, wherein the write circuit includes one or more of poly-Si, Si, Ge, poly-Ge, III-V, GaN, MoS2, WSe2, MoSe2, WSe2, InS, HfS, ZnS, ZnSe, In2O3, ZnO, AZO, IGZO, or IZO.

[0170] Example 39 can be combined with any example, wherein the readout circuit is bonded to the storage device using a bonding material, and the bonding material includes one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC). (Other possible items) (Item 1) A write circuit; A storage device; Readout circuit and A gain cell embedded dynamic random access memory (eDRAM) device comprising: An apparatus comprising: the read circuit is located at least partially below the write circuit and in a plane different from the plane of the write circuit, the storage device will couple the write circuit to the read circuit, and one or more of the write circuit or the read circuit is bonded to the storage device; Device. (Item 2) The write circuitry a layer having a drain region; a channel layer; a gate oxide layer; a gate layer having a write word line interface; a source region having a write bit line interface; Item 1. The device according to item 1, comprising: (Item 3) The readout circuit a channel region; a gate oxide layer; a gate layer; a source region having a read bit line interface; a drain region having a read word line interface; Item 1. The device according to item 1, comprising: (Item 4) The write circuitry Layers and a drain region; a conductive region coupling the drain region to the storage device through the layer; a channel layer; a gate oxide layer; a gate layer; a source region having a write bit line interface; Item 1. The device according to item 1, comprising: (Item 5) The readout circuit a gate region; a gate oxide region formed at least partially overlying said gate region; a channel region formed at least partially overlying the gate oxide region; a source region formed over a portion of the channel region; a drain region formed over a portion of the channel region; Item 1. The device according to item 1, comprising: (Item 6) The write circuitry a channel region; a gate oxide region formed at least partially overlying the channel region; a gate region formed at least partially overlying the gate oxide region; a source region formed over a portion of the channel region; a drain region formed over a portion of the channel region; Item 1. The device according to item 1, comprising: (Item 7) The write circuitry a channel region; a source region formed below a portion of the channel region; a drain region formed below a portion of the channel region; a gate oxide region formed at least partially overlying the channel region; a gate region formed at least partially over the gate oxide region; Item 1. The device according to item 1, comprising: (Item 8) the storage device at least one capacitor; and a dielectric in contact with said at least one capacitor. Item 1. The device according to item 1, comprising: (Item 9) Item 10. The apparatus of item 1, wherein the storage device comprises a capacitor on a bit line (COB). (Item 10) Item 10. The apparatus of item 1, wherein the write circuit comprises one or more of poly-Si, Si, Ge, poly-Ge, III-V, GaN, MoS2, WSe2, MoSe2, WSe2, InS, HfS, ZnS, ZnSe, In2O3, ZnO, AZO, IGZO, or IZO. (Item 11) Item 10. The apparatus of item 1, wherein the write circuit is bonded to the storage device using a bonding material. (Item 12) Item 12. The apparatus of item 11, wherein the bonding material comprises one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC). (Item 13) Item 10. The apparatus of item 1, wherein the readout circuit is bonded to the storage device using a bonding material. (Item 14) Item 14. The apparatus of item 13, wherein the bonding material comprises one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC). (Item 15) 2. The device of claim 1, comprising a computational near memory (CNM) circuit, the CNM circuit coupled to the read circuit or the write circuit. (Item 16) Item 10. The apparatus of item 1, comprising a memory emulation circuit that provides output from the gain cell eDRAM device at different effective output rates. (Item 17) 1. A method of forming a gain cell memory device, comprising: forming a first region on a first substrate, the first region comprising word line drivers, readout circuitry, and active fins; forming a dielectric region over the first region; forming at least one accumulation region within the dielectric region; forming a layer of non-silicon based write circuitry over the dielectric region; bonding a second substrate to the layer of non-silicon based write circuitry; removing the first substrate to expose the active fins; A method comprising: (Item 18) bonding a second substrate to the layer of non-silicon-based write circuit includes applying a bonding material to opposing surfaces of the second substrate and the layer of non-silicon-based write circuit, the bonding material including one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC); Item 17. The method according to item 17. (Item 19) bonding a second substrate to said layer of non-silicon based write circuitry; applying the bonding material using one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC); pressing the bonding materials on the opposing surfaces together; Item 19. The method according to item 18, comprising: (Item 20) Item 18. The method of item 17, wherein the step of forming a layer of write circuitry on the dielectric region includes the step of bonding a layer of write circuitry to a surface of the dielectric region. (Item 21) Item 18. The method of item 17, comprising forming circuitry in the second substrate. (Item 22) at least one processor; at least one memory coupled to said at least one processor; A system comprising: the at least one memory A write circuit; A storage device; Readout circuit and A gain cell embedded dynamic random access memory (eDRAM) device comprising: Equipped with the read circuit is located at least partially below the write circuit and in a plane different from the plane of the write circuit, the storage device will couple the write circuit to the read circuit, and one or more of the write circuit or the read circuit is bonded to the storage device; system. (Item 23) the storage device at least one capacitor; and a dielectric in contact with said at least one capacitor. Item 23. The system of item 22, comprising: (Item 24) 23. The system of claim 22, wherein the write circuit comprises one or more of poly-Si, Si, Ge, poly-Ge, III-V, GaN, MoS2, WSe2, MoSe2, WSe2, InS, HfS, ZnS, ZnSe, In2O3, ZnO, AZO, IGZO, or IZO. (Item 25) 23. The system of claim 22, wherein the readout circuit is bonded to the storage device using a bonding material, the bonding material comprising one or more of silicon dioxide (SiO), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

Claims

1. a plurality of gain cell embedded dynamic random access memory (eDRAM) devices; at least two of the plurality of gain cell eDRAM devices; A write circuit; A storage device; Readout circuit and and the write circuitry is disposed at least partially above the storage device; the read circuitry is disposed in a plane different from a plane of the write circuitry, at least partially below the write circuitry and at least partially below the storage device, the storage device coupling the write circuitry to the read circuitry; Device.

2. The apparatus of claim 1 , wherein the write circuitry is bonded to the storage device using a bonding material.

3. the write circuit is bonded to the storage device using a bonding material; 10. The apparatus of claim 1, wherein the bonding material comprises one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbonitride (SiCN), or silicon oxycarbide (SiOC).

4. The write circuitry a layer having a drain region; a channel layer; a gate oxide layer; a gate layer having a write word line interface; a source region having a write bit line interface; 4. The device according to claim 1, comprising:

5. The readout circuit a channel region; a gate oxide layer; a gate layer; a source region having a read bit line interface; a drain region having a read word line interface; 5. The apparatus according to claim 1, comprising:

6. The write circuitry Layers and a drain region; a conductive region coupling the drain region to the storage device through the layer; a channel layer; a gate oxide layer; a gate layer; a source region having a write bit line interface; 6. The apparatus of claim 1, 2, 3 or 5, comprising:

7. The readout circuit a gate region; a gate oxide region formed over a portion of the gate region; a channel region formed over a portion of the gate oxide region; a source region formed over a portion of the channel region; a drain region formed over a portion of the channel region; 7. The apparatus of claim 1, 2, 3, 4, or 6, comprising:

8. The write circuitry a channel region; a gate oxide region formed over a portion of the channel region; a gate region formed on a portion of the gate oxide region; a source region formed over a portion of the channel region; a drain region formed over a portion of the channel region; 8. The apparatus of claim 1, 2, 3, 5 or 7, comprising:

9. The write circuitry a channel region; a source region formed below a portion of the channel region; a drain region formed below a portion of the channel region; a gate oxide region formed over a portion of the channel region; a gate region formed on a portion of the gate oxide region; 8. The apparatus of claim 1, 2, 3, 5 or 7, comprising:

10. the storage device at least one capacitor; and a dielectric in contact with said at least one capacitor.

10. The apparatus of claim 1, comprising:

11. 11. The apparatus of claim 1, wherein the storage device comprises a capacitor on a bit line (COB).

12. 12. The apparatus of claim 1, wherein the write circuitry comprises one or more of poly-Si, Si, Ge, poly-Ge, III-V, GaN, MoS2, WSe2, MoSe2, WSe2, InS, HfS, ZnS, ZnSe, In2O3, ZnO, AZO, IGZO, or IZO.

13. 13. The apparatus of claim 1, further comprising a computational near memory (CNM) circuit, the CNM circuit being coupled to the read circuit or the write circuit.

14. Computational Near Memory (CNM) circuitry; 14. The apparatus of claim 1, wherein the CNM circuitry performs one or more of vector-vector multiplication, multiplication and accumulation (MAC), a dot product engine that performs AND, OR, XOR, NOT, neural network activation operations, softmax exponentiation, data compression, encryption, a media accelerator, a string matching or regular expression accelerator, or pointer chasing.

15. 15. The apparatus of claim 1, further comprising a memory emulation circuit that provides an output from the gain cell eDRAM device to emulate the output read rate of a static random access memory (SRAM) device.

16. the emulation circuitry comprises one or more of a controller, a multiplexer, or a register; 16. The apparatus of claim 13 or 15, wherein the controller controls forwarding of memory access requests to multiple banks of a memory device, and wherein, according to a selection by the controller, the multiplexer either sends data from the memory device to the computational near memory circuitry or receives data from the computational near memory circuitry and provides it to the memory device.

17. at least one processor; at least one memory coupled to said at least one processor; A system comprising: the at least one memory a plurality of gain cell embedded dynamic random access memory (eDRAM) devices; at least two of the plurality of gain cell eDRAM devices; A write circuit; A storage device; Readout circuit and and the write circuitry is disposed at least partially above the storage device; the read circuitry is disposed at least partially below the storage device; the read circuit is disposed at least partially below the write circuit and in a plane different from that of the write circuit; the storage device coupling the write circuitry to the read circuitry; one or more of the write circuitry or the read circuitry is coupled to the storage device; system.

18. 20. The system of claim 17, wherein the storage device comprises at least one capacitor and a dielectric in contact with the at least one capacitor.

19. 19. The system of claim 17 or 18, wherein the storage device comprises a capacitor on a bitline (COB).

20. 20. The system of claim 17, further comprising a computational near memory (CNM) circuit, the CNM circuit being coupled to the read circuit or the write circuit.

21. 21. The system of claim 17, further comprising a memory emulation circuit that provides an output from the gain cell eDRAM device to emulate the output read rate of a static random access memory (SRAM) device at a set output rate.

22. 22. The system of any one of claims 17 to 21, wherein the write circuitry comprises one or more of poly-Si, Si, Ge, poly-Ge, III-V, GaN, MoS2, WSe2, MoSe2, WSe2, InS, HfS, ZnS, ZnSe, In2O3, ZnO, AZO, IGZO, or IZO.

23. the read circuit is bonded to the storage device using a bonding material; 23. The system of any one of claims 17-22, wherein the bonding material comprises one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

24. the write circuit is bonded to the storage device using a bonding material; 24. The system of any one of claims 17-23, wherein the bonding material comprises one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

Images