Antenna device and method for forming the same

Abstract

This invention provides a novel manufacturing process for producing low-cost, high-performance phased array antennas. [Solution] A method for forming an antenna device includes the steps of receiving a substrate made of glass and forming a redistribution layer (RDL) on the substrate. The formation of the RDL includes the steps of depositing a first metallized layer on a first surface of the substrate, depositing a first patterned dielectric layer having a first thickness on the first metallized layer, depositing a second metallized layer on the first patterned dielectric layer, and forming a second patterned dielectric layer on the second metallized layer. The second dielectric layer comprises a photoimageable dielectric (PID) material. The second patterned dielectric layer has a second thickness at least twice the first thickness.

Description

[Technical Field]

[0001] (Priority claims and cross-references) This application claims priority to U.S. Provisional Applications No. 63 / 726,718 and No. 63 / 726,727, filed on 2 December 2024, the disclosures of both of these applications being incorporated herein by reference in their entirety. [Background technology]

[0002] In modern wireless communication technology, satellite communications are attracting considerable attention because they offer advantages over conventional terrestrial communication technologies, such as improved signal coverage and larger bandwidth. Integrating satellite communication systems into existing cellular terrestrial networks appears promising for expanding both the coverage and bandwidth of current wireless communication infrastructure. Furthermore, phased array antenna technology is commonly used in satellite communications to improve power efficiency over relatively long transmission distances. However, current electronic and semiconductor manufacturing technologies, which are suitable for low-frequency bands, are insufficient to provide a cost-effective and high-performance solution for forming phased array antennas that operate in high-frequency bands for satellite communications. As a result, the market introduction of satellite communication-based products has been slow. Therefore, there is a need to develop novel manufacturing processes for producing low-cost, high-performance phased array antennas. [Overview of the Initiative]

[0003] According to embodiments of the present disclosure, a method for forming an antenna device includes the steps of receiving a substrate made of glass and forming a redistribution layer (RDL) on the substrate. The steps for forming an RDL include depositing a first metallization layer on a first surface of the substrate, depositing a first patterned dielectric layer having a first thickness on the first metallization layer, depositing a second metallization layer on the first patterned dielectric layer, and forming a second patterned dielectric layer on the second metallization layer. The second dielectric layer comprises a photoimageable dielectric (PID) material. The second patterned dielectric layer has a second thickness that is at least twice the first thickness.

[0004] According to embodiments of the present disclosure, the antenna device includes a substrate made of glass and a redistribution layer (RDL) disposed on a first surface of the substrate. The RDL includes a first metallized layer on the first surface of the substrate, a first dielectric layer having a first thickness on the first metallized layer, a second metallized layer on the first dielectric layer and electrically coupled to the first metallized layer, and a second dielectric layer on the second metallized layer and the first dielectric layer. The second dielectric layer comprises a photoimageable dielectric (PID) material and has a thickness at least twice that of the first thickness.

[0005] Through the proposed antenna device arrangement, the redistribution layer (RDL) of the antenna device may be formed in a cost-effective manner with a thickness corresponding to the operating frequency of the antenna device. The performance of the aforementioned antenna device can also be maintained or improved. [Brief explanation of the drawing]

[0006] The aspects of this disclosure will be best understood from the following detailed description with reference to the accompanying drawings. Please note that, in accordance with standard industry practices, various features are not depicted at a consistent scale. In practice, the dimensions of various features may be arbitrarily enlarged or reduced to clarify the explanation.

[0007] [Figure 1A] This is a perspective view of a phased array antenna according to some embodiments of the present disclosure.

[0008] [Figure 1B] This is a cross-sectional view of a phased array antenna shown in Figure 1A, according to some embodiments of the present disclosure.

[0009] [Figure 2A] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2B] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2C] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2D] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2E] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2F] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2G] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2H] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2I] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2J]A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2K] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2L] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2M] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2N] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2O] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2P] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 2Q] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure.

[0010] [Figure 3A] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 3B] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 3C] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 3D] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 3E] A cross-sectional view of an intermediate stage of a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 3F] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 3G] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 3H] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure. [Figure 3I] This is a cross-sectional view of an intermediate step in a method for forming a phased array antenna according to some embodiments of the present disclosure.

[0011] [Figure 4A] This is a cross-sectional view of a phased array antenna according to some embodiments of the present disclosure.

[0012] [Figure 4B] This is a superimposed top view of conductive vias in different metallized layers according to some embodiments of the present disclosure.

[0013] [Figure 5] This is a cross-sectional view of an antenna device according to several comparative embodiments.

[0014] [Figure 6] This is a schematic flowchart of a method for forming an antenna device according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0015] The following disclosure provides many different embodiments or examples for carrying out different features of the subject matter provided. To simplify this disclosure, specific embodiments of the components and their arrangements are described below. Naturally, these are merely examples and not intended to be limiting. For example, in the following description, the formation of the first feature above or on top of the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, or it may include embodiments in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature do not come into direct contact. Furthermore, the reference numerals and / or letters may be repeated in various embodiments of this disclosure. This repetition is for the purpose of simplification and clarity and does not, in itself, indicate the relationships between the various embodiments and / or configurations described.

[0016] Furthermore, spatially relative terms such as "down," "below," "lower part," "upper part," and "upper part" may be used herein to facilitate descriptions of the relationship between one element or feature and another element (or multiple elements) or feature (or multiple features), as shown in the drawings. Spatially relative terminology is intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawing. The apparatus may be oriented in other ways (90-degree rotation or orientation in other directions), and spatially relative descriptive terms used herein may be interpreted accordingly.

[0017] Although the numerical ranges and parameters representing the broad scope of this disclosure are approximations, the numerical values ​​shown in each specific example are reported as accurately as possible. However, each value inherently contains a certain error that inevitably arises from the standard deviation observed in each test measurement. Furthermore, as used herein, the terms “about,” “substantial,” or “effectively” generally mean within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the terms “approximately,” “substantial,” or “substantially” mean, as considered by those skilled in the art, within the acceptable standard error of the mean. Except for the examples of operation / operation, or unless otherwise specified, all numerical ranges, quantities, values, and percentages of material quantities, durations of time, temperatures, operating conditions, and ratios disclosed herein should be understood in all cases to be modified by the terms “approximately,” “roughly,” “approximately,” “substantial,” or “substantially.” Accordingly, unless otherwise indicated, the numerical parameters set forth in this disclosure and the appended claims are approximations that may vary as needed. At the very least, each numerical parameter should be interpreted by applying standard rounding techniques in light of the number of significant figures reported. In this specification, the scope can be expressed as from one endpoint to another, or between two endpoints. Unless otherwise specified, all scope disclosed herein includes endpoints.

[0018] As used herein, the term “connected” may be interpreted as “electrically connected,” and the term “coupled” may also be interpreted as “electrically coupled.” "Connected" and "joined" may also be used to indicate that two or more elements cooperate or interact with each other.

[0019] Embodiments of the present disclosure include antenna devices designed for terrestrial and / or non-terrestrial radio communications, such as phased array antennas. The structure of a phased array antenna includes an array of antenna units and an array of radio frequency (RF) chips on both sides of the substrate. According to some embodiments, the substrate is a glass substrate with high flatness, low loss, and low cost, making it more suitable for large-scale phased array antennas than other low-loss materials such as ceramics. Furthermore, in order to electromagnetically couple RF signals between the antenna patch and the slits of a phased array antenna, one or more slits or slots are formed in the antenna ground plane. According to some embodiments, the region of the glass substrate between the antenna patch and the slit is substantially free of conductive elements, thereby reducing the cost of forming glass through-vias (TGVs) that carry RF signals within the substrate. Furthermore, the antenna device is located on a substrate and includes a redistribution layer (RDL) that functions as a circuit layer for housing signal lines and a ground plane. When an RDL is incorporated into an RF circuit with a glass substrate that does not contain a TGV to operate with high-frequency RF signals, such as RF signals of 10 gigahertz (GHz) or higher, the thickness of the RDL should be specifically determined to correspond to the wavelength of the operating frequency of the RF signal. However, currently available cost-effective film technologies for forming RDLs in other applications are not suitable for forming RDLs used in TGV-free glass substrates with a determined RDL thickness. Considering the above, this disclosure proposes a novel and cost-effective method for forming RDL having a determined thickness. As a result, high-performance phased array antennas can be realized at relatively low manufacturing costs.

[0020] Figure 1A is a perspective view of a phased array antenna 200 according to some embodiments of the present disclosure. Figure 1B is a cross-sectional view of the phased array antenna 200 shown in Figure 1A, according to several embodiments. The cross-sectional view follows the section line AA in Figure 1A. According to some embodiments, the phased array antenna 200 is an RF transmitter configured to transmit an RF signal, or an RF receiver configured to receive an RF signal. The phased array antenna 200 includes an array of antenna units, the dimensions of which are determined based on requirements, and the 3x5 array of the phased array antenna 200 is for illustrative purposes only. Other array configurations of the phased array antenna 200 are also within the scope intended of this disclosure. The phased array antenna 200 includes a substrate 202, an RDL 204, an array of antenna patches 206, and an array of RF chips 208. The number of antenna patches 206 may be the same as the number of RF chips 208.

[0021] RDL204 has an upper surface, and substrate 202 has a lower surface on the side of substrate 202 opposite to RDL204. The array of antenna patches 206 is formed on the underside of the substrate 202, and the array of RF chips 208 is positioned on the top surface of the RDL 204. Each of the RF chips 208 may include one or more semiconductor dies configured to generate, transmit, receive, or process RF signals. RF signals in satellite communications may operate at frequencies within the range between tens of kilohertz (kHz), such as 10 kHz, and hundreds of gigahertz (GHz), such as 300 GHz, for example, around 30 GHz. According to some embodiments, the antenna patch 206 is configured to emit an RF signal received from the RF chip 208 and radiate the RF signal outward, or to receive an RF signal from an external source and transmit the RF signal to the RF chip 208. The antenna patch 206 may be made of a conductive material such as copper, and may have a circular or elliptical shape. According to some embodiments, the antenna patch 206 may have a thickness of about 10 micrometers (μm) to about 100 μm.

[0022] According to some embodiments, the substrate 202 is formed from a transparent material such as glass, fused silica, silicon oxide, or quartz. According to some embodiments, the substrate 202 isolates the antenna patch 206 from the RDL 204 and RF chip 208. The RF signal may be transmitted from the RF chip 208 to the antenna patch 206 via the RDL204 and signal channel 202C in the substrate 202. The thickness of substrate 202 may be approximately 0.5 mm to approximately 1.5 mm. The signal channel 202C may be formed from the transparent material of the substrate 202. Since the material of substrate 202 is transparent to RF signals, substrate 202 itself can function as the material for signal channel 202C, without including any additional conductive material, such as TGV, within the projection area of ​​antenna patch 206, thereby enabling signal channel 202C to operate to electromagnetically transmit RF signals between RDL 204 and antenna patch 206. Substrate 202, which does not include such TGV, helps reduce manufacturing costs and time.

[0023] According to some embodiments, a key design parameter of the phased array antenna 200 is the thickness of the RDL204. In contrast to other low-frequency applications, in circuit design for RF circuits or antennas, the thickness of the RDL204 needs to be within a specific range, not only to reduce the size of the antenna package, but also due to a rule that stipulates that the thickness of the RDL204 corresponds to half the wavelength of the RF signal, in order to optimize the performance of the RF signal. Furthermore, the manufacturing cost of the proposed phased array antenna 200 can be reduced by using cost-effective techniques for forming the RDL204.

[0024] Existing cost-effective RDL technology uses a printed circuit board (PCB) as the RDL substrate, as shown in Figure 5. Figure 5 is a cross-sectional view of an antenna device 100 according to several comparative embodiments. According to such comparative embodiments, the antenna device 100 is an antenna unit of a phased array antenna. The antenna device 100 may include an RF chip 102, an RDL 104, a plurality of conductive bumps 106, and one or more antenna patches 108. The RF chip 102 and antenna patch 108 may be the same as the RF chip 208 and antenna patch 206, respectively, and for simplicity, the description of similar features will be omitted.

[0025] When a PCB is used as an RDL substrate, the RDL 104 may include multiple dielectric layers 112, one or more conductive wires or pads 114, and multiple conductive vias 116. The dielectric layer 112 can be formed from FR-4 (glass fiber epoxy laminate), prepreg (resin-impregnated glass cloth), epoxy, or another suitable dielectric material. The conductive wire or pad 114 may be patterned to form a signal line or ground plane that extends horizontally for transmitting or receiving RF signals. Similarly, the conductive via 116 is arranged to form a conductive path in the vertical direction for transmitting or receiving RF signals. The conductive wires / pads 114 and conductive vias 116 may be further interconnected via RDL 104 and conductive bumps 106 to electrically transmit RF signals between the RF chip 102 and the antenna patch 108.

[0026] According to several comparative embodiments, the thickness of a typical single-layer FR-4 dielectric layer 112 is approximately 0.8 mm to 3.2 mm. While the use of FR-4 or other similar epoxy materials for forming PCBs as substrates for RDL104 is a proven approach and offers cost advantages, the use of such materials may not be suitable for high-frequency applications, particularly those where RF signals operate at frequencies used in satellite communications, such as 30 GHz or higher. This is because important dimensions of the antenna device 100 or the phased array antenna 200, such as the width and spacing of the conductive wires 114, or the total thickness of the RDL 104 or 204, are determined to decrease as the frequency of the RF signal increases (or, conversely, as the wavelength of the RF signal decreases). Furthermore, the dimensions of the conductive wire 114 should satisfy the impedance matching requirements. To achieve impedance matching between most RF components, transmission lines within an RF circuit must have a characteristic impedance of approximately 50 ohms (Ω). According to general design principles based on the classical surface microstrip impedance equation, to achieve an impedance of 50 ohms, when the signal frequency increases to levels above 10 GHz, for example, 30 GHz, the thickness of the RDL104 must be reduced to less than approximately 100 μm, for example, less than 60 μm. For example, the thickness of RDL104 may be approximately 15 μm to approximately 60 μm. To achieve this, the thickness of each individual component layer of the RDL104, for example, the dielectric layer 112, must be significantly less than 60 μm, which is considerably smaller than the thickness of the typical single-layer FR-4 dielectric layer 112 described above. Therefore, PCB-based technologies for supporting FR-4 layers with a thickness of less than 100 μm may not be commercially viable. Furthermore, FR-4 type PCB materials generally exhibit high signal loss at high frequencies, making them suitable only for low-frequency RF applications, such as those operating in a frequency band of approximately 1-2 GHz. As a result, the process of forming RF circuits operating at GHz frequencies using current PCB-based technology dramatically increases costs, if possible.

[0027] Another well-known technique for forming RDLs is the fan-out panel-level process (FOPLP), which involves forming rewiring circuits on a glass-based panel using deposition-based techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) to form liquid crystal display (LCD) devices. Such deposition-based technologies applied to glass-based panels are widely used in the display panel industry. The typical thickness of the RDL204 shown in Figure 1B, formed using FOPLP technology with a three-layer structure, is approximately 2 μm to 15 μm, which is considerably lower than the 100 μm threshold required for RF signal transmission. However, since the proposed RF circuit includes a glass substrate 202 without TGV and a slit in RDL204 for transmitting RF signals, the effects of the slit design should be taken into consideration. According to some embodiments, the dimensions of the slits increase as the total thickness of the RDL204 decreases. Nevertheless, it has been found that reducing the slit size increases the signal loss of the RF signal. As a result, if the total thickness of the RDL204 is less than approximately 20 μm, the efficiency of the phased array antenna 200 becomes unacceptable due to high signal loss from the slits. Therefore, the total thickness of RDL204 should be maintained at a level greater than approximately 20 μm. Considering the above, FOPLP technology may not be a good choice for forming RDL204 because it is also insufficient to meet the minimum thickness requirements of RDL204.

[0028] To address the above issues, this disclosure proposes a new design and a new manufacturing process for forming RDL204. The proposed RDL204 is formed using a composite film formation process that utilizes a combination of build-up film, thin-film transistor (TFT) technology, and FOPLP-based technology. The desired thickness of RDL204 can be achieved through a low-cost manufacturing process and improved RF performance at high frequencies.

[0029] As shown in Figure 1B, according to some embodiments, the RDL204 is formed of multiple metallized layers (conductive wire layers or conductive via layers) within a stack. The metallized layer includes patterned conductive wires and / or conductive vias, which are electrically interconnected to form a conductive path for transmitting RF signals.

[0030] For example, the first metallized layer M1 is a conductive wire layer formed on the upper surface of the substrate 202. The first metallized layer M1 may include one or more conductive planes configured as one or more ground planes of the phased array antenna 200. According to some embodiments, the ground plane defines or includes one or more slits, slots, or openings used to electromagnetically couple RF signals to and from the antenna patch 206 via the substrate 202. The first metallized layer M1 may contain a metallic material such as copper, titanium, chromium, tungsten, silver, aluminum, or another suitable metal. The first metallized layer M1 may have a thickness of approximately 0.5 μm to approximately 6 μm.

[0031] According to some embodiments, the RDL204 further includes an adhesive layer D0 formed between the substrate 202 and the first metallized layer M1, for example, on the upper surface of the substrate 202. The adhesive layer D0 may also serve to bond the first metallization layer M1 or the first dielectric layer D1 of RDL204 to the substrate 202. The adhesive layer D0 may have a thickness of approximately 1 μm to approximately 1.5 μm. The adhesive layer D0 may contain a dielectric material, such as silicon nitride, silicon oxide, or another suitable material.

[0032] The first dielectric layer D1 is formed on top of the first metallization layer M1. The first dielectric layer D1 may contain dielectric materials such as silicon nitride, silicon oxide, polymer materials, photoimaging dielectric (PID) materials (such as photosensitive polyimide (PSPI), photosensitive epoxy, photosensitive acrylic, photosensitive polybenzoxazole (PSPBO), photosensitive benzocyclobutene (PSBCB), siloxane-based PID, polyurethane-based PID, cyanate ester-based PID, and combinations thereof), or other suitable dielectric materials. The first dielectric layer D1 may have a thickness H1 of approximately 0.5 μm to approximately 10 μm, measured from the lower plane to the upper plane of the first dielectric layer D1. According to some embodiments, the first dielectric layer D1 includes a multilayer structure such as a sandwich structure having two silicon nitride layers and a polymer layer between the silicon nitride layers.

[0033] The second metallization layer M2 is formed on the first dielectric layer D1 and the first metallization layer M1. The second metallized layer M2 may be a conductive wire layer containing a plurality of conductive wires extending in the horizontal direction. The second metallized layer M2 may further include a plurality of conductive vias M2V that extend vertically and are electrically coupled to the first metallized layer M1. According to some embodiments, the conductive wires of the second metallized layer M2 are configured as digital signal paths for transmitting digital signals for the phased array antenna 200, such as control or calibration signals. The second metallization layer M2 may contain a metallic material such as copper, titanium, chromium, tungsten, silver, aluminum, or another suitable metal. The second metallized layer M2 may have a thickness of approximately 0.5 μm to approximately 6 μm.

[0034] The second dielectric layer D2 is formed on top of the second metallization layer M2. The second dielectric layer D2 may contain a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, polymer material, PID material, a combination thereof, or another suitable dielectric material. The second dielectric layer D2 may contain the same material as the first dielectric layer D1. The second dielectric layer D2 may have a thickness H2 of approximately 0.5 μm to approximately 10 μm, or approximately 1 μm to approximately 5 μm, measured from the lower plane to the upper plane of the second dielectric layer D2. According to some embodiments, the second dielectric layer D2 includes a multilayer structure such as a sandwich structure having two silicon nitride layers and a polymer layer between the silicon nitride layers.

[0035] The third metallization layer M3 is formed on the second dielectric layer D2 and the second metallization layer M2. The third metallized layer M3 may be a conductive plane layer containing a plurality of conductive wires or conductive planes extending in the horizontal direction. The third metallized layer M3 may further include a plurality of conductive vias M3V that extend vertically and are electrically coupled to the second metallized layer M2. According to some embodiments, the conductive wires or conductive planes of the third metallized layer M3 are configured as ground paths or ground planes of the phased array antenna 200. The third metallization layer M3 may contain a metallic material such as copper, titanium, chromium, tungsten, silver, aluminum, or another suitable metal. The third metallized layer M3 may have a thickness of approximately 0.5 μm to approximately 6 μm.

[0036] The third dielectric layer D3 is formed on top of the third metallization layer M3. The third dielectric layer D3 may include a dielectric material such as a polymer material, a PID material (e.g., a dry film dielectric material), or another suitable dielectric material. As used herein, dry film dielectric material refers to PID material provided in the form of a solid film that is laminated onto a substrate or otherwise coated without the use of a liquid precursor. The third dielectric layer D3 may contain a material different from or similar to the material of the first dielectric layer D1 or the second dielectric layer D2. The third dielectric layer D3 may have a thickness H3 of approximately 15 μm to approximately 50 μm, measured from the lower plane to the upper plane of the third dielectric layer D3. Thickness H3 is the main thickness H of RDL204. M It may have at least 50% of the main thickness H M This is measured between the lower surface of the first dielectric layer D1 and the upper surface of the third dielectric layer D3. The thickness H3 may be at least twice the thickness H1 of the first dielectric layer D1, or at least twice the thickness H2 of the second dielectric layer D2.

[0037] The fourth metallization layer M4 is formed on the third metallization layer M3 and extends within and above the third dielectric layer D3. The fourth metallized layer M4 may be a conductive plane layer that extends horizontally and includes a plurality of conductive wires configured as power rails and signal lines for transmitting power and RF signals, respectively. The fourth metallization layer M4 may further include a plurality of conductive vias M4V that penetrate vertically through the third dielectric layer D3 and are electrically coupled to the third metallization layer M3. The fourth metallization layer M4 may contain a metallic material such as copper, titanium, tungsten, silver, or another suitable metal. The conductive wires within the fourth metallized layer M4 may have a thickness of approximately 4 μm to approximately 15 μm. The conductive via M4V may have a width greater than the width of the wire or via in the first metallized layer M1, the second metallized layer M2, or the third metallized layer M3. The conductive via M4V may have a width greater than approximately 40 μm, for example, a width of approximately 40 μm to approximately 70 μm. The conductive via M2V or M3V may have a width of approximately 20 μm to approximately 40 μm. The thickness or width of the conductive wires / vias within the fourth metallization layer M4 is greater than that within the first metallization layer M1, the second metallization layer M2, or the third metallization layer M3 in order to carry more RF signals with more power and less resistance. According to some embodiments, the total thickness H of RDL204 measured from the bottom surface of the first dielectric layer D1 to the top surface of the fourth dielectric layer D4 is... TThe size is approximately 20 μm to 80 μm.

[0038] The fourth dielectric layer D4 is formed on the fourth metallization layer M4 and the third dielectric layer D3. The fourth dielectric layer D4 may include a dielectric material such as a solder resist, a polymer material, a PID material, or another suitable dielectric material. The fourth dielectric layer D4 may contain a material different from or similar to the material of the first dielectric layer D1, the second dielectric layer D2, or the third dielectric layer D3. The fourth dielectric layer D4 may have a thickness of approximately 4 μm to approximately 30 μm.

[0039] Multiple connectors 210 are formed between the RF chip 208 (see Figure 1A) and the fourth metallized layer M4. The connector 210 is formed to electrically connect the RF chip 208 to the conductive wires in the fourth metallized layer M4. The connector 210 may include conductive bumps such as controlled collapse chip connection (C4) bumps, microbumps, ball grid array bumps, line grid array bumps, pin grid array bumps, or other suitable types of bumps. The connector 210 may include solder bumps or copper bumps.

[0040] Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, 2O, 2P, and 2Q are cross-sectional views of intermediate steps in a method for forming a phased array antenna 200 according to several embodiments. Regarding additional embodiments of the methods shown in Figures 2A to 2Q, please understand that additional steps may be provided before, between, and after the steps shown in Figures 2A to 2Q, and that some of the steps described below may be replaced or eliminated. The order of the steps can be changed.

[0041] As shown in Figure 2A, the substrate 202 is provided or received. According to some embodiments, the substrate 202 is a glass substrate and comprises glass, fused silica, silicon oxide, quartz, or another suitable material. The substrate 202 may be transparent in color and transparent to RF signals. As shown in Figure 2B, an adhesive layer D0 is deposited on the upper surface of the substrate 202. The adhesive layer D0 may contain silicon nitride, silicon oxide, or another suitable adhesive material, and may be formed by a deposition process such as CVD, PVD, spin coating, or another suitable deposition process. The adhesive layer D0 may have a thickness of approximately 1 μm to approximately 1.5 μm.

[0042] As shown in Figure 2C, the first metallized layer M1 is formed on the adhesive layer D0 and the substrate 202. The first metallized layer M1 may contain a metallic material such as copper, titanium, chromium, tungsten, silver, aluminum, or another suitable metal. The first metallized layer M1 may have a thickness of approximately 0.5 μm to approximately 6 μm. The first metallized layer M1 may be formed by deposition, photolithography, and etching processes. The deposition process may include PVD, CVD, or another suitable deposition process. The deposition process for the first metallization layer M1 may be similar to that used in existing LCD metal wire deposition processes. LCD metal wire deposition processes are more cost-effective than those used to form high-density interconnect structures for PCB applications.

[0043] As shown in Figure 2D, the first dielectric layer D1 is deposited on the first metallization layer M1 and the substrate 202. The first dielectric layer D1 may have a thickness H1 of approximately 0.5 μm to approximately 10 μm. The first dielectric layer D1 may be formed by PVD, CVD, or another suitable deposition process. According to some embodiments, a planarization process such as mechanical polishing or chemical mechanical polishing (CMP) is performed to planarize the upper surface of the first dielectric layer D1.

[0044] As shown in Figure 2E, the first dielectric layer D1 is patterned to form a recess R1. The recess R1 may expose a portion of the conductive plane or conductive wire within the first metallized layer M1. The recess R1 may be formed, for example, using a photolithography operation including exposure, post-exposure baking, development, and curing.

[0045] Figure 2F shows the formation of the second metallized layer M2 on the first dielectric layer D1 and within the recess R1. According to some embodiments, conductive planes or wires arranged in the second metallized layer M2, and conductive vias M2V arranged in the recess R1, are conformally formed on the upper surface of the first dielectric layer D1. The recess R1 is only partially filled by the conductive via M2V of the second metallized layer M2. The second metallized layer M2 may have a thickness of approximately 0.5 μm to approximately 6 μm. The conductive via M2V of the second metallized layer M2 may have a width of approximately 20 μm to approximately 40 μm. The second metallized layer M2 may be formed using deposition, photolithography, and etching processes. The deposition process may include PVD, CVD, or another suitable deposition process. The deposition process for the second metallization layer M2 may be similar to that used in existing LCD metal wire deposition processes.

[0046] As shown in Figure 2G, the second dielectric layer D2 is deposited on the first metallized layer M1 and the first dielectric layer D1. The second dielectric layer D2 may have a thickness H2 of approximately 0.5 μm to approximately 10 μm, or approximately 1 μm to approximately 5 μm. According to some embodiments, the second dielectric layer D2 includes a multilayer structure such as a sandwich structure, which is formed by depositing a first silicon nitride layer, a polymer layer, and a second silicon nitride layer in a stack. The second dielectric layer D2 may be formed using PVD, CVD, or another suitable deposition process. The material, thickness, and method for forming the second dielectric layer D2 may be the same as those for the first dielectric layer D1.

[0047] As shown in Figure 2H, the second dielectric layer D2 is patterned to form a recess R2. The recess R2 may expose a portion of the conductive plane or conductive wire within the second metallized layer M2. The recess R2 may be formed using photolithography.

[0048] Figure 2I shows the formation of the third metallized layer M3 on top of the second dielectric layer D2 and within the recess R2. According to some embodiments, conductive planes or wires arranged in the third metallized layer M3, and conductive vias M3V arranged in the recess R2, are formed conformally on the upper surface of the second dielectric layer D2. The recess R2 is only partially filled by the conductive via M3V of the third metallized layer M3. The third metallized layer M3 may have a thickness of approximately 0.5 μm to approximately 6 μm. The conductive via M3V of the third metallized layer M3 may have a width of approximately 20 μm to approximately 40 μm. The third metallization layer M3 may be formed using deposition, photolithography, and etching processes. The deposition process may include PVD, CVD, or another suitable deposition process. The deposition process for the third metallization layer M3 may be similar to that used in existing LCD metal wire deposition processes. The material, thickness, and method for forming the third metallized layer M3 may be the same as those for the second metallized layer M2.

[0049] As described above, the high flatness of the substrate 202 can contribute to the successful formation of the phased array antenna 200. Therefore, glass-based materials are used for the substrate 202 due to their high flatness and low cost compared to other material options. However, during the formation of the constituent layers of the RDL204, for example, the first dielectric layer D1 and the second dielectric layer D2, one or more thermal operations may be performed on the RDL204 and the substrate 202. The materials of the substrate 202, the dielectric material of the first dielectric layer D1, and the materials of the second dielectric layer D2 may have different coefficients of thermal expansion (CTE). As a result, the CTE mismatch between the substrate 202 and the first dielectric layer D1 and the second dielectric layer D2 can generate stress that causes warping of the substrate 202. For example, different stresses exerted on the front and back sides of the substrate 202 due to CTE mismatch can cause warping of the substrate 202. Such warping can be more severe in larger applications, such as with panel substrates having dimensions of approximately 220 cm x 250 cm or more.

[0050] To address the above problem, this disclosure proposes a method for controlling the thickness H1 of the first dielectric layer D1 and the thickness H2 of the second dielectric layer D2. When the thickness H1 or H2 is controlled within a predetermined range, the stress caused by CTE mismatch is reduced, and the effects of warping are reduced to an acceptable level that does not seriously affect subsequent processes of RDL204. According to some embodiments, the thickness H1 or H2 is limited to about 0.5 μm to about 10 μm. According to some embodiments, the sum of the thicknesses H1 and H2 is H S The particle size is maintained between approximately 2 μm and 20 μm. If the thickness H1 or H2 is less than approximately 0.5 μm, the electrical insulation performance provided by the first dielectric layer D1 or the second dielectric layer D2 will be reduced, adversely affecting the performance of the first metallization layer M1, the second metallization layer M2, and the third metallization layer M3. However, when the sum H of the thickness H1 and the thickness H2 is greater than about 20 μm, the warping effect causes reliability problems of the RDL204. S

[0051] According to some embodiments, the total thickness H measured between the lower surface of the first dielectric layer D1 and the upper surface of the fourth dielectric layer D4 T is from about 20 μm to about 80 μm. According to some embodiments, the main thickness H measured between the lower surface of the first dielectric layer D1 and the upper surface of the third dielectric layer D3 M is from about 15 μm to about 60 μm. According to some embodiments, the ratio of the sum H of the thicknesses to the main thickness H M is 50% or less, less than 40%, or less than 33.3%. S

[0052] Existing RDL structures such as RDL104 shown in FIG. 5 are formed of a plurality of metallization layers and a plurality of dielectric layers. The thicknesses of the dielectric layers are substantially equal, and the materials or layer structures of the dielectric layers are the same to achieve uniform insulation performance and reduce design complexity. However, the application of such a design in a conventional RDL structure or PCB structure using a laminated substrate or a semiconductor (e.g., silicon) substrate is not sufficient to solve the problems encountered in the RDL104 formed on the glass substrate 202 in other ways.

[0053] Furthermore, in order to effectively solve the above warping problem and expand the process window in the range of the thickness H1 or H2, it is further proposed to reduce the size of the substrate 202 before forming the third dielectric layer D3. As shown in FIG. 2J, a dicing or sawing operation is performed on the phased array antenna 200 to cut the substrate 202 into smaller substrate units. For ease of explanation, the substrate unit after the dicing operation is also numbered 202. According to some embodiments, the dicing or sawing operation is performed by a cutting tool 220 such as a laser blade, a diamond blade, or another suitable cutting tool. After the dicing or sawing operation, the substrate 202 is divided into four or any appropriate number of substrate units 202. According to some embodiments, each of the cut substrate units 202 may include a substrate region for housing one or more phased array antennas 200.

[0054] As shown in Figure 2K, the material for the third dielectric layer D3 is placed on top of the third metallization layer M3 and the second dielectric layer D2. The material of the third dielectric layer D3 may include a dielectric material such as a polymer material, a PID material (e.g., a dry film dielectric material), or another suitable dielectric material. The third dielectric layer D3 may contain a material different from the material of the first dielectric layer D1 or the second dielectric layer D2. The third dielectric layer D3 may have a thickness H3 of approximately 10 μm to approximately 50 μm. Thickness H3 is the main thickness H of RDL204. M It has at least 50% of it. The thickness H3 may be at least twice the thickness H1 of the first dielectric layer D1, or at least twice the thickness H2 of the second dielectric layer D2. The third dielectric layer D3 is placed on the surface of the phased array antenna 200 if the material is in the form of a dry film.

[0055] As shown in Figure 2L, a pressing operation is performed on the third dielectric layer D3. The pressing operation is performed by a pressing tool 230 that applies a downward force in a heated environment to bond the third dielectric layer D3 to the third metallized layer M3 and the second dielectric layer D2, thereby facilitating adhesion between the third dielectric layer D3 and the third metallized layer M3 or the second dielectric layer D2. According to some embodiments, the pressing operation includes a planarization operation that can help obtain a relatively flat surface of the third dielectric layer D3.

[0056] According to some embodiments, the film placement and film pressing operations are completed by the lamination process. The lamination process may include the material placement step and the pressing step shown in Figures 2K and 2L, respectively. According to some embodiments, the lamination process includes using heat and pressure to transfer a dry film dielectric material from a carrier sheet to a phased array antenna 200. The laminator 232 can be used to perform a lamination process using a dry film dielectric material for the third dielectric layer D3 to laminate the third dielectric layer D3 onto the second dielectric layer D2 and the third metallized layer M3. The lamination process may be performed by a vacuum laminator 232 to improve the bonding or lamination between the third dielectric layer D3 and the third metallized layer M3 or the second dielectric layer D2.

[0057] The laminated material of the third dielectric layer D3 has the advantage of being able to be much thicker than the first dielectric layer D1 and the second dielectric layer D2, which are formed using a deposition process for LCD applications. As a result, the main thickness H of RDL204 measured between the upper surface of the first metallization layer M1 and the upper surface of the third dielectric layer D3 was M This may correspond to the wavelength of the RF signal. However, because the third dielectric layer D3 needs to be formed by lamination, a significant downward pressure is applied to the phased array antenna 200, and the constituent layers of RDL204 and the substrate 202 must be kept sufficiently planar or flat to prevent the downward pressure from damaging the substrate 202, which is prone to warping, especially if the substrate 202 is manufactured from a glass-based material. Therefore, effective warpage control can help ensure the successful completion of the lamination of the third dielectric layer D3. As described above, the thickness H1 of the first dielectric layer D1 and the thickness H2 of the second dielectric layer D2 are maintained within a predetermined range, and the larger substrate 202 is cut into smaller substrate units 202. One or both of the above measures are used to reduce the degree or possibility of warping of the substrate 202, thereby reducing the degree of damage to the substrate unit 202 during the lamination of the third dielectric layer D3.

[0058] As shown in Figure 2M, a trench or recess R3 is formed that penetrates the third dielectric layer D3. Trench R3 exposes the portion of the third metallized layer M3. According to some embodiments, the trench R3 is etched using a laser drilling operation. A focused laser beam is used to melt or vaporize the material of the third dielectric layer D3 at a predetermined location in the trench R3. According to some embodiments, etching of trench R3 does not involve photolithography operations. Trench R3 may include substantially vertical sidewalls, in contrast to the conductive vias M2V and M3V of the V-shaped second and third metallization layers M2 and M3. According to some embodiments, the trench R3 has a substantially uniform width along the depth of the third dielectric layer D3. The width of trench R3 may be greater than approximately 40 μm, for example, between approximately 40 μm and approximately 70 μm.

[0059] As shown in Figure 2N, the fourth metallized layer M4 is formed by penetrating the third dielectric layer D3 and extending over the third dielectric layer D3. The fourth metallized layer M4 includes horizontal conductive wires extending over the third dielectric layer D3 and conductive vias M4V penetrating the third dielectric layer D3. The conductive wires within the fourth metallized layer M4 may have a thickness of approximately 4 μm to approximately 15 μm. The width of the conductive via M4V may be greater than approximately 40 μm, for example, between approximately 40 μm and approximately 70 μm. A photolithography process may be used to pattern conductive wires or conductive planes of the fourth metallization layer M4 on the third dielectric layer D3. The conductive material of the fourth metallization layer M4 is formed using a deposition process, such as electrochemical deposition (ECD) or another suitable deposition process.

[0060] As shown in Figure 2O, the fourth dielectric layer D4 is deposited and patterned on the third dielectric layer D3 and the fourth metallization layer M4. The fourth dielectric layer D4 may include a dielectric material, such as a solder resist, a polymer material, a PID material, or another suitable material. The fourth dielectric layer D4 may be different from the first dielectric layer D1 or the second dielectric layer D2. The fourth dielectric layer D4 may have a thickness of approximately 4 μm to approximately 30 μm. The fourth dielectric layer D4 may be formed using a deposition process. The deposition process may include CVD, PVD, screen printing, spraying, or another suitable deposition process. The patterning operation of the fourth dielectric layer D4 may include a photolithography operation or a screen printing process. The patterned fourth dielectric layer D4 includes a recess R4. A portion of the fourth metallized layer M4 is exposed through the recess R4.

[0061] As shown in Figure 2P, multiple antenna patches 206 are formed on the underside of the substrate 202. The antenna patch 206 may contain a metal paste formed using a screen printing operation that utilizes a silk screen.

[0062] As shown in Figure 2Q, multiple connectors 210 are formed within the recess R4. The connector 210 may include conductive bumps such as controlled collapse chip connection (C4) bumps, microbumps, ball grid array bumps, line grid array bumps, pin grid array bumps, or other suitable types of bumps. Connector 2101 may include solder bumps or copper bumps.

[0063] Although not shown separately, multiple RF chips 208 are bonded to the fourth metallized layer M4 via connectors 210. The RF chip 208 may be bonded to the fourth metallized layer M4 before or after the formation of the antenna patch 206.

[0064] Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, and 3I are cross-sectional views of intermediate steps in a method for forming a phased array antenna 300 according to several embodiments. Regarding additional embodiments of the methods shown in Figures 3A to 3I, please understand that additional steps may be provided before, between, and after the steps shown in Figures 3A to 3I, and that some of the steps described below may be replaced or eliminated. The order of the steps can be changed. Since the method for forming the phased array antenna 300 is similar in many embodiments to the method for forming the phased array antenna 200, a description of similar features will be omitted for simplicity.

[0065] As shown in Figure 3A, the substrate 202 is received or provided. The adhesive layer D0 is deposited on the upper surface of the substrate 202, and the first metallized layer M1 is formed and patterned on top of the adhesive layer D0. The materials, configuration, and method for forming the substrate 202, adhesive layer D0, and first metallization layer M1 are the same as those described with reference to Figures 2A to 2C for forming the phased array antenna 200. According to some embodiments, the first metallized layer M1 comprises titanium and copper and is formed using PVD, for example, sputtering. According to some other embodiments, the first metallized layer M1 contains copper and is formed using an ECD process. According to some embodiments, the conductive plane or conductive wire of the first metallized layer M1 has a thickness of about 0.5 μm to about 6 μm.

[0066] As shown in Figure 3B, the first dielectric layer D1 is deposited and patterned on the first metallization layer M1 and the adhesive layer D0. According to some embodiments, the first dielectric layer D1 includes a PID layer such as a dry film dielectric material or another suitable insulating material. The first dielectric layer D1 may be formed by a lamination process. According to some embodiments, the first dielectric layer D1 is patterned using photolithography to form a recess R1. According to some embodiments, the first dielectric layer D1 has a thickness H1 of about 0.5 μm to about 10 μm.

[0067] As shown in Figure 3C, the second metallized layer M2 is formed on the first dielectric layer D1 and within the recess R1 of the first dielectric layer D1. According to some embodiments, the second metallized layer M2 comprises titanium and copper and is formed using PVD, for example, sputtering. According to some other embodiments, the second metallized layer M2 contains copper and is formed using an ECD process. According to some embodiments, the conductive plane or conductive wire of the second metallized layer M2 or conductive via M2V has a thickness of about 0.5 μm to about 6 μm. The conductive via M2V may have a width of approximately 20 μm to approximately 40 μm.

[0068] As shown in Figure 3D, the second dielectric layer D2 is deposited and patterned to form a recess R2 on the second metallized layer M2 and the first dielectric layer D1. According to some embodiments, the second dielectric layer D2 includes a PID layer such as a dry film dielectric material or another suitable insulating material. The second dielectric layer D2 may be formed by a lamination process. According to some embodiments, the second dielectric layer D2 is patterned using photolithography to form a recess R2. According to some embodiments, the second dielectric layer D2 has a thickness H2 of about 0.5 μm to about 10 μm.

[0069] As shown in Figure 3E, the third metallized layer M3 is formed on the second dielectric layer D2 and within the recess R2 of the second dielectric layer D2. According to some embodiments, the third metallized layer M3 comprises titanium and copper and is formed using PVD, for example, sputtering. According to some other embodiments, the third metallized layer M3 contains copper and is formed using an ECD process. According to some embodiments, the conductive plane or conductive wire of the third metallized layer M3 has a thickness of about 0.5 μm to about 6 μm.

[0070] As shown in Figure 3F, the third dielectric layer D3 is deposited on top of the third metallization layer M3. According to some embodiments, the third dielectric layer D3 includes a PID layer such as a dry film dielectric material or another suitable insulating material similar to the first dielectric layer D1 or the second dielectric layer D2. The third dielectric layer D3 may be formed by a lamination process. According to some embodiments, the third dielectric layer D3 has a thickness of about 15 μm to about 50 μm.

[0071] According to some embodiments, the thickness H1 of the first dielectric layer D1 or the thickness H2 of the second dielectric layer D2 is limited to about 0.5 μm to about 10 μm. According to some embodiments, the sum of the thicknesses H1 and H2 is H S This is limited to approximately 2 μm to 20 μm. If the thickness H1 or H2 is less than approximately 0.5 μm, the electrical insulation performance provided by the first dielectric layer D1 or the second dielectric layer D2 will be reduced, adversely affecting the performance of the first metallization layer M1, the second metallization layer M2, and the third metallization layer M3. However, the sum of the thicknesses H1 and H2 is H S If the warpage is greater than approximately 20 μm, the warpage effect causes reliability issues with the RDL204.

[0072] According to some embodiments, the main thickness H measured between the lower surface of the first dielectric layer D1 and the upper surface of the third dielectric layer D3 is M The size ranges from approximately 15 μm to approximately 60 μm. According to some embodiments, the main thickness H M The sum of thicknesses H S The ratio is approximately 50% or less, less than 40%, or less than 33.3%.

[0073] Although not shown separately, the phased array antenna 300 undergoes a dicing or sawing operation in a manner similar to that described with reference to Figures 2K and 2L, before the third dielectric layer D3 is deposited and pressed against or alternatively stacked with the third metallization layer M3 and the second dielectric layer D2.

[0074] As shown in Figure 3G, the third dielectric layer D3 is patterned to form trenches R3 that penetrate the third dielectric layer D3. According to some embodiments, the trench R3 is formed by a laser drilling operation. Subsequently, as shown in Figure 3H, the fourth metallization layer M4 is formed on the third dielectric layer D3 and within the trench R3. The fourth metallization layer M4 may be formed using deposition, photolithography, and etching operations. According to some embodiments, the fourth metallized layer M4 comprises titanium and copper and is formed using PVD, for example, sputtering. According to some other embodiments, the fourth metallized layer M4 contains copper and is formed using an ECD process. According to some embodiments, the conductive plane or conductive wire of the fourth metallized layer M4 has a thickness of about 4 μm to about 15 μm. According to some embodiments, the conductive via M4V of the fourth metallized layer M4 has a width greater than about 40 μm, for example, a width of about 40 μm to about 70 μm.

[0075] As shown in Figure 3I, the fourth dielectric layer D4, the antenna patch 206, and the connector 210 are deposited and patterned onto the phased array antenna 300. The materials, configuration, and method for forming the fourth dielectric layer D4, the antenna patch 206, and the connector 210 are the same as those described with reference to Figures 2O to 2R for forming the phased array antenna 200.

[0076] Figure 4A is a cross-sectional view of a phased array antenna 400 according to some embodiment of the present disclosure. Since the phased array antenna 400 is similar to the phased array antenna 300 in many aspects, a description of similar features will be omitted for simplicity. The main difference between the phased array antenna 400 and the phased array antenna 300 is that the third dielectric layer D3 of the phased array antenna 400 is patterned to form a trench R3 (not shown separately) using photolithography in a similar manner to that used to form recesses R1 or R2. The trench R3 etched using photolithography may include sidewalls with a gentler slope. In other words, a trench R3 etched using a laser drilling operation (see, for example, Figure 2M) may include more vertical sidewalls than one formed using a photolithography operation.

[0077] Furthermore, the fourth metallized layer M4 formed on the phased array antenna 400 may have a conformal shape with the patterned third dielectric layer D3. The fourth metallization layer M4 may be formed using deposition, photolithography, and etching operations. According to some embodiments, the fourth metallized layer M4 comprises titanium and copper and is formed using PVD, for example, sputtering. According to some other embodiments, the fourth metallized layer M4 contains copper and is formed using an ECD process. According to some embodiments, the conductive plane or conductive wire of the fourth metallized layer M4 has a thickness of about 4 μm to about 15 μm. According to some embodiments, the conductive via M4V of the fourth metallized layer M4 has a width greater than about 40 μm, for example, a width of about 40 μm to about 70 μm.

[0078] Figure 4B is a top view of conductive vias M2V, M3V, and M4V in different metallized layers of RDL204 of a phased array antenna 400 according to some embodiments of the present disclosure. Conductive vias M2V, M3V, and M4V do not overlap from a top view perspective and satisfy the design rule check requirements. According to some embodiments, the conductive vias M2V, M3V, and M4V are arranged directly adjacent to each other without overlapping from a top view perspective, thereby reducing the footprint of the RDL204. According to some embodiments, the conductive vias M2V, M3V, and M4V are in contact with each other from a top view perspective.

[0079] Figure 6 is a schematic flowchart of a method 600 for forming a phased array antenna according to several embodiments. Regarding additional embodiments of the method shown in Figure 6, it should be understood that additional steps may be provided before, during, and after the steps shown in Figure 6, and that some of the steps described below may be replaced or eliminated. The order of the steps can be changed.

[0080] In step 602, a substrate made of glass is received.

[0081] In step 604, a redistribution layer (RDL) is formed on the substrate. Details of RDL formation are provided in steps 6042, 6044, 6046, and 6048.

[0082] In step 6042, a first metallized layer is deposited on the first surface of the substrate.

[0083] In step 6044, a first patterned dielectric layer having a first thickness is formed on the first metallized layer.

[0084] In step 6046, a second metallized layer is formed on the first patterned dielectric layer.

[0085] In step 6048, a second patterned dielectric layer having a second thickness at least twice the first thickness is formed on the second metallized layer.

[0086] In step 606, an antenna patch is formed on the second surface of the substrate opposite to the first surface.

[0087] The foregoing outlines some features of embodiments so that those skilled in the art may better understand the aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages of the embodiments described herein. Furthermore, those skilled in the art should understand that such equivalent structures can be modified, substituted, and altered in this Specification without departing from the spirit and scope of this Disclosure.

Claims

1. The steps include receiving a substrate made of glass, The step of forming a redistribution layer (RDL) on the substrate is included, and the step of forming the RDL is The steps include depositing a first metallized layer on the first surface of the substrate, The steps include depositing a first patterned dielectric layer having a first thickness on the first metallized layer, The steps include depositing a second metallized layer on the first patterned dielectric layer, The steps include forming a second patterned dielectric layer on the second metallized layer, The second patterned dielectric layer comprises a photoimageable dielectric (PID) material, A method for forming an antenna device having a second thickness at least twice the first thickness.

2. The method according to claim 1, wherein the step of depositing the first metallized layer is carried out by physical vapor deposition (PVD).

3. The method according to claim 1, further comprising the step of depositing a third metallized layer on the second patterned dielectric layer by electrochemical deposition (ECD).

4. The method according to claim 3, wherein the step of depositing the third metallized layer includes the step of depositing conductive vias penetrating the second patterned dielectric layer.

5. The method according to claim 1, further comprising the step of depositing an adhesive layer on the first surface prior to the step of depositing the first metallized layer, wherein the adhesive layer comprises a material comprising silicon nitride, silicon oxide, or polyimide.

6. The method according to claim 1, further comprising the step of depositing a third patterned dielectric layer on the first surface prior to the step of depositing the second patterned dielectric layer, wherein the sum of the thickness of the first layer and the thickness of the third patterned dielectric layer is less than the thickness of the second layer.

7. The method according to claim 6, wherein the sum of the first thickness and the thickness of the third patterned dielectric layer is about 2 μm to about 20 μm.

8. The method according to claim 1, further comprising the step of depositing an antenna patch on a second surface of the substrate opposite to the first surface.

9. The method according to claim 8, wherein the first metallized layer is configured to define a slit configured to electromagnetically couple a radio frequency signal to the antenna patch via the substrate.

10. The step of forming the aforementioned second patterned dielectric layer is: The steps include placing the PID material on the second metallized layer, The method according to claim 1, comprising the step of pressing the PID material to produce a substantially flat surface of the second patterned dielectric layer.

11. The method according to claim 1, wherein the step of forming the second patterned dielectric layer is performed using a vacuum laminator.

12. The method according to claim 1, further comprising the step of cutting the substrate into a plurality of substrate units before the step of forming the second patterned dielectric layer.

13. An antenna device, A substrate made of glass, The substrate includes a redistribution layer (RDL) disposed on the first surface of the substrate, wherein the RDL is A first metallized layer located on the first surface of the substrate, A first dielectric layer having a first thickness is located on the first metallized layer, A second metallized layer is located on the first dielectric layer and is electrically coupled to the first metallized layer, The second metallized layer and the second dielectric layer located on the first dielectric layer are included, The antenna device wherein the second dielectric layer comprises a photoimageable dielectric (PID) material and has a thickness at least twice that of the first thickness.

14. The antenna device according to claim 13, wherein the first dielectric layer comprises silicon nitride, silicon oxide, polymer, PID, or photosensitive polyimide.

15. The antenna device according to claim 13, wherein the first thickness is approximately 0.5 μm to approximately 10 μm.

16. The antenna device according to claim 13, wherein the thickness of the RDL, measured from the lower surface of the bottom dielectric layer to the upper plane of the second dielectric layer, is approximately 15 μm to approximately 60 μm.

17. The antenna device according to claim 13, wherein the first metallized layer includes a conductive plane configured as the ground plane of the antenna device.

18. The radio frequency (RF) chip located on the RDL, The antenna device according to claim 13, further comprising: an antenna patch on a second surface of the substrate opposite to the first surface.

19. The antenna device according to claim 18, wherein the substrate does not include a conductive element within the projection area of ​​the antenna patch.

20. The antenna device according to claim 18, wherein the RDL further includes a third metallized layer disposed between the RF chip and the second dielectric layer, and the third metallized layer is configured to transmit power and RF signals between the RDL and the RF chip.

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