Multilayer wiring board and method for manufacturing a multilayer wiring board

Abstract

To provide a technique for configuring a capacitor in a circuit board with high precision using a single element and forming a capacitor structure with an excellent withstand voltage.SOLUTION: In a multilayer wiring board according to the present invention in which capacitors are built, at least one of the capacitors is configured by providing a lower electrode, a dielectric layer, and an upper electrode in order from the one closest to the core substrate, the lower electrode is arranged on the core substrate, the upper electrode includes a portion that constitutes a capacitor by overlapping with the dielectric layer and the lower electrode in the normal direction of the surface of the core substrate, and a portion extending from a portion constituting the capacitor to a portion within the plane of the core substrate that does not overlap with the lower electrode, and the lower electrode includes an inclined portion having an inclination dz / dx of 0.02 um / um or more and 0.5 um / um or less in a cross-sectional view.SELECTED DRAWING: Figure 4F

Description

Technical Field

[0001] The present invention relates to a multilayer wiring board and a method for manufacturing the same.

Background Art

[0002] In recent years, in mobile communication, the fifth-generation communication standard that expands the communication band from the conventional 750 MHz to 2.5 GHz to 3.5 GHz to 6 GHz (Sub6 GHz band) has been widely promoted. In the fifth-generation communication standard, as a synchronization technology, a wideband TDD method with a bandwidth of 500 MHz to 900 MHz is adopted. To meet such frequency requirements, an LC filter that utilizes electrical resonance using an inductor and a capacitor is used. Since the frequency filter needs to be provided for each frequency band and the mounting area is also large, it has become a factor hindering the miniaturization and thinning of communication modules.

[0003] So far, technologies have been proposed to reduce the components occupying the substrate surface and miniaturize and thin the wiring board by incorporating passive components such as inductors and capacitors into the wiring board. Patent Document 1 discloses a technique for realizing a diplexer that performs frequency division at 1.4 GHz by forming a capacitor on the surface of a glass substrate and forming a part of an inductor in the glass substrate to constitute an LC filter. Patent Document 2 discloses a technique for realizing a capacitor structure formed on a glass substrate.

[0004] As shown in Patent Documents 1 and 2, forming a capacitor using a plurality of elements has room for improvement in terms of characteristic degradation due to wiring resistance and parasitic capacitance at the connection portions between elements, variation in the capacitance value of the capacitor due to the superimposition of processing variations, and an increase in the mounting area. Patent Document 3 proposes a method for providing a multilayer wiring board and a module having the multilayer wiring board, which are excellent in performance, mountability, and productivity, by configuring a capacitor with a smaller capacitance value than conventional ones with high accuracy in a circuit board with a single element.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Patent No. 5982585 [Patent Document 2] Special Publication No. 2018-534763 [Patent Document 3] Japanese Patent Publication No. 2021-190661 [Overview of the project] [Problems that the invention aims to solve]

[0006] While the technology disclosed in Patent Document 3 allows for the precise construction of a capacitor with a smaller capacitance value than conventional capacitors as a single element within a circuit board, the voltage withstand capability becomes a problem. Because wiring is routed through stepped areas separated by a dielectric, film non-uniformity is likely to occur, leading to a decrease in voltage withstand capability. This aspect has not been sufficiently considered.

[0007] Therefore, the present invention aims to provide a technology for forming a capacitor structure with excellent voltage resistance by configuring a single capacitor element within a circuit board with high precision. [Means for solving the problem]

[0008] To solve the above problems, one representative multilayer wiring board of the present invention is a multilayer wiring board incorporating a capacitor, wherein at least one of the capacitors is configured by providing a lower electrode, a dielectric layer, and an upper electrode in order from the side closest to the core substrate, the lower electrode is placed on the core substrate, and the upper electrode has a portion that forms a capacitor by overlapping with the dielectric layer and the lower electrode in the direction normal to the surface of the core substrate, and a portion that extends from the portion forming the capacitor to a portion in the surface of the core substrate that does not overlap with the lower electrode, and the lower electrode has a sloping portion in cross-sectional view in which the inclination dz / dx is 0.02 μm / μm or more and 0.5 μm / μm or less. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a technology for forming a capacitor with high precision as a single element within a circuit board, and for forming a capacitor structure with excellent voltage resistance. Issues, structures, and effects other than those mentioned above will be clarified by the following explanation of the implementation methods. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 shows a conventional capacitor structure. [Figure 2] Figure 2 shows another structure of the capacitor in a conventional example. [Figure 3] Figure 3 is a schematic diagram illustrating the process of forming a capacitor structure. [Figure 4A] Figure 4A shows the process of forming the lower electrode in the first embodiment. [Figure 4B] Figure 4B shows the process of forming a resist in the first embodiment. [Figure 4C] Figure 4C shows the process of forming the lower electrode in the first embodiment. [Figure 4D] Figure 4D shows the process of removing the resist in the first embodiment. [Figure 4E] Figure 4E shows the process of forming a dielectric layer in the first embodiment. [Figure 4F] Figure 4F shows the process of forming the adhesion layer and the upper electrode in the first embodiment. [Figure 5] Figure 5 illustrates the process of forming the lower electrode of the first embodiment. [Figure 6] Figure 6 illustrates the differences caused by the presence or absence of an adhesion layer. [Figure 7] Figure 7 shows other shapes of the lower electrode. [Figure 8A] Figure 8A shows the process of bonding the first support to the glass substrate. [Figure 8B]FIG. 8B is a diagram showing a process of forming a laser modification portion. [Figure 8C] FIG. 8C is a diagram showing a process of forming an adhesion layer and a conductive layer. [Figure 8D] FIG. 8D is a diagram showing a process of forming a resist. [Figure 8E] FIG. 8E is a diagram showing a process of forming a lower electrode. [Figure 8F] FIG. 8F is a diagram showing a process of forming a dielectric layer. [Figure 8G] FIG. 8G is a diagram showing a process of forming a second wiring layer. [Figure 8H] FIG. 8H is a diagram showing a process of forming a third wiring layer. [Figure 8I] FIG. 8I shows a process of forming an insulating resin layer. [Figure 8J] FIG. 8J is a diagram showing a process of adhering a second support. [Figure 8K] FIG. 8K is a diagram showing a process of peeling a first support. [Figure 8L] FIG. 8L is a diagram showing a process of forming a through hole in a glass substrate. [Figure 8M] FIG. 8M is a diagram showing a process of forming a fourth wiring layer and a process of forming an insulating resin layer. [Figure 8N] FIG. 8N is a diagram showing a process of peeling a second support. [Figure 8O] FIG. 8O is a diagram showing a process of forming a build-up layer.

MODE FOR CARRYING OUT THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited by this embodiment. Also, in the description of the drawings, the same parts are denoted by the same reference numerals.

[0012] The positions, sizes, shapes, and ranges of the components shown in the drawings may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.

[0013] In this disclosure, "surface" may refer not only to the surface of the plate-like member, but also to the interface of a layer contained within the plate-like member that is substantially parallel to the surface of the plate-like member. Furthermore, "upper surface" and "lower surface" refer to the surfaces shown above or below the plate-like member or the layers contained within the plate-like member in the drawing. In addition, "upper surface" and "lower surface" may also be referred to as "first surface" and "second surface."

[0014] Furthermore, "side surface" refers to the surface or thickness of a layer within a plate-like member or a layer contained within a plate-like member. In addition, a part of the surface and the side surface together are sometimes referred to as the "end." Furthermore, "upward" refers to the vertically upward direction when a plate-like member or layer is placed horizontally. In addition, "upward" and its opposite, "downward," may be referred to as the "positive Z-axis direction" and the "negative Z-axis direction," respectively, while the horizontal direction may be referred to as the "X-axis direction" and the "Y-axis direction."

[0015] Furthermore, "through-electrodes provided on a glass substrate" refers to conductive paths provided to electrically connect the first and second surfaces of a glass substrate when the glass substrate is used as part of a multilayer wiring board, and it is not necessarily required that the glass substrate be completely penetrated by a single conductive material. If the conductive path from the first surface and the conductive path from the second surface are connected, it is included as a through-electrode. Moreover, the form of the through-electrode may be a filled type in which a through-hole (including both bottomed and completely through-holes) is filled with conductive material, or a conformal type in which only the side walls of the through-hole are covered with conductive material.

[0016] Furthermore, "planar shape" and "planar view" refer to the shape of a surface or layer as viewed from above. In addition, "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer as viewed from the horizontal when it is cut in a specific direction.

[0017] [Conventional example] First, we will explain the conventional example with reference to Figures 1 to 3.

[0018] Figure 1 shows a capacitor structure in a conventional example. Figure 1 shows the case where the first wiring L1a and the second wiring L2a are arranged to intersect. Figure 1(a) is a schematic plan view, and Figure 1(b) is a schematic cross-sectional view along line Ca in Figure 1(a). Here, the first wiring L1a, dielectric layer DLa, and second wiring L2a are formed in order on a glass substrate Ga. An adhesive layer ALa is formed between the first wiring L1a and the glass substrate Ga. In the plan view of Figure 1(a), the first electrode L1ap of the first wiring L1a and the second electrode L2ap of the second wiring L2a are visible on the outermost surface.

[0019] In the capacitor structure shown in Figure 1, voltage withstand capability is a problem. The region Ra enclosed by the dotted line in Figure 1(b) is a point where there is a risk of voltage withstand capability, i.e., leakage current may occur. In region Ra, the second wiring L2a is routed through a stepped area with the dielectric layer DLa in between, forming a structure in which the dielectric is sandwiched between the first wiring L2a, the dielectric layer DLa, and the second wiring L2a. In such a structure, the dielectric layer DLa tends to become an uneven film. As a result, the voltage withstand capability decreases.

[0020] Figure 2 shows another structure of the capacitor structure in a conventional example. Figure 2 shows a case where the direction in which the first wiring L1 extends and the direction in which the second wiring L2 extends are the same, and the ends of the wirings are offset. Figure 2(a) is a schematic plan view, and Figure 2(b) is a schematic cross-sectional view along line C2 in Figure 2(a). Here, the first wiring L1b, dielectric layer DLb, and second wiring L2b are formed in order on top of each other on the glass substrate Gb. An adhesive layer ALb is formed between the first wiring L1b and the glass substrate Gb.

[0021] In the capacitor structure shown in Figure 2, the withstand voltage is a problem, just as in the case of Figure 1. The region Rb enclosed by the dotted line in Figure 2(b) is a point where there is a risk of withstand voltage, i.e., leakage current may occur. In region Rb, the second wiring L2b is routed through the stepped portion with the dielectric layer DLb in between, forming a structure in which the dielectric is sandwiched between the first wiring L2a, the dielectric layer DLa, and the second wiring L2a. In such a structure, the dielectric layer DLa tends to become an uneven film. As a result, the withstand voltage decreases.

[0022] Refer to Figure 3 to consider the cause of the voltage withstand problem. Figure 3 is a schematic diagram showing the process of forming a capacitor structure.

[0023] Figure 3(a) shows the structure before the dielectric layer is formed in the conventional capacitor structure formation process. Here, an adhesive layer ALc and a first wiring L1c are formed on the glass substrate Gc.

[0024] Figure 3(b) schematically shows the process of forming a dielectric layer in a conventional capacitor structure formation process. Here, when forming the dielectric layer, generally, for example, by plasma CVD, SiN, SiO2, TaO x Methods for forming such materials are employed. Plasma CVD is a process with high linearity. Therefore, when a dielectric film is deposited, it is easier to deposit the film in the direction indicated by the arrow, but it is difficult to deposit the film on the side wall of the first wiring L1c.

[0025] Figure 3(c) schematically shows the structure after the dielectric layer formation process in a conventional capacitor structure formation process. The films formed on the upper surface of the first wiring layer L1c and the upper surface of the glass substrate Gc are formed with uniform and stable thickness. In contrast, the films formed on the sides of the first wiring layer L1c tend to be thin, and the variation in thickness is large, making it difficult to form stable films.

[0026] Figure 3(d) shows a structure in which the second wiring L2c is formed during a conventional capacitor structure formation process. In the region Rc where the capacitor structure is formed on the side of the first electrode L1c, it is difficult to obtain a sufficient thickness of the dielectric layer DLc, and defects may also be more likely to occur. As a result of the formation of such a structure, the withstand voltage of the capacitor structure decreases, leading to the generation of leakage current and, in some cases, a short circuit.

[0027] [First Embodiment] A method for forming a capacitor structure according to the first embodiment will be described with reference to Figures 4A to 4F. The capacitor structure is composed of a lower electrode, a dielectric layer, and an upper electrode arranged in order from the core substrate. The lower electrode is placed on the core substrate, and the upper electrode has a portion that forms a capacitor by overlapping with the dielectric layer and the lower electrode in the direction normal to the surface of the core substrate, and a portion that extends from the portion forming the capacitor to a portion in the plane that does not overlap with the lower electrode. In the first embodiment, a glass substrate is used as the core substrate.

[0028] Figure 4A shows the process of forming the lower electrode in the first embodiment. Here, a conductive layer 3 is formed on the glass substrate 1. The adhesion layer 2 is formed to improve the adhesion between the glass substrate 1 and the conductive layer 3.

[0029] Figure 4B shows the process of forming a resist in the first embodiment. The resist 4 is patterned to form the desired shape of the lower electrode. The resist patterning is performed, for example, by photolithography.

[0030] Figure 4C shows the process of forming the lower electrode in the first embodiment. For example, the conductive layer 3 and the adhesion layer 2 are etched by wet etching. The lower electrode 5 is the portion of the conductive layer 3 that remains after etching. As shown here, the corners of the upper edge of the lower electrode 5 are rounded and inclined. This is because isotropic wet etching was performed instead of linear plasma etching. This requires conditions such as the degree of adhesion between the conductive layer 3 and the resist 4 and the etching rate. These will be discussed later.

[0031] Figure 4D shows the process of stripping the resist in the first embodiment. The stripping solution is selected according to the type of resist. As a result, the lower electrode 5 has a shape with a sloped portion Sl on its upper surface in cross-sectional view. It is desirable that the slope angle dz / dx of the sloped portion Sl be in the range of 0.02 μm / μm to 0.5 μm / μm.

[0032] Furthermore, the upper limit of the inclination angle dz / dx of the inclined portion Sl should be 0.5 μm / μm or less, and more preferably 0.3 μm / μm or less. This is because, in the manufacturing process of this configuration, the dry film resist used for patterning cannot adequately follow the shape changes caused by etching of the conductive layer 3, resulting in gaps or areas of insufficient adhesion between the dry film resist and the conductive layer 3. Etching solution can penetrate through these areas, causing the conductive layer 3 to be etched more than necessary. Regarding the resist's ability to follow, although it depends on the type of resist, in inclined portions with angles greater than a certain degree, gaps may occur or areas of unstable adhesion may occur, causing variations in the shape of the lower electrode 5. In addition, in regions with large inclination angles, variations in the dielectric film thickness of the inclined portion become large when variations in angle occur, causing variations in capacitance from one individual to another.

[0033] Furthermore, if the lower limit of the tilt angle dz / dx is less than 0.02 μm / μm, variations in the formation of the lower electrode 5 occur, leading to large variations in capacitance. When etching and patterning the lower electrode 5, the edges of the conductive layer 3 are etched in a thin film, and depending on the crystal state of Cu, areas where Cu remains in an island-like manner may occur. If the tilt angle is too large, these areas become larger, and controlling these areas is difficult, thus causing variations in capacitance.

[0034] Figure 4E shows the process of forming the dielectric layer in the first embodiment. The dielectric layer 6 is formed, for example, by sputtering. Because a sloped portion is formed on the upper surface of the lower electrode 5, the dielectric layer 6 is formed to have a sufficient thickness on the lower electrode 5. Furthermore, since a dielectric layer 6 with a stable thickness is obtained from the upper surface to the side wall of the lower electrode 5, the dielectric strength of the capacitor structure is improved.

[0035] Figure 4F shows the process of forming the adhesion layer and the upper electrode in the first embodiment. The adhesion layer 7 and the second electrode 8 are formed on the glass substrate 1 using a sputtering method or the like, and then patterned to a predetermined shape by photolithography.

[0036] (Resist adhesion) Here, with reference to Figure 5, the adhesion between the conductive layer 3 and the resist 4 will be explained. Figure 5 is a diagram illustrating the process of forming the lower electrode in the first embodiment. Figure 5(a) shows the state before wet etching is performed. The resist 4 has been patterned by photolithography to form the lower electrode, and an opening has been formed therein.

[0037] Figure 5(b) shows the case where the adhesion between the conductive layer 3 and the resist 4 is greater than a predetermined value. When the etching solution reaches the opening, etching proceeds isotropically. Etching proceeds quickly in the part of the conductive layer 3 that is the thickness (Z axis direction), while etching proceeds slowly in the parts of the interface on the adhesion layer 2 side and the interface on the resist 4 side.

[0038] Figure 5(c) shows the case where the adhesion between the conductive layer 3 and the resist 4 is below a predetermined value. In this case, the etching solution penetrates the interface between the conductive layer 3 and the resist 4, and etching proceeds first. In this way, a lower electrode 5 with a curved shape can be formed on the upper surface.

[0039] (The effect of the adhesive layer) Furthermore, with reference to Figure 6, the function of the adhesion layer 2 between the glass substrate 1 and the conductive layer 3 will be explained. Figure 6 is a diagram illustrating the difference caused by the presence or absence of the adhesion layer.

[0040] Figure 6(a1) shows the structure after the wet etching process when there is no adhesion layer. Figure 6(a2) shows the structure in which the dielectric layer and upper electrode are formed when there is no adhesion layer. In Figure 6(a2), the adhesion layer between the dielectric layer and the upper electrode is omitted from the display. When there is no adhesion layer, the etching solution penetrates between the glass substrate 1 and the conductive layer 3 during the wet etching process, and the interface of the conductive layer 3 on the glass substrate 1 side is etched first, as shown in region Rp, resulting in a so-called undercut. Since the dielectric layer 6 is also formed in region Rp, when an undercut occurs, the deposition of the dielectric layer 6 becomes unstable, which causes a decrease in the breakdown voltage of the capacitor.

[0041] Figure 6(b1) shows the structure after the wet etching process when an adhesion layer is present. Figure 6(b2) shows the structure in which the dielectric layer and upper electrode are formed when an adhesion layer is present. In Figure 6(b2), the adhesion layer between the dielectric layer and the upper electrode is omitted from the diagram. Because of the adhesion layer, the etching solution does not penetrate between the glass substrate 1 and the conductive layer 3 during the wet etching process. The lower electrode 5 can be formed through the wet etching process while maintaining adhesion between the conductive layer 3 and the glass substrate 1. Since no undercuts occur, the dielectric layer 6 can be formed stably.

[0042] When forming the adhesion layer on a glass substrate 1, the glass is pre-treated by cleaning it with a cleaning solution containing potassium hydroxide. Then, a conductive layer such as a Ti, Cr, or palladium film is formed as the adhesion layer, and a Cu film is deposited on top of it to form a lower electrode with excellent adhesion and high conductivity.

[0043] (Other examples of lower electrodes) Although a lower electrode 5 with a curved shape on its upper surface is shown, the shape of the lower electrode is not limited to this. Figure 7 shows other shapes of the lower electrode. Figure 7(a) is an inverse taper shape, Figure 7(b) is an undercut shape, Figure 7(c) is a rounded shape, and Figure 7(d) is a constricted shape. Any of these shapes can be realized by changing the etching conditions. Furthermore, when forming a dielectric layer, the instability of film formation can be eliminated.

[0044] [Examples] A method for manufacturing a multilayer wiring board having a capacitor structure according to the first embodiment will be described with reference to Figures 8A to 8O. Figures 8A to 8O schematically show the cross-sectional shape of the multilayer wiring board. The multilayer wiring board incorporates capacitors, and at least one of them has a capacitor structure according to the first embodiment.

[0045] Figure 8A shows the process of bonding the first support 12 to the glass substrate 10. The first support 12 is bonded to the glass substrate 10 using the first adhesive layer 11 to form a laminated structure consisting of the glass substrate 10, the first adhesive layer 11, and the first support 12.

[0046] The first adhesive layer 11 is an adhesive layer for temporarily fixing the first support to the glass substrate 10. To bond the first support 12 to the glass substrate 10, for example, a laminator, a vacuum pressure press, or a reduced pressure bonding machine can be used. As the glass substrate 10, a 150 μm thick alkali-free glass EN-A1 manufactured by AGC was used. A 500 μm thick version of the same glass was used for the first support 12. It is desirable to use a glass substrate as the base material for a multilayer wiring board, and it is even more desirable to use alkali-free glass. Being glass allows for a flat surface to be obtained and a flat bottom electrode to be obtained. It can also withstand the temperature required to deposit a dielectric film to obtain the desired resistance value. Furthermore, alkali-free glass suppresses ion migration and leakage from the interface between the dielectric and the glass, making it possible to form a multilayer wiring board including a capacitor with excellent voltage resistance. The first embodiment is not limited to these. It is also desirable that the first support 12 has flatness and thermal expansion coefficient similar to that of the glass substrate 10, but it is not limited to these.

[0047] Figure 8B shows the process of forming the laser-modified portion. A laser is irradiated onto the laminated structure to form a laser-modified portion 13, which will serve as the starting point for the through-hole. The laser-modified portion 13 extends, for example, perpendicular to the glass substrate 10, i.e., in the direction normal to the glass substrate 10, and can be formed at approximately any desired position within the plane of the glass substrate 10.

[0048] Next, referring to Figures 8C through 8O, the process of forming the first wiring layer (lower electrode) will be explained. In summary, the process of forming the first wiring layer involves forming a Cu film on a glass substrate by sputtering, forming a desired pattern by photolithography, and removing unwanted Cu films by wet etching. Figure 8C shows the process of forming the adhesion layer 14 and the conductive layer 15.

[0049] First, as a pretreatment, the surface of the glass substrate 10 facing the surface on which the first support 12 is formed was cleaned using a cleaning solution containing potassium hydroxide, and a chromium film of 50 nm was formed on the glass substrate as an adhesion layer 14 by sputtering. Note that other metals such as Ti and Ni may be used for the adhesion layer 14, and the thickness can be in the range of 10 nm to 1,000 nm. It is even preferable that the thickness of the adhesion layer 14 be between 30 nm and 100 nm. If the adhesion layer 14 is too thin, a continuous film cannot be obtained, resulting in variations in adhesion. If it is too thick, it becomes difficult to control the shape of the adhesion layer 14 in the thickness direction. In either case, this can lead to a decrease in dielectric strength. Note that the thickness of the adhesion layer 14 is not limited to this.

[0050] Subsequently, a Cu film was formed as the conductive layer 15 with a thickness of 1 μm by sputtering. If the thickness of the conductive layer 15 is too thick, it becomes necessary to widen the line width to ensure the desired gradient. Conversely, if it is too thin, it will cause wiring resistance, i.e., ESR (Equivalent Series Resistance). For this reason, the thickness of the conductive layer 15 is preferably between 50 nm and 5 μm. More preferably between 200 nm and 2 μm. The surface roughness Sq (root mean square height) of the Cu film was 30 nm. Note that the thickness of the conductive layer 15 is not limited to this.

[0051] In the first embodiment, in addition to the conductive layer 15, Cu is also used as an electrode material. This is because using highly conductive Cu as an electrode reduces parasitic resistance, making it possible to obtain a capacitor with superior characteristics.

[0052] Next, the surface of the conductive layer 15 was treated with 6% sulfuric acid. Note that the surface treatment is not limited to this, and may be selected as appropriate from the viewpoint of surface roughness and adhesion to the resist. Examples include micro-roughening treatment and chemical bonding treatment to improve adhesion to the resist.

[0053] Figure 8D shows the process of forming the resist. The resist patterning was performed by photolithography using a dry film resist (DFR) RD1215 manufactured by Hitachi Chemical Co., Ltd. While dry film resists are generally used, liquid resists may also be used. The resist layer formed on the conductive layer 15 was exposed and developed to form a resist 16 with the desired pattern. The adhesion strength of the DFR at this time was 0.2 kgf / cm.

[0054] Here, when forming a pattern using wet etching, which will be described later, etching generally proceeds isotropically. However, in pattern etching performed when two types of films are included, such as a resist 16 and a conductive layer 15, the etching solution penetrates the boundary between the two films, and etching proceeds first from the area where the etching solution has penetrated. By controlling the adhesion strength between the conductive layer 15 and the resist 16, the inclination of the upper surface of the lower electrode can be controlled.

[0055] Furthermore, if the adhesion strength is 0.5 kgf / cm or higher, pre-etching will not proceed at the boundary, and a sufficient gradient cannot be obtained. Conversely, if it is 0.1 kgf / cm or lower, etching at the boundary will proceed too much, and the resist will peel off if the wiring width of the conductive layer 15 is narrow. Therefore, it is desirable that the adhesion strength be in the range of 0.1 kgf / cm to 0.5 kgf / cm.

[0056] The adhesion strength can be determined by measuring the load when peeling the material at room temperature, a speed of 1 mm / min, and a peeling angle of 90°. The measurement can be performed using a tensile testing machine such as the AC-50C-SL manufactured by TSE Corporation. Furthermore, methods for controlling adhesion strength include, but are not limited to, methods such as changing the surface roughness of the sputtered film, selecting a resist, or using surface treatment before resist formation. For example, by setting the surface roughness Sq of the sputtered film to 10-100 nm, using a dry film resist containing acrylic resin, ethylene glycol monomethyl ether, N,N-dimethylformamide, styrene, etc., and treating the surface of the sputtered film with 6% sulfuric acid, the desired adhesion strength can be obtained.

[0057] Figure 8E shows the process for forming the lower electrode. Here, the conductive layer 15 was patterned by etching. An etching solution containing sulfuric acid and hydrogen peroxide was used, and the etching solution was applied by spray treatment. The etching rate was controlled to 0.7 μm / min, and the etching time was set to film thickness / etching rate × 1.5 times. At this time, the inclination dz / dx of the cross-sectional shape of the end of the lower electrode was 0.1 μm / μm. If there are areas where the inclination angle exceeds a certain level, the shape of the upper electrode becomes unstable, constriction occurs, and the capacitance accuracy decreases.

[0058] Regarding the etching rate, by setting the etching rate to 1.0 μm / min or less, etching at the boundary between the resist and the conductive layer 15 was promoted, and a gradient was obtained. Below 0.3 μm / min, the gradient became too large, and in some cases the resist peeled off during the process. Undercutting at the interface between the glass and the lower electrode can be suppressed by controlling the etching time. If the etching time is too short, residue is generated, and in some cases a short circuit occurs. Even if a short circuit does not occur, it can cause parasitic capacitance, leading to variations in capacitance accuracy. From this perspective, it is desirable that the etching rate for wet etching be in the range of 0.3 μm / min to 1.0 μm / min, and the etching time be in the range of film thickness / etching rate × 1.2 to film thickness / etching rate × 1.7.

[0059] Next, the DFR is peeled off to reveal the first wiring layer (lower electrode), which consists of a patterned adhesion layer 14 and a conductive layer 15. For peeling off the DFR, an amine-based peeling solution R-100 manufactured by Mitsubishi Gas Chemical Co., Ltd. was used, but the peeling method and peeling solution are not limited to this method.

[0060] Figure 8F shows the process of forming the dielectric layer. Dielectric layer 17 is formed using a plasma CVD apparatus. x It is formed by depositing a film with a thickness of 800 nm.

[0061] The type of dielectric is not limited, but the resistance of the dielectric layer 17 is 1.0 × 10 10 A resistance of Ωcm or higher is desirable. The dielectric film can be made to have high resistance, thereby ensuring sufficient dielectric strength. Other dielectric materials include SiO2. x Ta2O3 can be used.

[0062] Furthermore, the film thickness of the dielectric layer 17 is preferably between 200 nm and 2000 nm. Even with a sloped lower electrode, the surface has fine irregularities and roughness, and the degree of these varies between in-plane and substrate layers. By making the film thickness of the dielectric layer 17 200 nm or more, the effects of irregularities and roughness can be suppressed, and multilayer wiring boards containing capacitors with excellent voltage resistance can be stably manufactured. At thicknesses of 2000 nm or more, cracks are more likely to occur in the dielectric, which can cause capacitance variations and, in some cases, lead to a decrease in voltage resistance. In addition, in multilayer wiring boards, the dielectric interferes with connections to other layers, so it is necessary to remove (etch) areas other than those that are needed. If the dielectric layer 17 is made thicker than necessary, etching takes time, leading to increased manufacturing costs.

[0063] The resistance of a dielectric film varies depending on the deposition method, the type of gas used (even with the same deposition method), power, deposition pressure, and temperature. For example, a desired dielectric film can be obtained by depositing a film using plasma CVD with an output of 0.5 kW to 2.5 kW and a gas containing NH3 and SiH4 in the range of 100°C to 350°C, or by depositing a film using a gas containing N2O and SiH4 with an output of 0.5 kW to 2.5 kW in the range of 100°C to 350°C.

[0064] Furthermore, the resistance value of the dielectric is the volume resistivity. The method for measuring the volume resistivity of the dielectric layer involves depositing a Ti / Cu sputtered film onto glass and patterning it using photolithography to form the lower electrode portion of the dielectric and the measurement electrode. A dielectric layer and a conductive layer 3 are deposited and patterned using photolithography to form the upper electrode portion and the measurement electrode. The dielectric on the measurement electrode is removed by dry etching to obtain the dielectric sandwiched between the electrodes. The area of ​​the dielectric sandwiched between the electrodes is set to 1 mm², and the dielectric layer thickness is set to 400 nm. The relationship between voltage and current is measured using a parameter analyzer (e.g., Keithley 4200A) to obtain the resistance value (Ω), and the volume resistivity (Ωcm) can be obtained from the relationship between area and thickness.

[0065] Next, the second wiring layer (upper electrode) is formed. In summary, the process of forming the second wiring layer involves forming a Cu film on the dielectric film by sputtering, forming a desired pattern by photolithography, and removing unwanted Cu films by wet etching. Figure 8G shows the process of forming the second wiring layer. In summary, Figure 8G shows the process of covering the capacitor with an inorganic insulating film, opening the inorganic insulating film to obtain conductivity with another layer, and forming the wiring.

[0066] First, a 50 nm thick Ti film was formed on the dielectric layer 17 as an adhesion layer 18 by sputtering. Other materials such as Cr and Ni may be used for the adhesion layer 18, and its thickness can be in the range of 10 nm to 1,000 nm. Furthermore, the adhesion layer 18 is optional. The adhesion layer 18 is preferably between 30 nm and 100 nm thick. If the adhesion layer 18 is too thin, a continuous film cannot be obtained, resulting in variations in adhesion. If it is too thick, controlling the shape in the thickness direction of the adhesion layer becomes difficult, which can lead to a decrease in dielectric strength.

[0067] Subsequently, a Cu film was formed as the conductive layer 19 with a thickness of 1 μm by sputtering. The thickness of the conductive layer 19 is not limited, but if it is too thick, it will lead to increased process costs, and if it is too thin, it will cause wiring resistance and ESR, so a thickness of 50 nm to 10 μm is desirable. More preferably, it is between 200 nm and 5 μm.

[0068] Next, the surface of the sputtered film is treated with 6% sulfuric acid, and then DFR (RD1215) is applied and photolithography is performed to pattern the resist. After patterning the conductive layer 19 by etching, the DFR is peeled off to reveal the second wiring layer, which consists of the patterned adhesion layer 18 and the conductive layer 19.

[0069] Furthermore, the first wiring layer (lower electrode) and the second wiring layer (upper electrode) are arranged to overlap when viewed from above. In other words, the first wiring layer (lower electrode) and the second wiring layer (upper electrode) are arranged to intersect, or overlap, in the vertical direction, that is, in the direction normal to the surface of the glass substrate 10. A capacitor is formed at the intersection of the first wiring layer (lower electrode) and the second wiring layer (upper electrode), and the wiring itself is routed within the plane, making it easy to obtain conductivity with the layers above and below. In addition, since it is not necessary to place vias for interlayer connection above and below the capacitor, a capacitor with a small capacitance value can be precisely positioned as a single element.

[0070] Next, an insulating layer 20 was formed. As the insulating film 19, SiN was used in a plasma CVD apparatus. xA film of 800 nm was deposited. Note that the insulating film 19 is not limited to the above; for example, an insulating resin may be used. In that case, the process for obtaining interlayer conductivity, as described later, should also be a method suitable for the material. Preferably, the capacitor is made of an inorganic insulating film (SiN, SiO, TaO). x By covering it with this material, the parasitic resistance is reduced compared to resin, improving the capacitor characteristics. In addition, moisture resistance is improved, suppressing the deterioration of capacitor characteristics due to moisture absorption.

[0071] Next, to obtain interlayer conductivity, a portion of the insulating layer 20 was etched. Patterning was performed using photolithography, and a portion of the insulating layer 20 was removed using a dry etching process to create an etched opening Ap.

[0072] Figure 8H shows the process for forming the third wiring layer. A seed layer 21 for power supply is formed on the insulating layer 20 by sputtering, and a pattern is formed using resist. A plating treatment of 2 μm to 20 μm is performed. After that, the unnecessary resist pattern is peeled off, the seed layer 21 is removed, and the third wiring layer 22 is formed.

[0073] Figure 8I shows the process of forming the insulating resin layer 23. Figure 8I can also be said to show the process of forming the organic insulating film. The insulating resin layer 23 is a material containing at least one of the following: epoxy resin, polyimide resin, or polyamide resin, and containing fillers such as silica, titanium oxide, or urethane. It is preferably a liquid or film-like material. For example, an organic insulating resin is an epoxy resin containing silica filler. In the case of liquid resins, the insulating resin layer can be formed by spin coating; in the case of film-like resins, a vacuum laminator can be used to heat and pressurize under vacuum. The material of the insulating resin layer 23 can be appropriately selected as needed. If inorganic materials are used, it becomes difficult to secure the thickness of inductors and wiring when constructing a multilayer wiring board, and the material becomes brittle, reducing mechanical strength. Therefore, it is desirable to form an insulating resin layer 23 using an insulating resin.

[0074] Figure 8J shows the process of bonding the second support. A second adhesive layer 24 is formed on the laminated structure, and the second support 25 is bonded using the second adhesive layer 24.

[0075] The second adhesive layer 24 can be appropriately selected from materials such as a resin that absorbs light such as UV light and becomes peelable by generating heat, sublimation, or alteration, a resin that becomes peelable by foaming due to heat, or a material containing functional groups that temporarily fix the core substrate and the first support 12, similar to the first adhesive layer 11. However, it is desirable that it be a different material from the first adhesive layer 11.

[0076] Figure 8K shows the process of peeling off the first support. The first support 12 is peeled off, and the first adhesive layer 11 is removed. When peeling off the first support 12, an appropriate peeling method can be selected from UV light irradiation, heat treatment, physical peeling, etc., depending on the material used for the first adhesive layer 11.

[0077] Figure 8L shows the process of forming through holes in a glass substrate. The laser-modified portion 13 of the glass substrate 10 is selectively removed by etching to form through holes 26. Wet etching using an aqueous hydrogen fluoride solution is suitable for this etching process. The etching method is not limited to this.

[0078] Figure 8M shows the process of forming the fourth wiring layer and the insulating resin layer. A seed layer for power supply is formed in the through hole 26 and on the surface of the glass substrate 10, and a pattern is formed with resist. After plating with a thickness of 2 μm to 20 μm, the unnecessary resist pattern is peeled off, the seed layer is removed, and the fourth wiring layer 27 is formed. After the fourth wiring layer 27 is formed, the insulating resin layer 28 is formed.

[0079] Figure 8N shows the process of peeling off the second support 25. The second support 25 is peeled off, and the second adhesive layer 24 is also removed. When peeling off the second support 25, an appropriate peeling method can be selected from UV light irradiation, heat treatment, physical peeling, etc., depending on the material used for the second adhesive layer 24.

[0080] Figure 8O shows the process for forming the build-up layer. After forming vias in the insulating resin layers 23 and 28 with a laser, a seed layer is formed on the vias, and then the build-up layer 29 is formed using a semi-additive process (i.e., a series of steps including resist pattern formation, plating, resist stripping, seed layer removal, and insulating resin layer formation). At least one wiring layer is laminated within the build-up layer 29, and the number of layers can be set as needed.

[0081] Next, after forming an outer protective film such as solder resist, bonding pads 30 for semiconductor elements and bonding pads 31 for the substrate are formed. Surface treatment with Ni / Au, Ni / Pd / Au, IT, OSP (water-soluble preflux), etc. is applied, and solder for bonding semiconductor elements and solder for bonding the substrate are formed as needed to complete the multilayer wiring board.

[0082] (Examples and comparative examples) As an example of the first embodiment, capacitors with different inclinations of the cross-sectional shape at the end of the lower electrode, dielectric resistance values, and dielectric thicknesses were created, and their capacitance was evaluated and compared using an LCR meter, and their dielectric strength using a parameter analyzer. For the capacitance values, the average value (Ave.) and standard deviation (σ) were calculated, and the variation of 3σ / Ave. was compared. The following evaluation values ​​were obtained for multiple capacitor structures formed on a single substrate.

[0083] The conditions for evaluating the dielectric strength are as follows: • Measuring device: Parameter analyzer (4200A-SCS model, manufactured by Keithley) • Test voltage: 15V • Printing time: 5 seconds • Measurement item: Current value I(A) • Criteria for judgment: Current value (charge / discharge current) 50mA or less Furthermore, the conditions for evaluating capacity variation are as follows: • Measuring device: LCR meter (4287A, manufactured by Keysight Technologies) • Measurement frequency: 1MHz • Criteria for evaluation: Variability 3σ (sigma) / Ave. (mean) 0.03 or less

[0084] [Table 1]

[0085] Item "Judgment" ○ indicates that the predetermined level was met in terms of variability and withstand voltage. As shown in Examples 1 to 16, when the inclination dz / dx of the inclined portion of the lower electrode is 0.5 μm / μm or less and the dielectric film thickness capacitance is 200 nm or more and 2000 nm or less, the variation in capacitor capacitance can be suppressed and the decrease in withstand voltage can be suppressed.

[0086] (Effects / Actions) By forming the lower electrode using the sputtering method, a flat electrode surface can be obtained. Electrode shape formation by photolithography allows for high-precision single-element capacitor formation, and wet etching allows for control of the wiring end shape and the creation of a slope. Forming a dielectric material on the sloped lower electrode improves the dielectric strength. The upper electrode is formed by sputtering a Cu film, photolithography, and wet etching to obtain a capacitor structure. Using wet etching on the sputtered film allows for high-precision formation of capacitors with small capacitance values. Thus, the present invention makes it possible to form a capacitor structure with excellent voltage resistance by configuring a single capacitor element within a circuit board with high precision.

[0087] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of the present invention.

[0088] This disclosure also includes the following aspects: (Aspect 1) A multilayer wiring board with a built-in capacitor, At least one of the capacitors is configured such that a lower electrode, a dielectric layer, and an upper electrode are provided in order from the side closest to the core substrate. The lower electrode is placed on the core substrate, The upper electrode has a portion that forms a capacitor by overlapping with the dielectric layer and the lower electrode in the direction normal to the surface of the core substrate, and a portion that extends from the capacitor portion to a portion in the surface of the core substrate that does not overlap with the lower electrode. The lower electrode is characterized by having a sloping portion in cross-sectional view where the inclination dz / dx is 0.02 μm / um or more and 0.5 μm or less, in a multilayer wiring substrate. (Aspect 2) A multilayer wiring board according to Embodiment 1, A multilayer wiring substrate characterized in that the thickness of the dielectric layer is 200 nm or more and 2000 nm or less. (Aspect 3) A multilayer wiring board according to embodiment 1 or 2, The resistance value of the dielectric layer is 1.0 × 10 10 A multilayer wiring board characterized by having a density of Ωcm or greater. (Aspect 4) A multilayer wiring board according to any one of embodiments 1 to 3, A multilayer wiring board characterized in that the core substrate is a glass substrate. (Appendix 5) A multilayer wiring board according to any one of embodiments 1 to 4, A multilayer wiring board characterized in that the upper electrode and the lower electrode are made of Cu. (Aspect 6) A method for manufacturing a multilayer wiring board with a built-in capacitor, The process involves forming a Cu film on a glass substrate by sputtering, creating a desired pattern by photolithography, and removing unwanted Cu films by wet etching to form a base electrode. The process of forming a dielectric film, The process involves forming a Cu film on a dielectric film by sputtering, creating a desired pattern by photolithography, and removing unwanted Cu films by wet etching to form an upper electrode. A method for manufacturing a multilayer wiring board, characterized by having the following features. (Aspect 7) A method for manufacturing a multilayer wiring board according to embodiment 6. The method for manufacturing a multilayer wiring substrate incorporating a capacitor is characterized in that, in the step of forming the lower electrode, the adhesion strength between the Cu film and the resist used for photolithography is 0.1 kgf / cm or more and 0.5 kgf / cm or less. (Pattern 8) A method for manufacturing a multilayer wiring board according to embodiment 6 or 7, A method for manufacturing a multilayer wiring substrate, characterized in that it includes a step of forming an adhesion layer on the glass substrate before forming the Cu film in the step of forming the lower electrode. (Aspect 9) A method for manufacturing a multilayer wiring board according to any one of embodiments 6 to 8, In the process of forming the lower electrode, A method for manufacturing a multilayer wiring board containing a capacitor, characterized by setting the wet etching rate to a range of 0.3 μm / min to 1.0 μm / min and the etching time to a range of film thickness / etching rate × 1.2 to film thickness / etching rate × 1.7. (Aspect 10) A method for manufacturing a multilayer wiring board according to any one of embodiments 6 to 9, A method for manufacturing a multilayer substrate, characterized by comprising the steps of covering a capacitor with an inorganic insulating film, opening an opening in the inorganic insulating film to obtain conductivity with another layer, forming wiring, and forming an organic insulating film. [Explanation of Symbols]

[0089] 1, 10: Glass substrate 2, 7, 14, 18: Close contact layer 3, 15, 19: Conductive layer 4, 16: Resist 5: Lower electrode 6, 17: Dielectric layer 11: First adhesive layer 12: First support 13: Laser modification section 20: Insulating layer 21: Seed Layer 23, 28: Insulating resin layer 24:Second adhesive layer 25:Second support 26: Through hole 27: 4th wiring layer 29: Build-up layer 30: Bonding pads for semiconductor devices 31: Bonding pads for circuit boards ALa, ALb: Adhesive layer Ap: Etched opening DLa, DLb, DLc: Dielectric layer Na, Gb, Gc: Glass substrate

Claims

1. A multilayer wiring board with a built-in capacitor, At least one of the capacitors is configured such that a lower electrode, a dielectric layer, and an upper electrode are provided in order from the side closest to the core substrate. The lower electrode is placed on the core substrate, The upper electrode has a portion that forms a capacitor by overlapping with the dielectric layer and the lower electrode in the direction normal to the surface of the core substrate, and a portion that extends from the capacitor portion to a portion in the surface of the core substrate that does not overlap with the lower electrode. The lower electrode is characterized by having a sloping portion in which, in a cross-sectional view, the inclination dz / dx is 0.02 μm / μm or more and 0.5 μm / μm or less, in a multilayer wiring board.

2. A multilayer wiring board according to claim 1, A multilayer wiring substrate characterized in that the thickness of the dielectric layer is 200 nm or more and 2000 nm or less.

3. A multilayer wiring board according to claim 1, The resistance value of the dielectric layer is 1.0 × 10 １０ A multilayer wiring board characterized by having a density of Ωcm or greater.

4. A multilayer wiring board according to claim 1, A multilayer wiring board characterized in that the core substrate is a glass substrate.

5. A multilayer wiring board according to claim 1, A multilayer wiring board characterized in that the upper electrode and the lower electrode are made of Cu.

6. A method for manufacturing a multilayer wiring board with a built-in capacitor, The process involves forming a Cu film on a glass substrate by sputtering, creating a desired pattern by photolithography, and removing unwanted Cu films by wet etching to form a base electrode. The process of forming a dielectric film, The process involves forming a Cu film on a dielectric film by sputtering, creating a desired pattern by photolithography, and removing unwanted Cu films by wet etching to form an upper electrode. A method for manufacturing a multilayer wiring board, characterized by having the following features.

7. A method for manufacturing a multilayer wiring board according to claim 6. The method for manufacturing a multilayer wiring substrate incorporating a capacitor is characterized in that, in the step of forming the lower electrode, the adhesion strength between the Cu film and the resist used for photolithography is 0.1 kgf / cm or more and 0.5 kgf / cm or less.

8. A method for manufacturing a multilayer wiring board according to claim 6, A method for manufacturing a multilayer wiring substrate, characterized in that it includes a step of forming an adhesion layer on the glass substrate before forming the Cu film in the step of forming the lower electrode.

9. A method for manufacturing a multilayer wiring board according to claim 6, In the process of forming the lower electrode, A method for manufacturing a multilayer wiring board containing a capacitor, characterized by setting the wet etching rate to a range of 0.3 μm / min to 1.0 μm / min and the etching time to a range of film thickness / etching rate × 1.2 to film thickness / etching rate × 1.

7.

10. A method for manufacturing a multilayer wiring board according to claim 6, A method for manufacturing a multilayer substrate, characterized by comprising the steps of covering a capacitor with an inorganic insulating film, opening an opening in the inorganic insulating film to obtain conductivity with another layer, forming wiring, and forming an organic insulating film.

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