Semiconductor memory

Abstract

We provide semiconductor memory devices capable of high-speed operation. [Solution] The semiconductor memory device comprises a plurality of memory block regions aligned in a first direction, a hookup region aligned in the first direction with respect to the plurality of memory block regions, and a wiring region extending in the first direction and aligned with the plurality of memory block regions in a second direction intersecting the first direction. Each of the plurality of memory block regions comprises a plurality of memory strings extending in the first direction and aligned in the second direction, and a first wiring extending in the second direction and commonly connected to the plurality of memory strings. The wiring region extends in the first direction and comprises a second wiring commonly connected to a plurality of first wirings corresponding to the plurality of memory block regions. The hookup region extends in a third direction intersecting the first and second directions and comprises contact electrodes electrically connected to the second wiring. A first transistor is provided in the current path between the first wiring and the second wiring.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known in which multiple memory cells are stacked in a direction intersecting the surface of the substrate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent No. 10,607,995 [Patent Document 2] Japanese Patent Publication No. 2017-056452 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] We provide semiconductor memory devices capable of high-speed operation. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment comprises a plurality of memory block regions aligned in a first direction, a hookup region aligned in the first direction with respect to the plurality of memory block regions, and a wiring region extending in the first direction and aligned with the plurality of memory block regions in a second direction intersecting the first direction. Each of the plurality of memory block regions comprises a plurality of memory strings extending in the first direction and aligned in the second direction, and a first wiring extending in the second direction and commonly connected to the plurality of memory strings. The wiring region comprises a second wiring extending in the first direction and commonly connected to a plurality of first wirings corresponding to the plurality of memory block regions. The hookup region comprises contact electrodes extending in a third direction intersecting the first and second directions and electrically connected to the second wiring. A first transistor is provided in the current path between the first wiring and the second wiring. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a circuit diagram showing a part of the configuration of the semiconductor memory device. [Figure 3] This is a schematic plan view showing a part of the configuration of the semiconductor memory device. [Figure 4] This is a schematic plan view showing an enlarged portion of Figure 3. [Figure 5] This is a schematic perspective view including the portion shown in Figure 4. [Figure 6] Figure 4 is a schematic cross-sectional view taken along line AA' of the structure shown, viewed in the direction of the arrow. [Figure 7] Figure 4 is a schematic cross-sectional view taken by cutting the structure along line BB' and viewing it in the direction of the arrow. [Figure 8] Figure 4 is a schematic cross-sectional view taken along the CC' line of the structure shown, viewed in the direction of the arrow. [Figure 9] This is a schematic plan view showing a portion of the configuration of the hookup region (RHU). [Figure 10] Figure 9 is a schematic cross-sectional view taken by cutting the structure along line DD' and viewing it in the direction of the arrow. [Figure 11] Figure 9 is a schematic cross-sectional view taken by cutting the structure along the EE' line and viewing it in the direction of the arrow. [Figure 12] This is a schematic plan view illustrating a modified example of the semiconductor memory device according to the first embodiment. [Figure 13] This is a circuit diagram showing a part of the configuration of a semiconductor memory device according to the second embodiment. [Figure 14] This is a schematic plan view showing a part of the configuration of the semiconductor memory device. [Figure 15] This is a schematic plan view illustrating the method for manufacturing a semiconductor memory device according to the first and second embodiments. [Figure 16]This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 17] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 18] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 19] This is a schematic plan view illustrating the manufacturing method. [Figure 20] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 21] This is a schematic plan view illustrating the manufacturing method. [Figure 22] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 23] This is a schematic plan view illustrating the manufacturing method. [Figure 24] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 25] This is a schematic plan view illustrating the manufacturing method. [Figure 26] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 27] This is a schematic plan view illustrating the manufacturing method. [Figure 28] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 29] This is a schematic plan view illustrating the manufacturing method. [Figure 30] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 31] This is a schematic plan view illustrating the manufacturing method. [Figure 32] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 33] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the third embodiment. [Figure 34] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the fourth embodiment. [Figure 35] This is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 36] This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device. [Figure 37] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 38] This is a schematic cross-sectional view illustrating the manufacturing method. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0013] Furthermore, in this specification, the direction along a predetermined plane may be referred to as the first direction, the direction intersecting the first direction along this predetermined plane may be referred to as the second direction, and the direction intersecting this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0015] [First Embodiment] [composition] Fig. 1 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the first embodiment. Fig. 2 is a circuit diagram showing a partial configuration of the semiconductor memory device according to the first embodiment. As shown in, for example, Fig. 1, the semiconductor memory device according to the present embodiment includes a plurality of memory block regions R BLK and a hook-up region R HU and a plurality of connection line regions R LBIY . The memory block regions R BLK are arranged in a matrix in the X direction and the Y direction. The hook-up region R HU is provided corresponding to a plurality of memory block regions R BLK arranged in the Y direction. The hook-up region R HU is adjacent to the memory block region R BLK in the Y direction. The connection line regions R LBIY are provided corresponding to a plurality of memory block regions R BLK arranged in the Y direction and the hook-up regions R HU corresponding thereto. The connection line region R LBIY is arranged in the X direction in parallel with a plurality of memory block regions R BLK .

[0016] The memory block region R BLK is provided with a plurality of memory strings MS extending in the Y direction and arranged in the X direction, and a local block connection line LBIX extending in the X direction and commonly connected to the plurality of memory strings MS.

[0017] The memory string MS includes, for example, as shown in Fig. 2, a plurality of memory transistors (memory cells MC) connected in series and a selection transistor SG connected thereto. One end of the memory string MS is connected to the local block connection line LBIX, and the other end is connected to the source line CSL.

[0018] The connection line region R LBIY(Figure 1) shows a local block connection line LBIY extending in the Y direction. Multiple local block connection lines LBIX, aligned in the Y direction, are commonly connected to local block connection line LBIY. Furthermore, local block connection line LBIY is connected to the hookup region R HU It is electrically connected to a peripheral circuit (not shown) via at least one of the multiple contact electrodes CC provided therein.

[0019] In the example shown in Figures 1 and 2, one memory block region R BLK A local block selection transistor SWX1 is provided between the multiple memory strings MS and the local block connection line LBIY. In the example shown in Figure 1, a local block selection transistor SWY1 is provided between the local block connection line LBIY and the contact electrode CC.

[0020] The local block selection transistor SWX1 selects at least one memory block region R BLK It functions as a switch for selecting an option.

[0021] In the following, during write and read operations, the memory block area R containing the memory cell MC that is the target of the operation is considered. BLK The selected memory block region R BLK This refers to the memory block area R that does not include the memory cell MC that is the target of the operation. BLK This is the unselected memory block region R BLK It is sometimes called that.

[0022] During write and read operations, for example, the selected memory block region R BLK And the selected memory block region R BLK The local block connection line LBIY connected to and the local block selection transistor SWX1 provided between them are set to the ON state, and the unselected memory block region R BLK And the unselected memory block region R BLKThe local block selection transistor SWX1, which is located between the local block connection line LBIY and the other, is turned OFF.

[0023] The local block selection transistor SWY1 functions as a switch for selecting at least one local block connection line LBIY.

[0024] During write and read operations, for example, the selected memory block region R BLK The local block selection transistor SWY1, located between the local block connection line LBIY and the contact electrode CC connected to that local block connection line LBIY, is turned ON, while the local block selection transistor SWY1, located between the other local block connection line LBIY and the contact electrode CC connected to that local block connection line LBIY, is turned OFF.

[0025] Figure 3 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the first embodiment. Figure 3 shows two adjacent memory block regions R in the Y direction. BLK Figure 4 shows a part of it. Figure 4 is a schematic plan view showing an enlarged portion of Figure 3. Figures 3 and 4 are plan views showing the configuration of the memory layer ML, which will be described later. Figure 5 is a schematic perspective view including the part shown in Figure 4. Figure 6 is a schematic cross-sectional view of the structure shown in Figure 4, cut along line AA' and viewed in the direction of the arrow. Figure 7 is a schematic cross-sectional view of the structure shown in Figure 4, cut along line BB' and viewed in the direction of the arrow. Figure 8 is a schematic cross-sectional view of the structure shown in Figure 4, cut along line CC' and viewed in the direction of the arrow.

[0026] Figure 3 shows the memory block region R BLK Multiple memory strings MS and local block connection lines LBIX are provided in region R. SWX , and also, the connecting line region R LBIY This shows the local block connection line LBIY located at [location].

[0027] In the following explanation, among the multiple memory strings MS, the region where multiple memory cells MC are provided is referred to as the memory cell region R. MC A region where multiple selection transistors SG are provided is the selection transistor region R. SG1 ,R SG2 It is sometimes called the selected transistor region R. SG1 This is the selected transistor region R SG2 It is installed in a location closer to the local block connection line LBIX.

[0028] Figure 5 shows a part of the semiconductor substrate Sub. The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B). As shown in Figure 5, the semiconductor memory device according to this embodiment comprises a plurality of memory layers ML arranged in the Z direction above the semiconductor substrate Sub. An insulating layer 101 such as silicon oxide (SiO2) is provided between two adjacent memory layers ML in the Z direction.

[0029] The memory layer ML comprises multiple semiconductor layers 110 aligned in the X direction. Each of these multiple semiconductor layers 110 comprises multiple memory cell regions R as described with reference to Figure 3. MC , and multiple selectable transistor regions R SG1 ,R SG2 It extends in the Y direction over a certain distance. The semiconductor layer 110 functions, for example, as the channel region of a plurality of memory cells MC and a selection transistor SG connected in series. The semiconductor layer 110 may contain, for example, undoped polycrystalline silicon (Si).

[0030] Memory block area R BLK In this case, for example, as shown in Figure 4, an insulating layer 123 made of silicon oxide (SiO2) or the like is provided between adjacent semiconductor layers 110 in the X direction.

[0031] Memory cell region R MCIn this configuration, for example, as shown in Figure 4, a plurality of conductive layers 120 are provided between the semiconductor layer 110 and the insulating layer 123, aligned in the Y direction, and a gate insulating layer 130 is provided between each of the plurality of conductive layers 120 and the semiconductor layer 110.

[0032] The conductive layer 120 functions, for example, as the gate electrodes of multiple memory transistors and the word lines connected thereto. The conductive layer 120 may contain, for example, titanium nitride (TiN), tungsten (W), and a multilayer film thereof. The conductive layer 120 extends in the Z direction, penetrating multiple memory layers ML, as shown in Figures 5 and 6, and faces the semiconductor layer 110 of each memory layer ML.

[0033] The gate insulating layer 130 comprises, for example, a tunnel insulating layer 131 provided on the X-direction side surface of the semiconductor layer 110, a charge storage layer 132 provided on the X-direction side surface, and a block insulating layer 133 provided on the X-direction side surface, as shown in Figure 6.

[0034] The tunnel insulating layer 131 may contain, for example, silicon oxide (SiO2).

[0035] The charge storage layer 132 may contain, for example, polycrystalline silicon (Si). Furthermore, this polycrystalline silicon (Si) may contain N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may not contain these impurities.

[0036] The block insulating layer 133 may contain, for example, silicon oxide (SiO2). Alternatively, the block insulating layer 133 may contain an insulating metal oxide film such as aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0037] Selected transistor region R SG1 ,R SG2 In this case, for example, as shown in Figure 4, a conductive layer 140 is provided, and the selected transistor region R SG2 A conductive layer 144 is provided in the vicinity of it.

[0038] The conductive layer 140 functions, for example, as a contact electrode for supplying voltage to the semiconductor layer 110. The conductive layer 140 may also include a semiconductor layer such as polycrystalline silicon (Si) containing P-type impurities such as boron (B). The conductive layer 140 extends in the Z direction, penetrating multiple memory layers ML.

[0039] Furthermore, the conductive layer 140 is used as a contact electrode, etc., for supplying voltage to the semiconductor layer 110, and is located in a selected transistor region R SG1 ,R SG2 They may also be established in other areas.

[0040] The conductive layer 144 functions, for example, as a contact electrode for supplying voltage to the semiconductor layer 110. The conductive layer 144 may include a semiconductor layer such as polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P). The conductive layer 144 extends in the Z direction, penetrating multiple memory layers ML. The conductive layer 144 may also function as part of the source line CSL.

[0041] Furthermore, the conductive layer 144 is used as a contact electrode, etc., for supplying voltage to the semiconductor layer 110, and is located in a selected transistor region R SG2 They may also be provided in areas other than their immediate vicinity.

[0042] Also, the selected transistor region R SG1 ,R SG2 In this configuration, for example, as shown in Figure 4, a plurality of conductive layers 150 are provided between the semiconductor layer 110 and the insulating layer 123, aligned in the Y direction, and a gate insulating layer 160 is provided between each of the plurality of conductive layers 150 and the semiconductor layer 110.

[0043] The conductive layer 150 functions, for example, as the gate electrode of a selection transistor SG and the wiring connected thereto. The conductive layer 150 may contain, for example, titanium nitride (TiN), tungsten (W), and a multilayer film thereof. The conductive layer 150 extends in the Z direction, penetrating multiple memory layers ML, as shown in Figure 7, for example, and faces the semiconductor layer 110 of each memory layer ML.

[0044] The gate insulating layer 160 comprises, for example, an insulating layer 161 provided on the X-direction side surface of the semiconductor layer 110, and an insulating layer 163 provided on the X-direction side surface thereof, as shown in Figure 7.

[0045] The insulating layer 161 may contain, for example, silicon oxide (SiO2).

[0046] The insulating layer 163 may contain, for example, silicon oxide (SiO2). Alternatively, the insulating layer 163 may contain an insulating metal oxide film such as aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0047] The configuration of the gate insulating layer 160 shown in Figure 7 is merely illustrative, and for example, the gate insulating layer 160 may have the same configuration as the gate insulating layer 130. In such a case, for example, the gate insulating layer 160 may include a layer similar to the charge storage layer 132 (Figure 6) provided between the insulating layer 161 and the insulating layer 163.

[0048] Selected transistor region R SG1 In adjacent regions in the Y direction, for example, as shown in Figure 4, the memory layer ML includes a conductive layer 170 that extends substantially in the X direction. In addition, a plurality of insulating layers 171 are provided along the conductive layer 170.

[0049] The conductive layer 170 functions, for example, as a local block connection line LBIX (Figures 1 and 2). The conductive layer 170 may also contain a conductive layer such as titanium nitride (TiN). The conductive layer 170 is connected to a plurality of semiconductor layers 110 via semiconductor layers 111. The conductive layer 170 is electrically connected, for example, to the semiconductor layers 110 in a plurality of memory strings MS arranged on both sides of the conductive layer 170 in the Y direction.

[0050] The semiconductor layer 111 is provided on both sides of the conductive layer 170 in the Y direction. The semiconductor layer 111 may contain, for example, polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P).

[0051] The insulating layer 171 may contain, for example, silicon oxide (SiO2). The insulating layer 171 extends in the Z direction, penetrating multiple memory layers ML.

[0052] Connecting line region R LBIY In this case, for example, as shown in Figure 4, the memory layer ML includes a conductive layer 180 extending in the Y direction. Also, the connection line region R LBIY Multiple insulating layers 181 are provided along the conductive layer 180.

[0053] The conductive layer 180 functions, for example, as a local block connection line LBIY (Figures 1 and 2). The conductive layer 180 may also contain a conductive layer such as titanium nitride (TiN). The conductive layer 180 is connected to region R via the semiconductor layer 112. SWX It is connected to the semiconductor layer 110 inside.

[0054] The semiconductor layer 112 is provided on a portion of the side surface of the conductive layer 180. The semiconductor layer 112 may contain, for example, the same material as the semiconductor layer 111.

[0055] The insulating layer 181 may contain, for example, silicon oxide (SiO2). The insulating layer 181 extends in the Z direction, penetrating multiple memory layers ML, as shown in Figure 5, for example.

[0056] area RSWX As shown in Figures 3 and 4, for example, it is located adjacent to local block connection line LBIX and local block connection line LBIY. Region R SWX A local block selection transistor SWX1 is provided (Figure 4).

[0057] area R SWX In this configuration, for example, as shown in Figure 4, a plurality of conductive layers 350 are provided between the semiconductor layer 110 and the insulating layer 123, aligned in the Y direction, and a gate insulating layer 360 is provided between each of the plurality of conductive layers 350 and the semiconductor layer 110.

[0058] The conductive layer 350 functions, for example, as the gate electrode of the local block selection transistor SWX1 and the wiring connected thereto. The conductive layer 350 may contain, for example, titanium nitride (TiN), tungsten (W), and a multilayer film thereof. The conductive layer 350 extends in the Z direction, penetrating multiple memory layers ML, as shown in Figure 8, for example, and faces the semiconductor layer 110 of each memory layer ML.

[0059] The gate insulating layer 360 comprises, for example, an insulating layer 361 provided on the X-direction side surface of the semiconductor layer 110, and an insulating layer 363 provided on the X-direction side surface thereof, as shown in Figure 8.

[0060] The insulating layer 361 may contain, for example, silicon oxide (SiO2).

[0061] The insulating layer 363 may contain, for example, silicon oxide (SiO2). Alternatively, the insulating layer 363 may contain an insulating metal oxide film such as aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0062] The configuration of the gate insulating layer 360 shown in Figure 8 is merely illustrative, and for example, the gate insulating layer 360 may have the same configuration as the gate insulating layer 130. In such a case, for example, the gate insulating layer 360 may include a layer similar to the charge storage layer 132 (Figure 6) provided between the insulating layer 361 and the insulating layer 363.

[0063] In the example shown in Figure 4, region R SWX In the semiconductor layer 110, multiple conductive layers 350 are provided in one region in the X direction, and a conductive layer 140 is provided in the other region in the X direction. The conductive layer 140 is provided between the insulating layer 123 and the semiconductor layer 110. This conductive layer 140 functions, for example, as a body contact electrode of a local block selection transistor SWX1.

[0064] Please note that this configuration is merely an example, and the specific configuration can be adjusted as needed. For example, region R SWX In addition, multiple conductive layers 350 may be provided not only in the region on one side of the semiconductor layer 110 in the X direction, but also in the region on the other side of the semiconductor layer 110 in the X direction. These multiple conductive layers 350 may be provided, for example, between the insulating layer 123 and the semiconductor layer 110. Furthermore, gate insulating layers 360 may be provided between each of these multiple conductive layers 350 and the semiconductor layer 110.

[0065] Furthermore, for example, the conductive layers 120, 150, and 350 shown in Figure 4 may all be arranged in the Y direction at the same pitch.

[0066] Figure 9 shows the hookup region R. HU This is a schematic plan view showing a part of the structure. Figure 10 is a schematic cross-sectional view of the structure shown in Figure 9, cut along line DD' and viewed in the direction of the arrow. Figure 11 is a schematic cross-sectional view of the structure shown in Figure 9, cut along line EE' and viewed in the direction of the arrow.

[0067] Hookup area R HUIn this case, for example as shown in Figure 9, the memory layer ML comprises a plurality of conductive layers 190 extending approximately in the X direction. Also, the hookup region R HU Multiple insulating layers 191 are provided along the conductive layer 190. Furthermore, a hookup region R HU and the connecting line region R LBIY Between them is region R SWY A system is in place.

[0068] The conductive layer 190 functions, for example, as a lead-out wiring from the contact electrode CC to each memory layer ML. The conductive layer 190 may also include a conductive layer such as titanium nitride (TiN). The conductive layer 190 is connected to region R via the semiconductor layer 113. SWY It is connected to the semiconductor layer 110 inside.

[0069] The semiconductor layer 113 is provided on a portion of the side surface of the conductive layer 190. The semiconductor layer 113 may contain, for example, the same material as the semiconductor layer 111.

[0070] The insulating layer 191 may include an insulating layer such as silicon oxide (SiO2). The insulating layer 191 extends in the Z direction, penetrating multiple memory layers ML.

[0071] Also, the hookup region R HU In this configuration, for example, as shown in Figure 9, a plurality of contact electrodes CC are provided, arranged in the X and Y directions along the conductive layer 190. Between the plurality of contact electrodes CC, the memory layer ML includes an insulating layer 102, such as silicon nitride (SiN).

[0072] The contact electrode CC comprises, for example, a substantially cylindrical portion 192 and a substantially disc-shaped portion 193 provided at the lower end of this portion 192, as shown in Figure 10.

[0073] Part 192 may include, for example, a barrier conductive layer 194 made of titanium nitride (TiN) and a conductive layer 195 made of tungsten (W). Part 192 extends in the Z direction through multiple memory layers ML.

[0074] Part 193 may include, for example, a barrier conductive layer 194 made of titanium nitride (TiN). Part 193 is included in any of the memory layers ML and is connected to the X-direction side of the conductive layer 190 included in any of the memory layers ML. Note that the hookup region R HU The device may be provided with contact electrodes CC corresponding to all memory layers ML. In this case, the number of contact electrodes CC may be equal to the number of memory layers ML, or it may be greater than the number of memory layers ML.

[0075] area R SWY A local block selection transistor SWY1 is provided.

[0076] area R SWY In this configuration, for example, as shown in Figure 9, a plurality of conductive layers 450 are provided between the semiconductor layer 110 and the insulating layer 123, aligned in the Y direction, and a gate insulating layer 460 is provided between each of the plurality of conductive layers 450 and the semiconductor layer 110.

[0077] The conductive layer 450 functions, for example, as the gate electrode of the local block selection transistor SWY1 and the wiring connected thereto. The conductive layer 450 may contain, for example, titanium nitride (TiN), tungsten (W), and a multilayer film thereof. The conductive layer 450 extends in the Z direction, penetrating multiple memory layers ML, as shown in Figure 11, for example, and faces the semiconductor layer 110 of each memory layer ML.

[0078] The gate insulating layer 460 comprises, for example, an insulating layer 461 provided on the X-direction side surface of the semiconductor layer 110, and an insulating layer 463 provided on the X-direction side surface thereof, as shown in Figure 11.

[0079] The insulating layer 461 may contain, for example, silicon oxide (SiO2).

[0080] The insulating layer 463 may contain, for example, silicon oxide (SiO2). Alternatively, the insulating layer 463 may contain an insulating metal oxide film such as aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0081] The configuration of the gate insulating layer 460 shown in Figure 11 is merely illustrative, and for example, the gate insulating layer 460 may have the same configuration as the gate insulating layer 130. In such a case, for example, the gate insulating layer 460 may include a layer similar to the charge storage layer 132 (Figure 6) provided between the insulating layer 461 and the insulating layer 463.

[0082] Furthermore, the conductive layer 180 (local block connection line LBIY) is connected to region R via the semiconductor layer 114. SWY It is connected to the semiconductor layer 110 inside.

[0083] The semiconductor layer 114 is provided on a portion of the side surface of the conductive layer 180. The semiconductor layer 114 may contain, for example, the same material as the semiconductor layer 111.

[0084] In the example shown in Figure 9, region R SWY In the semiconductor layer 110, multiple conductive layers 450 are provided in one region in the X direction, and a conductive layer 140 is provided in the other region in the X direction. The conductive layer 140 is provided between the insulating layer 123 and the semiconductor layer 110. This conductive layer 140 functions, for example, as a body contact electrode of the local block selection transistor SWY1.

[0085] Please note that this configuration is merely an example, and the specific configuration can be adjusted as needed. For example, region R SWY In addition, multiple conductive layers 450 may be provided not only in the region on one side of the semiconductor layer 110 in the X direction, but also in the region on the other side of the semiconductor layer 110 in the X direction. These multiple conductive layers 450 may be provided, for example, between the insulating layer 123 and the semiconductor layer 110. Furthermore, gate insulating layers 460 may be provided between each of these multiple conductive layers 450 and the semiconductor layer 110.

[0086] [effect] A semiconductor memory device is known that has layers aligned in the Z direction, with each layer comprising multiple semiconductor layers and multiple conductive layers. In such a semiconductor memory device, a hookup region may be provided to connect each layer aligned in the Z direction to peripheral circuits. Multiple contact electrodes extending in the Z direction are provided in the hookup region. In addition, in such a semiconductor memory device, local wiring is provided in each layer aligned in the Z direction to connect the contact electrodes to the multiple semiconductor layers.

[0087] In each layer aligned in the Z direction, increasing the number of semiconductor layers connected to local wiring can reduce the chip area, but this can increase the load capacitance associated with the local wiring and semiconductor layers, sometimes leading to a decrease in operating speed.

[0088] In this embodiment, a local block selection transistor SWX1 is provided between the local block connection line LBIX and the local block connection line LBIY, and a local block selection transistor SWY1 is provided between the local block connection line LBIY and the contact electrode CC.

[0089] With this configuration, the selected memory block region R BLK The local block selection transistor SWX1 connected to it is turned ON, and the unselected memory block region R BLK By setting the local block selection transistor SWX1 connected to it to the OFF state, the unselected memory block region R BLK It is possible to reduce the load capacity resulting from this and improve the operating speed.

[0090] Also, the selected memory block region R BLK The local block selection transistor SWY1 connected to it is turned ON, and multiple connected memory block regions R BLK By setting the local block selection transistor SWY1, which is all unselected, to the OFF state, the connected memory block region R BLKThis also reduces the load capacity originating from the local block connection line LBIY, which is entirely unselected, and further improves the operating speed.

[0091] [Differentiation] Local block connection lines LBIX and region R as illustrated in Figures 3 to 5. SWX This configuration is merely an example, and the specific configuration can be adjusted as needed.

[0092] Figure 12 is a schematic plan view illustrating a modified example of the semiconductor memory device according to the first embodiment. For example, the configuration of this modified example illustrated in Figure 12 includes two local block connection lines LBIXa aligned in the Y direction instead of local block connection line LBIX, and region R SWX Instead, two regions R are provided between the two local block connection lines LBIXa. SWXa It is equipped with.

[0093] The local block connection line LBIXa is basically provided in the same way as the local block connection line LBIX (Figure 4). However, the conductive layer 170 (Figure 12) that functions as the local block connection line LBIXa is electrically connected, for example, to the semiconductor layers 110 in multiple memory strings MS that are aligned on one side of the conductive layer 170 in the Y direction.

[0094] area R SWXa A local block selection transistor SWX1a is provided.

[0095] The local block selection transistor SWX1a is basically provided in the same way as the local block selection transistor SWX1 (Figure 4). However, the local block selection transistor SWX1a is connected to the conductive layer 180 via a semiconductor layer 112a provided on the side surface of the conductive layer 180, for example. The semiconductor layer 112a contains the same material as the semiconductor layer 112.

[0096] In this configuration, the number of memory strings MS connected to a single local block connection line LBIXa is halved compared to the configuration according to the first embodiment (Figures 3 to 5), thus enabling further reduction of load capacity.

[0097] [Second Embodiment] [composition] Figure 13 is a circuit diagram showing a partial configuration of the semiconductor memory device according to the second embodiment. Figure 14 is a schematic plan view showing a partial configuration of the semiconductor memory device according to the second embodiment.

[0098] In the following description, components similar to those in the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0099] The semiconductor memory device according to this embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device according to this embodiment, the local block selection transistor SWX1 (Figure 1) is not provided between the local block connection line LBIX and the local block connection line LBIY, and instead, local block selection transistors SWX2N and SWX2P are provided in parallel (Figure 13).

[0100] The local block selection transistors SWX2N and SWX2P select at least one memory block region R BLK It functions as a switch for selecting. The local block selection transistor SWX2N is an N-type transistor that uses electrons as carriers. The local block selection transistor SWX2N is connected to the conductive layers 170 and 180 via semiconductor layers 111 and 112 made of polycrystalline silicon (Si) or the like that containing N-type impurities. The local block selection transistor SWX2P is a P-type transistor that uses holes as carriers. The local block selection transistor SWX2P is connected to the conductive layers 170 and 180 via semiconductor layers 115 and 115b made of polycrystalline silicon (Si) or the like that containing P-type impurities.

[0101] During write and read operations, for example, the selected memory block region RBLK and at least one of the local block selection transistors SWX2N and SWX2P provided between the selected memory block region R BLK and the local block connection line LBIY connected thereto is turned on, and the non-selected memory block region R BLK and the non-selected memory block region R BLK and both of the local block selection transistors SWX2N and SWX2P provided between the local block connection line LBIY connected thereto are turned off.

[0102] Also, as shown in FIG. 14 for example, the semiconductor memory device according to the present embodiment has one region R SWX (FIG. 4) replaced by regions R SWX2N and region R SWX2P (FIG. 14).

[0103] Region R SWX2N is provided, for example, as shown in FIG. 14, at a position adjacent to one side in the Y direction of the local block connection line LBIX and the local block connection line LBIY. In region R SWX2N a local block selection transistor SWX2N is provided.

[0104] The local block selection transistor SWX2N is basically provided in the same manner as the local block selection transistor SWX1 (FIG. 4).

[0105] Region R SWX2P is provided, for example, as shown in FIG. 14, at a position adjacent to the other side in the Y direction of the local block connection line LBIX and the local block connection line LBIY. In region R SWX2P a local block selection transistor SWX2P is provided.

[0106] The local block selection transistor SWX2P is basically provided in the same manner as the local block selection transistor SWX1 (FIG. 4). However, the region R where the local block selection transistor SWX2P is provided SWX2PThis device includes a conductive layer 144 instead of the conductive layer 140.

[0107] Furthermore, the local block selection transistor SWX2P is connected to the conductive layer 170 via a semiconductor layer 115 provided on a part of the side surface of the conductive layer 170 in the Y direction. The semiconductor layer 115 may contain, for example, polycrystalline silicon (Si) containing P-type impurities such as boron (B).

[0108] Furthermore, the local block selection transistor SWX2P is connected to the conductive layer 180, for example, via a semiconductor layer 115b provided on the X-direction side of the conductive layer 180. The semiconductor layer 115b may contain the same material as the semiconductor layer 115.

[0109] [effect] In this embodiment, local block selection transistors SWX2N and SWX2P, which are N-type and P-type transistors respectively, are provided in parallel between the local block connection line LBIX and the local block connection line LBIY. With this configuration, even when the capacitive coupling between adjacent memory layers ML in the Z direction is strong, voltage transfer between the local block connection line LBIX and the local block connection line LBIY can be reliably performed in the memory layer ML under operation.

[0110] [Manufacturing method] Figures 15 to 32 are schematic plan views or cross-sectional views illustrating the manufacturing methods of semiconductor memory devices according to the first and second embodiments. Figures 15, 19, 21, 23, 25, 27, 29, and 31 are schematic diagrams that represent the semiconductor layers 110, 111, 112, 115, conductive layers 120, 140, 144, 150, 170, 180, 350, insulating layers 123, 171, 181, and gate insulating layers 130, 160, 360 according to the first and second embodiments, respectively, on a single plane to illustrate their manufacturing methods. Note that the conductive layer 450 and gate insulating layer 460 are basically formed in the same way as the conductive layers 150, 350 and gate insulating layers 160, 360, and are therefore omitted.

[0111] Figure 16 is a schematic cross-sectional view of the structure shown in Figure 15, cut along the line F1-F1' and viewed in the direction of the arrow. Figures 17 and 18 are cross-sectional views of the portion corresponding to Figure 16. Figure 20 is a schematic cross-sectional view of the structure shown in Figure 19, cut along the line F1-F1' and viewed in the direction of the arrow. Figure 22 is a schematic cross-sectional view of the structure shown in Figure 21, cut along the line F1-F1' and viewed in the direction of the arrow. Figure 24 is a schematic cross-sectional view of the structure shown in Figure 23, cut along the line F2-F2' and viewed in the direction of the arrow. Figure 26 is a schematic cross-sectional view of the structure shown in Figure 25, cut along the line F3-F3' and viewed in the direction of the arrow. Figure 28 is a schematic cross-sectional view of the structure shown in Figure 27, cut along the line F4-F4' and viewed in the direction of the arrow. Figure 30 is a schematic cross-sectional view of the structure shown in Figure 29, cut along the line F5-F5' and viewed in the direction of the arrow. Figure 32 is a schematic cross-sectional view of the structure shown in Figure 29, cut along the line F6-F6' and viewed in the direction of the arrow.

[0112] In this manufacturing method, for example, as shown in Figure 16, multiple insulating layers 101 and multiple insulating layers 102 are formed alternately. This process is carried out, for example, by CVD (Chemical Vapor Deposition).

[0113] Next, as shown in Figures 15 and 16, for example, openings 120A, 123A, 140A, 144A, 150A, 171A, 181A, and 350A are formed. These openings 120A, 123A, 140A, 144A, 150A, 171A, 181A, and 350A are extended in the Z direction, similar to openings 120A and 123A shown in Figure 16, exposing the X-direction sides of multiple insulating layers 101 and multiple insulating layers 102 aligned in the Z direction. This process is carried out, for example, by RIE (Reactive Ion Etching).

[0114] Next, as shown in Figure 17, for example, sacrificial layers 120B and 123B containing silicon oxide (SiO2) and amorphous silicon (Si), or carbon (C), etc., and insulating layers 120O and 123O of silicon oxide (SiO2), etc., are sequentially formed inside the openings 120A and 123A. This process is carried out, for example, by CVD.

[0115] Furthermore, similar to the process shown in Figure 17, sacrificial layers 140B, 144B, 150B, 171B, 181B, and 350B (see Figure 19) are formed inside the openings 140A, 144A, 150A, 171A, 181B, and 350A, and insulating layers 140O, 144O, 150O, 171O, 181O, and 350O of silicon oxide (SiO2) or the like are formed on top of these insulating layers.

[0116] Next, as shown in Figure 18, for example, the insulating layer 123O and the sacrificial layer 123B are removed to form an opening, and then a portion of the insulating layer 102 is removed through the opening to form an opening 123A'. A portion of the X-direction side surface of the sacrificial layer 120B is exposed in the opening 123A'. This process is carried out by, for example, RIE, wet etching, etc.

[0117] Next, as shown in Figures 19 and 20, for example, an insulating layer 123 is formed inside the opening 123A'. This process is carried out, for example, by CVD.

[0118] Next, as shown in Figures 21 and 22, for example, the insulating layer 120O and the sacrificial layer 120B are removed to form an opening 120A (see Figure 6), and then a portion of the insulating layer 102 is removed through the opening 120A. Furthermore, a semiconductor layer 110, a tunnel insulating layer 131, and a charge storage layer 132 are sequentially formed in the space created by removing a portion of the insulating layer 102 through the opening 120A. Additionally, a block insulating layer 133, a conductive layer 120, and an insulating layer 120O are formed in the opening 120A. This process is carried out by methods such as RIE, CVD, or wet etching.

[0119] Next, as shown in Figures 23 and 24, for example, the insulating layers 150O, 350O and sacrificial layers 150B, 350B are removed to form openings 150A, 350A, and then a portion of the insulating layer 102 is removed through the openings 150A, 350A. In addition, a semiconductor layer 110 and insulating layers 161, 361 are sequentially formed in the space created by removing a portion of the insulating layer 102 through the openings 150A, 350A, and insulating layers 163, 363, conductive layers 150, 350, and insulating layers 150O, 350O are formed in the openings 150A, 350A. This process is carried out by methods such as RIE, CVD, or wet etching.

[0120] Next, as shown in Figures 25 and 26, for example, the insulating layer 144O and the sacrificial layer 144B are removed to form an opening 144A, and the conductive layer 144 and the insulating layer 144O are formed in the opening 144A. This process is carried out by, for example, RIE, CVD, etc.

[0121] Next, as shown in Figures 27 and 28, for example, the insulating layer 140O and the sacrificial layer 140B are removed to form an opening 140A, and the conductive layer 140 and the insulating layer 140O are formed in the opening 140A. This process is carried out by, for example, RIE, CVD, etc.

[0122] Next, as shown in Figures 29 and 30, for example, the insulating layer 171O and sacrificial layer 171B, and a portion of the insulating layer 181O and sacrificial layer 181B are removed to form openings 171A and 181A. Then, a portion of the semiconductor layer 110 and a portion of the insulating layer 102 are removed through the openings 171A and 181A. In addition, the semiconductor layer 110, semiconductor layers 111 and 112, and conductive layers 170 and 180 are sequentially formed in the space created by removing a portion of the insulating layer 102 through the openings 171A and 181A. Furthermore, the insulating layer 171 and insulating layer 171O are formed in opening 171A, and the insulating layer 181 and insulating layer 181O are formed in opening 181A. This process is carried out by, for example, RIE, CVD, wet etching, etc.

[0123] Next, for example, as shown in FIGS. 31 and 32, after removing the remaining portions of the insulating layer 181O and the sacrificial layer 181B to form the opening 181A, a part of the semiconductor layer 110, a part of the insulating layer 102, and a part of the semiconductor layer 112 are removed through the opening 181A. Also, through the opening 181A, the semiconductor layer 110, the semiconductor layer 115, and the conductive layer 180 are sequentially formed in the space formed by removing a part of the insulating layer 102, and the insulating layer 181 and the insulating layer 181O are formed in the opening 181A. This process is performed, for example, by RIE, CVD, wet etching, or the like.

[0124] [Third Embodiment] [Configuration] FIG. 33 is a schematic plan view showing a part of the configuration of the semiconductor memory device according to the third embodiment.

[0125] In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0126] The semiconductor memory device according to the present embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device (FIG. 33) according to the present embodiment, the local block selection transistor SWY1 (FIG. 1) is not provided between the local block connection line LBIY and the contact electrode CC. In the semiconductor memory device (FIG. 33) according to the present embodiment, the local block selection transistor SWX1 is provided between the plurality of memory strings MS and the contact electrode CC.

[0127] [Effect] In the present embodiment, the local block selection transistor SWX1 connected to the selected memory block region R BLK is turned on, and the local block selection transistor SWX1 connected to the non-selected memory block region R BLK is turned off. According to such a configuration, it is possible to reduce the load capacitance component derived from the non-selected memory block region R BLK and improve the operating speed.

[0128] [Fourth Embodiment] [composition] Figure 34 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the fourth embodiment.

[0129] In the following description, components similar to those in the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0130] The semiconductor memory device according to this embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to this embodiment (Figure 34) does not have a local block selection transistor SWX1 (Figure 1) between the local block connection line LBIX and the local block connection line LBIY. The semiconductor memory device according to this embodiment (Figure 33) has a contact electrode CC and a plurality of memory block regions R BLK A local block selection transistor SWY1 is provided between them.

[0131] [effect] In this embodiment, the selected memory block region R BLK The local block selection transistor SWY1 connected to it is turned ON, and multiple connected memory block regions R BLK The local block selection transistor SWY1, which is all unselected, is set to the OFF state. With this configuration, the memory block region R connected to the OFF local block selection transistor SWY1 is BLK Furthermore, it is possible to reduce the load capacity originating from the local block connection line LBIY, thereby improving the operating speed.

[0132] [Fifth Embodiment] [composition] Figure 35 is a schematic plan view showing a partial configuration of the semiconductor memory device according to the fifth embodiment. Figure 35 is a cross-sectional view of the portion corresponding to Figure 7, and shows a cross-section of the selection transistor SG.

[0133] In the following description, components similar to those in the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0134] The semiconductor memory device according to this embodiment is basically configured the same as the semiconductor memory device according to the first embodiment (Figure 7). However, the semiconductor memory device according to this embodiment (Figure 35) includes a semiconductor layer 110_5 instead of semiconductor layer 110, and a gate insulating layer 160_5 instead of gate insulating layer 160.

[0135] The semiconductor layer 110_5 is basically constructed in the same way as the semiconductor layer 110 (Figure 7). However, as shown in Figure 35, for example, the semiconductor layer 110_5 has a portion that protrudes toward the conductive layer 150 on the side facing the conductive layer 150. Of the semiconductor layer 110_5, the side facing the conductive layer 150 and the side closest to the conductive layer 150 is called surface SS1. Also, of the insulating layer 101, the side facing the conductive layer 150 is called surface SS2. Surface SS1 is located on the conductive layer 150 side of surface SS2.

[0136] The gate insulating layer 160_5 is basically constructed in the same way as the gate insulating layer 160 (Figure 7). However, the gate insulating layer 160_5 includes an insulating layer 161_5 instead of insulating layer 161.

[0137] The insulating layer 161_5 is basically constructed in the same way as the insulating layer 161. However, the insulating layer 161_5 is provided, for example, on the X-direction side of the semiconductor layer 110_5 on the conductive layer 150 side, and on a part of the Z-direction side of the semiconductor layer 110_5. The insulating layer 161_5 includes a portion PT1 that covers at least a part of the X-direction side of the semiconductor layer 110_5, and a portion PT2 that covers at least a part of the Z-direction side of the semiconductor layer 110_5.

[0138] Furthermore, the semiconductor layer 110 (Figures 8 and 11) included in the local block selection transistors SWX1 and SWY1 may also have a portion that protrudes toward the conductive layers 350 and 450 on the side facing the conductive layers 350 and 450, similar to the semiconductor layer 110_5. In such a configuration, the insulating layers 361 and 461 included in the local block selection transistors SWX1 and SWY1 may be provided on the X-direction side of the semiconductor layer 110 facing the conductive layers 350 and 450, and on a part of the Z-direction side of the semiconductor layer 110, similar to the insulating layer 161_5.

[0139] [Manufacturing method] Figures 36 to 38 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the fifth embodiment. Figures 36 to 38 correspond to a part of the configuration shown in Figure 35.

[0140] The manufacturing method is basically the same as that of the first and second embodiments. However, in the manufacturing method according to the fifth embodiment, instead of the steps corresponding to Figures 23 and 24, the following steps, which will be explained with reference to Figures 36 to 38, are performed.

[0141] For example, in the process shown in Figure 36, after removing the insulating layer 150O and the sacrificial layer 150B to form an opening 150A, a portion of the insulating layer 102 is removed through the opening 150A, and a semiconductor layer 110_5B is formed in the space created by removing the portion of the insulating layer 102 through the opening 150A. The semiconductor layer 110_5B contains the same material as the semiconductor layer 110_5.

[0142] Next, in the process shown in Figure 37, for example, a portion of the insulating layers 101 and 123 on the side of opening 150A is removed through opening 150A to form opening 150A_5. Parts of the X-direction side and Z-direction side of the semiconductor layer 110_5B are exposed in opening 150A_5. This process is carried out by, for example, RIE, wet etching, etc.

[0143] Next, in the process shown in Figure 38, for example, an insulating layer 161_5 is formed on the side of the semiconductor layer 110_5 on the side of the opening 150A_5, and on a part of the side of the semiconductor layer 110_5 in the Z direction. This process is carried out, for example, by thermal oxidation.

[0144] Next, an insulating layer 163 and a conductive layer 150 are formed in the opening 150A_5 in order, thereby forming the structure described with reference to Figure 35.

[0145] [effect] In a semiconductor memory device having layers aligned in the Z direction, where each layer comprises multiple semiconductor layers and multiple conductive layers, if the semiconductor layers aligned in the Z direction each function as a channel region of a transistor, inter-channel interference in the Z direction may cause the transistor threshold voltage to rise.

[0146] In this embodiment, in the selection transistor SG (Figure 35) with conductive layer 150 as the gate electrode, and the local block selection transistors SWX1 and SWY1 with conductive layers 350 and 450 as the gate electrodes, a portion of the insulating layer 101 provided between the memory layers ML is removed and recessed. With this structure, the portion of the semiconductor layer 110_5 that functions as the channel region is covered from the Z direction by the conductive layers 150, 350, and 450, and is electrically shielded on both sides in the Z direction.

[0147] With this configuration, it is possible to suppress inter-channel interference in the Z direction in the selection transistor SG and local block selection transistors SWX1 and SWY1, prevent an increase in the threshold voltage of the transistors, and improve the operating current.

[0148] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0149] CC... Contact electrode, LBIX... Local block connection line, LBIY... Local block connection line, MS... Memory string, R BLK ...memory block area, R HU ...hookup area, R LBIY ...connection line region, SWX1...local block selection transistor, SWY1...local block selection transistor.

Claims

1. Multiple memory block regions aligned in the first direction, A hookup region aligned in the first direction with respect to the plurality of memory block regions, A wiring region extending in the first direction and in a second direction intersecting the first direction, adjacent to the plurality of memory block regions. Equipped with, The aforementioned multiple memory block regions are, each, A plurality of memory strings extending in the first direction and aligned in the second direction, A first wiring extending in the second direction and commonly connected to the plurality of memory strings and Equipped with, The wiring region extends in the first direction and includes a second wiring that is commonly connected to a plurality of first wirings corresponding to a plurality of memory block regions. The hook-up region extends in a third direction intersecting the first and second directions and is equipped with a contact electrode electrically connected to the second wiring. A first transistor is provided in the current path between the first wiring and the second wiring. Semiconductor memory device.

2. The memory comprises a plurality of memory layers arranged in the third direction, Each of the plurality of memory layers comprises the plurality of memory strings, the first wiring, the second wiring, and the first transistor. The hookup region comprises multiple contact electrodes corresponding to the multiple memory layers. The semiconductor memory device according to claim 1.

3. A second transistor is provided in the current path between the second wiring and the contact electrode. The semiconductor memory device according to claim 1.

4. A third transistor is provided in parallel with the first transistor in the current path between the first wiring and the second wiring. The first transistor is an N-type transistor, The third transistor is a P-type transistor. The semiconductor memory device according to claim 1.

5. A fourth transistor is provided in parallel with the second transistor in the current path between the second wiring and the contact electrode. The second transistor is an N-type transistor, The fourth transistor is a P-type transistor. The semiconductor memory device according to claim 3.

6. The gate electrode of the first transistor is It includes a plurality of first electrodes extending in the third direction, The plurality of first electrodes are aligned in the first direction. The semiconductor memory device according to claim 1.

7. The aforementioned plurality of memory strings are, A plurality of memory cells arranged in the first direction, A plurality of memory gates arranged in the first direction correspond to a plurality of memory cells arranged in the first direction and Equipped with, The pitch at which the plurality of first electrodes are arranged is equivalent to the pitch at which the plurality of memory gate electrodes are arranged. The semiconductor memory device according to claim 6.

8. Multiple memory block regions aligned in the first direction, A wiring region extending in the first direction and in a second direction intersecting the first direction, adjacent to the plurality of memory block regions. Each includes a first memory layer and a second memory layer arranged in a third direction intersecting the first and second directions, An interlayer insulating layer provided between the first memory layer and the second memory layer and Equipped with, The aforementioned multiple memory block regions are, each, A plurality of semiconductor portions extending in the first direction and aligned in the second direction, A first wiring extending in the second direction and commonly connected to the plurality of semiconductor parts Equipped with, The wiring region extends in the first direction and includes a second wiring that is commonly connected to a plurality of first wirings corresponding to a plurality of memory block regions. A plurality of memory gate electrodes are arranged in the first direction and extend in the third direction, and are facing the first semiconductor layer and the interlayer insulating layer, which are one of the plurality of semiconductor parts. A selective gate electrode is provided between the plurality of memory gate electrodes and the first wiring, extending in the third direction and facing the first semiconductor layer and the interlayer insulating layer. A system was established, At least a portion of the side surface of the first semiconductor layer facing the selected gate electrode is From the side of the interlayer insulating layer facing the selected gate electrode, provided on the side of the selected gate electrode Semiconductor memory device.

9. A gate insulating layer is provided between the first semiconductor layer and the selected gate electrode. The gate insulating layer is A first portion covering at least a portion of the side surface in the second direction of the first semiconductor layer, A second portion that covers at least a portion of the side surface in the third direction of the first semiconductor layer and Equipped with, The semiconductor memory device according to claim 8.

10. The first memory layer and the second memory layer are, respectively, The current path between the first wiring and the second wiring includes a first transistor. The semiconductor memory device according to claim 8.

11. The first transistor comprises a second semiconductor layer, A first electrode is provided that extends in the third direction and faces the second semiconductor layer and the interlayer insulating layer, The side surface of the second semiconductor layer facing the first electrode is, From the side surface of the interlayer insulating layer facing the first electrode, provided on the side facing the first electrode. The semiconductor memory device according to claim 10.

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