Indication device

Abstract

To improve display quality of a display device.SOLUTION: A display device comprises: a transistor having an oxide semiconductor layer, a gate electrode opposed to the oxide semiconductor layer, and a gate insulating film provided between the oxide semiconductor layer and the gate electrode, on a first substrate; a drain electrode connected to the transistor; a pixel electrode connected to the drain electrode; and a first insulating film and a second insulating film provided between the drain electrode and the pixel electrode. The drain electrode extends in a first direction, the first insulating film includes a first contact hole and a second contact hole, which are provided along the first direction in a region overlapping the drain electrode, and the second insulating film includes a third contact hole and a fourth contact hole, which are provided along the first direction in the region overlapping the drain electrode.SELECTED DRAWING: Figure 7

Description

[Technical Field] 【0001】 One embodiment of the present invention relates to a display device. [Background technology] 【0002】 In recent years, progress has been made in the development of transparent displays that allow the background of the opposite side to be seen from one side (see Patent Document 1). With a transparent display, images can be viewed from both the front and back sides, so images or text can be seen from two opposing directions with the transparent display in between. [Prior art documents] [Patent Documents] 【0003】 [Patent Document 1] Japanese Patent Publication No. 2020-160254 [Overview of the project] [Problems that the invention aims to solve] 【0004】 In display devices such as transparent displays, pixel electrodes are connected to drain electrodes via contact holes provided in the insulating film. If mask misalignment occurs when forming the contact holes, variations in the contact resistance between the pixel electrode and the drain electrode occur for each pixel, resulting in a decrease in the display quality of the display device. 【0005】 One of the objectives of this embodiment is to improve the display quality of a display device. [Means for solving the problem] 【0006】 A display device according to one embodiment of the present invention has a transistor having an oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer, and a gate insulating film provided between the oxide semiconductor layer and the gate electrode, a drain electrode connected to the transistor, a pixel electrode connected to the drain electrode, and a first insulating film and a second insulating film provided between the drain electrode and the pixel electrode, wherein the drain electrode extends in a first direction, a first contact hole and a second contact hole are provided in the first insulating film in a region overlapping with the drain electrode along the first direction, and a third contact hole and a fourth contact hole are provided in the second insulating film in a region overlapping with the drain electrode along the first direction, and when viewed from above, the axis of symmetry of the third contact hole in the first direction is shifted in a second direction intersecting the first direction with respect to the axis of symmetry of the first contact hole in the first direction, and the axis of symmetry of the fourth contact hole in the first direction is shifted in a third direction opposite to the second direction with respect to the axis of symmetry of the second contact hole in the first direction. [Brief explanation of the drawing] 【0007】 [Figure 1] This is a perspective view illustrating the overview of a display device according to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view showing the structure corresponding to the area between A1 and A2 of the display device shown in Figure 1. [Figure 3] This is a plan view illustrating the configuration of a display device according to one embodiment of the present invention. [Figure 4] This is a circuit diagram representing pixels in a display device according to one embodiment of the present invention. [Figure 5] This is a timing chart of pixels in a display device according to one embodiment of the present invention. [Figure 6] This is a planar layout of pixels in a display device according to one embodiment of the present invention. [Figure 7] This is an enlarged view of the planar layout of pixels in a display device according to one embodiment of the present invention. [Figure 8]It is a cross-sectional view of a pixel in a display device according to an embodiment of the present invention. [Figure 9] It is an enlarged view further enlarging the planar layout of the pixel shown in FIG. 7. [Figure 10] It is a view when the pixel shown in FIG. 7 is cut along the C1-C2 line. [Figure 11] It is a view when the pixel shown in FIG. 7 is cut along the E1-E2 line. [Figure 12] It is a planar layout of a pixel in a display device according to an embodiment of the present invention. [Figure 13] It is a planar layout of a pixel in a display device according to an embodiment of the present invention. [Figure 14] It is a planar layout of a pixel in a display device according to an embodiment of the present invention. [Figure 15] It is a planar layout of a pixel in a display device according to an embodiment of the present invention. [Figure 16] It is a planar layout of a pixel in a display device according to an embodiment of the present invention. [Figure 17] It is a planar layout of a pixel in a display device according to an embodiment of the present invention. 【Mode for Carrying Out the Invention】 【0008】 Hereinafter, each embodiment of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in various modes without departing from the gist thereof, and is not to be construed as being limited to the description of the embodiments illustrated below. Also, regarding the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part may be schematically represented compared to the actual mode, but such schematic diagrams are only examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each figure, elements that are the same as or similar to those described with respect to the already shown figures may be denoted by the same reference numerals, and duplicate descriptions may be omitted. Note that in this specification and the like, ordinal numbers are for convenience in distinguishing parts and sites, etc., and do not indicate priority or order. 【0009】 In this invention, when multiple films are formed by processing a single film, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer. Furthermore, when multiple films are formed by processing a single film, they may be described separately as -1, -2, etc. in this specification. 【0010】 In this specification, expressions such as "above" and "below" describe the relative positional relationship between the structure of interest and other structures. In this specification, in a side view, the direction from the first substrate (described later) toward the pixel electrode is defined as "above," and the opposite direction is defined as "below." In this specification and the claims, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the expression "above" includes both cases: when one structure is placed directly above another structure so as to be in contact with it, and when another structure is placed above another structure via yet another structure. 【0011】 Furthermore, in this specification, bottom gate drive refers to a system where the on / off state is controlled by a gate electrode located below the semiconductor layer. Furthermore, in this specification, top gate drive refers to a system where the on / off state is controlled by a gate electrode located above the semiconductor layer. Furthermore, in this specification, dual gate drive refers to a system where the on / off state is controlled by inputting the same control signal to gate electrodes located above and below the semiconductor layer. 【0012】 (First Embodiment) A display device 10 according to one embodiment of the present invention will be described with reference to Figures 1 to 17. 【0013】 <Overview of the display device> Figure 1 shows a perspective view of a display device 10 according to one embodiment of the present invention. The display device 10 includes a display panel 102 which includes an array substrate 150 (also called a first substrate), a counter substrate 152 (also called a second substrate), a liquid crystal layer (not shown) between the array substrate 150 and the counter substrate 152, a gate drive circuit 28, a source drive circuit 38, a light source 104, and a first transparent substrate 151A and a second transparent substrate 151B which sandwich the display panel 102. In the following description with reference to Figure 1, one direction of the plane in the display panel 102 is referred to as the D1 direction, the direction perpendicular to the D1 direction is referred to as the D2 direction, and the direction perpendicular to the D1-D2 plane is referred to as the D3 direction. 【0014】 The array substrate 150 and the opposing substrate 152 are light-transmitting. Preferably, the array substrate 150 and the opposing substrate 152 are transparent to visible light. The opposing substrate 152 is positioned in the D3 direction so as to face the array substrate 150. The array substrate 150 and the opposing substrate 152 are bonded together by a sealing material 154 while facing each other with a gap between them. A liquid crystal layer (not shown) is provided in the gap between the array substrate 150 and the opposing substrate 152. 【0015】 The display panel 102 has a display area 12 and a peripheral area 14 outside the display area 12. Multiple pixels PIX are arranged in the row direction and column direction in the display area 12. Here, the row direction refers to the direction parallel to the D1 direction, and the column direction refers to the direction parallel to the D2 direction. In the display area 12, m pixels are arranged in the row direction and n pixels are arranged in the column direction. The values ​​of m and n are set appropriately according to the vertical display resolution and the horizontal display resolution. Gate wiring (also called scan signal lines) is arranged in the D1 direction in the display area 12, and source wiring (also called data signal lines) is arranged in the D2 direction. 【0016】 A gate drive circuit 28 and a source drive circuit 38 are provided in the peripheral region 14 of the array substrate 150. Figure 1 shows an embodiment in which the gate drive circuit 28 and the source drive circuit 38 are provided as integrated circuits (ICs) and mounted on the array substrate 150 using the COG (Chip on Glass) method. The gate drive circuit 28 and the source drive circuit 38 are not limited to the embodiment shown, and may be mounted using the COF (Chip on Film) method, or may be formed by thin-film transistors (TFTs) on the array substrate 150. 【0017】 The peripheral region 14 includes a gate wiring region 32, a common wiring region 22, and a source wiring region 42. The gate wiring region 32 is a region where a pattern is formed by wiring connecting the gate drive circuit 28 and the gate wiring GL arranged in the display region 12. The common wiring region 22 is a region where a pattern is formed by common wiring. Circuit-wise, the common wiring region 22 is used as wiring to apply a common voltage to the common electrode 218 (see Figure 8) provided on the opposing substrate 152. The source wiring region 42 is a region where a pattern is formed by wiring connecting the source drive circuit 38 and the data signal lines arranged in the display region 12. 【0018】 The light source 104 has a structure aligned along the D1 direction. The light source 104 is composed of, for example, light-emitting diodes (LEDs) arranged along the D1 direction. The detailed structure of the light source 104 is not limited, and in addition to light-emitting diodes arranged along the D1 direction, optical components such as reflectors, diffusers, and lenses may be included. The light source 104 and the light emission control circuit 110 that controls the light source 104 may be provided as separate components independent of the display panel 102. Furthermore, the timing of light emission of the light source 104 may be controlled by the light emission control circuit 110 which is synchronized with the gate drive circuit 28 and the source drive circuit 38. The light emission control circuit 110 that controls the light source 104 may be provided as a separate component, like the light source 104, separate from the display panel 102, or it may be mounted on the array substrate 150 as an individual component, or it may be incorporated into the gate drive circuit 28 or the source drive circuit 38. 【0019】 The first transparent substrate 151A and the second transparent substrate 151B are provided so as to sandwich the display area 12 and the peripheral area 14. The first transparent substrate 151A and the second transparent substrate 151B function as protective members for the display panel 102. Furthermore, as will be explained with reference to Figure 2, the first transparent substrate 151A and the second transparent substrate 151B also function as light guide plates that introduce light emitted from the light source 104 into the display panel 102. 【0020】 Figure 2 shows the cross-sectional structure of the display device 10 corresponding to the area between A1 and A2 shown in Figure 1. As shown in Figure 2, a first transparent substrate 151A is provided on the array substrate 150 side of the display panel 102, and a second transparent substrate 151B is provided on the opposing substrate 152 side. The first transparent substrate 151A and the second transparent substrate 151B are made of glass or plastic. Preferably, the first transparent substrate 151A and the second transparent substrate 151B have the same refractive index as the array substrate 150 and the opposing substrate 152. The array substrate 150 and the first transparent substrate 151A, and the opposing substrate 152 and the second transparent substrate 151B are bonded together with a transparent adhesive (not shown). 【0021】 The display panel 102 is arranged with an array substrate 150 and a counter substrate 152 facing each other, with a liquid crystal layer 210 provided between them. The array substrate 150 is larger than the counter substrate 152, and is sized such that a portion of the peripheral region 14 is exposed from the counter substrate 152. A drive circuit (source drive circuit 38 in Figure 2) is mounted on the array substrate 150. A flexible printed circuit 34 is also attached to the peripheral edge of the array substrate 150. 【0022】 The light source 104 is positioned adjacent to one side of either the first transparent substrate 151A or the second transparent substrate 151B. Figure 2 shows a configuration in which the light source 104 is positioned along one side of the second transparent substrate 151B. Figure 2 also shows a configuration in which the light source 104 is mounted on the array substrate 150, but there are no limitations on the configuration in which the light source 104 is positioned, and there are no limitations on the mounting structure as long as the mounting position can be fixed. The light source 104 may be supported, for example, by a housing surrounding the display panel 102. 【0023】 As shown in Figure 2, the light source 104 is positioned along the first side surface 15C of the second transparent substrate 151B. As shown in Figure 2, the light source 104 irradiates light L onto the first side surface 15C of the second transparent substrate 151B. The light source 104 is sometimes called a side light source because it emits light L toward the first side surface 15C. The first side surface 15C of the second transparent substrate 151B facing the light source 104 becomes the light incident surface. 【0024】 As schematically shown in Figure 2, light L incident on the first side surface 15C of the second transparent substrate 151B propagates in the direction away from the first side surface 15C (direction D2) while being reflected by the second plane 15B of the second transparent substrate 151B and the first plane 15A of the first transparent substrate 151A. When light L moves outward from the first plane 15A of the first transparent substrate 151A and the second plane 15B of the second transparent substrate 151B, it moves from a medium with a high refractive index to a medium with a low refractive index. At this time, if the angle of incidence of light L incident on the first plane 15A and the second plane 15B is greater than the critical angle, total internal reflection occurs, and the light is guided in the direction D2 while being reflected by the first plane 15A and the second plane 15B. 【0025】 The liquid crystal layer 210 is formed of polymer-dispersed liquid crystal. The liquid crystal layer 210, formed of polymer-dispersed liquid crystal, is controlled to alternate between scattering and non-scattering states for each pixel PIX (see Figure 1). As shown in Figure 2, when light L propagates while reflecting off the first plane 15A and the second plane 15B, if there is a pixel in the liquid crystal layer 210 that is in a scattering state, at least some of the light is scattered, and the incident angle of the scattered light becomes smaller than the critical angle, causing the scattered light LA ​​and LB to be emitted to the outside from the first plane 15A and the second plane 15B, respectively, and the emitted scattered light LA ​​and LB are observed by the observer. In the display panel 102, the areas other than those from which the scattered light LA ​​and LB are emitted are substantially transparent because the array substrate 150 and the opposing substrate 152, as well as the first transparent substrate 151A and the second transparent substrate 151B, are light-transmitting (transparent to visible light), and the liquid crystal layer 210 is in a non-scattering state, allowing the observer to see the back side through the display panel 102. 【0026】 Figure 3 is a plan view illustrating the configuration of the array substrate 150 of a display device 10 according to one embodiment of the present invention. As shown in Figure 3, the array substrate 150 includes a display area 12 and a peripheral area 14. 【0027】 The display area 12 has multiple pixels PIX arranged in a matrix. Each of the multiple pixels PIX has multiple transistors and liquid crystal elements. 【0028】 The peripheral region 14 is provided so as to surround the display region 12. The peripheral region 14 refers to the area on the array substrate 150 from the display region 12 to the edge of the array substrate 150. In other words, the peripheral region 14 refers to the area on the array substrate 150 other than the area on which the display region 12 is provided (i.e., the area outside the display region 12). 【0029】 In addition to the gate drive circuit 28 and source drive circuit 38, the peripheral region 14 is provided with a gate wiring region 32, a source wiring region 42, common wiring 16 and 18, terminal sections 26 and 36, flexible printed circuits 24 and 34, and various test circuits. The terminal sections 26 and 36 are arranged along one side of the array substrate 150. 【0030】 A flexible printed circuit board 24 is connected to the terminal section 26. The flexible printed circuit board 24 supplies various signals to the gate drive circuit 28, common wiring 16, 18, ESD protection circuit 59, and QD pad 56. The gate drive circuit 28 is connected to multiple gate wiring GLs, and each of the multiple gate wiring GLs is electrically connected to each of the multiple pixels PIX in the display area 12. In Figure 3, the area where multiple gate wiring GLs are provided is represented as the gate wiring area 32, and the detailed arrangement of the multiple gate wiring GLs is not shown. The number of gate wiring GLs connected to the two gate drive circuits 28 corresponds to the number of rows of pixels PIX in the display area 12. In Figure 3, the gate wiring area 32 is shown to be spaced apart from the display area 12, but in reality, the gate wiring GLs and pixels PIX are electrically connected. 【0031】 A flexible printed circuit 34 is connected to the terminal section 36. The flexible printed circuit 34 supplies a video signal to the source drive circuit 38. The source drive circuit 38 is connected to a plurality of source wirings SL, and each of the plurality of source wirings SL is electrically connected to each of the plurality of pixels PIX in the display area 12. In Figure 3, the area where the plurality of source wirings SL are provided is represented as the source wiring area 42, and the detailed arrangement of the plurality of source wirings SL is not shown. The number of source wirings SL connected to the eight source drive circuits 38 corresponds to at least three times the number of rows of pixels PIX in the display area 12. In this embodiment, the case where the number of source wirings SL is four times the number of rows of pixels PIX in the display area 12 will be described. Note that in Figure 3, the source wiring area 42 is shown to be provided separately from the display area 12, but in reality, the source wirings SL and pixels PIX are electrically connected. 【0032】 Between the gate wiring area 32 and the display area 12, a common wiring 18, an ESD protection circuit 46, a gate inspection circuit 48, and an inspection line 54 are provided. Between the source wiring area 42 and the display area 12, a common wiring 18, an ESD protection circuit 46, a source inspection circuit 52, and an inspection line 54 are provided. The inspection line 54 is connected to the ESD protection circuit 58 and the QD pad 56. The common wiring 18 is also connected to the ESD protection circuit 59. 【0033】 The common wiring 16 is provided so as to surround the peripheral region 14 on the array substrate 150, and signals are supplied from the two flexible printed circuits 24. The common wiring 16 is also electrically connected to the mesh-like common wiring region 22. 【0034】 The display device 10 is not limited to high-speed drive panels such as the transparent displays shown in Figures 1 and 2. The display device 10 can be applied to large panels used in non-transparent display devices. 【0035】 <Pixel Circuit> Figure 4 is a diagram illustrating the pixel circuit of a pixel PIX in a display device 10 according to one embodiment of the present invention. In this embodiment, a display device 10 is described that can simultaneously supply an ON voltage to four gate wirings GL and simultaneously charge four pixel PIX arranged in the column direction by four source wirings SL. This makes it possible to make one horizontal period longer than the horizontal period of line sequential charging. In other words, the time required to scan all pixel lines arranged in the display area 12 can be reduced to one-quarter. Therefore, a sufficient charging period for the pixel PIX can be ensured in high-speed drive panels such as transparent displays and in large panels. The configuration of the pixel PIX in this embodiment will be described in detail below. 【0036】 In Figure 4, four pixels PIX1 to PIX4 are arranged in the column direction (D2 direction). Each of the four pixels PIX1 to PIX4 is electrically connected to each of the four gate wirings GL1 to GL4. Each of the four pixels PIX1 to PIX4 is also electrically connected to each of the four source wirings SL1 to SL4. Each of the four pixels PIX1 to PIX4 is connected to the capacitive wiring CW. In the following explanation, when pixels PIX1 to PIX4 are not distinguished, they will be referred to as pixel PIX. Similarly, when gate wirings GL1 to GL4 and source wirings SL1 to SL4 are not distinguished, they will be referred to as gate wiring GL and source wiring SL. 【0037】 Each pixel PIX comprises a transistor Tr, a liquid crystal element LE, and a retaining capacitor C. The gate of transistor Tr is connected to the gate wiring GL, the source of transistor Tr is connected to the source wiring SL, and the drain of transistor Tr is connected to one electrode of the liquid crystal element LE and one electrode of the retaining capacitor C. The other electrode of the liquid crystal element LE is connected to the common electrode 218 (Figure 8). The other electrode of the retaining capacitor C is connected to the capacitance wiring CW. 【0038】 The transistor Tr has the function of controlling the writing time of the video signal supplied from the source wiring SL to the pixels PIX by switching between an on state and an off state. By turning the transistor Tr on, the potential corresponding to the video signal supplied from the source wiring SL can be written to the retaining capacitor C electrically connected to the transistor Tr. Conversely, by turning the transistor Tr off, the potential held in the retaining capacitor C can be retained. 【0039】 Figure 5 is a timing chart of a display device 10 according to one embodiment of the present invention. Normally, gate wiring GL is supplied with an ON voltage one row at a time, sequentially charging the pixel rows aligned in the D2 direction with the same source wiring SL. In contrast, in this embodiment, an ON voltage is supplied to four gate wirings GL simultaneously, causing each of the transistors Tr of the four pixels PIX to be turned ON at the same time. In this state, video signals are supplied simultaneously to different source wirings SL1 to SL4. This makes it possible to drive four pixels aligned in the D2 direction simultaneously. 【0040】 <Pixel Planar Layout> Referring to Figure 6, the planar layout of pixels PIX in a display device 10 according to one embodiment of the present invention will be described. Figure 6 shows the configuration of PIX-A1, PIX-A2, PIX-B1, and PIX-B2 in a planar view. 【0041】 As shown in Figure 6, gate wirings GLn-1 to GLn+1 are arranged along the D1 direction. Source wirings SL1 to SL4 are arranged along the D2 direction. Here, the aperture region of pixel PIX-B1 is the area enclosed by the adjacent gate wirings GLn-1, GLn, source wiring SL1, and source wiring S4. 【0042】 As shown in Figure 6, source wiring SL1 and SL3, and source wiring SL2 and SL4 are provided so as to sandwich a row of pixels PIX-B1 and PIX-B2. In other words, four source wirings SL1 to SL4 are arranged between a row of pixels PIX-A1 and PIX-A2 and a row of pixels PIX-B1 and PIX-B2. 【0043】 A transistor Tr is provided in region 250 where the gate wiring GL and source wirings SL1 to SL4 intersect. Furthermore, the transistor Tr is connected to a pixel electrode in region 230. The pixel electrode is provided in the aperture region of pixel PIX-B1. 【0044】 In display devices such as transparent displays, pixel electrodes are connected to drain electrodes via contact holes provided in the insulating film. If mask misalignment occurs when forming the contact holes, variations in the contact resistance between the pixel electrode and the drain electrode occur for each pixel, resulting in a decrease in the display quality of the display device. 【0045】 Therefore, in the display device 10 according to one embodiment of the present invention, even if mask misalignment occurs when forming contact holes, the variation in the magnitude of contact resistance between the pixel electrode and the drain electrode for each pixel is suppressed. 【0046】 Figure 7 is an enlarged view of the region 230 in pixel PIX-B1 where the transistor Tr is located. Figure 7 illustrates the arrangement of each layer when viewed from above. Figure 8 is a cross-sectional view of the region 230 shown in Figure 7 along the line B1-B2. Figure 8 illustrates the stacking order of each layer when viewed in cross-section. 【0047】 As shown in Figure 7, conductive layers 202-1 and 206-3 and 206-4 extend along the D2 direction. Conductive layer 202-1 functions as a gate trace GL (gate electrode). Conductive layer 206-3 functions as a drain electrode, and conductive layer 206-4 functions as a source trace SL (source electrode). An oxide semiconductor layer 204-1 is provided so as to overlap with conductive layer 202-1. Conductive layer 208-1 is also provided so as to overlap with conductive layer 202-1 and oxide semiconductor layer 204-1. Conductive layer 208-1 functions as a back gate. In this embodiment, transistor Tr is described as a bottom-gate driven transistor, but is not limited to this; it may be a top-gate driven transistor or a dual-gate driven transistor. Conductive layer 206-4 is connected to conductive layer 202-2, which is provided in the same layer as conductive layer 202-1, via a contact hole 213-3. 【0048】 Contact holes 215-1 and 215-2 are provided in the region overlapping with conductive layer 206-3. Additionally, contact holes 217-1 and 217-2 are provided in the region overlapping with conductive layer 206-3. Contact holes 215-1, 215-2, 217-1, and 217-2 will be described in detail later. 【0049】 Furthermore, a planarization film 207 and a transparent conductive layer 212 are provided so as to cover the source wiring SL and the transistor Tr. When the display device 10 is applied to a transparent display, it is preferable that the planarization film 207 is removed in the aperture region of the pixel PIX. This makes it possible to suppress light absorption by the planarization film 207 in the aperture region. In addition, a conductive layer 214 is provided so as to cover the transistor Tr. The transparent conductive layer 212 and the conductive layer 214 function as capacitive wiring. The conductive layer 214 also functions as a light-shielding layer. The pixel electrode 216-1 functions as a pixel electrode and is provided in the aperture region. The pixel electrode 216-1 does not cover the source wiring SL and the transistor Tr, but covers a part of the conductive layer 206-3. 【0050】 As shown in Figure 8, a transistor Tr is provided on the array substrate 150. The transistor Tr has a conductive layer 202-1 provided on the array substrate 150, an oxide semiconductor layer 204-1 provided opposite to the conductive layer 202-1, and a gate insulating film 203 provided between the conductive layer 202-1 and the oxide semiconductor layer 204-1. The oxide semiconductor layer 204-1 is connected to conductive layers 206-3 and 206-4. 【0051】 An insulating film 205 (also called the first insulating film) is provided on the conductive layers 206-3 and 206-4. The insulating film 205 functions as a passivation film. The insulating film 205 has, for example, a laminated structure of an oxide insulating film 205a and a nitride insulating film 205b. The gate insulating film 203 also has a laminated structure of a nitride insulating film 203a and an oxide insulating film 203b. By sandwiching the oxide semiconductor layer 204-1 between the oxide insulating film 205a and the oxide insulating film 203b, oxygen is released from the oxide insulating film 203b and the oxide insulating film 205a during the process. This is preferable because it can repair oxygen vacancies in the oxide semiconductor layer 204-1. Furthermore, a conductive layer 208-1 is provided on the insulating film 205 at a position facing the oxide semiconductor layer 204-1. 【0052】 A planarization film 207 is provided on the conductive layer 208-1 and the insulating film 205. The planarization film 207 is provided to alleviate the irregularities of the various wirings that constitute the transistor Tr. In Figure 8, the planarization film 207 is provided in the region that overlaps with the conductive layer 206-4 and the transistor Tr. Furthermore, since the planarization film 207 is removed in the aperture region, the planarization film 207 is not provided between the conductive layer 206-3 and the pixel electrode 216-1. In other words, the insulating film 205 and the insulating film 209 (also called the second insulating film) are in contact with each other between the conductive layer 206-3 and the pixel electrode 216-1. 【0053】 A transparent conductive layer 212 is provided on the planarized film 207. A conductive layer 214 is provided on the transparent conductive layer 212. The transparent conductive layer 212 and the conductive layer 214 function as capacitive wiring CW. The conductive layer 214 also functions as a light-shielding layer. An insulating film 209 is provided on the transparent conductive layer 212 and the conductive layer 214. A pixel electrode 216-1 is provided on the insulating film 209. The pixel electrode 216-1 is connected to the conductive layer 206-3 via contact holes 215-1, 215-2, and contact holes 217-1, 217-2 provided in the insulating films 205 and 209. 【0054】 As shown in Figures 7 and 8, on the planarization film 207 overlapping the transistor Tr, the edge of the transparent conductive layer 212 is positioned between the edge of the conductive layer 214 and the pixel electrode 216-1. This arrangement shields the transistor Tr from light while improving the light transmittance in the aperture region. 【0055】 A counter substrate 152 is provided opposite the array substrate 150. The counter substrate 152 is provided with a light-shielding layer 219 and a common electrode 218. The light-shielding layer 219 functions as a black matrix. In the structure shown in Figure 8, the light-shielding layer 219 is provided in the region that overlaps with the conductive layer 206-4. The light-shielding layer 219 is arranged in a grid pattern so as to cover the gate wiring GL and source wiring SL1 to source wiring SL4. The common electrode 218 is large enough to cover the entire surface of the display area 112. The light-shielding layer 219 may be made of a metal film and functions as an auxiliary electrode by being provided in contact with the common electrode 218 which is made of a transparent conductive film. A liquid crystal layer 210 is provided between the array substrate 150 and the counter substrate 152 and is sealed with a sealing material 154 (see Figure 1). The pixel electrode 216-1, the liquid crystal layer 210, and the common electrode 218 constitute the liquid crystal element LE. 【0056】 Figure 9 illustrates the positional relationship between contact holes 215-1 and 215-2 formed in the insulating film 205 provided on the conductive layer 206-3, and contact holes 217-1 and 217-2 formed in the insulating film 209. 【0057】 As shown in Figure 9, the conductive layer 206-3 extends in the D2 direction (also called the first direction). Contact holes 215-1 and 215-2 are provided in the insulating film 205 in the region overlapping with the conductive layer 206-3. In addition, contact holes 217-1 and 217-2 are provided in the insulating film 209 in the region overlapping with the conductive layer 206-3. 【0058】 The area of ​​contact hole 215-1 is expressed as length L1 in the D1 direction × length L2 in the D2 direction. The area of ​​contact hole 217-1 is expressed as length L3 in the D1 direction × length L4 in the D2 direction. Here, the axis of symmetry of contact hole 215-1 in the D2 direction is represented by SA1, and the axis of symmetry of contact hole 217-1 in the D2 direction is represented by SA2. 【0059】 The area of ​​contact hole 215-2 is represented by the length L1 in the D1 direction × the length L2 in the D2 direction. The area of ​​contact hole 217-2 is represented by the length L3 in the D1 direction × the length L4 in the D2 direction. Here, the axis of symmetry of contact hole 215-2 in the D2 direction is represented by SA3, and the axis of symmetry of contact hole 217-2 in the D2 direction is represented by SA4. Also, the axis of symmetry of contact hole 215-1 in the D1 direction is represented by SA5. Also, the axis of symmetry of contact hole 217-1 in the D1 direction is represented by SA7. The axis of symmetry of contact hole 215-2 in the D1 direction is represented by SA6. The axis of symmetry of contact hole 217-2 in the D1 direction is represented by SA8. In Figure 9, the axis of symmetry SA5 and the axis of symmetry SA7 overlap (contend), and the axis of symmetry SA6 and the axis of symmetry SA8 overlap. 【0060】 The axis of symmetry SA2 in the D2 direction of contact hole 217-1 is offset in the -D1 direction (also called the second direction) relative to the axis of symmetry SA1 in the D2 direction of contact hole 215-1, on the opposite side of the D1 direction. Similarly, the axis of symmetry SA4 in the D2 direction of contact hole 217-2 is offset in the D1 direction (also called the third direction) relative to the axis of symmetry SA3 in the D2 direction of contact hole 215-2. 【0061】 In the insulating film 205, in the region overlapping with the conductive layer 206-3, contact holes 215-2 are aligned with contact holes 215-1 along the D2 direction. Also, in the insulating film 209, in the region overlapping with the conductive layer 206-3, contact holes 217-2 are aligned with contact holes 217-1 along the D2 direction. 【0062】 In this embodiment, the case where length L1 is the same as length L3 is described, but length L1 and length L3 may be different lengths. Also, in this embodiment, the case where length L2 is longer than length L4 is described, but length L4 may be longer than length L2. Furthermore, length L2 may be the same length as length L4. 【0063】 In Figure 9, the area of ​​contact hole 215-1 is larger than the area of ​​contact hole 217-1, and the area of ​​contact hole 215-2 is larger than the area of ​​contact hole 217-2. Also, the area of ​​contact hole 215-1 is approximately the same as the area of ​​contact hole 215-2, and the area of ​​contact hole 217-1 is approximately the same as the area of ​​contact hole 217-2. 【0064】 Figure 9 shows an example where the symmetry axis SA3 of contact hole 215-2 is shifted in the -D1 direction relative to the symmetry axis SA1 of contact hole 215-1, but the symmetry axes SA1 and SA3 may coincide. Similarly, Figure 9 shows an example where the symmetry axis SA4 of contact hole 217-2 is shifted in the D1 direction relative to the symmetry axis SA2 of contact hole 217-1, but the symmetry axes SA2 and SA4 may coincide. The amount of shift between symmetry axes SA1 and SA2, and between symmetry axes SA3 and SA4, can be appropriately set with respect to the length of the conductive layer 206-3 in the D1 direction. 【0065】 In Figure 9, the axis of symmetry SA2 of contact hole 217-1 is shifted in the -D1 direction by 50% of the length L1 in the D1 direction of contact hole 215-1 relative to the axis of symmetry SA1 of contact hole 215-1. At the same time, the axis of symmetry SA4 of contact hole 217-2 is shifted in the D1 direction by 50% of the length L1 in the D1 direction of contact hole 217-2 relative to the axis of symmetry SA3 of contact hole 215-2. 【0066】 In Figure 9, the area S1 of the region where the pixel electrode 216-1 contacts the conductive layer 206-3 via contact holes 215-1 and 217-1 (also called the first region) is approximately the same as the area S2 of the region where the pixel electrode 216-1 contacts the conductive layer 206-3 via contact holes 215-2 and 217-2 (also called the second region). The sum of areas S1 and S2, totaling area S3, corresponds to the area in contact between the conductive layer 206-3 and the pixel electrode 216. If there is no displacement in the position of the mask for forming the contact holes, the sum of areas S1 and S2, totaling area S3, will be approximately the same for each of the multiple pixels PIX. 【0067】 Figure 10 is a cross-sectional view obtained by cutting along the C1-C2 line through the contact holes 215-2 and 217-2 shown in Figure 7. As shown in Figure 10, a gate insulating film 203 (nitride insulating film 203a and oxide insulating film 203b) is provided on the array substrate 150, and a conductive layer 206-3 that functions as a drain electrode is provided on the gate insulating film 203. An insulating film 205 (oxide insulating film 205a and nitride insulating film 205b) is provided on the conductive layer 206-3. A contact hole 215-2 is provided in the insulating film 205. An insulating film 209 is provided on the insulating film 205. A contact hole 217-2 is provided in the insulating film 209. A pixel electrode 216 is provided on the insulating film 209. The pixel electrode 216 is connected to the conductive layer 206-3 via the contact hole 217-2 provided in the insulating film 209 and the contact hole 215-2 provided in the insulating film 205. As shown in Figure 10, the insulating film 209 is provided in contact with the upper surface of the conductive layer 206-3. The pixel electrode 216 is provided in contact with the upper surface of the insulating film 205. 【0068】 Figure 11 is a cross-sectional view of contact holes 215-2 and 217-2 shown in Figure 7, cut along the E1-E2 line. As shown in Figure 11, the conductive layer 206-3 is in contact with the pixel electrode 216 at two locations. The length L2 of contact holes 215-1 and 215-2 is longer than the length L4 of contact holes 217-1 and 217-2. Also, the axis of symmetry in the D1 direction of each contact hole 215-1 and 215-2 coincides with the axis of symmetry in the D1 direction of each contact hole 217-1 and 217-2. Therefore, the ends of contact holes 217-1 and 217-2 are located inside each of contact holes 215-1 and 215-2. In other words, the top and side surfaces of contact holes 215-1 and 215-2 are covered by the insulating film 209. In the region where contact hole 215-1 is provided and the region where contact hole 215-2 is provided, the insulating film 209 is in contact with the conductive layer 206-3 (drain electrode). 【0069】 Figure 12 shows that, compared to Figure 9, the positions of contact holes 217-1 and 217-2 are further shifted in the D1 direction relative to the positions of contact holes 215-1 and 215-2. 【0070】 The axis of symmetry SA2 of contact hole 217-1 is shifted in the -D1 direction by less than 50% of the length L1 in the D1 direction of contact hole 215-1 relative to the axis of symmetry SA1 of contact hole 215-1. At this time, the axis of symmetry SA4 of contact hole 217-2 is shifted in the D1 direction by more than 50% of the length L1 in the D1 direction of contact hole 215-2 relative to the axis of symmetry SA3 of contact hole 215-2. In Figure 12, the axis of symmetry SA2 of contact hole 217 may be shifted in the -D1 direction by less than 100% of the length L1 in the D1 direction of contact hole 215-1 relative to the axis of symmetry SA1 of contact hole 215-1. Alternatively, the axis of symmetry SA4 of contact hole 217 may be shifted in the D1 direction by less than 100% of the length L1 in the D1 direction of contact hole 215-2 relative to the axis of symmetry SA3 of contact hole 215-2. 【0071】 In Figure 12, the area S1' of the region where the pixel electrode 216-1 contacts the conductive layer 206-3 via contact holes 215-1 and 217-1 is larger than the area S2' of the region where the pixel electrode 216-1 contacts the conductive layer 206-3 via contact holes 215-2 and 217-2. The sum of areas S1' and S2', resulting in area S3', corresponds to the area in contact between the conductive layer 206-3 and the pixel electrode 216. As a result, even if there is a shift in the position of each mask for forming the contact holes 215 and 217, the sum of areas S1' and S2', resulting in area S3', can be made approximately the same for each of the multiple pixels PIX. Note that contact holes 217-1 and 217-2 are shifted only in the D1 direction. Therefore, the area S3 between the pixel electrode 216 and the conductive layer 206-3 shown in Figure 9 and the area S3' between the pixel electrode 216 and the conductive layer 206-3 shown in Figure 12 are approximately the same. 【0072】 Figure 13 shows that, compared to Figure 9, the positions of contact holes 217-1 and 217-2 are further shifted in the D1 and D2 directions relative to the positions of contact holes 215-1 and 215-2. 【0073】 Even if the positions of contact holes 217-1 and 217-2 are shifted in the D1 and D2 directions relative to the positions of contact holes 215-1 and 215-2, the area S1" in which the pixel electrode 216-1 contacts the conductive layer 206-3 via contact holes 215-1 and 217-1 is larger than the area S2" in which the pixel electrode 216-1 contacts the conductive layer 206-3 via contact holes 215-2 and 217-2. The sum of areas S1" and S2" equals area S3", which corresponds to the area in contact between the conductive layer 206-3 and the pixel electrode 216. As a result, even if there is a shift in the position of each mask for forming the contact holes 215 and 217, the sum of areas S1" and S2" equals area S3" can be made approximately the same for each of the multiple pixels PIX. Furthermore, the length L2 in the D2 direction of contact holes 215-1 and 215-2 is longer than the length L4 in the D2 direction of contact holes 217-1 and 217-2. Therefore, even if contact holes 217-1 and 217-2 are shifted in the D2 direction, it is possible to prevent them from protruding from contact holes 215-1 and 215-2 in the D2 direction. In other words, as long as contact holes 217-1 and 217-2 do not protrude from contact holes 215-1 and 215-2 in the +D2 or -D2 direction, the symmetry axes SA7 and SA8 may be shifted in the +D2 or -D2 direction with respect to the symmetry axes SA5 and SA6. The range of allowable shift of symmetry axes SA2 and SA4 with respect to symmetry axes SA1 and SA3 is the same as in Figure 9, so a detailed explanation is omitted. 【0074】 For example, in the display device shown in Figure 9, if the end of a contact hole 215-1 formed in the insulating film 205 is located inside the end of a contact hole 217-1 formed in the insulating film 209, the insulating film 205 may be etched along the shape of the contact hole 217-1 at the lower end of the contact hole 217-1 located on the insulating film 205. This can cause a void to form at the lower end of the contact hole 217-1 located on the insulating film 205, potentially causing a step break in the pixel electrode 216. This can hinder the electrical connection between the pixel electrode 216 and the conductive layer 206-3. Furthermore, if the pixel electrode and the drain electrode are in contact at one location, a misalignment between the mask for forming the contact hole in the insulating film 205 and the mask for forming the contact hole in the insulating film 209 can result in variations in the contact area between the pixel electrode and the drain electrode for each pixel. 【0075】 Contact holes are typically formed by etching using a resist mask. The resist mask may vary in position within the substrate surface depending on the substrate's curvature. When contact holes need to be formed in both the insulating film 205 and the insulating film 209, misalignment of the resist mask formed on the insulating film 205 and the resist mask formed on the insulating film 209 can cause variations in the contact area between the pixel electrode and the drain electrode for each pixel. In other words, this can cause variations in the contact resistance between the pixel electrode and the drain electrode for each pixel. This variation in contact resistance may lead to a decrease in the display quality of the display device. 【0076】 In the display device 10 according to one embodiment of the present invention, contact holes 215-1 and 215-2 are formed in the insulating film 205 located between the pixel electrode 216-1 and the conductive layer 206-3 which functions as a drain electrode, and contact holes 217-1 and 217-2 are formed in the insulating film 209. Furthermore, the positions where contact holes 215-2 and 217-2 are provided are offset from each other. As a result, the lower end of contact hole 217-1 is located on the insulating film 205, and the lower end of contact hole 217-1 is also located on the conductive layer 206-3. Therefore, even if a step break occurs in the pixel electrode 216 at the end of contact hole 217-1 located on the insulating film 205, step breaks in the pixel electrode 216 can be suppressed at the end of contact hole 217-1 located on the conductive layer 206. This ensures electrical connection between the pixel electrode 216 and the conductive layer 206-3. 【0077】 Furthermore, because the pixel electrode and the drain electrode are in contact at two locations, even if there is a misalignment in the mask used to form contact holes in the insulating film 209, variations in the contact area between the pixel electrode and the drain electrode can be suppressed for each pixel. In other words, variations in the contact resistance between the pixel electrode and the drain electrode can be suppressed for each pixel. As a result, a decrease in the display quality of the display device can be suppressed. 【0078】 Next, the region 250 where the gate wiring GL and source wiring SL1 to SL4 intersect will be explained with reference to Figures 14 to 17. Note that the region 230 described earlier is also shown in Figures 14 to 17. 【0079】 Figure 14 shows the planar layout of conductive layers 202-1 to 202-9, oxide semiconductor layers 204-1 to 204-5, and conductive layers 206-1 to 206-11 in region 250. Conductive layers 202-1 to 202-9 are provided on the array substrate 150 (glass substrate). Conductive layer 202-1 extends in the D1 direction but has a region that branches in the D2 direction. Conductive layers 202-2 to 202-9 also extend in the D2 direction. Oxide semiconductor layers 204-1 to 204-5 are provided on conductive layer 202-1 via a gate insulating film 203 (see Figure 8). Oxide semiconductor layers 204-1 to 204-5 are arranged in a line in the D2 direction. In this embodiment, an example is shown in which five oxide semiconductor layers 204-1 to 204-5 are used to construct a transistor Tr. The effect of heat generation can be reduced by separating the oxide semiconductor layer into multiple oxide semiconductor layers 204-1 to 204-5. The number of oxide semiconductor layers is not particularly limited. The oxide semiconductor layers 204-1 to 204-5 are made less prone to light leakage because the conductive layer 202-1 reflects the light that has been guided through the glass substrate (array substrate 150) from the conductive layer 202-1 side toward the oxide semiconductor layers 204-1 to 204-5. The conductive layers 206-1 to 206-11 are provided on the gate insulating film 203 and the oxide semiconductor layers 204-1 to 204-5. Conductive layers 206-1, 206-2, and 206-11 extend in the D1 direction, and conductive layers 206-3 to 206-10 extend in the D2 direction. 【0080】 Conductive layer 202-1 is superimposed on conductive layers 206-1, 206-2, and 206-11. Conductive layer 202-1 is connected to conductive layer 206-1 via a contact hole 213-1 provided in the gate insulating film 203, and is connected to conductive layer 206-2 via a contact hole 213-2 provided in the gate insulating film 203. The region of conductive layer 202-1 extending in the D1 direction functions as gate wiring. The region of conductive layer 202-1 extending in the D2 direction functions as gate electrode. 【0081】 Conductive layers 202-2 and 202-3 overlap with conductive layer 206-4. Conductive layer 202-2 is connected to conductive layer 206-4 via a contact hole 213-3 provided in the gate insulating film 203, and conductive layer 202-3 is connected to conductive layer 206-4 via a contact hole 213-4 provided in the gate insulating film 203. Conductive layer 206-4 intersects with conductive layer 202-1. Conductive layer 206-4 functions as the first source wiring SL1. In addition, the region of conductive layer 206-4 that does not overlap with conductive layers 202-2 and 202-3 functions as the source electrode of transistor Tr. Conductive layer 206-3 functions as the drain electrode of transistor Tr. 【0082】 Conductive layer 202-4 is superimposed on conductive layer 206-5 and connected to conductive layer 206-5 via contact holes 213-5 provided in gate insulating film 203. Conductive layer 202-5 is superimposed on conductive layer 206-6 and connected to conductive layer 206-6 via contact holes 213-6 provided in gate insulating film 203. Conductive layer 206-5 is connected to conductive layer 206-6 via conductive layer 208-2 (see Figure 15). As a result, conductive layers 206-5, 206-6, and 208-2 function as the third source wiring SL3. 【0083】 Conductive layer 202-6 is superimposed on conductive layer 206-7 and connected to conductive layer 206-7 via contact holes 213-7 provided in the gate insulating film 203. Conductive layer 202-7 is superimposed on conductive layer 206-8 and connected to conductive layer 206-8 via contact holes 213-8 provided in the gate insulating film 203. Conductive layer 206-7 is connected to conductive layer 206-8 via conductive layer 208-3 (see Figure 15). Conductive layers 206-7, 206-8, and 208-3 function as the second source wiring SL2. 【0084】 Conductive layer 202-8 is superimposed on conductive layer 206-9 and connected to conductive layer 206-9 via contact hole 213-9 provided in gate insulating film 203. Conductive layer 202-9 is superimposed on conductive layers 206-9 and conductive layer 206-10. Conductive layer 202-9 is connected to conductive layer 206-9 via contact hole 213-10 provided in gate insulating film 203. Conductive layer 202-9 is also connected to conductive layer 206-10 via contact hole 213-11 provided in gate insulating film 203. Conductive layer 206-9 has a region that intersects with conductive layer 202-1. Conductive layers 206-9 and conductive layers 206-10 function as the fourth source wiring SL4. 【0085】 Furthermore, the conductive layer 202-1 is superimposed on the conductive layer 206-11 and is connected to the conductive layer 206-11 via a contact hole 213-12 provided in the gate insulating film 203. 【0086】 Conductive layers 202-9 and 206-8 have bent regions. Conductive layer 202-9 has a region where it overlaps with and intersects with conductive layer 206-8. In other words, it has a region where the second source wiring SL2 and the fourth source wiring SL4 intersect. 【0087】 Although not described in detail here, as shown in Figure 6, conductive layers 202-2 and 206-5 have bent regions. Conductive layer 202-2 overlaps with conductive layer 206-5 and has a region where they intersect. In other words, the first source wiring SL1 has a region where it intersects with the third source wiring SL3. 【0088】 As shown in Figure 14, the gate wiring GL is constructed by laminating conductive layer 202-1 and conductive layers 206-1 and 206-2. Conductive layer 202-1 extends along the D1 direction. In the region where the gate wiring GL intersects with source wirings SL1 to SL4, only conductive layer 202-1 is provided, and conductive layers 206-1 and 206-2 are spaced apart. Source wiring SL1 is constructed by laminating conductive layers 202-2 and 202-3 and conductive layer 206-4. In the region where source wiring SL1 intersects with the gate wiring GL, only conductive layer 206-4 is provided, and conductive layers 202-2 and 202-3 are spaced apart. As a result, even if static electricity is generated during the manufacturing process of the display area 12 and peripheral area 14 of the array substrate 150, the static electricity can be dissipated, thereby suppressing the occurrence of defects caused by static electricity. 【0089】 Figure 15 shows the planar layout of conductive layers 206-1 to 206-11 and conductive layers 208-1 to 208-3 in region 250. Conductive layers 206-1 to 206-11 are as described in Figure 15. Conductive layers 208-1 to 208-3 are provided on the insulating film 205 (see Figure 8). Conductive layer 208-1 has a region extending in the D2 direction and a region extending in the D1 direction. The region extending in the D2 direction overlaps with oxide semiconductor layers 204-1 to 204-5. The region extending in the D1 direction overlaps with conductive layer 206-11 and is connected to conductive layer 206-11 via contact holes 215-7 provided in the insulating film 205. Conductive layer 208-2 extends in the D2 direction. The conductive layer 208-2 is superimposed on conductive layers 206-5 and 206-6 and is connected to conductive layers 206-5 and 206-6 via contact holes 215-3 and 215-4 provided in the insulating film 205. The conductive layer 208-3 extends in the D2 direction. The conductive layer 208-3 is superimposed on conductive layers 206-7 and 206-8 and is connected to conductive layers 206-7 and 206-8 via contact holes 215-5 and 215-6 provided in the insulating film 205. 【0090】 Figure 16 shows the planar layout of the planarization film 207, transparent conductive layer 212, and conductive layer 214 in region 250. The planarization film 207 is removed in the aperture region of the pixel PIX, as shown in Figure 8. In other words, the planarization film 207 is provided on top of the wiring region. The transparent conductive layer 212 is provided on top of the planarization film 207. The conductive layer 214 is provided on top of the transparent conductive layer 212. The transparent conductive layer 212 and the conductive layer 214 function as capacitive wiring CW. The transparent conductive layer 212 is provided on conductive layers 206-1 to 206-11 via the planarization film 207. Therefore, the source wiring SL1 to SL4 and the capacitive wiring CW wiring are spaced apart, making them less susceptible to the potential influence from the capacitive wiring CW. Also, the electrical resistance of the conductive layer 214 is smaller than that of the transparent conductive layer 212. Therefore, within the display area 12, variations in the potential of the capacitive wiring CW depending on the position of the pixel PIX are suppressed. The transparent conductive layer 212 has an opening 223, and the conductive layer 214 has an opening 225. The openings 223 and 225 are provided so as to overlap. 【0091】 The transparent conductive layer 212 and the conductive layer 214 are arranged in a grid pattern so as to cover the gate wiring GL and source wiring SL1 to SL4. This reduces the retention capacitance C between the region where the transparent conductive layer 212 is not provided and the pixel electrode 216. The retention capacitance C is adjusted by the size of the region where the transparent conductive layer 212 is not provided. Note that the transparent conductive layer 212 may be provided over the entire surface instead of in a grid pattern. The conductive layer 214 is provided so as to cover the transistor Tr. This suppresses light leakage from the transistor Tr. 【0092】 The conductive layer 214 is shown as being provided on top of the transparent conductive layer 212, but it may also be provided below the transparent conductive layer 212. The conductive layer 214 only needs to be laminated with the transparent conductive layer 212. The conductive layer 214 has light-shielding properties. Therefore, it can shield the wiring area from light. The width of the conductive layer 214 is set to be greater than the combined width of the source wirings SL1 to SL4 in a plan view. Also, the width of the conductive layer 214 is set to be greater than the width of the gate wiring GL in a plan view. This makes it possible to suppress the emission of reflected light reflected from the edges of the source wirings SL1 to SL4 by the display panel 11. Note that the width of the conductive layer 214 and the combined width of the source wirings SL1 to SL4 refer to the length in the direction (D2 direction) that intersects the direction in which the source wirings SL1 to SL4 extend. Also, the width of the gate wiring GL refers to the length in the direction (D2 direction) that intersects the direction in which the gate wiring GL extends. 【0093】 Figure 17 shows the planar layout of the conductive layers 206-1 to 206-11 and the pixel electrodes 216-1 to 216-4 in region 250. The conductive layers 206-1 to 206-11 are as described in Figure 14. The pixel electrodes 216-1 to 216-4 are provided on the insulating film 209. The pixel electrodes 216-1 to 216-4 are provided in the aperture region of the pixel PIX. Pixel electrode 216-1 is connected to conductive layer 206-3 via contact holes 217-1 and 217-2 provided in the insulating film 209, and contact holes 215-1 and 215-2 provided in the insulating film 205 (see Figure 15). The insulating film 209 has a contact hole 217-3. The contact hole 217-3 is provided so as to overlap with the openings 223 and 225 (see Figure 16). By providing openings 223, 225 and contact holes 217-3 on the planarized film 207, moisture contained in the planarized film 207 can be released through the openings 223, 225 and contact holes 217-3. 【0094】 As explained above, in the display area 12, the conductive layers 202 and 206 are arranged to extend in a stacked manner, serving as gate wirings GL1 to GL4 and source wirings SL1 to SL4. By arranging the source wirings SL1 to SL4 in a stacked manner, the resistance of the source wirings SL1 to SL4 and the wiring capacitance can be made uniform. Furthermore, source wirings SL1 and SL3 can be arranged to cross each other, and source wirings SL2 and SL4 can be arranged to cross each other. 【0095】 <Materials of each component of the display device 10> As the array substrate 150 and the opposing substrate 152, rigid substrates that are translucent and not flexible, such as glass substrates, quartz substrates, and sapphire substrates, can be used. On the other hand, if the array substrate 150 and the opposing substrate 152 need to be flexible, flexible substrates containing resin and having flexibility, such as polyimide substrates, acrylic substrates, siloxane substrates, or fluororesin substrates, can be used as the array substrate 150 and the opposing substrate 152. Impurities may be introduced into the above resins to improve the heat resistance of the array substrate 150 and the opposing substrate 152. Furthermore, when the display device 10 is applied to a large transparent display, it is preferable to use glass substrates as the array substrate 150 and the opposing substrate 152. The first transparent substrate 151A and the second transparent substrate 151B are provided to protect the array substrate 150 and the opposing substrate 152. For this reason, it is preferable to use, for example, translucent glass substrates, plastic substrates, etc. 【0096】 Silicon nitride (SiN) is used as the nitride insulating film 203a, 205b, and insulating film 209. x ), silicon nitride (SiN x O y ), aluminum nitride (AlN x ), aluminum nitride (AlN x O y In this embodiment, silicon nitride is used as the nitride insulating film 203a, 205b, and insulating film 209. The silicon nitride film is formed, for example, by sputtering. 【0097】 As the oxide insulating films 203b and 205a, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ) are used. In this embodiment, silicon oxide is used as the oxide insulating films 203b and 205a. 【0098】 The above-mentioned SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than that of oxygen (x > y). Also, SiN x O y and AlN x O y are silicon compounds and aluminum compounds containing oxygen in a ratio less than that of nitrogen (x > y). 【0099】 As the planarization film 207, an organic insulating material such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used. 【0100】 As the conductive layers 202, 208, and 214, general metal materials can be used. For example, as these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and alloys or compounds thereof are used. As the above-mentioned members, the above-mentioned materials may be used in a single layer or in a laminated form. 【0101】 As the oxide semiconductor layer 204, an oxide semiconductor having semiconductor properties can be used. The oxide semiconductor layer 204 is translucent. For example, as the oxide semiconductor layer 204, an oxide semiconductor containing two or more metals including indium (In) can be used. As the oxide semiconductor layer 204, for example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) may be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 may be used. However, the oxide semiconductor layer 204 used in this embodiment is not limited to the above composition, and an oxide semiconductor with a different composition can also be used. 【0102】 A mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO) can be used as the transparent conductive layer 212, the pixel electrode 216, and the common electrode 218. Other materials may be used for the transparent conductive layer. The light-shielding layer 219 used for the black matrix BM can be formed from a black resin or metal material. The black matrix BM is formed in contact with the common electrode 218 (see Figure 8). By forming the black matrix BM from a metal material relative to the common electrode 218, which is formed from a transparent conductive film, it can function as an auxiliary electrode to reduce resistance loss. As the metal material for forming the black matrix BM, chromium, molybdenum, titanium, etc., which have a relatively low reflectivity compared to aluminum, may be used as a single layer or in a laminated form. 【0103】 When the display device 10 is applied to a transparent display, it is preferable to use a polymer-dispersed liquid crystal as the liquid crystal layer 210. The polymer-dispersed liquid crystal includes bulk and fine particles. The orientation of the fine particles changes in the bulk according to the potential difference between the pixel electrode 216 and the common electrode 218. By individually controlling the potential of the pixel electrode 216 for each pixel PIX, at least the degree of light transmission and dispersion is controlled for each pixel PIX. The degree of scattering of the liquid crystal layer (fine particles) is controlled according to the voltage of each pixel electrode 216 and the voltage of the common electrode 218. For example, the liquid crystal layer may use a polymer-dispersed liquid crystal such that the degree of scattering increases as the voltage between the voltage of each pixel PIX and the common electrode 218 increases, or it may use a polymer-dispersed liquid crystal such that the degree of scattering increases as the voltage between the voltage of each pixel electrode 216 and the common electrode 218 decreases. 【0104】 In the liquid crystal layer 210, the ordinary refractive indices of the bulk and fine particles are equal to each other. When no voltage is applied between the pixel electrode 216 and the common electrode 218, the refractive index difference between the bulk and fine particles is zero in all directions. The liquid crystal layer 210 is in a non-scattering state and does not scatter the light emitted from the light source. The light emitted from the light source propagates away from the light source 3 (light-emitting part) while being reflected by the first main surface of the array substrate 150 and the first main surface of the opposing substrate 152. When the liquid crystal layer 210 is in a non-scattering state and does not scatter the light L emitted from the light source, the background of the opposing substrate 152 is visible from the array substrate 150, and the background of the array substrate 150 is visible from the opposing substrate 152. 【0105】 Between the pixel electrode 216 to which a voltage is applied and the common electrode 218, the optical axis of the microparticle is tilted by the electric field generated between the pixel electrode 216 and the common electrode 218. Since the bulk optical axis does not change due to the electric field, the orientation of the bulk optical axis and the optical axis of the microparticle are different from each other. In a pixel PIX where the voltage is applied to the pixel electrode 216, light emitted from the light source is scattered. As described above, a portion of the scattered light emitted from the light source is radiated outward from the first main surface of the array substrate 150 or the first main surface of the opposing substrate 152 and is observed by the observer. 【0106】 In pixels PIX where no voltage is applied to the pixel electrode 216, the background on the first main surface side of the opposing substrate 152 is visible from the first main surface of the array substrate 150, and the background on the first main surface 10A side of the array substrate 150 is visible from the first main surface 20A of the opposing substrate 152. When a video signal is input to the display device 10 of this embodiment, a voltage is applied to the pixel electrode 216 of the pixel PIX on which the image is displayed, and the image based on the video signal is visible along with the background. In this way, when the polymer-dispersed liquid crystal is in a scattering state, an image is displayed in the display area. 【0107】 While preferred embodiments have been described above, this disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure. [Explanation of symbols] 【0108】 10: Display device, 11: Display panel, 12: Display area, 14: Peripheral area, 16: Common wiring, 18: Common wiring, 22: Common wiring, 24: Flexible printed circuit, 26: Terminal section, 28: Gate drive circuit, 32: Gate wiring area, 34: Flexible printed circuit, 36: Terminal section, 38: Source drive circuit, 42: Source wiring area, 46: ESD protection circuit, 48: Gate inspection circuit, 52: Source inspection circuit, 54: Inspection line, 56: QD pad, 58: ESD protection circuit, 59: ESD protection circuit, 62: Area, 64: Area, 66: Area, 71: Area, 72: Area, 102: Display panel, 104: light source, 105: insulating layer, 150: array substrate, 152: opposing substrate, 202: conductive layer, 203: gate insulating film, 204: oxide semiconductor layer, 205: insulating film, 206: conductive layer, 207: planarization film, 208: conductive layer, 209: insulating film, 210: liquid crystal layer, 212: transparent conductive layer, 213: contact hole, 214: conductive layer, 215: contact hole, 216: pixel electrode, 217: contact hole, 218: common electrode, 220: encapsulant, GL: gate wiring, SL: source wiring, CL: common wiring, CW: capacitive wiring, C: retaining capacitance, LE: liquid crystal element, PIX: pixel

Claims

[Claim 1] A transistor having an oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer, and a gate insulating film provided between the oxide semiconductor layer and the gate electrode, on a first substrate, The drain electrode connected to the transistor, The pixel electrode connected to the drain electrode, The drain electrode and the pixel electrode are provided with a first insulating film and a second insulating film, The drain electrode extends in the first direction, In the first insulating film, a first contact hole and a second contact hole are provided along the first direction in a region overlapping with the drain electrode. In the second insulating film, a third contact hole and a fourth contact hole are provided along the first direction in a region overlapping with the drain electrode. A display device in which, when viewed from above, the axis of symmetry of the first contact hole in the first direction is offset from the axis of symmetry of the third contact hole in the first direction in a second direction intersecting the first direction, and the axis of symmetry of the second contact hole in the first direction is offset from the axis of symmetry of the fourth contact hole in the first direction in a third direction opposite to the second direction. [Claim 2] The display device according to claim 1, wherein the second insulating film is in contact with the drain electrode in the region where the first contact hole is provided and in the region where the second contact hole is provided. [Claim 3] The area of ​​the first contact hole is larger than the area of ​​the third contact hole. The display device according to claim 1, wherein the area of ​​the second contact hole is larger than the area of ​​the fourth contact hole. [Claim 4] The area of ​​the first contact hole is approximately the same as the area of ​​the second contact hole. The display device according to claim 1, wherein the area of ​​the third contact hole is substantially the same as the area of ​​the fourth contact hole. [Claim 5] The display device according to claim 1, wherein the area of ​​the first region in which the pixel electrode contacts the drain electrode via the first contact hole and the third contact hole is different from the area of ​​the second region in which the pixel electrode contacts the drain electrode via the second contact hole and the fourth contact hole. [Claim 6] The display device according to claim 1, wherein the area of ​​the first region in which the pixel electrode is connected to the drain electrode via the first contact hole and the third contact hole is substantially the same as the area of ​​the second region in which the pixel electrode is connected to the drain electrode via the second contact hole and the fourth contact hole. [Claim 7] The display device according to claim 1, wherein the pixel electrode is in contact with the upper surface of the first insulating film in the third contact hole and the fourth contact hole. [Claim 8] A second substrate is provided opposite to the first substrate, A liquid crystal layer provided between the first substrate and the second substrate, The display device according to claim 1, further comprising: a light source arranged so as to enter toward the side surface of the first substrate or toward the side surface with the second substrate. [Claim 9] The aforementioned liquid crystal layer is a polymer-dispersed liquid crystal, When the polymer-dispersed liquid crystal is in a scattering state, an image is displayed in the display area. The display device according to claim 8, wherein when the polymer-dispersed liquid crystal is in a non-scattering state, the background of the second substrate is visible from the first substrate in the display area, and the background of the first substrate is visible from the second substrate.

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