Curable compositions and insulating films

JP2026101651APending Publication Date: 2026-06-22DUPONT ELECTRONICS INC
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Patent Information

Application Number
JP2025244445
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-12-10
Filing Date
2025-12-10
Publication Date
2026-06-22

AI Technical Summary

Technical Problem

Conventional via fabrication techniques for printed circuit boards (PCBs) generate resin smears during drilling, requiring wet processes that produce harmful waste and are not cost-effective due to slow plasma etching rates.

Method used

A curable composition comprising maleimide resin, cyanate ester, polyphenylene ether oligomer, thermoplastic elastomer, epoxy resin, curing catalyst, additives, and boron nitride particles is used to enhance plasma etching rates without compromising electrical and mechanical properties.

Benefits of technology

The composition achieves higher plasma etching rates, reducing production time and environmental impact while maintaining low dielectric loss tangent and coefficient of thermal expansion, suitable for high-density PCB manufacturing.

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Abstract

The present invention provides a curable composition and an insulating film. [Solution] This disclosure provides a curable composition comprising (a) a maleimide resin, (b) a cyanate ester, (c) a polyphenylene ether oligomer, (d) a thermoplastic elastomer, (e) an epoxy resin, (f) a curing catalyst, (g) an additive, and (h) an inorganic filler, particularly boron nitride particles. This disclosure also provides an insulating film comprising the aforementioned curable composition, which is particularly suitable for manufacturing printed circuit boards (PCBs). The insulating film exhibits excellent electrical properties, including a low dielectric loss tangent (Df) and a low coefficient of thermal expansion (CTE). Furthermore, the insulating film offers significant advantages in reducing production time in PCB manufacturing processes involving plasma etching steps.
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Citation Information

Patent Citations

  • Method for manufactunring a multilayer circuit structure having embedded trace layers

    US20220201853A1