Ceramic electronic components

Abstract

This invention provides ceramic electronic components with improved capacitance change (TCC) characteristics with respect to temperature changes, DC-bias characteristics, dielectric constant, and high-temperature reliability. [Solution] One or more of the dielectric crystal grains 10 contained in the dielectric layer contain titanium (Ti), tin (Sn), and dysprosium (Dy), and the material includes a core 11 and a shell 12 surrounding at least a part of the core, wherein the core has a tin (Sn) content of less than 0.2 moles per 100 moles of titanium (Ti) and a dysprosium (Dy) content of less than 0.1 moles per 100 moles of titanium (Ti), and the shell includes a first region 12a in which the number of moles of tin (Sn) per 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti), and a second region 12b in which the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) per 100 moles of titanium (Ti).

Description

[Technical Field]

[0001] This invention relates to ceramic electronic components. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC), a type of ceramic electronic component, is a chip-type capacitor that is mounted on the printed circuit boards of various electronic products, such as video equipment including liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones and mobile phones, on-board chargers (OBCs) for electric vehicles, and DC-DC converters, to charge or discharge electricity.

[0003] As the size of various electronic components on which multilayer ceramic capacitors are mounted decreases and their integration density increases, the size of the multilayer ceramic capacitors themselves also needs to be reduced, which in turn necessitates an improvement in capacitance per unit volume.

[0004] One typical method for achieving miniaturization and high capacitance in multilayer ceramic capacitors is to form a thin dielectric layer; however, in this case, it can be difficult to ensure sufficient dielectric constant and reliability in harsh environments.

[0005] Conventional Patent Document 1 presents a method for simultaneously ensuring high dielectric constant and high reliability by having at least one of the dielectric crystal grains in the dielectric layer have a core-double shell structure, and by including one or more first elements (Sn, Sb, Ge, Si, Ga, In, and Zr) in the first shell of the double shell structure, and one or more second elements (Ca and Sr) in the second shell.

[0006] However, multilayer ceramic capacitors for general electronic equipment are required to have dielectric properties where the change in capacitance is within ±15% in the temperature range of -55°C to 85°C, while multilayer ceramic capacitors for IT products are required to have dielectric properties where the change in capacitance is within ±22% in the temperature range of -55°C to 105°C.

[0007] Furthermore, these small, high-capacitance multilayer ceramic capacitors tend to experience a significant decrease in capacitance due to DC bias.

[0008] Therefore, there is a need to improve the dielectric crystal grain structure to reduce the change in capacitance due to temperature changes (TCC) and to mitigate the phenomenon of capacitance changing in response to DC voltage (DC-bias). [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] KR 10-2022-0088099 A [Overview of the project] [Problems that the invention aims to solve]

[0010] One of the various objectives of the present invention is to provide ceramic electronic components with improved TCC characteristics.

[0011] One of the various objectives of the present invention is to provide a ceramic electronic component with improved DC-bias characteristics.

[0012] One of the various objectives of the present invention is to provide ceramic electronic components with improved dielectric constant.

[0013] One of the various objectives of the present invention is to provide ceramic electronic components with improved high-temperature reliability.

[0014] However, the object of the present invention is not limited to the above-described content and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for solving the problem]

[0015] A ceramic electronic component according to one embodiment of the present invention includes a dielectric layer containing a plurality of dielectric crystal grains, a body containing internal electrodes, and external electrodes disposed on the body and connected to the internal electrodes, wherein one or more of the plurality of dielectric crystal grains contain titanium (Ti), tin (Sn), and dysprosium (Dy), and includes a core and a shell surrounding at least a part of the core, wherein the core has a tin (Sn) content of less than 0.2 moles per 100 moles of titanium (Ti) and a dysprosium (Dy) content of less than 0.1 moles per 100 moles of titanium (Ti). The above shell includes a first region where the number of moles of tin (Sn) per 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti), and a second region where the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) per 100 moles of titanium (Ti). When the maximum ferret diameter of the dielectric crystal grains including the above core and shell is LG, and the maximum ferret diameter of the above core is LC, then LC / LG can satisfy the condition of 0.49 or more and 0.73 or less. [Effects of the Invention]

[0016] One of the various effects of the present invention is that the dielectric constant of the ceramic electronic component is improved by having one or more of the plurality of dielectric crystal grains include a core and a shell surrounding at least a part of the core, and the shell includes a first region in which the number of moles of tin (Sn) per 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti), and a second region in which the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) per 100 moles of titanium (Ti).

[0017] One of the various effects of the present invention is that one or more of a plurality of dielectric crystal grains include a core and a shell surrounding at least a part of the core, and the shell has a first region where the number of moles of tin (Sn) with respect to 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) with respect to 100 moles of titanium (Ti), and a second region where the number of moles of dysprosium (Dy) with respect to 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) with respect to 100 moles of titanium (Ti). When the maximum Feret diameter of the dielectric crystal grain including the core and the shell is LG and the maximum Feret diameter of the core is LC, LC / LG satisfies 0.49 or more and 0.73 or less, thereby improving the TCC characteristics and DC-bias characteristics of the ceramic electronic component.

[0018] However, the diverse and significant advantages and effects of the present invention are not limited to the above-described content, and can be more easily understood in the process of explaining the specific embodiments of the present invention.

Brief Description of Drawings

[0019] [Figure 1] A perspective view of a ceramic electronic component according to an embodiment of the present invention is schematically shown. [Figure 2] A cross-sectional view taken along line I-I' of FIG. 1 is schematically shown. [Figure 3] A cross-sectional view taken along line II-II' of FIG. 1 is schematically shown. [Figure 4] A schematic diagram schematically showing a dielectric crystal grain and a grain boundary according to an example. [Figure 5] (a), (b), and (c) are images obtained by analyzing the core-shell structure of a dielectric crystal grain by TEM-EDX. [Figure 6] A schematic diagram schematically showing the structure of a dielectric crystal grain according to an example. [Figure 7] A graph showing the line-profile analysis results of measuring the contents of Sn and Dy along line A-A' of FIG. 6. [Figure 8]This is a schematic diagram of the enlarged view of region P in Figure 1. [Figure 9] This graph shows the line-profile analysis results, which measured the Sn and Ni content along the B-B' line in Figure 8. [Figure 10] This image shows the Sn element mapped from TEM-EDX analysis of the interface between the dielectric layer and the internal electrode. [Modes for carrying out the invention]

[0020] Embodiments of the present invention will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present invention can be modified into several other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to give a more complete explanation of the present invention to a person of the ordinary skill. Accordingly, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for a clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0021] Furthermore, in order to clearly illustrate the present invention in the drawings, parts unrelated to the explanation have been omitted, and the size and thickness of each illustrated component are shown arbitrarily for the convenience of explanation; therefore, the present invention is not necessarily limited by the illustrations. Also, components with the same function within the scope of the same concept are described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a certain component, unless otherwise stated to the contrary, it does not mean that other components are excluded, but rather that other components may be further included.

[0022] In the drawing, the X direction can be defined as the direction in which the first internal electrode and the second internal electrode are alternately arranged with the dielectric layer in between, or as the first direction, and of the Y and Z directions which are perpendicular to the X direction, the Y direction can be defined as the second direction and the Z direction as the third direction.

[0023] Figure 1 is a schematic perspective view of a ceramic electronic component according to one embodiment of the present invention; Figure 2 is a schematic cross-sectional view along the line I-I' in Figure 1; Figure 3 is a schematic cross-sectional view along the line II-II' in Figure 1; Figure 4 is a schematic diagram showing dielectric crystal grains and grain boundaries according to one embodiment; Figures 5(a), (b), and (c) are images of the core-shell structure of dielectric crystal grains analyzed by TEM-EDX; Figure 6 is a schematic diagram showing the structure of dielectric crystal grains according to one embodiment; and Figure 7 is a graph showing the line-profile analysis results of measuring the Sn and Dy content along the line A-A' in Figure 6.

[0024] In the following, with reference to Figures 1 to 7, a ceramic electronic component 100 according to one embodiment of the present invention and various embodiments thereof will be described in detail.

[0025] A ceramic electronic component 100 according to one embodiment of the present invention includes a dielectric layer 111 containing a plurality of dielectrics, a body 110 containing internal electrodes 121 and 122, and external electrodes 130 and 140 disposed on the body 110 and connected to the internal electrodes 121 and 122, wherein one or more of the plurality of dielectric crystal grains 10 contain titanium (Ti), tin (Sn), and dysprosium (Dy), and includes a core 11 and a shell 12 surrounding at least a part of the core 11, wherein the tin (Sn) content of the core 11 is less than 0.2 moles per 100 moles of titanium (Ti), and the dysprosium (Dy) content is less than 0.2 moles per 100 moles of titanium (Ti) The amount is less than 0.1 moles, and the shell 12 includes a first region 12a where the number of moles of tin (Sn) per 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti), and a second region 12b where the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) per 100 moles of titanium (Ti). When the maximum ferret diameter of the dielectric crystal grain 10 including the core 11 and shell 12 is LG, and the maximum ferret diameter of the core 11 is LC, then LC / LG can satisfy the condition of 0.49 or more and 0.73 or less.

[0026] The main body 110 may include a dielectric layer 111 and internal electrodes 121 and 122. The dielectric layer 111 and internal electrodes 121 and 122 can be arranged alternately within the main body 110, and the direction in which the internal electrodes 121 and 122 and the main body 110 are arranged alternately can be defined as the stacking direction or the first direction.

[0027] There are no particular restrictions on the specific shape of the main body 110, but as shown in Figure 1, the main body 110 can be hexahedral or a similar shape. Furthermore, although the shape of the main body 110 is not a perfectly straight hexahedron due to shrinkage during the firing process and a separate polishing process, it can be substantially hexahedral.

[0028] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2 and connected to the third surface 3 and the fourth surface 4 and facing each other in a third direction. The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM).

[0029] As shown in Figure 4, the dielectric layer 111 can contain multiple dielectric crystal grains 10. Furthermore, grain boundaries 20 can be arranged between the multiple dielectric crystal grains 10.

[0030] On the other hand, one or more of the multiple dielectric crystal grains 10 may include a core 11 and a shell 12 surrounding at least a part of the core, and the shell 12 may be divided into a first region 12a and a second region 12b depending on the content of tin (Sn) and dysprosium (Dy).

[0031] Referring to Figure 5(a), it can be confirmed that the dielectric layer consists of dielectric crystal grains and crystal grain boundaries. Referring to Figure 5(b), which shows the distribution of tin (Sn) content, and Figure 5(c), which shows the distribution of dysprosium (Dy) content, it can be confirmed that the shell according to the present invention contains regions in which the tin (Sn) content is concentrated.

[0032] Referring to Figure 6, the shell 12 according to one embodiment of the present invention surrounds at least a portion of the core 11, and the shell 12 may include a first region 12a and a second region 12b.

[0033] Referring to Figure 7, core 11 can be a region that simultaneously satisfies the conditions that the tin (Sn) content is less than 0.2 moles per 100 moles of titanium (Ti) and that the dysprosium (Dy) content is less than 0.1 moles per 100 moles of titanium (Ti).

[0034] Referring to Figure 7, the shell 12 can be seen as a region located outside the core 11 in the dielectric crystal grains 10. The region where the number of moles of tin (Sn) per 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti) can be seen as the first region 12a, and the region where the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) per 100 moles of titanium (Ti) can be seen as the second region 12b.

[0035] The dielectric layer 111 or one or more dielectric crystal grains 10 contained in the dielectric layer 111 may contain titanium (Ti). The titanium (Ti) contained in one or more of the dielectric crystal grains 10 may be a component derived from titanium (Ti) contained in the barium titanate-based material forming the dielectric layer 111.

[0036] The main component of the dielectric composition forming the dielectric layer 111 is not particularly limited as long as sufficient capacitance can be obtained. For example, a barium titanate-based material, a lead composite perovskite-based material, a strontium titanate-based material, or the like can be used. The barium titanate-based material can contain BaTiO3-based ceramic powder. Examples of the ceramic powder include BaTiO3, (Ba

[0040] , Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) or Ba(Ti 1-y Zr y )O3 (0 < y < 1), etc.

[0037] In addition to the barium titanate-based main component containing titanium (Ti), the dielectric layer 111 can contain various additives. In one embodiment of the present invention, in order to realize the core-shell structure of the dielectric crystal grains 10, the dielectric layer 111 can further contain tin (Sn) and dysprosium (Dy) in addition to titanium (Ti). Similarly, one or more of the plurality of dielectric crystal grains 10 can further contain tin (Sn) and dysprosium (Dy) in addition to titanium (Ti).

[0038] On the other hand, the average thickness td of the dielectric layer 111 does not need to be particularly limited.

[0039] For example, for miniaturization and high capacitance of the ceramic electronic component 100, the average thickness td of the dielectric layer 111 can be 0.35 μm or less, and for ensuring the reliability of the ceramic electronic component 100 under high temperature and high voltage, the average thickness td of the dielectric layer 111 can be 3.0 μm or more.

[0040] <000017In one embodiment, the average thickness td of the dielectric layer 111 can mean the average thickness of one or more dielectric layers among a plurality of dielectric layers.

[0041] The average thickness td of the dielectric layer 111 can be measured by scanning images of the cross-sections of the main body 110 in the first and third directions using a scanning electron microscope (SEM). For example, the average thickness td of the dielectric layer 111 can be the average of the thicknesses measured at the 1 / 4, 2 / 4, and 3 / 4 points, which are four equal parts of the dielectric layer in the length direction, using the point where the center line in the length direction and the center line in the thickness direction of the capacitance forming section meet and one adjacent dielectric layer as a reference. By extending such measurements to the two upper and two lower dielectric layers that are equally spaced, using the point where the center line in the length direction and the center line in the thickness direction of the capacitance forming section meet and one adjacent dielectric layer as a reference, the average thickness of the dielectric layer can be further generalized.

[0042] The main body 110 may include a capacitance forming section Ac in which capacitance is formed, comprising a first internal electrode 121 and a second internal electrode 122 disposed inside the main body 110 and arranged to face each other with a dielectric layer 111 in between.

[0043] Furthermore, the capacitance-forming portion Ac, which contributes to the capacitance formation of the capacitor, can be formed by repeatedly stacking multiple first internal electrodes 121 and second internal electrodes 122 with a dielectric layer 111 in between.

[0044] Referring to Figure 2, cover portions 112 and 113 can be arranged on one and the other surface of the capacitance forming portion Ac in the first direction. The cover portions 112 and 113 can be formed by laminating a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming portion Ac, respectively, and can basically serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0045] The cover portions 112 and 113 do not contain internal electrodes and can be made of the same material as the dielectric layer 111. That is, the cover portions 112 and 113 can be made of ceramic material, for example, the same ceramic material as the dielectric layer 111.

[0046] The average thickness tc of the cover portions 112 and 113 is not particularly limited. However, in order to more easily achieve miniaturization and high capacitance of ceramic electronic components, the average thickness tc of the cover portions 112 and 113 may be 15 μm or less.

[0047] The average thickness tc of the cover portions 112 and 113 can represent the size in the first direction and can be the average value of the sizes of the cover portions 112 and 113 in the first direction measured at five equally spaced points on the upper or lower part of the volume forming portion Ac.

[0048] Referring to Figure 3, margin portions 114 and 115 can be arranged on one and the other surfaces of the volume-forming portion Ac in the third direction.

[0049] The margin portions 114 and 115 include a margin portion 114 located on the fifth surface 5 of the main body 110 and a margin portion 115 located on the sixth surface 6. That is, the margin portions 114 and 115 may be located on both sides of the ceramic main body 110 in the width direction.

[0050] As shown in Figure 3, the margin portions 114 and 115 can represent the regions between the interface between both ends of the first internal electrode 121 and the second internal electrode 122 and the body 110 in a cross-section obtained by cutting the main body 110 in the width-thickness (WT) direction.

[0051] The margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0052] The margin portions 114 and 115 may be formed by applying a conductive paste to the ceramic green sheet and forming internal electrodes, except where the margin portions are formed.

[0053] Furthermore, in order to suppress the step caused by the internal electrodes 121 and 122, the laminated internal electrodes may be cut so that they are exposed on the fifth surface 5 and sixth surface 6 of the main body, and then a single dielectric layer or two or more dielectric layers may be laminated in the width direction on both sides of the capacitance forming portion Ac to form margin portions 114 and 115.

[0054] On the other hand, the width of the margin portions 114 and 115 does not need to be particularly limited. However, in order to more easily achieve miniaturization and high capacitance of ceramic electronic components, the average width of the margin portions 114 and 115 may be 15 μm or less.

[0055] The average width of the margin portions 114 and 115 can represent the average size of the margin portions 114 and 115 in the third direction, and may be the average value of the sizes of the margin portions 114 and 115 in the third direction measured at five equally spaced points on the side surface of the volume forming portion Ac.

[0056] The internal electrodes 121 and 122 may be included in the main body 110 together with the dielectric layer 111.

[0057] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122, which are arranged alternately facing each other across the dielectric layer 111 that constitutes the main body 110, and can be exposed on the third surface 3 and the fourth surface 4 of the main body 110, respectively.

[0058] Referring to Figures 1 and 2, the first internal electrode 121 can be separated from the fourth surface 4 and exposed via the third surface 3, and the second internal electrode 122 can be separated from the third surface 3 and exposed via the fourth surface 4.

[0059] In this configuration, the first internal electrode 121 and the second internal electrode 122 can be electrically isolated from each other by the dielectric layer 111 placed in between them.

[0060] The materials used to form the internal electrodes 121 and 122 are not particularly limited, and any material with excellent electrical conductivity can be used. For example, the internal electrodes 121 and 122 may contain one or more of the following: nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0061] On the other hand, there is no need to specifically limit the average thickness te of the internal electrodes 121 and 122.

[0062] For example, in order to increase the capacitance of the ceramic electronic component 100 while miniaturizing it, the average thickness te of the internal electrodes 121 and 122 can be 0.35 μm or less, and in order to ensure the reliability of the ceramic electronic component 100 under high temperature and high voltage conditions, the average thickness te of the internal electrodes 121 and 122 can be 3.0 μm or more.

[0063] The average thickness te of the internal electrodes 121 and 122 can mean the average thickness of one or more internal electrodes among the multiple internal electrodes 121 and 122.

[0064] The average thickness te of the internal electrodes 121 and 122 can be measured by scanning images of the cross-sections of the main body 110 in the first and third directions using a scanning electron microscope (SEM). For example, the average thickness te of the internal electrodes 121 and 122 can be the average of the thicknesses measured at the 1 / 4, 2 / 4, and 3 / 4 points, which are four equal parts of the internal electrode lengthwise, based on the point where the center line in the lengthwise direction and the center line in the thicknesswise direction of the capacitance forming section meet, and the internal electrode layer adjacent to it, extracted from images of the internal electrodes cut in the center of the widthwise direction of the main body 110 using a scanning electron microscope (SEM). By extending such measurements to the two upper and two lower internal electrodes that are equally spaced based on the point where the center line in the lengthwise direction and the center line in the thicknesswise direction of the capacitance forming section meet, the average thickness of the internal electrodes can be further generalized.

[0065] Referring to Figure 1, external electrodes 130 and 140 can be placed on the main body 110.

[0066] Referring to Figures 1 and 2, the external electrodes 130 and 140 may include a first external electrode 130 that contacts the third surface 3 of the main body 110 and a second external electrode 140 that contacts the fourth surface 4.

[0067] In this embodiment, a structure is described in which the ceramic electronic component 100 has two external electrodes 130 and 140. However, the number and shape of the external electrodes 130 and 140 can be changed depending on the form of the internal electrodes 121 and 122 or other purposes.

[0068] On the other hand, the external electrodes 130 and 140 can be formed using any material that has electrical conductivity, such as metal, and the specific material can be determined by considering electrical properties, structural stability, etc. Furthermore, they can have a multilayer structure.

[0069] For example, the external electrodes 130 and 140 may include electrode layers 131 and 141 placed on the main body 110 and plating layers 132, 133, 142, and 143 formed on the electrode layers 131 and 141.

[0070] To give a more specific example for the electrode layers 131 and 141, the electrode layers may be fired electrodes containing a conductive metal and glass, or resin-based electrodes containing a conductive metal and resin.

[0071] Furthermore, the electrode layers 131 and 141 may be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body. Also, the electrode layers may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto a fired electrode.

[0072] The conductive metal contained in the electrode layers 131 and 141 can be any material with excellent electrical conductivity, and is not particularly limited. For example, the conductive metal can be one or more of nickel (Ni), copper (Cu), and their alloys, and is preferably copper (Cu) to improve adhesion to the main body.

[0073] The plating layers 132, 133, 142, and 143 play a role in improving mounting characteristics. The types of plating layers 132, 133, 142, and 143 are not particularly limited and may be plating layers containing one or more of Ni, Sn, Pd, and their alloys, and may be formed in multiple layers.

[0074] To give a more specific example for the plating layers 132, 133, 142, and 143, the plating layers may be Ni plating layers or Sn plating layers, and the Ni plating layers 132, 142 and Sn plating layers 133, 143 may be formed sequentially on the electrode layers 131, 141, or the Sn plating layers may be formed sequentially. Furthermore, the plating layers may include multiple Ni plating layers and / or multiple Sn plating layers.

[0075] The core-shell structure of dielectric crystal grains can be divided into a core that ensures dielectric constant and a shell that ensures insulating properties. Therefore, by appropriately adjusting the core and shell structures, the capacitance and reliability of ceramic electronic components can be ensured simultaneously.

[0076] In particular, Patent Document 1 presents a method for simultaneously ensuring high dielectric constant and high reliability by having at least one of the dielectric crystal grains have a core-double shell structure. However, with only the structure presented in Patent Document 1, it is difficult to ensure the TCC characteristics and DC-bias characteristics of ceramic electronic components.

[0077] On the other hand, when ceramic electronic components are miniaturized and have high capacitance, or when they operate under high temperature and high voltage, it can be important to ensure not only dielectric constant and reliability, but also TCC characteristics and DC-bias characteristics. In this invention, one or more of the plurality of dielectric crystal grains 10 include a core 11 and a shell 12 surrounding at least a part of the core 11, and the shell 12 includes a first region 12a in which the tin (Sn) content is greater than the dysprosium (Dy) content and a second region 12b in which the dysprosium (Dy) content is greater than the tin (Sn) content, and by adjusting the specific gravity occupied by the core in the dielectric crystal grain, it is possible to ensure TCC characteristics and DC-bias characteristics and mitigate the decrease in dielectric constant and reliability.

[0078] Specifically, according to one embodiment of the present invention, the core 11 can mean a region in which the tin (Sn) content is less than 0.2 moles per 100 moles of titanium (Ti) and the dysprosium (Dy) content is less than 0.1 moles per 100 moles of titanium (Ti), and the shell 12 may be a region in the dielectric crystal grain 10 excluding the core 11. The shell 12 can be arranged to surround at least a part of the core 11 and may include a first region 12a in which the number of moles of tin (Sn) per 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti), and a second region 12b in which the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) per 100 moles of titanium (Ti).

[0079] When the dielectric crystal grains 10 have a core-shell structure, in order to improve the TCC characteristics and DC-bias characteristics, it is necessary to form the cores 11 so that they occupy the maximum possible specific gravity within the dielectric crystal grains 10. However, in a typical core-shell structure, increasing the specific gravity of the cores 11 may lead to an excessive increase in the size of the dielectric crystal grains 10 themselves, or the shells 12 may not be sufficiently formed, reducing the beneficial effects of the shells 12, such as increased insulation resistance and suppression of oxygen vacancy migration.

[0080] On the other hand, when Sn is substituted for Ti sites in the shell, the potential barrier is strengthened due to the increase in surface energy at the core-shell interface, and an effect of increasing the resistance of the shell can be expected. Therefore, in the present invention, by arranging a first region 12a in which Sn is concentrated between the core 11 and the second region 12b of the shell 12, the specific gravity occupied by the core 11 in the dielectric crystal grains 10 can be sufficiently increased, improving TCC characteristics and DC-bias characteristics. Furthermore, problems that may occur when increasing the specific gravity occupied by the core in the dielectric crystal grains in a general core-shell structure can also be mitigated or suppressed.

[0081] In one embodiment of the present invention, the specific gravity occupied by the core 11 in the dielectric crystal grain 10 can be expressed as the ratio (LC / LG) of the maximum ferret diameter LC of the core to the maximum ferret diameter LG of the dielectric crystal grain 10 including the core 11 and the shell 12.

[0082] If LC / LG is less than 0.49, the dielectric properties (X6S) where the change in capacitance is within ±22% between -55°C and 105°C may not be met, and the DC-bias characteristics may deteriorate. Therefore, in this invention, by adjusting LC / LG to 0.49 or higher, the X6S characteristics can be met and sufficient DC-bias characteristics can be ensured.

[0083] There is no particular upper limit on LC / LG. However, if LC / LG exceeds 0.73, forming a thin dielectric layer 111 may reduce reliability.

[0084] Therefore, in one embodiment of the present invention, by adjusting LC / LG to 0.49 or more and 0.73 or less, the dielectric constant can be improved, the reliability of the ceramic electronic component can be improved, and at the same time, X6S characteristics and sufficient DC-bias characteristics can be ensured.

[0085] On the other hand, if LC / LG exceeds 0.64, the MTTF (Mean Time To Failure) may decrease even if the content of sub-components that may be included in the dielectric layer 111 is adjusted. Therefore, more preferably, LC / LG may be between 0.49 and 0.64.

[0086] As shown in Figure 6, the maximum ferret diameter can refer to the maximum distance between two points measured along the outline of the dielectric crystal grain 10 or the core 11. The maximum ferret diameter can be measured by extracting the outlines of the dielectric crystal grain 10 and the core 11 using image analysis software such as Image, and then selecting the longest diameter among the measured distances between two points along the outlines.

[0087] On the other hand, the outer boundary of the dielectric crystal grain 10 or core 11 can be determined by processing an image analysis software on a TEM image or TEM-EDS mapping image obtained by observing the central part of the capacitance-forming portion Ac at a magnification of 225,000 times in the cross-sections in the first and second directions, which have been polished to the center of the third direction of the ceramic electronic component 100.

[0088] Specifically, the outer boundary of the dielectric crystal grain 10 may be determined as a grain boundary 20, which is a dark area in the TEM image, or as a boundary line between regions with different crystal structure orientations through diffraction pattern analysis. On the other hand, the outer boundary of the core 11 can be determined after TEM-EDS analysis by superimposing an image mapped with tin (Sn) and an image mapped with dysprosium (Dy), and then defining the boundary as a region that simultaneously satisfies the conditions that the tin (Sn) content is less than 0.2 moles per 100 moles of titanium (Ti) and the dysprosium (Dy) content is less than 0.1 moles per 100 moles of titanium (Ti).

[0089] After the boundary between the dielectric crystal grain 10 and the core 11 is determined, the maximum ferret diameter LG of the dielectric crystal grain 10, including the core 11 and shell 12, can be measured by the length of the line segment with the longest length drawn from two points on the boundary of the dielectric crystal grain 10, and the maximum ferret diameter LC of the core 11 can be measured by the length of the line segment with the longest length drawn from two points on the boundary of the core 11. Such measurements can be repeatedly performed on 10 or more dielectric crystal grains, including the core 11 and the shell 12, which includes the first region 12a and the second region 12b, and can be further generalized by taking the average value of such measurements.

[0090] On the other hand, the maximum ferret diameter LC of core 11 can be more clearly determined by performing a line-profile analysis along the line segment with the longest distance between two points on the outer boundary of core 11, and then measuring the length of the region that simultaneously satisfies the conditions that the tin (Sn) content is less than 0.2 moles per 100 moles of titanium (Ti) and the dysprosium (Dy) content is less than 0.1 moles per 100 moles of titanium (Ti).

[0091] In one embodiment, the specific gravity occupied by the core 11 in the dielectric crystal grain 10 can also be expressed as the correlation between the area of ​​the core 11, the area of ​​the first region 12a, and the area of ​​the second region 12b.

[0092] Specifically, in one embodiment, the area of ​​the core 11 may be larger than the area of ​​the first region 12a, and the area of ​​the second region 12b may be larger than the area of ​​the first region 12a. This allows the effect of improving TCC characteristics and DC-bias characteristics to be more pronounced by maintaining a high specific gravity of the core 11 in relation to the dielectric crystal grains 10. For similar reasons, in one embodiment, the area of ​​the core 11 may be larger than the sum of the areas of the first region 12a and the second region 12b.

[0093] The areas of core 11, first region 12a, and second region 12b are analyzed by TEM-EDS to map the tin (Sn) and dysprosium (Dy) elements. The regions are then divided into core 11 (where the tin (Sn) content is less than 0.2 moles per 100 moles of titanium (Ti) and the dysprosium (Dy) content is less than 0.1 moles per 100 moles of titanium (Ti)), first region 12a (where the number of moles of tin (Sn) per 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti), and second region 12b (where the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) per 100 moles of titanium (Ti)). The areas of each region can then be measured by dividing them pixel by pixel using the ImageJ program and calculating the area of ​​each region.

[0094] The tin (Sn) content in the first region 12a may be between 0.2 moles and 4.5 moles per 100 moles of titanium (Ti). This prevents the diffusion of elements contained in the second region 12b, as described later, into the core 11. Furthermore, the peak value of the tin (Sn) content can be formed within the first region 12a throughout the dielectric crystal grains 10, and the peak value of the tin (Sn) content can be formed within the range of between 0.2 moles and 4.5 moles per 100 moles of titanium (Ti).

[0095] The average tin (Sn) content per 100 moles of titanium (Ti) in the first region 12a may be more than twice the average tin (Sn) content per 100 moles of titanium (Ti) in the second region 12b. By concentrating the tin (Sn) in the first region 12a adjacent to the core 11, the decrease in reliability that may occur by increasing the size of the core 11 can be mitigated.

[0096] By concentrating the distribution of tin (Sn) in the first region 12a adjacent to the core 11, it is possible to satisfy S1 > S2 > Sc when the average content of tin (Sn) per 100 moles of titanium (Ti) in the core 11 is Sc, the average content of tin (Sn) per 100 moles of titanium (Ti) in the first region 12a is S1, and the average content of tin (Sn) per 100 moles of titanium (Ti) in the second region 12b is S2.

[0097] The dysprosium (Dy) in the dielectric layer 111 plays a role in improving the insulating properties, but if it is excessively diffused or substituted in the core 11, the dielectric constant may decrease. Therefore, in one embodiment, the dysprosium (Dy) content can be maximized in the second region 12b, and the average dysprosium (Dy) content can be highest in the second region 12b. That is, when the average dysprosium (Dy) content per 100 moles of titanium (Ti) in the core 11 is Dc, the average dysprosium (Dy) content per 100 moles of titanium (Ti) in the first region 12a is D1, and the average dysprosium (Dy) content per 100 moles of titanium (Ti) in the second region 12b is D2, the condition D2 > D1 > Dc can be satisfied.

[0098] In one embodiment, Dc and D1 can each be 0.04 moles or less per 100 moles of titanium (Ti), thereby suppressing the problem of excessive diffusion or substitution of dysprosium (Dy) in the core 11, which leads to a decrease in dielectric constant.

[0099] In one embodiment, the dielectric layer 111 may further contain one or more rare earth elements other than dysprosium (Dy). That is, the dielectric layer 111 may contain one or more of dysprosium (Dy) and rare earth elements other than dysprosium (Dy). This makes it possible to suppress the reliability degradation problem that may occur when the dielectric layer 111 contains only dysprosium (Dy) as a rare earth element.

[0100] When Rec is the average content of rare earth elements including dysprosium (Dy) per 100 moles of titanium (Ti) in core 11, Re1 is the average content of rare earth elements including dysprosium (Dy) per 100 moles of titanium (Ti) in the first region 12a, and Re2 is the average content of rare earth elements including dysprosium (Dy) per 100 moles of titanium (Ti) in the second region 12b, the condition Re2 > Re1 > Rc can be satisfied.

[0101] Examples of rare earth elements other than dysprosium (Dy) include lantanum (La), yttrium (Y), actinium (Ac), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0102] The dielectric layer 111 may contain a valence-fixed element. The type of valence-fixed element is not particularly limited, and in one embodiment, the dielectric layer 111 may contain vanadium (V) as the valence-fixed element. In this case, when Ret is the number of moles of rare earth elements per 100 moles of titanium (Ti) in the dielectric layer 111, and Vt is the number of moles of vanadium (V) per 100 moles of titanium (Ti), Vt / Ret can be greater than 0.056 and less than 0.222. If Vt / Ret is 0.056 or less, it is difficult to ensure TCC characteristics and reliability, and if Vt / Ret is 0.222 or more, the dielectric constant may decrease or the DC-bias characteristics may decrease.

[0103] Some of the tin (Sn) contained in the dielectric layer 111 can diffuse to the internal electrodes 121 and 122 through the firing process. Therefore, the internal electrodes 121 and 122 can contain not only nickel (Ni) but also tin (Sn).

[0104] Referring to Figure 8, interfaces 123 and 124 can be arranged between the internal electrodes 121 and 122 and the dielectric layer 111. Interfaces 123 and 124 can be formed by suppressing the diffusion of tin (Sn) contained in the dielectric layer 111 with a high concentration of nickel (Ni). As a result, interfaces 123 and 124 can form a peak value where the tin (Sn) content has its maximum value, as shown in Figure 9. The range of the peak value of the tin (Sn) content is not particularly limited, but when it is 0.55 moles or more per 100 moles of nickel (Ni), the effect of improving capacity, the characteristics of capacity change with temperature, and the effect of improving high-temperature reliability according to the present invention may become more pronounced.

[0105] On the other hand, referring to Figure 10, it can be confirmed that there is a region at the interface between the dielectric layer and the internal electrode where the tin (Sn) content is measured to be high, and in one embodiment, this region was defined as interface portions 123 and 124.

[0106] Referring to Figure 9, the interface can be defined as the region from the point where the nickel (Ni) content begins to decrease to 90 at% or less relative to the total elemental content excluding oxygen (O) in the internal electrode, up to 50 nm inward in the dielectric layer. Therefore, the internal electrodes 121 and 122 may be regions where the nickel (Ni) content exceeds 90 at% relative to the total elemental content excluding oxygen (O).

[0107] Referring to Figure 9, the peak value of the tin (Sn) content at the interface portions 123 and 124 can be formed to be biased towards the internal electrodes 121 and 122. The effect of capacity improvement, temperature-dependent capacity change characteristics, and high-temperature reliability according to the present invention can be made more pronounced.

[0108] Referring to Figure 9, when S1 is the average tin (Sn) content relative to the total elemental content excluding oxygen (O) in the internal electrodes 121 and 122, and S2 is the average tin (Sn) content relative to the total elemental content excluding oxygen (O) in the dielectric layer, the condition S1 > S2 can be satisfied. This delays the shrinkage of the internal electrodes 121 and 122 that occurs during the firing process, thereby improving the connectivity of the internal electrodes 121 and 122.

[0109] (Example of experiment) BaTiO3 particles corresponding to core 11 were synthesized using a hydrothermal synthesis method. During this process, the particle size of the BaTiO3 was synthesized to various sizes considering the size of core 11 in the final product. Subsequently, SnO2 was added to form the region that would become the first region 12a of the shell. A rare earth element oxide (Re2O3) was added as the first minor component, and terbium oxide (Tb4O7) was added in some cases. Vanadium oxide (V2O3) was added as the second minor component to promote grain growth and form the region that would become the second region 12b of the shell. After this, the dielectric powder was mixed with a dispersant using ethanol and toluene as solvents, and then a binder was added to fabricate a ceramic sheet. Ni electrodes were printed onto the molded ceramic sheet and laminated, then compressed and cut. The chips were calcined to remove the binder, and then fired to produce sample chips.

[0110] In this case, the maximum ferret diameter LC of the core 11 and the overall maximum ferret diameter LG of the dielectric crystal grains 10 may vary depending on the size of the initial BaTiO3 particles forming the core 11 and the size of the final dielectric crystal grains, which depends on the grain growth rate.

[0111] Table 1 below shows the maximum ferret diameter LC of core 11, the overall maximum ferret diameter LG of dielectric crystal grains 10, whether the first region 12a and the second region 12b of the shell are separated, and the content of each minor component for each test number. Table 2 shows the room-temperature dielectric constant and loss factor (DF, Dissipation Factor), change in capacitance with temperature, MTTF (Mean Time To Failure), and DC-bias characteristics determined for the final ceramic electronic component containing a dielectric layer that satisfies the conditions in Table 1.

[0112] The dielectric constant at room temperature and the dissipation factor (DF) were determined by measuring capacitance using an LCR meter under conditions of 1 kHz and AC 0.5 V. The dielectric constant of the MLCC chip dielectric was calculated from the capacitance, the dielectric thickness of the MLCC chip, the area of ​​the internal electrodes, and the number of layers. For DC effective capacitance, 10 samples were taken, measured after 60 seconds with a DC 3 V applied, and the average value was taken.

[0113] The change in capacitance due to temperature was measured under maintenance conditions of 1 kHz, 0.15 V, and 5 min in the temperature range of -55°C to 105°C. Ten samples were taken and measured, and the average value was then calculated.

[0114] The Mean Time To Failure (MTTF) value was calculated by applying a voltage corresponding to an electric field of 27 V / μm at 125°C to 10 samples, measuring the time it took for a failure to occur, and creating an average time. An MTTF of 20.1 hours or less was evaluated as poor (×), an MTTF exceeding 20.1 hours but 28 hours or less was evaluated as average (△), an MTTF exceeding 28 hours but 30 hours or less was evaluated as good (○), and an MTTF exceeding 30 hours was evaluated as excellent (◎).

[0115] DC-bias characteristic evaluation was performed on 10 samples using an LCR meter with a 3V DC bias voltage applied. The capacitance was measured by applying AC signals at low voltage and high frequency. A value of 0.78uF or less was evaluated as poor (×), a value exceeding 0.78uF but 0.82uF or less was evaluated as average (△), a value between 0.83uF and less than 0.87uF was evaluated as good (○), and a value of 0.87uF or more was evaluated as excellent (◎).

[0116] The final overall performance evaluation was as follows: if one or more of the individual characteristics of the example were defective, it was rated as poor (×); if there were no defects among the individual characteristics of the example but one or more were average, it was rated as average (△); and if all of the characteristics of the example were good or better, it was rated as excellent (◎).

[0117] [Table 1]

[0118] [Table 2]

[0119] Referring to Tables 1 and 2, for test numbers 8 to 31 where the LC / LG ratio is between 0.49 and 0.73, the TCC characteristics are normal (△) or better, and the DC characteristics are normal (△) or better, regardless of the content of the first and second subcomponents. In contrast, when the LC / LG ratio is less than 0.49, both the TCC characteristics and DC characteristics are poor (×), regardless of the content of the first and second subcomponents. Furthermore, for test numbers 8 to 31, the dielectric constant at room temperature exceeds 3300 in all cases, confirming that there is no decrease in dielectric constant.

[0120] Therefore, as in one embodiment of the present invention, when the LC / LG ratio is between 0.49 and 0.73, it can be confirmed that excellent dielectric constant, TCC characteristics, and DC characteristics of the ceramic electronic component 100 can be ensured.

[0121] On the other hand, in the case of test numbers 29-31 where the LC / LG exceeds 0.64, it can be confirmed that the MTTF is poor (×) regardless of the content of the first and second minor components. Therefore, in one example, if the LC / LG satisfies the range of 0.49 to 0.64, TCC characteristics and DC characteristics can be ensured, and the phenomenon of reduced reliability due to an excessive specific gravity of the core relative to the total crystal grains can be suppressed.

[0122] Although embodiments of the present invention have been described in detail above, the present invention is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims provided. Therefore, within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, and these also fall within the scope of the present invention.

[0123] Furthermore, the expression "one embodiment" used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and explain the unique and distinct features of each embodiment. However, the above-presented embodiments do not preclude their implementation in combination with features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a contradictory or contrary explanation of that matter in the other embodiment.

[0124] The terms used in this disclosure are used solely to illustrate one embodiment and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of Symbols]

[0125] 100 Ceramic Electronic Components 110 Main Unit 111 Dielectric layer 121, 122 Internal electrode 123, 124 Interface part 130, 140 external electrode 112, 113 Cover section 114, 115 Margin section 10 Dielectric crystal grains 11 cores 12 shells 12a 1st area 12b Second area

Claims

1. A dielectric layer containing multiple dielectric crystal grains, and a main body containing internal electrodes, Includes an external electrode disposed on the main body and connected to the internal electrode, One or more of the plurality of dielectric crystal grains include titanium (Ti), tin (Sn), and dysprosium (Dy), and includes a core and a shell surrounding at least a portion of the core. The core has a tin (Sn) content of less than 0.2 moles per 100 moles of titanium (Ti), and a dysprosium (Dy) content of less than 0.1 moles per 100 moles of titanium (Ti). The shell includes a first region in which the number of moles of tin (Sn) per 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti), and a second region in which the number of moles of dysprosium (Dy) per 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) per 100 moles of titanium (Ti). When the maximum ferret diameter of the dielectric crystal grains including the core and the shell is LG, and the maximum ferret diameter of the core is LC, LC / LG is a ceramic electronic component that satisfies the requirement of 0.49 to 0.

73.

2. The internal electrode comprises nickel (Ni) and tin (Sn), When the interface is defined as the region from the point where the nickel (Ni) content begins to decrease to 90 at% or less relative to the total elemental content of the internal electrode excluding oxygen (O) to 50 nm in the inward direction of the dielectric layer, The ceramic electronic component according to claim 1, wherein the interface has a peak value of tin (Sn) content of 0.55 moles or more per 100 moles of nickel (Ni).

3. The internal electrode comprises nickel (Ni) and tin (Sn), In the aforementioned internal electrode, the average content of tin (Sn) is given by S1 with respect to the total elemental content excluding oxygen (O). In the dielectric layer, when S2 is the average content of tin (Sn) with respect to the total elemental content excluding oxygen (O), A ceramic electronic component according to claim 1, satisfying S1 > S2.

4. The ceramic electronic component according to claim 1, wherein the nickel (Ni) content of the internal electrode exceeds 90 at% of the total elements excluding oxygen (O).

5. The ceramic electronic component according to claim 1, wherein the tin (Sn) content in the first region is 0.2 moles or more and 4.5 moles or less per 100 moles of titanium (Ti).

6. The ceramic electronic component according to claim 1, wherein the average content of tin (Sn) per 100 moles of titanium (Ti) in the first region is at least twice the average content of tin (Sn) per 100 moles of titanium (Ti) in the second region.

7. The average content of tin (Sn) in the core is Sc, relative to 100 moles of titanium (Ti). In the first region, the average content of tin (Sn) per 100 moles of titanium (Ti) is S1. When S2 is the average content of tin (Sn) per 100 moles of titanium (Ti) in the second region, A ceramic electronic component according to claim 1, satisfying S1 > S2 > Sc.

8. The average content of dysprosium (Dy) per 100 moles of titanium (Ti) in the aforementioned core is Dc. In the first region, the average content of dysprosium (Dy) per 100 moles of titanium (Ti) is D1. When D2 is the average content of dysprosium (Dy) per 100 moles of titanium (Ti) in the second region, A ceramic electronic component according to claim 1, satisfying D2 > D1 > Dc.

9. The ceramic electronic component according to claim 8, wherein Dc and D1 are each 0.04 moles or less.

10. The dielectric layer further contains one or more rare earth elements other than dysprosium (Dy), The average content of rare earth elements, including dysprosium (Dy), per 100 moles of titanium (Ti) in the aforementioned core is defined as Rec. In the first region, the average content of rare earth elements, including dysprosium (Dy), per 100 moles of titanium (Ti) is defined as Re1. When the average content of rare earth elements, including dysprosium (Dy), in the second region is Re2 relative to 100 moles of titanium (Ti), A ceramic electronic component according to claim 1, satisfying Re2 > Re1 > Rc.

11. The ceramic electronic component according to claim 10, wherein the rare earth element is lanthanum (La), yttrium (Y), actinium (Ac), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

12. The dielectric layer contains vanadium (V) as a valence-fixed element. In the dielectric layer, when Ret is the number of moles of rare earth elements per 100 moles of titanium (Ti) and Vt is the number of moles of vanadium (V) per 100 moles of titanium (Ti), A ceramic electronic component according to any one of claims 1 to 11, wherein Vt / Ret satisfies the condition greater than 0.056 and less than 0.

222.

13. The ceramic electronic component according to any one of claims 1 to 11, wherein the area of ​​the core is larger than the area of ​​the first region, and the area of ​​the second region is larger than the area of ​​the first region.

14. The ceramic electronic component according to any one of claims 1 to 11, wherein the area of ​​the core is greater than the sum of the area of ​​the first region and the area of ​​the second region.

15. A ceramic electronic component according to any one of claims 1 to 11, wherein LC / LG satisfies 0.49 or more and 0.63 or less.

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