Contact Integration in Complementary Field-Effect Transistor (CFET) Devices

Abstract

A semiconductor structure forming a complementary field-effect transistor (CFET) includes a first common metal gate, a second common metal gate, and a bottom field-effect transistor (FET) module comprising a pair of bottom common source / drain (S / D) contacts, which are electrically connected to each other via a first direction through the first common metal gate through a first bottom S / D epitaxial (epi) region and via the second common metal gate through a second bottom S / D epi region. The upper FET module includes an FET module and an upper FET module stacked on the bottom FET module in a second direction orthogonal to the first direction, the upper FET module comprising: an upper common S / D contact; a first upper S / D contact electrically connected to the upper common S / D contact through a first common metal gate in the first direction via a first upper S / D epitaxial region; and a second upper S / D contact electrically connected to the upper common S / D contact through a second common metal gate in the first direction via a second upper S / D epitaxial region.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 468,646, filed on 24 May 2023, which is incorporated herein by reference in its entirety.

[0002]

[0002] The embodiments described herein generally relate to semiconductor device manufacturing, and more specifically to contact integration in complementary field-effect transistor (CFET) devices. [Background technology]

[0003] Description of related technologies

[0003] It has been proposed to continue scaling beyond the physical limits of planar metal oxide semiconductor field-effect transistors (MOSFETs), three-dimensional FinFETs, multilayer nanosheet gate all-around FETs (GAA FETs), and complementary FETs (CFETs). In CFET architectures, n-devices and p-devices are stacked vertically from each other, eliminating the np spacing from the standard cell height. In currently proposed architectures, n-FETs and p-FETs stacked vertically in a single row are controlled by a common gate, resulting in a reduction in the device footprint, but routing of wiring through the metal layer is still required. Therefore, improvements to the CFET architecture are needed to further reduce the device footprint and the total length of the wiring metal in order to reduce parasitic resistance. [Overview of the project]

[0004]

[0004] Embodiments of the present disclosure provide a semiconductor structure for forming a complementary field-effect transistor (CFET). The semiconductor structure includes a first common metal gate, a second common metal gate, and a bottom field-effect transistor (FET) module, which includes a pair of bottom common source / drain (S / D) contacts, electrically connected to each other through the first common metal gate in a first direction via a first bottom S / D epitaxial (epi) region and through the second common metal gate in a first direction via a second bottom S / D epi region, and An upper FET module stacked on the bottom FET module in a second direction orthogonal to the first direction, the upper FET module includes an upper common S / D contact, a first upper S / D contact electrically connected to the upper common S / D contact through a first common metal gate in the first direction via a first upper S / D epitaxial region, and a second upper S / D contact electrically connected to the upper common S / D contact through a second common metal gate in the first direction via a second upper S / D epitaxial region.

[0005]

[0005] Embodiments of the present disclosure provide a method for forming a complementary field-effect transistor (CFET). The method involves performing an upper contact trench patterning process to form a first upper trench in a first front upper S / D epitaxial region, a second upper trench in a second front upper S / D epitaxial region, and a third upper trench in a first rear upper S / D epitaxial region and a second rear upper S / D epitaxial region, wherein the first front upper S / D epitaxial region and the first rear upper S / D epitaxial region are electrically connected via a first common metal gate, and the second front upper S / D epitaxial region and the second rear upper The process involves performing an upper contact trench patterning process in which the S / D epitaxial region is electrically connected via a second common metal gate, and performing an upper contact via patterning process to form a first via entering the first front bottom S / D epitaxial region through the first front upper S / D epitaxial region, and a second via adjacent to the second front upper S / D epitaxial region and the second front bottom S / D epitaxial region, wherein the first front bottom S / D epitaxial region and the first rear bottom S / D epitaxial region are electrically connected via a first common metal gate Performing an upper contact via patterning process, wherein the second front bottom S / D epitaxial region and the second rear bottom S / D epitaxial region are electrically connected via a gate, and the upper metal filling process is performed to place a first upper S / D contact in the first upper trench, a second upper S / D contact in the second upper trench, an upper common S / D contact in the third upper trench, and a first via contact in the first via, The method includes forming a second via contact within the second via; performing a bottom contact trench patterning process to form a first bottom trench in the first bottom front S / D epitaxial region and the second bottom front S / D epitaxial region, and a second bottom trench in the first bottom rear S / D epitaxial region and the second bottom rear S / D epitaxial region; and performing a bottom metal filling process to form a common bottom S / D contact inside the first bottom trench and the second bottom trench, respectively.

[0006]

[0006] Embodiments of the present disclosure provide a method for forming a complementary field-effect transistor (CFET). The method involves performing an upper contact trench patterning process to form a first upper trench in a first front upper S / D epitaxial region, a second upper trench in a second front upper S / D epitaxial region, and a third upper trench in a first rear upper S / D epitaxial region and a second rear upper S / D epitaxial region, wherein the first front upper S / D epitaxial region and the first rear upper S / D epitaxial region are electrically connected via a first common metal gate, and the second front upper S / D epitaxial region and the second rear upper The process involves performing an upper contact trench patterning process in which the S / D epitaxial regions are electrically connected via a second common metal gate, and performing an upper contact via patterning process to form a first via adjacent to the first front upper S / D epitaxial region and the first front bottom S / D epitaxial region, and a second via adjacent to the second front upper S / D epitaxial region and the second front bottom S / D epitaxial region, wherein the first front bottom S / D epitaxial region and the first rear bottom S / D epitaxial region are electrically connected via a first common metal gate. Performing an upper contact via patterning process, wherein the second front bottom S / D epitaxial region and the second rear bottom S / D epitaxial region are electrically connected via a gate, and the upper metal filling process is performed to place a first upper S / D contact in the first upper trench, a second upper S / D contact in the second upper trench, an upper common S / D contact in the third upper trench, and a first via contact in the first via, The method includes forming a second via contact within the second via; performing a bottom contact trench patterning process to form a first bottom trench in the first bottom front S / D epitaxial region and the second bottom front S / D epitaxial region, and a second bottom trench in the first bottom rear S / D epitaxial region and the second bottom rear S / D epitaxial region; and performing a bottom metal filling process to form a common bottom S / D contact inside the first bottom trench and the second bottom trench, respectively.

[0007]

[0007] To better understand the features of the present disclosure listed above, a more detailed description of the present disclosure briefly summarized above can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate exemplary embodiments and should not be considered as limiting the scope of the present disclosure. The present disclosure may allow other equally effective embodiments.

Brief Description of the Drawings

[0008] [Figure 1] It is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure. [Figure 2A-2B] It is an isometric view of a part of a semiconductor structure 200 that can form a complementary metal-oxide-semiconductor field-effect transistor (CFET) with a cell height twice the design according to one or more embodiments of the present disclosure. In FIG. 2B, the semiconductor structure 200 under the upper metal layer is shown. [Figure 2C] It shows an exemplary NAND gate circuit corresponding to a part of the semiconductor structure 200 shown in FIG. 2A. [Figure 3] It shows a process flow diagram of a method for forming cell transistors in a semiconductor structure according to one embodiment. [Figure 4A-4H] It is an isometric view of a part of a semiconductor structure corresponding to various states of the method in FIG. 3.

Modes for Carrying Out the Invention

[0009]

[0012] For ease of understanding, the same reference numbers are used to denote the same elements common to the figures where possible. Even without further description, it is considered that the elements and features of one embodiment can be beneficially incorporated into other embodiments. In the figures and the following description, a Cartesian coordinate system including the X-axis, Y-axis, and Z-axis is used. The directions represented by the arrows in the drawings are assumed to be the positive directions for convenience. It is assumed that some of the elements disclosed in some embodiments can be beneficially utilized in other embodiments without specific description.

[0010]

[0013] The embodiments described herein provide a double-cell-height structure for complementary FET (CFET) devices. In conventional CFET architectures, n-FET and p-FET devices stacked vertically in a single row may be controlled by a common gate connected to a metal layer (called a single-cell-height structure). In a double-cell-height structure, two stacks of n-FETs and p-FETs are interconnected and controlled by two common gates. The double-cell-height structure effectively reduces routing congestion and minimizes the complexity of CFET routing. As a result, shorter wiring lengths reduce the parasitic resistance of the CFET devices.

[0011]

[0014] Figure 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 including their respective transfer robots 112, 114, holding chambers 116, 11 and 8, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, substrates within the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to the ambient environment outside the processing system 100 (e.g., the atmospheric environment that may be present in the factory). For example, substrates can be processed in various chambers and transferred between various chambers during various processes performed on the substrates within the processing system 100, without disrupting the low-pressure or vacuum environment, while being maintained in a low-pressure (e.g., about 300 Torr or less) or vacuum environment. Therefore, the processing system 100 can provide an integrated solution for processing a portion of the substrate.

[0012]

[0015] Examples of processing systems that can be appropriately modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems, commercially available from Applied Materials, Inc. in Santa Clara, California, or other suitable processing systems. Other processing systems (including those from other manufacturers) may be adapted to benefit from the embodiments described herein.

[0013]

[0016] In the illustrated example in Figure 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 for facilitating substrate transfer. The docking station 132 is adapted to receive one or more front-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 located at one end of the respective factory interface robot 134, adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0014]

[0017] The load lock chambers 104 and 106 have ports 140 and 142 connected to the factory interface 102, respectively, and ports 144 and 146 connected to the transfer chamber 108, respectively. The transfer chamber 108 further has ports 148 and 150 connected to the holding chambers 116 and 118, respectively, and ports 152 and 154 connected to the processing chambers 120 and 122, respectively. Similarly, the transfer chamber 110 has ports 156 and 158 connected to the holding chambers 116 and 118, respectively, and ports 160, 162, 164, and 166 connected to the processing chambers 124, 126, 128, and 130, respectively. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 may be slit valve openings, for example, for passing substrates by transfer robots 112 and 114, and for providing a seal between each chamber to prevent gas from passing between them. Generally, any port is open for transferring substrates. Otherwise, the port is closed.

[0015]

[0018] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidly connected to a gas and pressure control system (not shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and fluid-connected conduits to various chambers. During operation, the factory interface robot 134 transfers the substrate from the FOUP 136 to the load lock chamber 104 or 106 via port 140 or 142. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 in an internal low-pressure or vacuum environment (which may include an inert gas). Thus, the pumping down of the load lock chamber 104 or 106 facilitates the passage of the substrate between, for example, the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

[0016]

[0019] With the substrate in the load lock chamber 104 or 106 pumped down, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 through port 144 or 146 into the transfer chamber 108. The transfer robot 112 can then transfer the substrate to either the processing chambers 120 or 122 via their respective processing ports 152 or 154, and to the holding chambers 116 or 118 via their respective ports 148 or 150 to hold it awaiting further transfer. Similarly, the transfer robot 114 can access the substrate in the holding chamber 116 or 118 via port 156 or 158 and transfer the substrate to either the processing chambers 124, 126, 128 or 130 via their respective ports 160, 162, 164 or 166, and to the holding chambers 116 or 118 via their respective ports 156 or 158 to hold it awaiting further transfer. The transfer and holding of substrates within and between various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0017]

[0020] Processing chambers 120, 122, 124, 126, 128, and 130 can be any suitable chamber for processing the substrate. In some embodiments, processing chamber 120 can perform etching, processing chamber 122 can perform cleaning, processing chamber 124 can perform selective removal, processing chamber 126 can perform chemical vapor deposition (CVD), and processing chambers 128 and 130 can perform their respective epitaxial growth processes. Processing chamber 120 is available from Selectra, which is available from Applied Materials in Santa Clara, California. TM It may also be an etching chamber. The processing chamber 122 is made of SiCoNi, which is available from Applied Materials in Santa Clara, California. TM A pre-wash chamber may also be used. The processing chamber 126 is available from W×Z, which is available from Applied Materials in Santa Clara, California. TM It may also be a chamber. Processing chamber 128 or 130 is available from Centura, which is available from Applied Materials in Santa Clara, California. TM Epi chamber is also acceptable.

[0018]

[0021] A system controller 168 is connected to the processing system 100 to control the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 by using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130 of the processing system 100, or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130. During operation, the system controller 168 enables data collection and feedback from each chamber to adjust the performance of the processing system 100.

[0019]

[0022] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuitry 174. The CPU 170 may be any form of general-purpose processor that can be used in an industrial setting. The memory 172, or non-temporary computer-readable medium, is accessible by the CPU 170 and may be one or more of the following types of memory: random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or other forms of local or remote digital storage. The support circuitry 174 is connected to the CPU 170 and may include a cache, clock circuitry, input / output subsystems, power sources, etc. Various methods disclosed herein can generally be implemented by the CPU 170 executing computer instruction code stored, for example, as software routines in memory 172 (or memory of a particular process chamber) under the control of the CPU 170. Once the computer instruction code is executed by the CPU 170, the CPU 170 controls the chamber to execute a process according to various methods.

[0020]

[0023] Other processing systems can also be configured in other ways. For example, more or fewer processing chambers can be connected to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transfer devices within the processing system.

[0021]

[0024] Figures 2A and 2B are isometric views of a portion of a semiconductor structure 200 that can form a complementary field-effect transistor (CFET) in a design with double the cell height according to one or more embodiments of the present disclosure. Figure 2B shows the semiconductor structure 200 below the upper metal layer. Figure 2C shows an exemplary NAND gate circuit corresponding to a portion of the semiconductor structure 200 shown in Figure 2A.

[0022]

[0025] The NAND gate circuit in FIG. 2C includes transistors Q1, Q2, Q3, and Q4. The first input terminal A is connected to the gate terminals of transistors Q1 and Q2. The second input terminal B is connected to the gate terminals of transistors Q3 and Q4. Transistors Q1 and Q3 are n-channel transistors and are connected in series between a reference voltage V SS (e.g., ground) and the output terminal C. Transistors Q2 and Q4 are p-channel transistors and are connected in parallel between the output terminal C and a power supply voltage V DD (e.g., a positive voltage with respect to the reference voltage V SS ). The output terminal C is connected to the drain terminals of transistors Q1, Q2, and Q4.

[0023]

[0026] The semiconductor structure 200 shown in FIGS. 2A and 2B includes a bottom field effect transistor (FET) module TR B , and an upper FET module TR B stacked in the Z direction above the bottom FET module TR T . In one embodiment, the bottom FET module TR B includes p-channel transistors Q2 and Q4, and the upper FET module TR TThis includes n-channel transistors Q1 and Q3. Transistor Q1 is formed from a common metal gate 202L, a source / drain (S / D) contact 204TL electrically connected to one end of a channel layer (not shown) extending in the Y direction through the common metal gate 202L via an S / D epitaxial (epi) region 206TL, and a common S / D contact 204T electrically connected to the other end of the channel layer via another S / D epitaxial region 206TL. Transistor Q2 is formed from a common metal gate 202L and a common S / D contact 204B, each electrically connected to one end of a channel layer (not shown) extending in the Y direction through the common metal gate 202L via an S / D epitaxial region 206BL. Transistor Q3 is formed from a common metal gate 202R, an S / D contact 204TR electrically connected to one end of a channel layer (not shown) extending in the Y direction through the common metal gate 202R via an S / D epitaxial region 206TR, and a common S / D contact electrically connected to the other end of the channel layer via another S / D epitaxial region 206TR. Transistor Q4 is formed from a common metal gate 202R and a common S / D contact 204B, each electrically connected to one end of a channel layer (not shown) extending in the Y direction through the common metal gate 202R via an S / D epitaxial region 206BR. Bottom FET module TR B The S / D epitaxial regions 206BL and 206BR within the S / D epitaxial region are approximately 10 depending on the desired conductivity characteristics of the S / D epitaxial regions 206BL and 206BR. 20 cm -3 From 5x10 21 cm -3 It may be doped with a p-type dopant such as boron (B) or gallium (Ga) at the specified concentration. Upper FET module TR T The S / D epitaxial regions 206TL and 206TR within the S / D epitaxial region are approximately 10 depending on the desired conductivity characteristics of the S / D epitaxial regions 206TL and 206TR. 20 cm -3 From 5x10 21 cm -3 It can be doped with n-type dopants such as phosphorus (P), arsenic (As), or antimony (Sb) at concentrations. In some other embodiments, the bottom FET module TRB The internal S / D epitaxial regions 206BL and 206BR may be doped with an n-type dopant, and the upper FET module TR T The S / D epiregions 206TL and 206TR within the molecule may be doped with a p-type dopant.

[0024]

[0027] The common metal gate 202L of transistors Q1 and Q2 is in the Z direction, above the FET module TR T It is positioned above and electrically connected to a metal layer 208A (not shown in Figure 2B) which is electrically connected to the first input terminal A via a contact plug 210A (shown in Figure 2B). The common metal gate 202R of transistors Q3 and Q4 is in the Z direction of the upper FET module TR T It is positioned above and electrically connected to a metal layer 208B (not shown in Figure 2B) which is electrically connected to the second input terminal B via a contact plug 210B. The drain contact 204TL of transistor Q1 and the common drain contact 204B of transistors Q2 and Q4 are connected in the Z direction to the upper FET module TR T It is positioned above and connected to a metal layer 208C (not shown in Figure 2B) which is electrically connected to the output terminal C via contact plug 210C and via contact 212L. The common drain contact 204B of transistors Q2 and Q4 is connected in the Z direction to the bottom FET module TR B It is located below and, via a contact plug (not shown), the power supply voltage V DD (For example, reference voltage V SS It is connected to a metal layer 208DD (not shown in Figure 2B) which is electrically connected to a positive voltage (towards ). The source contact 204TR of transistor Q3 is connected to the bottom FET module TR in the Z direction. B It is positioned below and a reference voltage V is applied via the contact plug 210SS and via contact 212R. SS It is electrically connected to a metal layer 208SS that is electrically connected to (for example, ground).

[0025]

[0028] The common metal gates 202L and 202R, S / D contacts 204TL and 204TR, common S / D contacts 204T and 204B, metal layers 208A, 208B, 208C, 208DD, and 208SS, contact plugs 210A, 210B, 210C, and 210SS, and via contacts 212L and 212R may be formed from tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), conductive oxides or nitrides thereof, or any combination thereof. The S / D epitaxial regions 206TL, 206BL, 206TR, and 206BR may be formed from epitaxially grown silicon (Si) or silicon germanium (SiGe). Channel layers (not shown) extending through common metal gates 202L and 202R may be formed from silicon (Si), germanium (Ge), silicon germanium (SiGe), or indium gallium zinc oxide (IGZO).

[0026]

[0029] The surfaces of the common metal gates 202L and 202R along the ZX plane are made of silicon carbide (SiO2). x C y The S / D contacts 204TL and 204TR, common S / D contacts 204T and 204B, S / D epitaxial regions 206TL, 206BL, 206TR, and 206BR, and via contacts 212L and 212R are embedded within interlayer dielectrics (ILDs) (not shown) formed of silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), or any combination thereof. The contact plugs 210A and 210B are encapsulated in dielectric layers (illustrated) formed of silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), or any combination of carbon-doped materials (e.g., silicon oxycarbide (SiOC), silicon oxycarbonite (SiOCN), or silicon carbon nitride (SiCN)).

[0027]

[0030] In the double-cell-height design shown in Figures 2A and 2B, transistors Q1 and Q3 are connected by a common S / D contact 204T, and transistors Q2 and Q4 are connected via a common S / D contact 204B. Therefore, routing through the metal layer required in the single-cell-height design is not necessary. Thus, the routing requirements within the metal layer are relaxed in the double-cell-height design.

[0028]

[0031] Figure 3 shows a process flow diagram of a method 300 for forming a semiconductor structure 400, which may be a semiconductor structure 200 forming part of a complementary field-effect transistor (CFET) according to one or more embodiments of the present disclosure. Figures 4A, 4A', 4B', 4C, 4C', 4D, 4D', 4E, 4E', 4F, 4F', 4G, 4G', 4H, and 4H' are isometric views of parts of the semiconductor structure 400 corresponding to various states of method 300. Figures 4A, 4A', 4B', 4C, 4C', 4D', 4E', 4E', 4F, 4F', 4G, 4G', 4H, and 4H' show only partial schematic diagrams of the semiconductor structure 400, and it should be understood that the semiconductor structure 400 may include any number of transistor sections and additional materials having the embodiments shown in the figures. Furthermore, while the method shown in Figure 3 will be described sequentially, it should be noted that other processing sequences, including one or more steps that are omitted and / or added and / or rearranged in a different desired order, are included within the scope of the embodiments of disclosure described herein.

[0029]

[0032] As shown in Figures 4A and 4A', the semiconductor structure 400 includes common metal gates 202L and 202R extending along the ZX plane, S / D epitaxial regions 206TL on the front and back of a channel layer (not shown) extending through the common metal gate 202L in the Y direction, S / D epitaxial regions 206BL on the front and back of a channel layer (not shown) extending through the common metal gate 202L in the Y direction, S / D epitaxial regions 206TR on the front and back of a channel layer (not shown) extending through the common metal gate 202R in the Y direction, and S / D epitaxial regions BR on the front and back of the common metal gate 202R in the Y direction. The S / D epitaxial regions 206TL, 206BL, 206TR, and 206BR on the front of the common metal gates 202L and 202R are fully shown in Figure 4A. The rear S / D epitaxial regions 206TL, 206BL, 206TR, and 206BR of the common metal gates 202L and 202R are fully shown in Figure 4A'. The bottom of the semiconductor structure 400, including the S / D epitaxial regions 206BL and 206BR, is a bottom field-effect transistor (FET) module TR B The upper part of the semiconductor structure 400, which includes S / D epitaxial regions 206TL and 206TR, is located in the Z direction, with the bottom FET module TR B The upper FET module TR stacked on top T It forms.

[0030]

[0033] The common metal gates 202L and 202R may be formed from tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), conductive oxides or nitrides, or any combination thereof. The S / D epitaxial regions 206TL, 206BL, 206TR, and 206BR may be formed from epitaxially grown silicon (Si) or silicon germanium (SiGe). Bottom FET module TR B The S / D epitaxial regions 206BL and 206BR within the S / D epitaxial regions 206BL and 206BR contain approximately 10 phosphorus (P), arsenic (As), or antimony (Sb), depending on the desired conductivity characteristics of the S / D epitaxial regions 206BL and 206BR. 20 cm-3 From 5x10 21 cm -3 It can be doped with an n-type dopant at a concentration of . Upper FET module TR T The S / D epitaxial regions 206TL and 206TR within the S / D epitaxial region are approximately 10 depending on the desired conductivity characteristics of the S / D epitaxial regions 206TL and 206TR. 20 cm -3 From 5x10 21 cm -3 It may be doped with a p-type dopant such as boron (B) or gallium (Ga) at the concentration. In some other embodiments, the bottom FET module TR B The internal S / D epitaxial regions 206BL and 206BR may be doped with a p-type dopant, and the upper FET module TR T The S / D epiregions 206TL and 206TR within the module may be doped with an n-type dopant.

[0031]

[0034] The channel layer (not shown) extending through the common metal gates 202L and 202R may be formed of silicon (Si), germanium (Ge), silicon germanium (SiGe), or indium gallium zinc oxide (IGZO).

[0032]

[0035] The surfaces of the common metal gates 202L and 202R along the ZX plane are made of silicon carbide (SiO2). x C y The S / D epitaxial regions 206TL, 206BL, 206TR, and 206BR are covered by spacers (not shown) formed of dielectric materials such as silicon nitride (Si3N4).

[0033]

[0036] Method 300 begins in block 310. In block 310, an upper contact trench patterning process is performed, as shown in Figures 4B and 4B', to form trenches 402TL, 402TR, and 404T. Trenches 402TL, 402TR, and 404T are formed by etching from the upper side of the semiconductor structure 400 into S / D epitaxial regions 206TL and 206TR and adjacent ILDs (not shown) to the S / D epitaxial regions 206TL and 206TR. The upper contact trench patterning process may include any suitable lithography and etching processes, such as photolithography and reactive ion etching (RIE) performed in a processing chamber, such as processing chamber 120 shown in Figure 1, and any suitable deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in a processing chamber, such as processing chambers 126, 128, or 130 shown in Figure 1.

[0034]

[0037] In block 320, an upper contact via patterning process is performed to form vias 406L and 406R, as shown in Figures 4C and 4C'. Via 406L is formed by etching from the upper side of the semiconductor structure 400 into the S / D epitaxial region 206TL through the S / D epitaxial region 206TL and MDI (not shown) between S / D epitaxial regions 206TL and 206BL. Via 406R is formed by etching from the upper side of the semiconductor structure 400 through the ILD (not shown) adjacent to the S / D epitaxial regions 206TR and 206BR. Thus, compared to an alternative embodiment in which via 406L is formed by etching through the ILD (not shown) adjacent to the S / D epitaxial regions 206TL and 206BL (either through the S / D epitaxial region 206TL or within the S / D epitaxial region 206BL), as shown in Figures 4D and 4D', the area over which vias 444 are formed is greater. However, in an alternative embodiment, the etching process is via ILD only, and therefore damage to the S / D epitaxial region 206TL or S / D epitaxial region 206BL can be avoided during the etching process.

[0035]

[0038] The upper contact via patterning process may include any suitable lithography and etching processes, such as photolithography and reactive ion etching (RIE), performed in a processing chamber such as processing chamber 120 shown in Figure 1, as well as any suitable deposition processes, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0036]

[0039] In block 330, as shown in Figures 4E and 4E' or 4F and 4F', an upper metal filling process is performed to form S / D contact 204TL in trench 402TL, S / D contact 204TR in trench 402TR, common S / D contact 204T in trench 404T, via contact 212L in via 406L, and via contact 212R in via 406R. The upper metal filling process may include forming metal silicides at the interfaces with the S / D epitaxial regions 206TL, 206BL, and 206TR in trenches 402TL, 402TR, and 404T, as well as in vias 406L and 406R, and filling trenches 402TL, 402TR, and 404T, as well as vias 406L and 406R, with a metal filling material. Metallic silicides may be titanium silicide (TiSi, TiSi2), nickel silicide (NiSi, Ni2Si), molybdenum silicide (MoSi, MoSi2), cobalt silicide (CoSi2), tantalum silicide (TaSi2), or any combination thereof. Metal filler materials may be tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), conductive oxides or nitrides thereof, or any combination thereof.

[0037]

[0040] The upper metal filling process may include any suitable deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or one performed within a processing chamber (e.g., processing chambers 126, 128, or 130 shown in Figure 1)).

[0038]

[0041] In block 340, a bottom contact trench patterning process is performed to form trenches 408, as shown in Figures 4E and 4E' or Figures 4F and 4F'. Trenches 408 are formed by etching from the bottom surface of the semiconductor structure 400 to S / D epitaxial regions 206BL and 206BR and adjacent ILDs (not shown) to S / D epitaxial regions 206BL and 206BR. The bottom contact trench patterning process may include any suitable lithography and etching process, such as photolithography and reactive ion etching (RIE) performed in a processing chamber, such as processing chamber 120 shown in Figure 1, and any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) performed in a processing chamber, such as processing chambers 126, 128, or 130 shown in Figure 1.

[0039]

[0042] In block 350, a bottom metal filling process is performed as shown in Figures 4G and 4G' or Figures 4H and 4H' to form a common S / D contact 204B within the trench 408. The bottom metal filling process may include forming a metal silicide at the interface with the S / D epitaxial regions 206BL and 206BR within the formed trench 408, and filling the trench 408 with a metal filling material to form the common S / D contact 204B. The metal silicide may be titanium silicide (TiSi, TiSi2), nickel silicide (NiSi, Ni2Si), molybdenum silicide (MoSi, MoSi2), cobalt silicide (CoSi2), tantalum silicide (TaSi2), or any combination thereof. The metal filler material may be tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), conductive oxides or nitrides thereof, or any combination thereof.

[0040]

[0043] The bottom metal filling process may include any suitable deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or one performed in a processing chamber (e.g., processing chambers 126, 128, or 130 shown in Figure 1)).

[0041]

[0044] The embodiments described herein provide a method for complementary FET (CFET) devices. In the method described herein, dummy contacts are deposited in place of the bottom source / drain (S / D) contacts for the bottom FET module of the CFET before high-temperature processing such as epitaxial deposition processes and substitution metal gate processes, and are then replaced with bottom S / D contacts formed of metal. This replacement S / D contact allows the use of the most optimized material for the bottom S / D contacts in the bottom FET module without thermal balance constraints.

[0042]

[0045] In the complementary FET (CFET) device with double the cell height according to the embodiments described herein, two stacks of n-FETs and p-FETs are interconnected by common S / D contacts and controlled by two common gates. The internal connection between the FET devices reduces routing through the metal layer above the FET devices, minimizing the routing complexity of the CFET device. Furthermore, the length of the wiring is shortened due to the absence of routing through the metal layer, and therefore the parasitic resistance of the CFET device is reduced.

[0043]

[0046] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A semiconductor structure that forms a complementary field-effect transistor (CFET), The first common metal gate, The second common metal gate, This is a bottom field-effect transistor (FET) module, A pair of bottom common source / drain (S / D) contacts, electrically connected to each other via a first bottom S / D epitaxial (epi) region through a first common metal gate in a first direction, and via a second bottom S / D epi region through a second common metal gate in the first direction. This includes a bottom field-effect transistor (FET) module, An upper FET module stacked on the bottom FET module in a second direction perpendicular to the first direction, Upper common S / D contact, A first upper S / D contact electrically connected to the upper common S / D contact via the first upper S / D epitaxial region and the first common metal gate in the first direction, A second upper S / D contact is electrically connected to the upper common S / D contact via the second upper S / D epitaxial region through the second common metal gate in the first direction, The upper FET module includes, A semiconductor structure that includes this.

2. The semiconductor structure according to claim 1, wherein the first bottom S / D epitaxial region and the second bottom S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with a p-type dopant, and the first upper S / D epitaxial region and the second upper S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with an n-type dopant.

3. The semiconductor structure according to claim 1, wherein the first bottom S / D epitaxial region and the second bottom S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with an n-type dopant, and the first upper S / D epitaxial region and the second upper S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with a p-type dopant.

4. The semiconductor structure according to claim 1, further comprising a via contact for electrically connecting the first upper S / D contact to one of the pair of bottom common S / D contacts.

5. The semiconductor structure according to claim 4, wherein the via contact is formed in the first bottom S / D epitaxial region connected to one of the pair of bottom common S / D contacts, passing through the first upper S / D epitaxial region connected to the first upper S / D contact.

6. The second direction further includes a first bottom metal layer and a second bottom metal layer located beneath the bottom FET module, The semiconductor structure according to claim 5, wherein the other of the pair of bottom common S / D contacts is electrically connected to the first bottom metal layer, and the second upper S / D contact is electrically connected to the second bottom metal layer.

7. The upper FET module in the second direction further includes a first upper metal layer, a second upper metal layer, and a third upper metal layer, The first upper metal layer is electrically connected to the first common metal gate. The second upper metal layer is electrically connected to the second common metal gate. The third upper metal layer is electrically connected to the first upper S / D contact. The semiconductor structure according to claim 1.

8. The semiconductor structure according to claim 1, wherein the first common metal gate and the second common metal gate each contain tungsten (W), ruthenium (Ru), or molybdenum (Mo).

9. A method for forming a complementary field-effect transistor (CFET), The upper contact trench patterning process is performed to form a first upper trench in the first front upper S / D epitaxial region, a second upper trench in the second front upper S / D epitaxial region, and a third upper trench in the first rear upper S / D epitaxial region and the second rear upper S / D epitaxial region, The first front upper S / D epitaxial region and the first rear upper S / D epitaxial region are electrically connected via a first common metal gate. The second front upper S / D epitaxial region and the second rear upper S / D epitaxial region are electrically connected via a second common metal gate. Perform the upper contact trench patterning process, The process involves performing an upper contact via patterning to form a first via that enters the first front bottom S / D epitaxial region through the first front upper S / D epitaxial region, and a second via adjacent to the second front upper S / D epitaxial region and the second front bottom S / D epitaxial region, The first front bottom S / D epitaxial region and the first rear bottom S / D epitaxial region are electrically connected via a first common metal gate. The second front bottom S / D epitaxial region and the second rear bottom S / D epitaxial region are electrically connected via the second common metal gate. Perform the upper contact via patterning process, The process involves performing an upper metal filling process to form a first upper S / D contact in the first upper trench, a second upper S / D contact in the second upper trench, an upper common S / D contact in the third upper trench, a first via contact in the first via, and a second via contact in the second via. The bottom contact trench patterning process is performed to form a first bottom trench in the first bottom front S / D epitaxial region and the second bottom front S / D epitaxial region, and a second bottom trench in the first bottom rear S / D epitaxial region and the second bottom rear S / D epitaxial region. A bottom metal filling process is performed to form a common bottom S / D contact inside the first bottom trench and the second bottom trench, respectively. Methods that include...

10. The method according to claim 9, wherein the first common metal gate and the second common metal gate each contain tungsten (W), ruthenium (Ru), or molybdenum (Mo).

11. The first front upper S / D epitaxial region, the second front upper S / D epitaxial region, the first rear upper S / D epitaxial region, and the second rear upper S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with an n-type dopant. The first front bottom S / D epitaxial region, the second front bottom S / D epitaxial region, and the second rear bottom S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with a p-type dopant. The method according to claim 9.

12. The first front upper S / D epitaxial region, the second front upper S / D epitaxial region, the first rear upper S / D epitaxial region, and the second rear upper S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with a p-type dopant. The first front bottom S / D epitaxial region, the second front bottom S / D epitaxial region, the first rear bottom S / D epitaxial region, and the second rear bottom S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe). The method according to claim 9.

13. The aforementioned upper metal filling process, At the interface with the first front upper S / D epitaxial region within the first upper trench, at the interface with the second front upper S / D epitaxial region within the second upper trench, at the interface with the first rear upper S / D epitaxial region and the second rear upper S / D region within the third upper trench, and at the interface with the first front upper S / D epitaxial region and the first front bottom S / D epitaxial region within the first via, a metal silicide is formed. The first upper trench, the second upper trench, the third upper trench, the first via, and the second via are filled with a metal-filling material. Includes, The bottom metal filling process is A metal silicide is formed at the interface between the first bottom front S / D epitaxial region and the second bottom front S / D epitaxial region within the first bottom trench, and at the interface between the first bottom rear S / D epitaxial region and the second bottom rear S / D epitaxial region within the second bottom trench. The first bottom trench and the second bottom trench are filled with a metal filling material, The method according to claim 9, including the method described in claim 9.

14. The method according to claim 13, wherein the metal silicide comprises titanium silicide, nickel silicide, or molybdenum silicide, and the metal filler comprises tungsten (W), ruthenium (Ru), or molybdenum (Mo).

15. A method for forming a complementary field-effect transistor (CFET), The upper contact trench patterning process is performed to form a first upper trench in the first front upper S / D epitaxial region, a second upper trench in the second front upper S / D epitaxial region, and a third upper trench in the first rear upper S / D epitaxial region and the second rear upper S / D epitaxial region, The first front upper S / D epitaxial region and the first rear upper S / D epitaxial region are electrically connected via a first common metal gate. The second front upper S / D epitaxial region and the second rear upper S / D epitaxial region are electrically connected via a second common metal gate. Perform the upper contact trench patterning process, The process involves performing an upper contact via patterning process to form a first via adjacent to the first front upper S / D epitaxial region and the first front bottom S / D epitaxial region, and a second via adjacent to the second front upper S / D epitaxial region and the second front bottom S / D epitaxial region, The first front bottom S / D epitaxial region and the first rear bottom S / D epitaxial region are electrically connected via a first common metal gate. The second front bottom S / D epitaxial region and the second rear bottom S / D epitaxial region are electrically connected via the second common metal gate. Perform the upper contact via patterning process, The process involves performing an upper metal filling process to form a first upper S / D contact in the first upper trench, a second upper S / D contact in the second upper trench, an upper common S / D contact in the third upper trench, a first via contact in the first via, and a second via contact in the second via. The bottom contact trench patterning process is performed to form a first bottom trench in the first bottom front S / D epitaxial region and the second bottom front S / D epitaxial region, and a second bottom trench in the first bottom rear S / D epitaxial region and the second bottom rear S / D epitaxial region. A bottom metal filling process is performed to form a common bottom S / D contact inside the first bottom trench and the second bottom trench, respectively. Methods that include...

16. The method according to claim 15, wherein the first common metal gate and the second common metal gate each contain tungsten (W), ruthenium (Ru), or molybdenum (Mo).

17. The first front upper S / D epitaxial region, the second front upper S / D epitaxial region, the first rear upper S / D epitaxial region, and the second rear upper S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with an n-type dopant. The method according to claim 15, wherein the first front bottom S / D epitaxial region, the second front bottom S / D epitaxial region, the first rear bottom S / D epitaxial region, and the second rear bottom S / D epitaxial region are epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with a p-type dopant.

18. The first front upper S / D epitaxial region, the second front upper S / D epitaxial region, the first rear upper S / D epitaxial region, and the second rear upper S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with a p-type dopant. The first front bottom S / D epitaxial region, the second front bottom S / D epitaxial region, the first rear bottom S / D epitaxial region, and the second rear bottom S / D epitaxial region are made of epitaxially grown silicon (Si) or silicon germanium (SiGe) doped with an n-type dopant. The method according to claim 15.

19. The aforementioned upper metal filling process, A metal silicide is formed at the interface between the first bottom front S / D epitaxial region and the second bottom front S / D epitaxial region within the first bottom trench, and at the interface between the first bottom rear S / D epitaxial region and the second bottom rear S / D epitaxial region within the second bottom trench. The first bottom trench and the second bottom trench are filled with a metal filling material, The method according to claim 15, including the method described in claim 15.

20. The method according to claim 19, wherein the metal silicide comprises titanium silicide, nickel silicide, or molybdenum silicide, and the metal filler comprises tungsten (W), ruthenium (Ru), or molybdenum (Mo).

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