Ideal diode bridge controller

Abstract

An ideal diode bridge controller is provided, which includes gate drivers connected to the transistors of a bridge rectifier, where the transistors are arranged as high-side and low-side transistors. The gate drivers alternately switch the transistors so that the bridge rectifier converts an input voltage of one of two polarities to an output voltage of one of two polarities. The gate drivers include low-side gate drivers for the low-side transistors, and each of the low-side gate drivers includes a linear drive circuit and a digital drive circuit. The linear drive circuit drives each low-side transistor to switch on and off based on the forward current through each low-side transistor. The digital drive circuit detects the reverse current through each low-side transistor and causes each low-side transistor to switch off in response to the reverse current.

Description

Technical Field

[0001] The present disclosure generally relates to diode bridges, and more particularly to ideal diode bridge controllers.

Background Art

[0002] Power over Ethernet (PoE) is a technology that enables power and data to be transmitted over standard Ethernet network cables. PoE eliminates the need for separate power cables and allows devices to receive both power and network connectivity through a single Ethernet cable.

[0003] Using PoE, power can be directly supplied to devices such as IP cameras, wireless access points, VoIP phones, and other networked devices through the Ethernet infrastructure. This simplifies the installation and deployment of these devices, especially in situations where power outlets are not easily accessible.

[0004] PoE operates by using the wires within an Ethernet cable to supply power along with the data signal. This is achieved by injecting power into the cable in a power sourcing equipment (PSE), which can be a PoE switch or a PoE injector, also referred to as a midspan device. The power is then extracted at the powered device (PD), which is the device that receives both power and data.

[0005] Various versions of PoE exist. The original PoE standard, also known as IEEE 802.3af, can supply up to 15.4 watts of power per port. A newer PoE standard, known as IEEE 802.3at, provides a higher power supply of up to 30 watts per port. Another PoE standard, known as IEEE 802.3bt, can supply an even higher power level, reaching up to 90 watts per port. [Overview of the Initiative]

[0006] Different versions of PoE do not guarantee voltage polarity at the power interface (PI) of the Ethernet cable. PoE systems generally include a diode bridge to ensure correct polarity at the PD input. Newer versions of PoE achieved higher power delivery by increasing the current, but this resulted in greater power loss in the diode bridge. Power loss can be reduced using an ideal diode bridge, which includes an ideal diode bridge controller connected to a bridge rectifier. In an ideal diode bridge, the diodes in the diode bridge are replaced by transistors that are switched on and off alternately by the ideal diode bridge controller to emulate the diode bridge. However, many conventional ideal diode bridge controllers are insufficient for use within PoE systems.

[0007] The exemplary implementations of this disclosure relate to diode bridges, and more particularly to ideal diode bridge controllers. This disclosure includes, but is not limited to, the following exemplary implementations:

[0008] Some exemplary implementations provide an ideal diode bridge controller comprising a gate driver for connecting to transistors of a bridge rectifier, wherein the transistors are arranged as high-side transistors and low-side transistors, and the gate driver switches the transistors on and off alternately in pairs to cause the bridge rectifier to convert an input voltage of one of two polarities to an output voltage of one of two polarities, and the gate driver includes a high-side gate driver for the high-side transistors and a low-side gate driver for the low-side transistors, and each of the low-side gate drivers includes a linear drive circuit for driving each of the low-side transistors to switch on and off based on the forward current passing through each of the low-side transistors, and a digital drive circuit for detecting the reverse current passing through each of the low-side transistors and switching each of the low-side transistors off in response to the reverse current, thereby providing an ideal diode bridge controller.

[0009] Some exemplary implementations provide a method that includes the steps of: switching the transistors of a bridge rectifier alternately on and off in pairs so that the bridge rectifier converts an input voltage of one of two polarities to an output voltage of one of two polarities, wherein the transistors are high-side transistors that are switched on and off by a high-side gate driver, and low-side gate drivers, wherein one of each low-side gate drivers is arranged as a low-side transistor that is switched on and off by a low-side gate driver, which includes a linear drive circuit and a digital drive circuit; driving one of each low-side transistors by the linear drive circuit to switch on and off based on a forward current passing through one of each low-side transistor; detecting a reverse current passing through one of each low-side transistor in the digital drive circuit; and switching one of each low-side transistor off in response to the reverse current.

[0010] It will be understood that this summary of the invention is provided solely for the purpose of summarizing some exemplary implementations in order to provide a basic understanding of some aspects of the present disclosure. Therefore, it will be understood that the above-described exemplary implementations are merely examples and should not be construed as narrowing the scope or spirit of the present disclosure in any way. Other exemplary implementations, aspects, and advantages will become apparent from understanding the following detailed description in conjunction with the accompanying diagrams illustrating the principles of some of the described exemplary implementations.

[0011] While the exemplary implementations of this disclosure have been described above using general terminology, we now refer to the attached drawings, which are not necessarily drawn to scale. [Brief explanation of the drawing]

[0012] [Figure 1]This disclosure illustrates an ideal diode bridge controller in several exemplary implementations. [Figure 2] We will illustrate several exemplary implementations of an ideal diode bridge controller similar to the ideal diode bridge controller in Figure 1, but including a control circuit. [Figure 3] This section provides examples of ideal diode bridge controllers that can correspond to the ideal diode bridge controller shown in Figure 2, using several exemplary implementation configurations. [Figure 4] We illustrate an ideal diode bridge controller, including two bridge rectifiers, using several exemplary implementation configurations. [Figure 5] Figure 4 is a block diagram of a Power over Ethernet (PoE) system including an ideal diode bridge controller, representing several exemplary implementation configurations. [Figure 6] This section illustrates various operations in operating an ideal diode bridge controller using several exemplary implementations. [Figure 7] Figure 3 illustrates various current and voltage graphs during simulation of an ideal diode bridge controller in several exemplary implementation configurations. [Figure 8A] This flowchart illustrates various steps in a methodology using a variety of exemplary implementations. [Figure 8B] This flowchart illustrates various steps in a methodology using a variety of exemplary implementations. [Figure 8C] This flowchart illustrates various steps in a methodology using a variety of exemplary implementations. [Figure 8D] This flowchart illustrates various steps in a methodology using a variety of exemplary implementations. [Figure 8E] This flowchart illustrates various steps in a methodology using a variety of exemplary implementations. [Figure 8F]This flowchart illustrates various steps in a methodology using a variety of exemplary implementations. [Figure 8G] This flowchart illustrates various steps in a methodology using a variety of exemplary implementations. [Figure 8H] This flowchart illustrates various steps in a methodology using a variety of exemplary implementations. [Figure 8I] This flowchart illustrates various steps in a methodology using a variety of exemplary implementations. [Figure 8J] This flowchart illustrates various steps in a methodology using a variety of exemplary implementations. [Modes for carrying out the invention]

[0013] Several implementations of this disclosure are described below more fully with reference to the accompanying drawings, which illustrate some, but not all, implementations of this disclosure. In fact, various implementations of this disclosure can be embodied in many different forms and should not be construed as being limited to the implementations described herein. Rather, these exemplary implementations are provided so that this disclosure is thorough and complete and so as to convey the scope of this disclosure to those skilled in the art. Throughout, similar reference numerals refer to similar elements.

[0014] Unless otherwise specified or evident from the context, references to the first, second, etc., should not be interpreted as meaning a specific order. A feature described as being above another feature (unless otherwise specified or evident from the context) may instead be below it, and vice versa; similarly, a feature described as being to the left of another feature may instead be to the right, and vice versa. Furthermore, while quantitative measures, values, geometric relationships, etc., may be referred to herein, unless otherwise specified, any one or more of these may be approximations to account for acceptable variations that may occur, such as those resulting from engineering tolerances.

[0015] As used herein, unless otherwise specified or clear from the context, "or" among a set of operands is "inclusive or" and thus is true if one or more of the operands is true, in contrast to "exclusive or" which is false when all of the operands are true. Thus, for example, "[A] or [B]" is true if [A] is true, or if [B] is true, or if both [A] and [B] are true. Further, the articles "a" and "an" mean "one or more" unless otherwise specified or clear from the context that the singular form is intended. Further, it should be understood that unless otherwise specified, the terms "data", "content", "digital content", "information", and similar terms may sometimes be used interchangeably.

[0016] Exemplary implementations of the present disclosure relate to a diode bridge, and in particular to an ideal diode bridge controller for Power over Ethernet (PoE). The features, aspects, and advantages of the present disclosure will become apparent from reading the following detailed description in conjunction with the accompanying drawings briefly described below. The present disclosure includes any combination of two, three, four, or more features or elements described in the present disclosure, whether or not such features or elements are explicitly combined or otherwise recited in the specific exemplary implementations described herein. The present disclosure is intended to be read holistically such that any separable feature or element of the present disclosure should be considered combinable in any of its aspects and exemplary implementations unless the context of the present disclosure clearly dictates otherwise.

[0017] FIG. 1 illustrates an ideal diode bridge 100 according to some exemplary implementations of the present disclosure. As shown, the ideal diode bridge 100 includes an ideal diode bridge controller 102 connected to a bridge rectifier 104. The bridge rectifier includes transistors Q1, Q2, Q3, Q4 arranged in two legs bridged by a pair of inputs IN1A, IN1B. As shown, in some examples, the transistors are field-effect transistors (FETs) such as metal-oxide-semiconductor FETs (MOSFETs). The transistors include high-side transistors Q2, Q3 and low-side transistors Q1, Q4. In some examples, the bridge rectifier includes a pair of outputs VOUTP, VOUTN to which an output voltage is provided, and in some of these examples, the high-side transistors Q2, Q3 are respectively connected between one of the positive ones of the pair of outputs, i.e., VOUTP, and one of each of the pair of inputs IN1A, IN1B, and the low-side transistors Q1, Q4 are respectively connected between one of each of the pair of inputs IN1A, IN1B and one of the negative ones of the pair of outputs, i.e., VOUTN.

[0018] The ideal diode bridge controller 102 includes a gate driver 106 connected to the pair of inputs IN1A, IN1B and the transistors Q1, Q2, Q3, Q4, and alternately turns on and off the transistors in pairs (Q2, Q4), (Q3, Q1) to cause the bridge rectifier to emulate a diode bridge with respect to the input voltage in the pair of inputs. In some examples, the gate driver can cause the bridge rectifier 102 to convert an input voltage of either of the two polarities to an output voltage of one of the two polarities. The gate driver 106 includes a high-side gate driver 108 for the high-side transistors Q2, Q3 and a low-side gate driver 110 for the low-side transistors Q1, Q4.

[0019] As similarly shown in Figure 1, each of the low-side gate drivers 110 includes a linear driver circuit 112 and a digital driver circuit 114. The linear driver circuit 112 (sometimes referred to as a linear driver or linear driver circuit) is an electronic circuit for providing a proportional and continuous output in response to a changing input signal. The digital driver circuit (sometimes referred to as a digital driver or digital driver circuit) is an electronic circuit for providing a discrete output (e.g., logic high or logic low) in response to an input signal.

[0020] According to some exemplary implementations of this disclosure, a linear drive circuit 112 can drive one of the low-side transistors Q1 / Q4 to switch on and off based on the forward current passing through each of the low-side transistors. A digital drive circuit 114 can detect the reverse current passing through each of the low-side transistors Q1 / Q4 and cause each of the low-side transistors to switch off in response to the reverse current.

[0021] In the ideal diode bridge controller 102, the forward current is the current flowing from IN1A / IN1B (depending on the polarity) to VOUTP, and as a result, the forward current flows from the source to the drain of the pair of transistors that are switched on (Q2, Q4) or (Q3, Q1) (as shown, the source and drain are labeled "S" and "D", respectively). The reverse current is the current flowing from VOUTP to IN1 / IN2, and therefore, the reverse current flows from the drain to the source of the pair of transistors that are switched on.

[0022] Figure 2 illustrates an ideal diode bridge 100 that includes an ideal diode bridge controller 202 similar to the ideal diode bridge controller 102, and includes a control circuit 204, in several exemplary implementations. In some of these exemplary implementations, the control circuit 204 is for selectively enabling and disabling gate drivers 106, which may include one linear drive circuit 112 and one digital drive circuit 114 of the low-side gate drivers 110, respectively. In some examples, the control circuit 204 may alternately enable and disable pairs of gate drivers 106 corresponding to pairs (Q2, Q4) and (Q3, Q1) in which the transistors are alternately switched on and off. In some examples, the control circuit 204 may receive a signal from the digital drive circuit 114 indicating that a reverse current has been detected, and in response to the signal, disable the gate driver 106. As similarly shown, the control circuit 204 may include an under-voltage lockout (UVLO) circuit 206 to disable the gate driver 106 when the input voltage is below a threshold voltage and to enable the gate driver 106 when the input voltage is above the threshold voltage. Hysteresis may be supplied by the UVLO circuit 206.

[0023] As described above, several exemplary implementations of the ideal diode bridge 100 can be designed for Power over Ethernet (PoE). In some examples, the ideal diode bridge controller 202 may be connectable to a component of a powered device (PD) in a PoE system, and the ideal diode bridge controller 202 and PD may be connectable to an external power source such as a wall adapter (WA). In some of these examples, the control circuit 204 may detect that the PD is connected to an external power source and disable the gate driver 106 when the ideal diode bridge controller 202 and PD are connected to an external power source.

[0024] As similarly shown in Figure 2 and described in more detail below, in some examples, one of the high-side gate drivers 108 may include a digital drive circuit 208 for driving one of the high-side transistors Q2 / Q3 to switch on and off based on the forward current passing through one of the high-side transistors.

[0025] Figure 3 illustrates an ideal diode bridge 100 including an ideal diode bridge controller 302, which may correspond to an ideal diode bridge controller 202 in several exemplary implementation forms. As shown, each of the digital drive circuits 208 of the high-side gate drivers 108 may include comparators U2 / U3 for outputting a switching signal to turn on each of the high-side transistors Q2 / Q3 when the source voltage VS is greater than the drain voltage VD, indicating that current is flowing through the MOSFET body diode of each of the high-side transistors Q2 / Q3. As similarly shown, in some examples, the comparators U2 / U3 may drive each of the low-side transistors Q2 / Q3 through their respective buffers U13 / U14. Each buffer U13 / U14 may be a tristate buffer having an enable / disable input supplied by the control circuit 204, which can be used to set each buffer U13 / U14 to a high impedance state in order to effectively disconnect the output of each buffer U13 / U14 from the gate of the respective transistor Q2 / Q3, thereby disabling the comparators U2 / U3 and the digital drive circuit 208.

[0026] In some examples, the digital drive circuit 208 includes a voltage offset Vcomp-on (implemented as a voltage source) that sets a minimum voltage difference, and in some of these examples, comparators U2 / U3 output a switching signal when the source voltage VS is greater than the drain voltage VD by at least the voltage offset (VS > (VD + Vcomp-on)). The voltage offsets described herein and other voltage offsets may be trimmable in that the voltage offsets may be adjusted or fine-tuned to specific values ​​to improve the performance of the ideal diode bridge controller 300. As similarly shown, in some examples, the digital drive circuit 208 includes a charge pump 304 connected to comparators U2 / U3 and buffers U13 / U14 so that the switching signal output by comparators U2 / U3 and buffered by buffers U13 / U14, if provided, is boosted to a voltage suitable for driving one of the high-side transistors Q2 / Q3. As shown similarly, in some examples, the outputs of each comparator U2 / U3 are supplied to their respective driver circuits U13 / U14, which in turn drive one of the high-side transistors Q2 / Q3.

[0027] Now, let's focus on the low-side gate drivers 110. In this case as well, each of the low-side gate drivers includes a linear drive circuit 112 and a digital drive circuit 114. As shown in Figure 3, in some examples, the linear drive circuit 112 of each of the low-side gate drivers 110 includes operational amplifiers U5 / U6, which have non-inverting inputs (+) and inverting inputs (-) connected to the source and drain of each of the low-side transistors Q1 / Q4, respectively. As shown similarly, in some examples, the operational amplifiers U5 / U6 may drive each of the low-side transistors Q1 / Q4 through their respective buffers U7 / U10. Similar to buffers U13 / U14, each buffer U7 / U10 may be a tristate buffer having enable / disable inputs supplied by the control circuit 204, which can be used to set each buffer U7 / U10 to a high impedance state in order to effectively disconnect the output of each buffer U7 / U10 from the gates of their respective transistors Q1 / Q4, thereby disabling the operational amplifiers U5 / U6 and the linear drive circuit 112.

[0028] In some examples, operational amplifiers U5 / U6 may adjust the forward voltage of one of the low-side transistors Q1 / Q4 based on the forward current. In the ideal diode bridge controller 302, the forward voltage of one of the low-side transistors Q1 / Q4 is the positive voltage between the source and drain of one of the low-side transistors Q1 / Q4, i.e., the source is at a higher voltage than the drain. In some examples, the linear drive circuit 112 may include a voltage offset Vopamp-reg (implemented as a voltage source) that sets a minimum voltage for operational amplifiers U5 / U6 to adjust the forward voltage of one of the low-side transistors Q1 / Q4 in linear mode. In saturation mode, operational amplifiers U5 / U6 may provide a gate-source voltage to adjust the forward voltage for a forward current up to the current corresponding to the voltage offset and the characteristic on-resistance RDS(on) of one of the low-side transistors Q1 / Q4, i.e., forward current = Vopamp-reg / RDS(on). Therefore, when the forward current increases significantly above Vopamp-reg / RDS(on), i.e., when the forward voltage is greater than Vopamp-reg, i.e., in one saturation mode of each of the low-side transistors Q1 / Q4, the forward voltage depends on the characteristic on-resistance RDS(on) and is not regulated by the operational amplifiers U5 / U6.

[0029] In some examples, each of the low-side gate drivers 110, one digital drive circuit 114, includes comparators U1 / U4 with non-inverting inputs (+) and inverting inputs (-) connected to the drain and source of each of the low-side transistors Q1 / Q4.

[0030] In some examples, comparators U1 / U4 may compare the drain voltage VD and source voltage VS of one of the low-side transistors Q1 / Q4 (shown as source voltage VS - Q1 / Q4 and drain voltage VD - Q1 / Q4). The comparator may output a signal to switch off one of the low-side transistors when the drain voltage VD is greater than the source voltage VS, indicating that a reverse current has been detected. As shown, in some examples, comparators U1 / U4 may drive one of the low-side transistors Q1 / Q4 through their respective buffers U8 / U12.

[0031] In some further examples, the digital drive circuit 114 includes a voltage offset Vcomp-off that sets a minimum voltage difference, and in some of these examples, the comparators U1 / U4 may output a signal when the drain voltage VD is greater than the source voltage VS by at least the voltage offset ((VD-Vcomp-off)>VS). The reverse current at this point may be Vcomp-off / RDS(on), where RDS(on) is the characteristic on-resistance RDS(on) of one of the low-side transistors Q1 / Q4, respectively.

[0032] As similarly shown, in some examples, the digital drive circuit 114 includes switching transistors Q5 / Q6 connected to one of the low-side transistors Q1 / Q4, such as in the form of a low-side switch. In this regard, the low-side switch is a switch positioned on the "low side" of the load of the ideal diode bridge controller 300 (i.e., the load side closer to VOUTN). In some of these examples, the signals output by the comparators U1 / U4 are switching signals to drive the switching transistors to turn Q5 / Q6 on, and the switching transistors Q5 / Q6 pull down the gate voltage of one of the low-side transistors Q1 / Q4, causing one of the low-side transistors to turn off.

[0033] In some further examples, the signal output by comparators U1 / U4 is a first signal, and the control circuit 204 outputs a second signal for selectively enabling the digital drive circuit 114. In these examples, the digital drive circuit 114 includes logic OR gates U9 / U11 ​​to switch off one of the low-side transistors Q1 / Q4 in response to either the first signal from the comparator or the second signal from the control circuit 204. In this regard, the logic OR gates may output switching signals to drive switching transistors Q5 / Q6 to lower the gate voltage of one of the low-side transistors Q1 / Q4, thereby switching off one of the low-side transistors.

[0034] Similarly, as shown, in the context of an ideal diode bridge controller 300 connected to a PD in a POE system, the control circuit 204 may include an input WA_Enable that can indicate that the ideal diode bridge controller 300 and the PD are connected to an external power supply. In these situations, the control circuit 204 may disable the gate driver 106. Disabling the gate driver 106 in these and other situations may include the control circuit disabling the linear drive circuit 112 of the low-side gate driver 110 by sending appropriate signals to the tristate buffers U7, U10 of the linear drive circuit 112 and setting the tristate buffers U7, U10 of the linear drive circuit 112 to a high impedance state. The control circuit may similarly disable the high-side gate driver 208 by sending appropriate signals to the tristate buffers U13, U14 of the high-side gate driver 208 and setting the tristate buffers U13, U14 of the high-side gate driver 208 to a high impedance state. Furthermore, as described above, the control circuit can send an appropriate (second) signal to the OR logic gates U9 and U11 of the digital drive circuit 114 of the low-side gate driver 110, driving the switching transistors Q5 / Q6 to turn on, and lowering the gate voltage of one of the low-side transistors Q1 / Q4, thereby turning off one of the low-side transistors.

[0035] In some examples, ideal diode bridge controllers 102, 202, and 302 can be implemented in a dual-bridge rectifier. Figure 4 illustrates an ideal diode bridge 400, comprising at least one ideal diode bridge controller 402 and two bridge rectifiers 404, in some exemplary implementation configurations. In this regard, the ideal diode bridge 400 may include two ideal diode bridge controllers 402 for the two bridge rectifiers 404. As shown, one of the two bridge rectifiers 404 may be coupled to inputs IN1A and IN2A, and the other of the two bridge rectifiers 404 may be coupled to inputs IN1B and IN2B. The input voltage may then be provided at the input pair of either of the two bridge rectifiers 404, which converts the input voltage into output voltages that can be provided to a pair of outputs VOUTP and VOUTN connected to both of the two bridge rectifiers, and the output voltages are provided to the output pair. As shown similarly, the high-side transistors Q2 and Q3 of each of the two bridge rectifiers 404 are connected to the positive of the output pair, VOUTP, and the low-side transistors Q1 and Q4 of each of the two bridge rectifiers 404 are connected to the negative of the output pair, VOUTN. Although not shown separately in Figure 4, the diode bridge controller 402 may include a control circuit 204 for each of the two bridge rectifiers 404, or the diode bridge controller 402 may include a single control circuit for both of the two bridge rectifiers 404.

[0036] Figure 5 is a block diagram of a Power over Ethernet (PoE) system 500 including an ideal diode bridge 400 in several exemplary implementation configurations. In this case as well, the PoE system may include an Ethernet cable 502 for supplying power along with data signals. Power can be injected into the Ethernet cable 502 at a power supply equipment (PSE). Power can then be extracted at a powered device (PD) 504, which is a device that receives power and data via the Ethernet cable 502. In this regard, the PD 504 can accept power supplied via the Ethernet cable 502 through which data is carried, and the ideal diode bridge 400 can provide polarity correction for the power supplied via the Ethernet cable. As shown, the PD 504 can receive power from a power interface (PI) 506 of the Ethernet cable, such as an Ethernet (e.g., RJ-45) connector, and the PD 504 receives power from the ideal diode bridge converter 400.

[0037] In the PoE system 500, the PD 504 and PSE may perform a handshake procedure when the PD is connected to the PSE via the Ethernet cable 502. When the PD 504 is connected to the PSE via the Ethernet cable 502, the PSE performs a detection operation to determine whether the PD 504 is PoE compatible and a classification operation to determine the power requirements of the PD 504. In the PoE system 500 of the exemplary implementation of the present disclosure, the ideal diode bridge controller 402 of the ideal diode bridge 400 may include an enable input for enabling or disabling the ideal diode bridge controller, and therefore the ideal diode bridge. In some examples, the PD 504 may then supply a logic high voltage to the enable input to disable the ideal diode bridge controller 402 during the detection and classification operation in order to reduce the effect of the current consumption of the ideal diode bridge 400 on the detection and classification currents.

[0038] One linear drive circuit 112 and one digital drive circuit 114 of the low-side gate driver 110 may cooperate to enable the low-side gate driver 110 to turn on transistors Q1 / Q4 in a controlled and smooth manner in response to the linear drive circuit 112, and to turn off transistors Q1 / Q4 rapidly (e.g., in less than 100 nanoseconds) in response to the digital drive circuit 114. In this context, rapid and similar terms refer to a time shorter than the rise time of the surge waveform as defined by the International Telecommunication Union (ITU) Recommendation ITU-TK.21, Resistibility of Telecommunication Equipment Installed in Customer Premises to Overvoltage and Overcurrent (2022). For example, transistors Q1 / Q4 can be rapidly turned off when the ideal diode bridge 400 and PD504 are connected to the external power supply 508, with the external power supply 508 providing a voltage greater than the input voltage. In another example, transistors Q1 / Q4 may be quickly switched off in response to the digital drive circuit 114 to prevent a short circuit between the PSE and the lightning surge voltage in the event of a negative current lightning surge.

[0039] A linear drive circuit 112 placed in the low-side gate driver 110 can also offer advantages over a high-side gate driver 108. In this regard, the linear drive circuit can avoid the need for the relatively large charge pump 304 of the high-side gate driver 108, and the operational amplifiers U5 and U6 provide sufficient current to the low side. Therefore, when the ideal diode bridge controller 102 is implemented in an integrated circuit (IC), placing the linear drive circuit 110 in the low-side gate driver can reduce the footprint of the ideal diode bridge controller 102, 202, or 302 and lower the cost of the IC.

[0040] To further illustrate exemplary implementations of the present disclosure, Figure 6 illustrates various operations in which the ideal diode bridge controllers 102, 202, or 302 are operated in several exemplary implementations. As shown in blocks 602, 604, and 606, the control circuit 204 may activate the ideal diode bridge controller when the input voltage is greater than the undervoltage lockout (UVLO) voltage and the ideal diode bridge controller is not connected to an external power supply (for example, as indicated by a logic low voltage at the activation input of the ideal diode bridge controller).

[0041] When forward source-drain current flows through one pair of transistors (Q2, Q4) but not through the other pair (Q3, Q1), the gate driver 106 switches on one pair of transistors (Q2, Q4), as shown in blocks 608, 610, and 612. As shown in Figure 3, for example, the control circuit 204 may receive inputs indicating the current flow through transistors Q1, Q2, Q3, and Q4 from the outputs of comparators U1, U2, U3, and U4. To switch on one pair of transistors (Q2, Q4), the control circuit may send appropriate signals to buffers (U13, U10) to activate one of the high-side gate driver 108 and the low-side gate driver 110, respectively. Alternatively, when forward source-drain current flows through the other pair of transistors (Q3, Q1) but not through the other pair (Q2, Q4), the gate driver switches the other pair of transistors (Q3, Q1) on, as shown in blocks 614, 616, and 618. In this case as well, as shown in Figure 3, for example, the control circuit 204 may send an appropriate signal to the buffers (U14, U7) to activate one of the high-side gate drivers 108 and the low-side gate driver 110 to switch the other pair of transistors (Q3, Q1) on.

[0042] When one pair of transistors (Q2, Q4) is ON and a reverse drain-source current is detected through that pair, the control circuit 204 quickly turns off the pair by disabling the gate driver 106, in particular the digital drive circuits 114, 208, as shown in blocks 620 and 622. Specifically, for example, the control circuit may send appropriate signals to buffer U13 and logic OR gate U11 to disabling one of the digital drive circuits 114, 208 for each of the pair of transistors (Q2, Q4). Similarly, when the other pair of transistors (Q3, Q1) is ON and a reverse drain-source current is detected through that pair, the control circuit quickly turns off the other pair by disabling the gate driver 106, as shown in blocks 624 and 626. The control circuit may also quickly turn off one or the other of the transistor pair (Q2, Q4) and (Q3, Q1) when it detects that the ideal diode bridge controller is connected to an external power supply (as indicated by a logic high voltage at the activation input of the ideal diode bridge controller), as shown in blocks 628 and 630.

[0043] Figure 7 illustrates graphs of various currents and voltages over time during a simulation of an ideal diode bridge controller 302 in several exemplary implementation configurations. In the illustrated examples, the low-side transistors Q1 and Q4 have a threshold voltage of 2.5V and a saturation voltage of 5V, but in other examples, the low-side transistors Q1 and Q4 may have other characteristic voltages. As shown, the current initially flows through one of the body diodes of each of the low-side transistors Q1 / Q4, as indicated by the gate-source voltage of zero. This can also be indicated by the increase in the source-drain voltage of each of the low-side transistors Q1 / Q4 to approximately 375mV, which is the forward voltage drop across the body diode as the current flows through it.

[0044] When the voltage across the body diode is greater than Vopamp-reg (plus the internal offset of the operational amplifier), the operational amplifiers U5 / U6 begin to adjust the source-drain forward voltage of Q1 / Q4 to Vopamp-reg up to the load current of Vopamp-reg / RDS(on) (where RDS(on) is the on-resistance of Q1 / Q4). This can be seen in the diagram, where the gate-source voltage is higher than the 2.5V threshold voltage of one of the low-side transistors Q1 / Q4 but lower than the 5V saturation voltage, and one of the low-side transistors Q1 / Q4 is not fully on.

[0045] For load currents greater than Vopamp-reg / RDS(on), the forward voltage depends on RRD(on). That is, when the forward voltage of one of the low-side transistors Q1 / Q4 is greater than Vopamp-reg, the operational amplifiers U5 / U6 can adjust the forward voltage. Although not shown in Figure 7, for example, when Vopamp-reg = 20mV and RRD(on) = 50mOhm, the operational amplifiers U5 / U6 can adjust the forward voltage of Q1 / Q4 up to a current of 20mV / 50mOhm = 400mA. For load currents greater than 400mA, Q1 / Q4 can be fully boosted, and the forward voltage increases based on the load current until it reaches the saturation voltage of Q1 / Q4, which is 5V in this example.

[0046] In the ideal diode bridge controller 302, forward current flows from the source to the drain of one of the transistor pairs (Q2, Q4) or (Q3, Q1). When an external power supply is connected to the ideal diode bridge controller 302 and PD, and the voltage of the external power supply is greater than the input voltage of the ideal diode bridge controller 302, current from the external power supply flows from the drain to the source and can damage the PSE. Therefore, the comparators U1 / U4 of the digital drive circuit 114 monitor the reverse current from the drain-source voltage and, in response to the reverse current, such as when the reverse current reaches the value of Vcomp-off / RDS(on), they can cause one of the low-side transistors Q1 / Q4 to be switched off very quickly. The gate driver 106 for the transistors can similarly be deactivated by the control circuit 204.

[0047] Figures 8A to 8J are flowcharts illustrating various steps in Method 800 in various exemplary implementation configurations. The Method includes the step of switching the transistors of a bridge rectifier alternately on and off in pairs, as shown in block 802 of Figure 8A, to cause the bridge rectifier to convert an input voltage of one of two polarities to an output voltage of one of two polarities. The transistors are high-side transistors and low-side gate drivers, which are switched on and off by a high-side gate driver, with each of the low-side gate drivers being configured as a low-side transistor, which is switched on and off by the low-side gate driver, including a linear drive circuit and a digital drive circuit. The Method includes the step of driving each of the low-side transistors to be switched on and off by the linear drive circuit based on the forward current passing through each of the low-side transistors, as shown in block 804. The Method includes the step of detecting the reverse current passing through each of the low-side transistors in the digital drive circuit, as shown in block 806. The method then includes the step of causing a digital drive circuit to switch off one of the low-side transistors in response to a reverse current, as shown in block 808.

[0048] In some examples, method 800 includes a step of selectively enabling and disabling high-side gate drivers and low-side gate drivers, which includes a step of selectively enabling and disabling one linear drive circuit and one digital drive circuit of each of the low-side gate drivers, as shown in block 810 of Figure 8B.

[0049] In some examples, method 800 includes the step of alternately enabling and disabling a pair of high-side gate drivers and low-side gate drivers corresponding to a pair of transistors that are alternately switched on and off, as shown in block 812 of Figure 8C.

[0050] In some examples, method 800 includes the step of receiving a signal from the digital drive circuit indicating that a reverse current has been detected, as shown in block 814 of Figure 8D. In some of these examples, method includes the step of disabling the high-side gate driver and the low-side gate driver in response to the signal from the digital drive circuit indicating that a reverse current has been detected, as shown in block 816.

[0051] In some examples, method 800 includes the step of disabling the high-side gate driver and the low-side gate driver when the input voltage is below a threshold voltage, as shown in block 818 of Figure 8E.

[0052] In some examples, method 800 includes the step of adjusting the forward voltage of each of the low-side transistors by a linear drive circuit, as shown in block 820 of Figure 8F, wherein the forward voltage is adjusted in saturation mode to a forward current up to a voltage offset and a current corresponding to the characteristic on-resistance of each of the low-side transistors.

[0053] In some examples, method 800 includes the step of comparing the drain voltage and source voltage of one of the low-side transistors in the digital drive circuit, as shown in block 822 of Figure 8G. In some of these examples, method includes the step of outputting a signal from the digital drive circuit to switch off one of the low-side transistors when the drain voltage is greater than the source voltage, indicating that a reverse current has been detected, as shown in block 824.

[0054] In some examples, method 800 includes the step of comparing the drain voltage and source voltage of each of the low-side transistors in the digital drive circuit, as shown in block 826 of Figure 8H. In some of these examples, method includes the step of outputting a signal from the digital drive circuit to switch each of the low-side transistors off when the drain voltage is greater than the source voltage by at least a voltage offset, as shown in block 828.

[0055] In some examples, each of the high-side gate drivers includes a digital drive circuit, and method 800 includes the step of driving each of the high-side transistors by the digital drive circuit to switch on and off based on the forward current passing through each of the high-side transistors, as shown in block 830 of Figure 8I.

[0056] In some examples, method 800 includes the step of comparing the source voltage and drain voltage of each of the high-side transistors in a digital drive circuit, as shown in block 832 of Figure 8J. In some of these examples, method includes the step of outputting a switching signal from the digital drive circuit to cause each of the high-side transistors to switch on when the source voltage is greater than the drain voltage, as shown in block 834, the switching signal being output when the source voltage is greater than the drain voltage by at least a voltage offset.

[0057] As described above and repeated below, this disclosure includes, without limitation, the following exemplary implementations.

[0058] Clause 1. An ideal diode bridge controller comprising a gate driver for connecting to transistors of a bridge rectifier, wherein the transistors are arranged as high-side transistors and low-side transistors, and the gate driver switches the transistors on and off alternately in pairs to cause the bridge rectifier to convert an input voltage of one of two polarities to an output voltage of one of two polarities, and the gate driver comprises a high-side gate driver for the high-side transistors and a low-side gate driver for the low-side transistors, and each of the low-side gate drivers comprises a linear drive circuit for driving each of the low-side transistors to switch on and off based on the forward current passing through each of the low-side transistors, and a digital drive circuit for detecting the reverse current passing through each of the low-side transistors and switching each of the low-side transistors off in response to the reverse current, the ideal diode bridge controller.

[0059] Clause 2. An ideal diode bridge controller as described in Clause 1, comprising a control circuit for selectively enabling and disabling gate drivers, and including a control circuit for selectively enabling and disabling one linear drive circuit and one digital drive circuit of each of the low-side gate drivers.

[0060] Clause 3. An ideal diode bridge controller as described in Clause 1 or 2, comprising a control circuit for alternately enabling and disabling a pair of gate drivers corresponding to a pair of transistors that are alternately switched on and off.

[0061] Clause 4. An ideal diode bridge controller as described in any one of Clauses 1 to 3, comprising a control circuit for receiving a signal from a digital drive circuit indicating that a reverse current has been detected and for disabling the gate driver in response to the signal.

[0062] Clause 5. An ideal diode bridge controller as described in any one of Clauses 1 to 4, comprising a control circuit including an undervoltage lockout (UVLO) circuit for disabling the gate driver when the input voltage is below a threshold voltage.

[0063] Clause 6. An ideal diode bridge controller as described in any one of Clauses 1 to 5, wherein the linear drive circuit includes an operational amplifier for adjusting the forward voltage of each of the low-side transistors based on the forward current, the linear drive circuit includes a voltage offset that sets a minimum voltage so that the operational amplifier adjusts the forward voltage of each of the transistors in linear mode, and the operational amplifier adjusts the forward voltage for a forward current up to a current corresponding to the voltage offset and the characteristic on-resistance of each of the low-side transistors in saturation mode.

[0064] Clause 7. The digital drive circuit is an ideal diode bridge controller as described in any one of Clauses 1 to 6, which includes a comparator for outputting a signal to switch off one of the low-side transistors when the drain voltage is greater than the source voltage, indicating that a reverse current has been detected.

[0065] Clause 8. An ideal diode bridge controller as described in any one of Clauses 1 to 7, comprising: a voltage offset for setting a minimum voltage difference; and a comparator for comparing the drain voltage and source voltage of one of the low-side transistors, and outputting a signal to switch off one of the low-side transistors when the drain voltage is greater than the source voltage by at least the voltage offset.

[0066] Clause 9. An ideal diode bridge controller as described in any one of Clauses 1 to 8, wherein each of the high-side gate drivers includes a digital drive circuit that drives each of the high-side transistors to switch on and off based on the forward current passing through each of the high-side transistors.

[0067] Clause 10. The ideal diode bridge controller as described in Clause 9, wherein the digital drive circuit includes a comparator for comparing the source voltage and drain voltage of one of the high-side transistors and outputting a switching signal to turn on one of the high-side transistors when the source voltage is greater than the drain voltage, the digital drive circuit includes a voltage offset to set a minimum voltage difference, and the comparator outputs a switching signal when the source voltage is greater than the drain voltage by at least the voltage offset.

[0068] Clause 11. A method comprising the steps of: switching a pair of transistors of a bridge rectifier alternately on and off so that the bridge rectifier converts an input voltage of one of two polarities to an output voltage of one of two polarities, wherein the transistors are high-side transistors that are switched on and off by a high-side gate driver, and low-side gate drivers, where each of the low-side gate drivers is arranged as a low-side transistor that is switched on and off by a low-side gate driver, including a linear drive circuit and a digital drive circuit; driving each of the low-side transistors by the linear drive circuit to switch on and off based on a forward current passing through each of the low-side transistors; detecting a reverse current passing through each of the low-side transistors in the digital drive circuit; and switching each of the low-side transistors off in response to the reverse current.

[0069] Clause 12. The method according to Clause 11, comprising the step of selectively enabling and disabling a high-side gate driver and a low-side gate driver, each comprising the step of selectively enabling and disabling one linear drive circuit and one digital drive circuit of the low-side gate driver.

[0070] Clause 13. The method according to Clause 11 or Clause 12, comprising the step of alternately enabling and disabling a pair of high-side gate drivers and low-side gate drivers corresponding to a pair of transistors that are alternately switched on and off.

[0071] Clause 14. The method according to any one of Clauses 11 to 13, comprising the steps of receiving a signal from a digital drive circuit indicating that a reverse current has been detected, and disabling the high-side gate driver and the low-side gate driver in response to the signal from the digital drive circuit indicating that a reverse current has been detected.

[0072] Clause 15. The method according to any one of Clauses 11 to 14, including the step of disabling the high-side gate driver and the low-side gate driver when the input voltage is below a threshold voltage.

[0073] Clause 16. The method according to any one of Clauses 11 to 15, comprising the step of adjusting the forward voltage of each of the low-side transistors by a linear drive circuit, wherein the forward voltage is adjusted in saturation mode to a forward current up to a voltage offset and a current corresponding to the characteristic on-resistance of each of the low-side transistors.

[0074] Clause 17. The method according to any one of Clauses 11 to 16, comprising the steps of comparing the drain voltage and source voltage of one of the low-side transistors in a digital drive circuit, and outputting a signal from the digital drive circuit to switch off one of the low-side transistors when the drain voltage is greater than the source voltage, indicating that a reverse current has been detected.

[0075] Clause 18. The method according to any one of Clauses 11 to 17, comprising the steps of comparing the drain voltage of one of the low-side transistors with its source voltage, and outputting a signal from the digital drive circuit to switch off one of the low-side transistors when the drain voltage is greater than the source voltage by at least a voltage offset.

[0076] Clause 19. The method according to any one of Clauses 11 to 18, wherein each of the high-side gate drivers includes a digital drive circuit, and the method includes the step of driving each of the high-side transistors by the digital drive circuit to switch on and off based on the forward current passing through each of the high-side transistors.

[0077] Clause 20. The method according to Clause 19, comprising the steps of: comparing the source voltage and drain voltage of each of the high-side transistors in a digital drive circuit; and outputting a switching signal from the digital drive circuit to turn on each of the high-side transistors when the source voltage is greater than the drain voltage, wherein the switching signal is output when the source voltage is greater than the drain voltage by at least a voltage offset.

[0078] Many modifications and other implementations of the Disclosure described herein will be conceived by those skilled in the art who are interested in the teachings presented in the foregoing description and the accompanying figures. Therefore, it should be understood that the Disclosure should not be limited to the specific implementations disclosed, and that modifications and other implementations are intended to be included within the scope of the appended claims. Furthermore, while the foregoing description and the accompanying figures illustrate exemplary implementations in the context of specific exemplary combinations of elements and / or functions, it should be understood that different combinations of elements and / or functions may be provided by alternative implementations without departing from the scope of the appended claims. In this regard, different combinations of elements and / or functions than those expressly described above are also contemplated, for example, as may be described in part of the appended claims. Specific terms are used herein, but they are used in a general and descriptive sense only and are not intended to be limiting.

Claims

1. An ideal diode bridge controller, A gate driver for connecting to the transistors of the bridge rectifier is provided, wherein the transistors are arranged as a high-side transistor and a low-side transistor, and the gate driver switches the transistors on and off alternately in pairs to cause the bridge rectifier to convert an input voltage of one of two polarities to an output voltage of one of the two polarities, and the gate driver includes a high-side gate driver for the high-side transistor and a low-side gate driver for the low-side transistor, and one of the low-side gate drivers is A linear drive circuit for driving each of the low-side transistors to switch them on and off based on the forward current passing through each of the low-side transistors, A digital drive circuit that detects the reverse current passing through each of the low-side transistors and switches each of the low-side transistors off in response to the reverse current, An ideal diode bridge controller, including the following:

2. The ideal diode bridge controller according to claim 1, comprising a control circuit for selectively enabling and disabling the gate drivers, and including the control circuit for selectively enabling and disabling each of the linear drive circuits and the digital drive circuits of the low-side gate drivers.

3. The ideal diode bridge controller according to claim 1, further comprising a control circuit for alternately enabling and disabling a pair of gate drivers corresponding to the pair of transistors that are alternately switched on and off.

4. The ideal diode bridge controller according to claim 1, comprising a control circuit for receiving a signal from the digital drive circuit indicating that the reverse current has been detected, and for disabling the gate driver in response to the signal.

5. The ideal diode bridge controller according to claim 1, further comprising a control circuit including an undervoltage lockout (UVLO) circuit for disabling the gate driver when the input voltage is lower than a threshold voltage.

6. The linear drive circuit includes an operational amplifier for adjusting the forward voltage of each of the low-side transistors based on the forward current. The ideal diode bridge controller according to claim 1, wherein the linear drive circuit includes a voltage offset that sets a minimum voltage, the operational amplifier adjusting the forward voltage in each of the linear modes of the transistors, the operational amplifier adjusting the forward voltage with respect to the forward current up to the voltage offset and the characteristic on-resistance of each of the low-side transistors in saturation mode.

7. The ideal diode bridge controller according to claim 1, wherein the digital drive circuit includes a comparator for comparing the drain voltage and source voltage of each of the low-side transistors and outputting a signal to switch each of the low-side transistors off when the drain voltage is greater than the source voltage, indicating that the reverse current has been detected.

8. The aforementioned digital drive circuit is The voltage offset that sets the minimum voltage difference, A comparator that compares the drain voltage and source voltage of each of the low-side transistors, and outputs a signal to switch each of the low-side transistors off when the drain voltage is at least as large as the voltage offset when the drain voltage is larger than the source voltage. The ideal diode bridge controller according to claim 1, including the above.

9. The ideal diode bridge controller according to claim 1, wherein each of the high-side gate drivers includes a digital drive circuit that drives each of the high-side transistors to switch on and off based on the forward current passing through each of the high-side transistors.

10. The digital drive circuit includes a comparator for comparing the source voltage and drain voltage of each of the high-side transistors, and for outputting a switching signal to turn on each of the high-side transistors when the source voltage is greater than the drain voltage. The ideal diode bridge controller according to claim 9, wherein the digital drive circuit includes a voltage offset for setting a minimum voltage difference, and the comparator outputs the switching signal when the source voltage is greater than the drain voltage by at least the voltage offset.

11. It is a method, A step of switching the transistors of a bridge rectifier alternately on and off in pairs so that an input voltage of one of two polarities is converted to an output voltage of one of the two polarities, wherein the transistors are high-side transistors that are switched on and off by a high-side gate driver, and low-side gate drivers, where one of each of the low-side gate drivers is arranged as a low-side transistor that is switched on and off by a low-side gate driver, including a linear drive circuit and a digital drive circuit. The steps include driving each of the low-side transistors by the linear drive circuit to switch them on and off based on the forward current passing through each of the low-side transistors, and in the digital drive circuit, The steps include detecting the reverse current passing through each of the low-side transistors, A step of switching off one of the low-side transistors in response to the aforementioned reverse current. Methods that include...

12. The method according to claim 11, further comprising the step of selectively enabling and disabling the high-side gate driver and the low-side gate driver, the step of selectively enabling and disabling the linear drive circuit and the digital drive circuit of each of the low-side gate drivers.

13. The method according to claim 11, further comprising the step of alternately enabling and disabling a pair of high-side gate drivers and low-side gate drivers corresponding to the pair of transistors that are alternately switched on and off.

14. The steps include receiving a signal from the digital drive circuit indicating that the aforementioned reverse current has been detected, In response to the signal from the digital drive circuit indicating that the reverse current has been detected, the steps include disabling the high-side gate driver and the low-side gate driver. The method according to claim 11, including the method described in claim 11.

15. The method according to claim 11, further comprising the step of disabling the high-side gate driver and the low-side gate driver when the input voltage is lower than a threshold voltage.

16. The method according to claim 11, comprising the step of adjusting the forward voltage of each of the low-side transistors by the linear drive circuit, wherein the forward voltage is adjusted in saturation mode with respect to the forward current up to a voltage offset and a current corresponding to the characteristic on-resistance of each of the low-side transistors.

17. In the digital drive circuit, the steps include comparing the drain voltage and source voltage of each of the low-side transistors, The steps include: when the drain voltage is greater than the source voltage, indicating that the aforementioned reverse current has been detected, outputting a signal from the digital drive circuit to switch off one of the low-side transistors; The method according to claim 11, including the method described in claim 11.

18. In the digital drive circuit, the steps include comparing the drain voltage and source voltage of each of the low-side transistors, When the drain voltage is greater than the source voltage by at least a voltage offset, the digital drive circuit outputs a signal to switch off one of the low-side transistors. The method according to claim 11, including the method described in claim 11.

19. The method according to claim 11, wherein each of the high-side gate drivers includes a digital drive circuit, and the method includes the step of driving each of the high-side transistors to switch on and off based on a forward current passing through each of the high-side transistors.

20. In the digital drive circuit, the steps include comparing the source voltage and drain voltage of each of the high-side transistors, A step of outputting a switching signal from the digital drive circuit to turn on one of the high-side transistors when the source voltage is greater than the drain voltage, wherein the switching signal is output when the source voltage is greater than the drain voltage by at least a voltage offset, and The method according to claim 19, including the method described in claim 19.

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