Semiconductor devices and their manufacturing methods, electronic devices

Abstract

This disclosure provides a semiconductor device, a method for manufacturing the same, and an electronic device. The semiconductor device comprises a substrate, and a memory section, a wiring section, and a peripheral circuit section provided on one side of the substrate, wherein the positions of the memory section, wiring section, and peripheral circuit section are different in a direction perpendicular to the substrate. The memory section includes at least two sub-memory arrays, the at least two sub-memory arrays being sequentially arranged along a first direction parallel to the substrate. Each sub-memory array includes at least one memory cell, each memory cell including a transistor. The wiring section includes at least one shared word line, and in at least two sub-memory arrays, the gates of transistors of memory cells located in different sub-memory arrays are electrically connected to the same shared word line, which is connected to the peripheral circuit section.

Claims

1. It is a semiconductor device, The device comprises a circuit board, and a memory section, a wiring section, and a peripheral circuit section provided on one side of the circuit board. In the direction perpendicular to the substrate, the positions of the memory section, the wiring section, and the peripheral circuit section are different. The memory section includes at least two sub-memory arrays, the at least two sub-memory arrays are sequentially arranged along a first direction parallel to the substrate, The sub-memory array includes at least one memory cell, and the memory cell includes a transistor. The wiring section includes at least one shared word line, In the at least two sub-memory arrays, the gates of the transistors of the memory cells located in different sub-memory arrays are electrically connected to the same shared word line, and the shared word line is connected to the peripheral circuit section. Semiconductor devices.

2. The gates of the transistors of the memory cells located at the same corresponding positions in different sub-memory arrays are electrically connected to the same shared word line. The semiconductor device according to claim 1.

3. The wiring section further includes at least two shared bit lines, and these at least two shared bit lines are connected in a one-to-one correspondence with the at least two sub-memory arrays. The semiconductor device according to claim 1 or 2.

4. The sub-memory array includes local bit lines, a strobe structure, and a plurality of the memory cells, the plurality of memory cells being sequentially arranged along a second direction parallel to the substrate. The local bit lines are electrically connected to the source or drain of the transistors in the plurality of memory cells, respectively, and the local bit lines are electrically connected to the strobe structure, thereby forming a memory cell array. The strobe structure is electrically connected to the corresponding shared bit line, The second direction intersects the first direction. The semiconductor device according to claim 3.

5. Multiple shared word lines, each connected in a one-to-one correspondence to multiple memory cells within the same sub-memory array, are located on the same wiring layer, the wiring layer is parallel to the substrate, and within the wiring layer, the multiple shared word lines are sequentially arranged along the second direction. The semiconductor device according to claim 4.

6. The sub-memory array has at least two memory cell rows, and the at least two memory cell rows are arranged sequentially along the first direction. At least two of the memory cell rows of the same submemory array are electrically connected to the same corresponding shared bit line. In at least two of the memory cell rows of the same submemory array, the shared word lines connected to different memory cell rows are located on different wiring layers, and the at least two wiring layers connected to at least two of the memory cell rows are sequentially arranged along a direction perpendicular to the substrate. The semiconductor device according to claim 4.

7. The memory cell includes a first transistor and a second transistor, the source or drain of the first transistor and the source or drain of the second transistor are both electrically connected to a local bit line. The shared word line connected in correspondence with the memory cell includes a first sub-shared word line and a second sub-shared word line, wherein the first sub-shared word line is electrically connected to the gate of the first transistor, and the second sub-shared word line is electrically connected to the gate of the second transistor. The first sub-shared word line and the second sub-shared word line are located in the same wiring layer, and within the wiring layer, the first sub-shared word line and the second sub-shared word line are arranged with a gap between them along the second direction and are offset in position along the first direction. A semiconductor device according to any one of claims 1 to 6.

8. The at least two sub-memory arrays are located on the same memory array layer, the memory unit has a plurality of memory array layers, and the plurality of memory array layers are sequentially stacked along a direction perpendicular to the substrate. The aforementioned plurality of memory array layers satisfy at least one of the following conditions: In the plurality of memory array layers, each sub-memory array whose orthogonal projection on the substrate overlaps is electrically connected to the same shared bit line. In the plurality of memory array layers, the gates of the transistors of each memory cell whose orthogonal projections on the substrate overlap are electrically connected to the same shared word line. A semiconductor device according to any one of claims 3 to 6.

9. The peripheral circuit section includes a word line driver circuit, and the shared word line is electrically connected to the word line driver circuit. The orthogonal projection of the word line driver circuit onto the substrate, and the orthogonal projection of the shared word line onto the substrate, both coincide with the orthogonal projection of the correspondingly connected memory cell onto the substrate. A semiconductor device according to any one of claims 1 to 8.

10. The number of the sub-memory arrays is multiple, and the multiple sub-memory arrays arranged sequentially along the first direction are divided into at least two memory arrays. In each sub-memory array of the same memory array, the gates of the transistors of the memory cells located at the same corresponding positions are electrically connected to the same shared word line. The gates of the transistors of the memory cells located at the same corresponding positions in the sub-memory arrays of different memory arrays are electrically connected to the same shared word line. The semiconductor device according to claim 9.

11. The number of the sub-memory arrays is multiple, and the multiple sub-memory arrays arranged sequentially along the first direction are divided into at least two memory arrays. In each sub-memory array of the same memory array, the gates of the transistors of the memory cells located at the same corresponding positions are electrically connected to the same shared word line. The gates of the transistors of the memory cells located at the same corresponding positions in the sub-memory arrays of different memory arrays are electrically connected to different shared word lines. The semiconductor device according to claim 9.

12. The word line driver circuit includes at least two subword line driver circuits, and the at least two subword line driver circuits are connected in a one-to-one correspondence with the at least two memory arrays. The semiconductor device according to claim 11.

13. At least two shared word lines, each electrically connected to the gates of transistors of memory cells located at the same corresponding positions in sub-memory arrays of different memory arrays, are located on the same wiring layer or on different wiring layers. The semiconductor device according to claim 11 or 12.

14. The peripheral circuit section includes a word line driver circuit, and the first sub-shared word line and the second sub-shared word line, which are connected in correspondence to the same memory cell, are each connected to different positions in the same word line driver circuit. The semiconductor device according to claim 7.

15. The peripheral circuit section further includes at least two sense amplifier circuits connected in a one-to-one correspondence with the at least two shared bit lines. The orthogonal projection of the sense amplifier circuit onto the substrate coincides with the orthogonal projection of the correspondingly connected shared bit line onto the substrate. A semiconductor device according to any one of claims 3 to 6.

16. The peripheral circuit section includes a word line driver circuit, and the word line driver circuit includes a plurality of bit points arranged in a matrix. Shared word lines located in the same wiring layer are each connected to different bit points in the same row of the word line driver circuit, and shared word lines located in different wiring layers are each connected to bit points in different rows of the word line driver circuit. The semiconductor device according to claim 6.

17. The memory section, the wiring section, and the peripheral circuit section are arranged sequentially along the direction away from the substrate. A semiconductor device according to any one of claims 1 to 16.

18. The peripheral circuit section, the wiring section, and the memory section are arranged sequentially along the direction away from the substrate. A semiconductor device according to any one of claims 1 to 16.

19. A method for manufacturing semiconductor devices, The aforementioned method, To provide a substrate, The aforementioned substrate is provided with a memory section, a wiring section, and a peripheral circuit section formed on one side thereof. In a direction perpendicular to the substrate, the positions of the memory section, the wiring section, and the peripheral circuit section are different, the memory section includes at least two sub-memory arrays, the at least two sub-memory arrays are sequentially arranged along a first direction parallel to the substrate, the sub-memory array includes at least one memory cell, and the memory cell includes a transistor. The wiring section includes at least one shared word line, and in the at least two sub-memory arrays, the gates of the transistors of the memory cells located in different sub-memory arrays are electrically connected to the same shared word line, and the shared word line is connected to the peripheral circuit section. A method for manufacturing semiconductor devices.

20. It is an electronic device, A semiconductor device comprising the semiconductor device described in any one of claims 1 to 18, electronic equipment.

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