Decoupling capacitor structure and assembly

Abstract

Decoupling capacitor structures, sacrificial component structures, and assemblies are provided. For example, a decoupling capacitor structure includes a first interposer having opposing first and second surfaces, and a decoupling capacitor having opposing first and second surfaces. The decoupling capacitor is disposed adjacent to the first interposer such that the first surface of the decoupling capacitor is adjacent to the second surface of the first interposer. A first external terminal and a third external terminal of the decoupling capacitor are formed on the first surface of the decoupling capacitor and are electrically connected to the first interposer. The decoupling capacitor structure may include a second interposer such that the decoupling capacitor is sandwiched between the first and second interposers. One or more decoupling capacitor structures can be disposed in a substrate to form a decoupling capacitor assembly, and multiple decoupling capacitor structures can be stacked to form a multilayer structure.

Description

[Technical Field]

[0001] Related applications This application is based on U.S. Provisional Patent Application No. 63 / 509,035, filed on June 20, 2023, which claims priority, and the literature is incorporated herein by reference. [Background technology]

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has resulted from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for miniaturization of electronic devices increases, the need for smaller and more ingenious packaging techniques for semiconductor chips has emerged. Interposers formed from organic, inorganic (e.g., glass), or silicon materials are often used to help implement high-density mounting of semiconductor chips. Such assemblies are often referred to as chip-on-interposers or chip-on-wafer (CoW) structures when the interposer is formed from a semiconductor material (e.g., silicon). The CoW structure can then be mounted on a build-up packaging substrate to form a CoWoS structure, and the resulting package can finally be connected to a printed circuit board. As part of the power delivery system to the chip, one or more decoupling capacitors are also typically used so that any sudden demands for current can be supplied to the chip while the voltage is kept constant or nearly constant. Unfortunately, however, the increasing switching speed in the chip has resulted in an increase in parasitic inductance. Thus, there is now a need for improved microelectronic assemblies that utilize decoupling capacitors. [Overview of the Initiative] [Means for solving the problem]

[0003] According to one embodiment of the present invention, the decoupling capacitor structure includes a first interposer having a first surface and a second surface on the opposite side, and a decoupling capacitor having a first surface and a second surface on the opposite side. The decoupling capacitor includes alternating dielectric layers and internal electrode layers. The internal electrode layers include a first internal electrode layer and a second internal electrode layer. The decoupling capacitor further includes a first external terminal, a second external terminal, a third external terminal, and a fourth external terminal, wherein the first external terminal is electrically connected to the first internal electrode layer and is disposed on the first surface of the decoupling capacitor, the second external terminal is electrically connected to the first internal electrode layer and is disposed on the second surface of the decoupling capacitor, the third external terminal is electrically connected to the second internal electrode layer and is disposed on the first surface of the decoupling capacitor, and the fourth external terminal is electrically connected to the second internal electrode layer and is disposed on the second surface of the decoupling capacitor. The decoupling capacitor is disposed adjacent to the first interposer such that the first surface of the decoupling capacitor is adjacent to the second surface of the first interposer. The first external terminal and the third external terminal are electrically connected to the first interposer.

[0004] According to another embodiment of the present invention, a decoupling capacitor assembly includes a substrate defining a cavity therein and a decoupling capacitor structure disposed within the cavity. The decoupling capacitor structure includes a first interposer having a first surface and a second surface on the opposite side, and a decoupling capacitor having the first surface and the second surface on the opposite side. The decoupling capacitor contains alternating dielectric layers and internal electrode layers. The internal electrode layers include a first internal electrode layer and a second internal electrode layer. The decoupling capacitor further includes a first external terminal, a second external terminal, a third external terminal, and a fourth external terminal, wherein the first external terminal is electrically connected to a first internal electrode layer and is disposed on a first surface of the decoupling capacitor; the second external terminal is electrically connected to a first internal electrode layer and is disposed on a second surface of the decoupling capacitor; the third external terminal is electrically connected to a second internal electrode layer and is disposed on a first surface of the decoupling capacitor; and the fourth external terminal is electrically connected to a second internal electrode layer and is disposed on a second surface of the decoupling capacitor. The decoupling capacitor is disposed adjacent to the first interposer such that the first surface of the decoupling capacitor is adjacent to the second surface of the first interposer. The first and third external terminals are electrically connected to the first interposer.

[0005] According to yet another embodiment of the present invention, the multilayer decoupling capacitor structure includes a plurality of interposers and a plurality of decoupling capacitors. Each of the plurality of decoupling capacitors has a first surface and a second surface on the opposite side, and each decoupling capacitor contains alternating dielectric layers and internal electrode layers. The internal electrode layers include a first internal electrode layer and a second internal electrode layer. Each decoupling capacitor further includes a first external terminal, a second external terminal, a third external terminal, and a fourth external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on the first surface of the decoupling capacitor, the second external terminal being electrically connected to the first internal electrode layer and disposed on the second surface of the decoupling capacitor, the third external terminal being electrically connected to the second internal electrode layer and disposed on the first surface of the decoupling capacitor, and the fourth external terminal being electrically connected to the second internal electrode layer and disposed on the second surface of the decoupling capacitor. Multiple interposers and multiple decoupling capacitors are arranged in at least two layers, each layer containing at least one decoupling capacitor of multiple decoupling capacitors arranged between two interposers of the multiple interposers. The at least two layers are stacked adjacent to each other such that one interposer of the multiple interposers is common to at least two layers.

[0006] According to yet another embodiment of the present invention, a microelectronic assembly includes a semiconductor structure, an assembly interposer electrically connected to the semiconductor structure, a package substrate electrically connected to the assembly interposer, a decoupling capacitor assembly, and a circuit board. The decoupling capacitor assembly includes a substrate defining a cavity therein and a decoupling capacitor structure disposed within the cavity. The decoupling capacitor structure includes a first interposer having a first surface and a second surface on the opposite side, and a decoupling capacitor having a first surface and a second surface on the opposite side. The decoupling capacitor contains alternating dielectric layers and internal electrode layers. The internal electrode layers include a first internal electrode layer and a second internal electrode layer. The decoupling capacitor further includes a first external terminal, a second external terminal, a third external terminal, and a fourth external terminal, the first external terminal being electrically connected to a first internal electrode layer and disposed on a first surface of the decoupling capacitor; the second external terminal being electrically connected to a first internal electrode layer and disposed on a second surface of the decoupling capacitor; the third external terminal being electrically connected to a second internal electrode layer and disposed on a first surface of the decoupling capacitor; and the fourth external terminal being electrically connected to a second internal electrode layer and disposed on a second surface of the decoupling capacitor. The decoupling capacitor is disposed adjacent to a first interposer such that the first surface of the decoupling capacitor is adjacent to the second surface of the first interposer. The first and third external terminals are electrically connected to the first interposer. The first interposer is electrically connected to a decoupling capacitor assembly substrate, and the decoupling capacitor assembly substrate is electrically connected to a package substrate. The second and fourth external terminals of the decoupling capacitor are electrically connected to the circuit board.

[0007] Other features and embodiments of the present invention are described in more detail below.

[0008] A complete and implementable disclosure of the present invention (including its best mode for those skilled in the art) is described more specifically in the remainder of the specification (including by reference to the accompanying drawings). [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view of one embodiment of the microelectronic assembly of the present invention. [Figure 2] This is a cross-sectional view of another embodiment of the microelectronic assembly of the present invention. [Figure 3] This is a cross-sectional view of yet another embodiment of the microelectronic assembly of the present invention. [Figure 4A] This is a perspective view of one embodiment of a decoupling capacitor that may be used in the present invention. [Figure 4B] Figure 4A is a side view of the internal electrode layer of the capacitor. [Figure 5A] This is a perspective view of another embodiment of a decoupling capacitor that may be used in the present invention. [Figure 5B] Figure 5A is an end view of the capacitor. [Figure 5C] Figure 5A is a side view of the capacitor. [Figure 6A] This is a perspective view of another embodiment of a decoupling capacitor that may be used in the present invention. [Figure 6B] Figure 6A is a side view of the internal electrode layer of the capacitor. [Figure 7A] This is a perspective view of another embodiment of a decoupling capacitor that may be used in the present invention. [Figure 7B] Figure 7A is a side view of the internal electrode layer of the capacitor. [Figure 7C] Figure 7A is a perspective view of the internal electrode layer of the capacitor. [Figure 7D] Figure 7A is a cross-sectional perspective view of the capacitor. [Figure 8A] Perspective view of another embodiment of a decoupling capacitor that can be used in the present invention. [Figure 8B] Side view of the internal electrode layer of the capacitor of FIG. 8A. [Figure 8C] Perspective view of the internal electrode layer of the capacitor of FIG. 8A. [Figure 8D] Cross-sectional perspective view of the capacitor of FIG. 8A. [Figure 9A] Perspective view of another embodiment of a decoupling capacitor that can be used in the present invention. [Figure 9B] Cross-sectional perspective view of the capacitor of FIG. 9A. [Figure 10A] Perspective view of yet another embodiment of a decoupling capacitor that can be used in the present invention. [Figure 10B] Side perspective view of one configuration of the internal electrode layer of the capacitor of FIG. 10A. [Figure 10C] Side perspective view of another configuration of the internal electrode layer of the capacitor of FIG. 10A. [Figure 11A] Side view of a decoupling capacitor structure that can be used in the present invention. [Figure 11B] Side view of another embodiment of a decoupling capacitor structure that can be used in the present invention. [Figure 11C] Side view of yet another embodiment of a decoupling capacitor structure that can be used in the present invention. [Figure 12A] Side view of yet another embodiment of a decoupling capacitor structure that can be used in the present invention. [Figure 12B] Perspective view of yet another embodiment of a decoupling capacitor structure that can be used in the present invention. [Figure 13A] Cross-sectional view of a decoupling capacitor assembly that can be used in the present invention. [Figure 13B] Cross-sectional view of another embodiment of a decoupling capacitor assembly that can be used in the present invention. [Figure 14A]This is a side view of a multilayer decoupling capacitor structure that can be used in the present invention. [Figure 14B] This is a side view of another embodiment of a multilayer decoupling capacitor structure that may be used in the present invention. [Figure 15A] This is a side view of an embodiment of a component structure having a sacrificial plate that can be used in the present invention. [Figure 15B] This is a side view of the embodiment shown in Figure 15A, with the sacrificial plate removed. [Figure 15C] This is a side view of the embodiment shown in Figure 15A, with a portion of each sacrificial plate removed. [Modes for carrying out the invention]

[0010] Repeated references to letters in this specification and in the figures are intended to represent the same or similar features or elements of the present invention.

[0011] Those skilled in the art will understand that this discussion is merely a description of illustrative embodiments and is not intended to limit any broader aspects of the present invention.

[0012] Generally speaking, the present invention is directed to a decoupling capacitor structure, a decoupling capacitor assembly, a multilayer decoupling capacitor structure, and a microelectronic assembly comprising a semiconductor structure, an assembly interposer electrically connected to the semiconductor structure, an organic package substrate electrically connected to the interposer, and at least one of the decoupling capacitor structure, decoupling capacitor assembly, or multilayer decoupling capacitor structure. Each structure or assembly includes at least one decoupling capacitor disposed adjacent to at least one interposer. The decoupling capacitor has a first surface and a second surface on the opposite side. The decoupling capacitor contains alternating dielectric layers and internal electrode layers, the internal electrode layers comprising a first internal electrode layer and a second internal electrode layer. A first external terminal is electrically connected to the first internal electrode layer and disposed on the first surface of the capacitor, and a second external terminal is electrically connected to the first internal electrode layer and disposed on the second surface of the capacitor. Similarly, the third external terminal is electrically connected to the second internal electrode layer and is located on the first surface of the capacitor, and the fourth external terminal is electrically connected to the second internal electrode layer and is located on the second surface of the capacitor. Typically, the first and second external terminals have the same polarity (e.g., positive), and the third and fourth external terminals have the same polarity (e.g., negative). Nevertheless, in the microelectronic assembly, the first and third external terminals of the decoupling capacitor are electrically connected to the package substrate, and the second and fourth external terminals of the decoupling capacitor are electrically connected to the printed circuit board.

[0013] Herein, various embodiments of the present invention will be described in more detail below.

[0014] I. Semiconductor Structures One or more semiconductor structures (e.g., dies, wafers, integrated circuit devices, etc.) can generally be used in microelectronic assemblies. Generally speaking, a semiconductor structure can include an insulating material (e.g., a dielectric material formed in multiple layers, as is known in the art) and multiple conductive paths formed through the insulating material. The insulating material can include dielectric materials such as silicon dioxide, silicon nitride, oxynitrides, polyimide materials, glass-reinforced epoxy matrix materials, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photo-imageable dielectrics, and / or benzocyclobutene-based polymers). The insulating material can also include a semiconductor material such as silicon, germanium, or III-V materials (e.g., gallium nitride) and one or more additional materials. For example, the insulating material can include silicon dioxide or silicon nitride. The conductive paths in the die may include conductive traces and / or conductive vias, and any of the conductive contacts in the die may be connected in any suitable manner. The semiconductor structure may include mixed-pitch dies (meaning the die has sets of conductive contacts with different pitches), for example, the die may have "coarser" conductive contacts for connecting to an interposer of a microelectronic assembly. The structure may also include single-sided dies (having conductive contacts on only one surface) and / or double-sided dies (conductive contacts on the first surface and on the second surface on the opposite side). The conductive paths in the die may be bordered by liner material (e.g., adhesive liners and / or barrier liners, etc.) as appropriate. The semiconductor structure may also include wafers.In some embodiments, the semiconductor structure includes monolithic silicon, fan-out or fan-in package dies, or die stacks (e.g., wafer stacks, die stacks, or multilayer die stacks).

[0015] Furthermore, the semiconductor structure may have an integrated circuit ("IC") structure, which may take the form of a discrete IC device or "chip." Such an IC device may include one or more device layers disposed on a die substrate. The die substrate may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination thereof). The die substrate may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate may be formed using alternative materials, which may or may not be combined with silicon, and which include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In addition, materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate. The device layer may include one or more transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)), supporting circuits for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. The device layer may include, for example, one or more source and / or drain (S / D) regions, a gate for controlling the current flow in the transistor between the S / D regions, and one or more S / D contacts for routing electrical signals to and from the S / D regions. Each transistor may include a gate formed from at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials.High-k dielectric materials can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to, hafnium oxide, silicon hafnium oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, silicon zirconium oxide, tantalum oxide, titanium oxide, titanium barium strontium oxide, titanium barium oxide, titanium strontium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and zinc lead niobate. In some embodiments, when high-k materials are used, an annealing process may be carried out to improve their quality for gate dielectrics.

[0016] The gate electrode can be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor is a PMOS or NMOS transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a filler metal layer. Furthermore, metal layers may be included for other purposes (e.g., barrier layers). With respect to PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). With respect to NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning). Electrical signals (e.g., power and / or input / output (I / O) signals) can be routed to and / or from devices in the device layer (e.g., transistors) through one or more interconnect layers disposed above the device layer. For example, conductive features of the device layer (e.g., gate and S / D contacts) can be electrically coupled to interconnect structures that can optionally form a metallization stack (also referred to as an "ILD stack") of the IC device. The interconnect structures can include lines and / or vias filled with conductive material (e.g., metal).Lines can be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate on which the device layer is formed. Vias can be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate on which the device layer is formed.

[0017] IC devices can include, for example, memory devices (e.g., random access memory (RAM) devices, e.g., static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridging RAM (CBRAM) devices, erasable programmable read-only memory (EPROM) chips, non-volatile memory (e.g., 3D XPoint), volatile memory (e.g., high-bandwidth memory), stacked memory, etc.); logic devices (e.g., AND, OR, NAND, or NOR gates, programmable logic devices, etc.); processor devices (e.g., central processing units (CPUs), graphics processing units (GPUs), etc.); application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and platform controller hubs (PCHs), as well as any other suitable memory, logic, and / or processor devices. Multiple devices can be combined on a single structure. For example, a memory array formed by multiple memory devices can be formed on the same die as processing devices or other logic configured to store information in the memory devices or to execute instructions stored in the memory array.

[0018] Furthermore, the semiconductor structure can be a “chiplet,” which is a small integrated circuit (IC) containing a clearly defined subset of functionality that is one part of a processing module that makes up a larger integrated circuit, such as a computer processor. In some embodiments, one or more chiplets are coupled in various ways to a host chip, and each of the one or more chiplets contains its own cache (e.g., including a last-level cache (LLC)) that is accessible to one or more cores of the host chip. The host chip can contain one or more processor cores, each capable of acting as a consumer of memory resources, and the chiplets can contain one or more memory arrays coupled to each of the processor cores of the host chip, each accessible by each of the processor cores. In this particular context, the terms “memory,” “memory array,” “memory resource,” and related terms generally refer to either cached memory or non-cache memory (e.g., system memory). Similarly, the term “memory controller” generally refers to controller circuitry that provides access to either cached memory or non-cache memory. The host chip can contain processor cores that will act as consumers of memory resources. For example, a host chip can run an operating system, a binary input / output system (BIOS), and / or various other software processes. To facilitate the execution of such software, a chiplet may include one or more memory arrays that are linked to the processor core via a hardware interface. In one embodiment, the memory array includes static random access memory (SRAM) cells or dynamic random access memory (DRAM) cells.Additionally or alternatively, processor cores can be coupled to cache data in a memory array; for example, a processor core may be coupled to access the last-level cache (LLC) of the memory array. In various other embodiments, the memory array may contain non-volatile memory (NVM) cells. The chiplet may also contain a memory controller coupled between the hardware interface and the memory array to control memory access on behalf of the process performed by the core. By providing the memory array within a chiplet disposed between the hardware interface and the host chip, data locality can be improved for use by one or more cores in a packaged device. This improved data locality enables access to memory resources that are relatively more space-efficient, time-efficient, and / or power-efficient.

[0019] Semiconductor structures can be arranged in a two-dimensional configuration or array (e.g., 2D, 2.1D, 2.3D, or 2.5D heterogeneous integration) as known in the art, or stacked to form a three-dimensional configuration. When using a stacked configuration, a semiconductor structure can contain two or more semiconductor substrates (e.g., chips, interposers, etc.) mounted on a circuit board. When implemented as a semiconductor chip, the substrate can be one of countless different types of circuit devices used in electronic devices, such as microprocessors, graphics processors, combined microprocessor / graphics processors, application-specific integrated circuits, or memory devices, and can be single-core or multi-core. The substrate can be constructed from bulk semiconductors (e.g., silicon or germanium, etc.) or semiconductor-on-insulator materials (e.g., silicon-on-insulator materials, etc.). Circuit boards can be semiconductor chip package substrates, circuit cards, or virtually any other type of printed circuit board. While monolithic structures can be used for circuit boards, a more typical configuration would involve utilizing a build-up design. In this regard, the circuit board may consist of a central core, with one or more build-up layers formed on top of the central core, and one or more additional build-up layers formed below the central core. The core itself may consist of a stack of one or more layers. Electrical paths between substrates and circuit boards, and between any two substrates, may be provided by interconnection structures.

[0020] II. Interposer As described above, the semiconductor structure is electrically connected to one or more interposers, and the resulting microelectronic assembly is now considered a “chip-on-interposer” structure. In particular, the interposer can provide an intervening substrate to help bridge the circuit board and the semiconductor structure, and to help spread the connections to a wider pitch or reroute the connections to different connections. The semiconductor structure can be electrically connected to the interposer by one or more coupling components. The coupling components can electrically and mechanically couple the chip-on-interposer structure to the circuit board and can include, for example, solder bumps, solder balls, male and female parts of sockets, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. The underfill material can be an insulating material such as a suitable epoxy material. When used, the underfill material can include capillary underfill, non-conductive film (NCF), or molded underfill. In some embodiments, the underfill material may include epoxy flux, which assists in soldering the semiconductor structure and subsequently polymerizes and encapsulates the interconnects within the interposer.

[0021] An interposer generally comprises an insulating material and one or more conductive paths through the insulating material (e.g., including conductive traces and / or conductive vias, as shown). In one embodiment, for example, the insulating material can be an organic material, such as a bismaleimidotriazine ("BT") resin material (e.g., BT, BT-epoxy resin, etc.), an epoxy resin material (e.g., glass fiber reinforced epoxy resin (e.g., FR4)), a polyimide material, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). Alternatively, the insulating material can be an inorganic interposer, such as one formed from a ceramic material (e.g., glass), as well as one formed from a semiconductor material (e.g., silicon, germanium, and other Group III-V materials (e.g., gallium nitride) and Group IV materials, etc.). The conductive paths serve as a mechanism for electrically connecting the interposer to a semiconductor structure via a connecting component. Such a path may include one or more metal interconnects and vias, as is known in the art. In one embodiment, for example, the interposer may be formed from silicon, and vias may be formed therein, which are referred to as “through-silicon vias” (“TSVs”).

[0022] Regardless of the mode in which it is formed, an interposer can be passive or active, depending on the particular embodiment. “Passive” generally means that the interposer generally does not have embedded electronic components. On the other hand, an “active” interposer generally contains one or more electronic components embedded in an insulating material. Examples of such electronic components may include, for example, capacitors (e.g., decoupling capacitors), resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, and microelectromechanical systems (MEMS) devices, can also be formed within the interposer. For example, an active interposer may include an active layer and a bulk semiconductor layer. The front surface of the active layer may be referred to herein as the “active side,” and the opposite surface of the bulk semiconductor layer may be referred to as the “rear side.” In one embodiment, the active layer may include one or more electronic components formed on the active side, such as a Level 1 (L1) memory element used as a memory cache for storing a configuration bitstream for configuring logic sectors within the coprocessor. The active layer may optionally include decryption / decryption circuits for processing encrypted and / or decrypted configuration bitstreams. The semiconductor layer may include a TSV connecting the electronic components in the active layer (e.g., the L1 memory element) to a linking element (e.g., a solder ball). For example, the L1 cache may receive the configuration bitstream from the host processor through the solder ball and the TSV. In this way, the energy efficiency of transferring signals and power between the interposer's active layer and the package substrate can be improved.

[0023] III. Package substrates In addition to the interposer, the microelectronic assembly further includes a “build-up” package substrate to help bridge high-density interconnections and functionality between the semiconductor structure, the interposer, and the circuit board. The package substrate generally includes an organic insulating material and one or more conductive paths through the insulating material (e.g., including conductive traces and / or conductive vias, as shown). The organic insulating material can include, for example, bismaleimidotriazine ("BT") resin materials (e.g., BT, BT-epoxy resin, etc.), epoxy resin materials (e.g., glass fiber reinforced epoxy resin (e.g., FR4)), polyimide materials, and low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). In some embodiments, the insulating material can be a laminate or build-up film (e.g., Ajinomoto build-up film). The conductive paths can connect the semiconductor structure to the circuit board and decoupling capacitors. Any suitable arrangement of conductive paths through any suitable number of insulating layers can generally be used. Conductive paths can be fabricated from any suitable conductive material (e.g., copper). Conductive paths can be bordered with liner material (e.g., adhesive liners and / or barrier liners) as appropriate. In certain embodiments, the package substrate can be a lower-density medium, and the semiconductor structure and / or interposer can be a higher-density medium. As used herein, the terms “lower density” and “higher density” are relative terms indicating that conductive paths in a lower-density medium (e.g., including conductive lines and conductive vias) have a larger and / or larger pitch than conductive paths in a higher-density medium.For example, higher-density media can be manufactured using a modified semi-additive or semi-additive build-up process with advanced lithography (featuring small vertical interconnection features formed by an advanced laser or lithography process), while lower-density media can be PCBs manufactured using standard PCB processes (e.g., a standard subtractive process using etching chemistry to remove unwanted copper areas, and featuring coarse vertical interconnection features formed by a standard laser process).

[0024] IV. Decoupling Capacitors As shown above, at least one decoupling capacitor is electrically connected to the package substrate and the circuit board (e.g., printed circuit board). Generally speaking, a decoupling capacitor contains a main body comprising alternating dielectric layers and internal electrode layers. The internal electrode layers include at least a first internal electrode layer and a second internal electrode layer. The capacitor may contain, for example, at least two sets of internal electrode layers, for example, at least three sets, or for example, at least four sets of internal electrode layers. Naturally, it should be understood that the capacitor may and is not necessarily limited to any number of sets of alternating dielectric layers and internal electrode layers.

[0025] Typically, a capacitor includes an upper surface (e.g., a first surface) and a lower surface opposite the upper surface (e.g., a second surface). The capacitor also includes at least one side surface, particularly at least two side surfaces, extending between the upper and lower surfaces. Furthermore, the capacitor may include at least one end surface, particularly at least two end surfaces, extending between the upper and lower surfaces. The side surfaces may extend in the length (L) direction and generally have longer dimensions than the end surfaces, while the end surfaces extend in the width (W) direction and generally have shorter dimensions. In one embodiment, the capacitor may have a parallelepiped shape, such as a rectangular parallelepiped shape. The overall dimensions of the capacitor may depend on the specific application. However, typically, the height or thickness of the capacitor is about 10 μm to about 5,000 μm, in some embodiments about 20 μm to about 2,500 μm, in some embodiments about 50 μm to about 1,500 μm, and in some embodiments about 100 μm to about 1,000 μm. When surrounded by a ball grid array, the height of the capacitor can be within 10% of the height (or diameter) of the balls in the ball grid array, for example, within 7%, for example, within 5%, for example, within 3%, for example, within 2%, for example, within 1%, etc. For example, such a height can be the original height before any reflow. Similarly, the length of the capacitor in the "L" direction can be approximately 50 μm to approximately 10,000 μm, and in some embodiments, approximately 100 μm to approximately 7,500 μm, and in some embodiments, approximately 1,000 μm to approximately 5,000 μm. The width of the capacitor in the "W" direction can be approximately 25 μm to approximately 5,000 μm, and in some embodiments, approximately 50 μm to approximately 3,500 μm, and in some embodiments, approximately 500 μm to approximately 2,500 μm.

[0026] The first and second internal electrode layers can be interleaved in a manner in which the dielectric layers are positioned opposite each other and spaced apart, with the dielectric layers located between them. Each set of alternating dielectric layers and internal electrode layers can be separated from adjacent sets by a certain distance. For example, this distance can be greater than the thickness of the individual dielectric layers in the set, for example, at least twice, in some embodiments at least three times, in some embodiments at least five times, and in some embodiments at least ten times, the thickness of the dielectric layers in the set. Each set of internal electrode layers, and / or the entire capacitor, can contain about 10 to about 4,000 internal electrode layers, in some embodiments about 50 to about 2,000, and in some embodiments about 100 to about 1,000 internal electrode layers. The thickness of the dielectric layers and / or internal electrode layers is not limited and can be any thickness as desired depending on the performance characteristics. For example, the thickness of the internal electrode layer and / or individual dielectric layers can be in the range of about 100 nm to about 10 μm, in some embodiments it can be in the range of about 500 nm to about 8 μm, and in some embodiments it can be in the range of about 1 μm to about 5 μm. In certain embodiments, if the capacitor includes a second set of alternating dielectric layers and internal electrode layers, the distance between the first internal electrode layer of one set and the last internal electrode layer of another set can be greater than the distance between adjacent internal electrode layers in a given set. For example, the distance between the first internal electrode layer of the first set and the last internal electrode layer of the second set can be greater than the distance between the first internal electrode layer of the first set and the second internal electrode layer.

[0027] While not always necessary, the dielectric region of a decoupling capacitor can also contain one or more voids. In this regard, the dielectric region can be a region containing dielectric material but not internal electrode material. Thus, the dielectric region can constitute a region that does not contain alternating dielectric layers and internal electrode layers. Therefore, the dielectric region can contain dielectric material between each set of alternating dielectric layers and internal electrode layers in the "W" direction. In addition, the dielectric region can contain dielectric material between the lateral edges of the electrodes in a given set of alternating dielectric layers and internal electrode layers and adjacent end surfaces in the longitudinal direction, for example, in the extent that such internal electrode layers do not extend to the end surfaces and are offset from the end surfaces. Such a dielectric region can be formed from ceramic green sheets of alternating dielectric layers and internal electrode layers, but it should be understood that such a region does not contain any internal electrode material or corresponding layers. As a result, air voids can be provided within such a region. In addition, the dielectric region can contain dielectric material present between the first internal electrode layer of each set and adjacent side surfaces of the capacitor. Furthermore, the dielectric region may also include dielectric material present between the last internal electrode layer of each set and the adjacent side surface of the capacitor. Alternatively, the dielectric region may include dielectric material between the lateral edges of adjacent lead tabs extending from the main body of the internal electrode layer. In one particular embodiment, the dielectric region may include a region within the capacitor present between two external terminals. In addition, it should be understood that the dielectric region may include any combination of the regions described above.

[0028] As shown above, the dielectric region includes a region that contains dielectric material but does not contain internal electrode material. Therefore, when air voids are not considered, the dielectric region can contain 90 volume% or more of dielectric material, for example, 93 volume% or more, for example, 95 volume% or more, for example, 97 volume% or more, for example, 98 volume% or more, for example, 99 volume% or more, for example, 100 volume% or more, etc. Such air voids can be free of any material, in particular any dielectric material or internal electrode material. In one embodiment, the air void can be enclosed by enclosure material (for example, partially or completely). In one embodiment, the air void can be partially enclosed by enclosure material. By partially enclosing, the enclosure material is only partially present around the interior of the air void, and is partially separated from the dielectric material. In this regard, at least certain peripheral portions of the air void can be in direct contact with the dielectric material of the dielectric region. In another embodiment, the air void can be completely or entirely enclosed by enclosure material. By being completely enclosed, the enclosure material is present around the interior of the air void, so that it is entirely separated from the dielectric material. Nevertheless, the enclosure material can be used to act as a barrier between the interior of the air void and the dielectric material in the dielectric region. In one embodiment, the enclosure material can be a non-conductive material. However, it should be understood that in one embodiment, the air void may not be enclosed (even partially) by enclosure material.

[0029] Voids can be provided without a barrier between the air void and the dielectric material of the dielectric region. Air voids can and are not necessarily limited to any shape. For example, the shape can be a sphere, a cylinder, etc. In one embodiment, the shape can be a sphere. Air voids can have maximum dimensions (e.g., length, width, diameter, etc.) from about 5 μm to about 5,000 μm, and in some embodiments, they can have maximum dimensions from about 50 μm to about 2,500 μm, and in some embodiments, from about 100 μm to about 1,000 μm. Voids can be formed using any known technique, for example, by printing a specific pattern on a ceramic green sheet, and then laminating and firing the stacked laminates. Alternatively, voids can be formed using various drilling techniques to provide any desired shape within the dielectric material of the dielectric region. Voids can also be provided using one or more vias (e.g., through-hole vias). The vias do not necessarily have to be filled with material (e.g., any conductive or nonconductive material), and air may be present inside them. In addition, in one embodiment, vias can be provided so that they exist only within the dielectric region. In this regard, vias can be provided so that they do not contact any of the internal electrode layers. In one embodiment, vias can extend from the upper surface of the capacitor to the lower surface of the capacitor. In this regard, vias can be columnar, extending through the thickness of the capacitor. Thus, vias can be through-hole conductive vias. In another embodiment, vias can extend only partially through the thickness of the capacitor. For example, vias can extend only partially through the thickness of the capacitor, for example, from about 10% to about 90% of the capacitor thickness, and in some embodiments, from about 20% to about 80%.

[0030] In addition to alternating internal electrode layers and dielectric layers, the decoupling capacitor also includes a first external terminal and a second external terminal, the first external terminal being electrically connected to the first internal electrode layer and located on a first surface (e.g., the upper surface) of the capacitor, and the second external terminal being electrically connected to the first internal electrode layer and located on a second surface (e.g., the lower surface) of the capacitor. Similarly, a third external terminal being electrically connected to the second internal electrode layer and located on the first surface of the capacitor, and a fourth external terminal being electrically connected to the second internal electrode layer and located on the second surface of the capacitor. Typically, the first and second external terminals have the same polarity (e.g., positive), and the third and fourth external terminals have the same polarity (e.g., negative). Nevertheless, the first and third external terminals of the decoupling capacitor are electrically connected to the package substrate, and the second and fourth external terminals of the decoupling capacitor are electrically connected to the printed circuit board.

[0031] Furthermore, the capacitor may include external terminals on the opposite end surfaces. For example, one or more of the external terminals may extend from a first surface (e.g., the upper surface) and / or a second surface (e.g., the lower surface) to the end surface. When present on the end surface, the external terminals may be present only partially on the end surface and not cover the entire end surface. In another embodiment, the capacitor may not include external terminals on the opposite end surfaces. In one particular embodiment, the external terminals may not be present on the side surfaces of the capacitor. Nevertheless, the external terminals generally include at least one first polarity terminal and at least one second and opposite polarity terminal. The capacitor may include at least one, for example, at least two, for example, at least four, for example, at least six, for example, at least eight, etc., first polarity terminals and / or second and opposite polarity terminals on the upper surface of the capacitor. Additionally, the capacitor may include the aforementioned number of terminals on the lower surface of the capacitor.

[0032] A capacitor may have an equal number of first polarity terminals and / or second polarity terminals on its upper and lower surfaces. The number of first polarity terminals may be equal to the number of second and opposite polarity terminals on the upper surface of the capacitor. The number of first polarity terminals may be equal to the number of second and opposite polarity terminals on the lower surface of the capacitor. The total number of terminals present on the upper surface of the capacitor may be equal to the total number of terminals present on the lower surface of the capacitor. The total number of first polarity terminals present on the upper and lower surfaces of the capacitor may be equal to the total number of second and opposite polarity terminals present on the upper and lower surfaces of the capacitor. Typically, similar polarity terminals on the lower surface of the capacitor corresponding to a particular set of alternating dielectric and internal electrode layers are electrically connected to similar polarity terminals on the upper surface of the capacitor. Similar polarity terminals located on the upper and lower surfaces of the capacitor do not necessarily have to be interlocked with each other. In this regard, corresponding similar polarity terminals on the upper and lower surfaces may not be offset by their terminal position, but instead may be positioned directly above or below another similar polarity terminal on the opposite upper or lower surface. In other words, corresponding similar polarity terminals corresponding to a particular set of alternating dielectric layers and internal electrode layers, and, among other things, the corresponding lead tabs of such sets, may be substantially aligned. Being substantially aligned means that the offset of one lateral edge of a polarity terminal on the upper surface from its side edge is within + / -10% of the offset of the corresponding polarity terminal on the lower surface from its side edge, for example, within + / -5%, for example, within + / -4%, for example, within + / -3%, for example, within + / -2%, for example, within + / -1%, for example, within + / -0.5%, etc.

[0033] The pitch of external terminals (i.e., the nominal distance between centers, also referred to as the center-to-center spacing) can be determined by a particular circuit board configuration. The pitch between external terminals in one direction (i.e., the x-direction or the y-direction) can be the same as the pitch between adjacent external terminals in the other direction (i.e., the y-direction or the x-direction, respectively). That is, the pitch between any two adjacent external terminals can be substantially the same as the pitch between any other two adjacent external terminals. The pitch can be, for example, in the range of about 0.1 mm to about 2 mm, in some embodiments in the range of about 0.2 mm to about 1.5 mm, and in some embodiments in the range of about 0.4 mm to about 1.4 mm.

[0034] If desired, external terminals can be positioned similarly to the configuration of a ball grid array. For example, external terminals can be provided to make contact as typically used by a ball grid array (particularly a surrounding ball grid array). In this regard, the pitch of the external terminals can be the same as the pitch of the surrounding ball grid array. That is, the pitch can be within 10% of the pitch of the surrounding ball grid array, for example, within 5%, within 2%, within 1%, within 0.5%, within 0.1%, etc. In addition, like a ball grid array, external terminals can be provided in rows and columns. That is, external terminals can be provided such that they exist in at least one row and at least two columns. For example, external terminals can be provided in at least two rows, for example, at least three rows, etc., for example, at least four rows, etc. The number of rows can be determined by the number of different sets of alternating dielectric layers and internal electrode layers. In addition, the external terminals can be provided in at least two columns, for example, at least three columns, for example, at least four columns, and so on. The number of columns can be determined by the number of different columnar tabs of the internal electrodes.

[0035] The length of an external terminal extending along the upper surface (i.e., extending longitudinally from one end surface to another) can be the same as the length of the corresponding external terminal extending along the lower surface. For example, the length of an external terminal can be approximately 0.3 mm to approximately 1.1 mm, in some embodiments approximately 0.4 mm to approximately 1 mm, and in some embodiments approximately 0.5 mm to approximately 0.9 mm. The length of an external terminal can also be less than the length of the capacitor, for example, 50% or less of the capacitor length, 40% or less, 30% or less, 25% or less, 20% or less, 15% or less, etc. If desired, each external terminal can have a different length. For example, an external terminal adjacent to an end surface can have a longer length than an external terminal offset from the end surface. In this regard, the ratio of the length of the external terminal adjacent to the end surface to the length of the external terminal offset from the end surface can be about 0.3 to about 5, in some embodiments about 0.5 to about 4, and in some embodiments about 0.7 to about 3. The width of the external terminal extending from one side surface to the opposite side surface can be the same on the upper and lower surfaces. For example, the width can be in the range of about 0.3 mm to about 1.1 mm, in some embodiments about 0.4 mm to about 1 mm, and in some embodiments about 0.5 mm to about 0.9 mm.

[0036] Referring to Figures 4A to 4B, one particular embodiment of a decoupling capacitor 10 that may be used in a microelectronic assembly of the present invention is shown in more detail. The capacitor 10 generally has a thickness "T", width "W", and length "L", such as those described above. Furthermore, as shown, the capacitor 10 has a 1×2 configuration in that it includes two external terminals along one dimension of the upper and lower surfaces. That is, the capacitor 10 includes a first external terminal 12 and a second external terminal 14 on the upper surface and two corresponding third and fourth external terminals (not shown) on the lower surface. The first external terminal 12 and the third external terminal (not shown) can have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) can also have the same polarity (i.e., negative). The width "BW" and length "BL" of the external terminals 12 and / or 14 can be within the range discussed above. Although not always necessary, a void 1350 can also be formed within the capacitor 10 between terminals 12 and 14, as described above.

[0037] Furthermore, the capacitor 10 includes a dielectric layer (not shown) and an internal electrode layer 110, as illustrated in Figure 4B. Specifically, the internal electrode layer 110 includes a first internal electrode layer 105 and a second set of internal electrode layers 115. In the particular embodiment shown, the internal electrode layers 105, 115 include at least one lead tab 120, 130, 140, 150 extending from the upper and bottom edges of the main body of the internal electrode layer. The lead tabs 120, 130, 140, 150 of the internal electrode layers 105, 115 can extend to the upper and lower surfaces of the capacitor and assist in forming external terminals. In this regard, the lead tabs 120, 130, 140, 150 are exposed on the upper and lower surfaces of the capacitor and can enable connections between the main body of the internal electrode layer and the external terminals. For example, lead tabs 120, 130, 140, and 150 may contain leading edges 123, 133, 143, and 153, which extend to the edge of the dielectric layer, enabling the formation of external terminals. The lengths of the lead tabs 120, 130, 140, and 150 can vary as desired, but are typically about 0.3 mm to about 1.2 mm, in some embodiments about 0.4 mm to about 1.1 mm, and in some embodiments about 0.5 mm to about 1 mm. When more than one lead tab is present along the edge, each lead tab may have the same length. In another embodiment, each lead tab may have different lengths. For example, a lead tab substantially aligned with the side edge of the internal electrode layer may have a longer length than a lead tab offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of the lead tab aligned with the side edge of the internal electrode layer to the length of the lead tab offset from the side edge of the internal electrode layer can be about 0.3 to about 5, in some embodiments about 0.5 to about 4, and in some embodiments about 0.7 to about 3.Being substantially aligned generally means that the offset of one lateral edge of the first lead tab and / or second lead tab at the upper edge from the lateral edge is within + / -10%, for example, within + / -5%, for example, within + / -4%, for example, within + / -3%, for example, within + / -2%, for example, within + / -1%, for example, within + / -0.5%, etc., of the offset of the corresponding lateral edge of the first lead tab and / or second lead tab at the bottom edge from the lateral edge.

[0038] As illustrated in Figure 4B, the first internal electrode layer 105 includes one lead tab 120, 130 extending from the main body 135 along the upper edge 105c and the bottom edge 105d. The second internal electrode layer 115 includes one lead tab 140, 150 extending from the main body 145 along the upper edge and the bottom edge. The lead tabs 120, 130 at the upper and bottom edges of the first internal electrode layer 105 can be aligned vertically. That is, the lateral edges 121, 122 of the first lead tab 120 along the upper edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c. In addition, such lateral edges 121 and 131 can be aligned with the side edge 105a of the internal electrode layer 105. However, it should be understood that both lateral edges 121 and 122 of the first lead tab 120 along the upper edge 105c can be aligned with the lateral edges 131 and 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c. In other words, both lateral edges 122 and 132 can be aligned and offset by the same distance from the side edges 105a and 105b along the bottom edge 105d and the upper edge 105c. Similarly, the lead tabs 140 and 150 on the upper and bottom edges of the second internal electrode layer 115 can be aligned vertically. That is, the lateral edges 141, 142 of the first lead tab 140 along the upper edge can be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite the upper edge. In one embodiment, both lateral edges 141, 142 of the first lead tab 140 along the upper edge can be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite the upper edge. The relationship between the lateral edges of the first lead tab at the upper edge and the lateral edges of the first lead tab at the bottom edge, as described with respect to the internal electrode layer 105, can also be applied to the internal electrode layer 115.Such an arrangement allows a gap to be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. Similarly, a gap can be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The size of each gap can be substantially the same.

[0039] The lead tabs 120 and 140 can be arranged in parallel with the lead tabs 130 and 150 extending from the internal electrode layers 105 and 115, respectively, so that the lead tabs extending from the alternating electrode layers 105 and 115 can be aligned in their respective rows. For example, the lead tabs 120 and 130 of the internal electrode layer 105 can be arranged in their respective stacked configurations, while the lead tabs 140 and 150 of the internal electrode layer 115 can be arranged in their respective stacked configurations.

[0040] It is understood that lead tab 120 is connected to external terminal 12, while lead tab 140 is connected to external terminal 14. Therefore, each lead tab 120 interlocks with each other with each other with the respective lead tab 140 in the same manner as external terminals 12 and 14. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0041] The distance between adjacent exposed lead tabs of the internal electrode layer in a given column can be specifically designed to help ensure guided formation of the terminations. The distance between exposed lead tabs of the internal electrode layer in a given column can be, for example, in the range of about 0.25 μm to about 10 μm, in some embodiments in the range of about 0.5 μm to about 5 μm, and in some embodiments in the range of about 1 μm to about 4 μm. Additionally, the distance between adjacent columnar stacks of electrode tabs can be, but is not limited to, at least twice as large as the distance between adjacent lead tabs in a given column to ensure that individual terminations do not mix. In some embodiments, the distance between adjacent columnar stacks of exposed metallization can be about four times the distance between adjacent exposed electrode tabs in a particular stack. However, such distances can vary depending on the desired capacitance performance and circuit board configuration. For example, the distance can be approximately 0.1 mm to approximately 1.5 mm, in some embodiments approximately 0.2 mm to approximately 1.3 mm, and in some embodiments approximately 0.3 mm to approximately 1 mm, when determined based on the center point of each lead tab or the distance between adjacent lateral edges of the lead tabs. In addition, such distances can correspond to the separation distance of balls on a ball grid array.

[0042] In the embodiments illustrated in Figures 4A to 4B, the capacitor includes two external terminals that extend to the ends of the capacitor. However, this is not always necessary. Referring to Figures 5A to 5C, one embodiment of the capacitor 10 is shown, in which a first external terminal 12, a second external terminal 14, and third and fourth external terminals (not shown) do not extend to the ends of the capacitor. To help achieve such a configuration in this particular embodiment, the capacitor 10 includes an internal electrode layer 110 containing a first internal electrode layer 105 and a second internal electrode layer 115. The first internal electrode layer 105 can extend to the upper surface of the capacitor 10, and the second internal electrode layer 115 extends to the lower surface of the capacitor. This extension assists in the formation of the external terminals. In this regard, the internal electrode layers can be exposed on the upper and lower surfaces of the capacitor, allowing for connections between the main body of the internal electrode layer and the external terminals. For example, the internal electrode layers 105 and 115 extend to the edges of the dielectric layer, enabling the formation of external terminals. The lateral or side edges of the internal electrode layers 105 and 115 can be aligned vertically. That is, the lateral edge of the first internal electrode layer 105 can be aligned with the lateral edge of the second internal electrode layer 115. In one embodiment, both lateral edges can be aligned. In another embodiment, the point of contact between the first internal electrode layer 105 and the external terminal can be aligned with the point of contact between the second internal electrode layer 115 and the external terminal. Additionally, the capacitor 10 in Figure 5A includes at least one first polarity terminal and at least one second and opposite polarity terminal on its upper surface. Although not shown, the lower surface includes at least one first polarity terminal and the second and opposite terminal.

[0043] In the embodiments illustrated in Figures 4A-4B and 5A-5C, the capacitor includes two external terminals on each surface. However, as shown above, the present invention is not limited by the number of external terminals, and / or the number of lead tabs extending from the upper and / or bottom edges. For example, referring to Figures 6A and 6B, a capacitor 20 is shown which has a 1×4 array configuration and therefore includes four external terminals on each surface. That is, the capacitor includes four terminals along two dimensions: the upper surface and the lower surface. In this regard, the capacitor includes a total of four external terminals on the upper surface (i.e., first external terminals 22a and 22b and second external terminals 24a and 24b), and a corresponding set of third and fourth external terminals (not shown) on the lower surface. The first external terminals 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminal (not shown) generally have the same polarity (i.e., negative). The capacitor 20 generally has a thickness "T", width "W", and length "L", such as those described above, and the width "BW" and lengths "BLA" and "BLB" of the external terminals 22a, 22b and / or 24a, 24b can be within the range discussed above. Also, although not required, a void 1350 can be formed in the capacitor 20 between the external terminals 22a, 24b, 22b, and / or 24a, as described above.

[0044] Furthermore, the capacitor 20 includes an internal electrode layer 210 containing a first internal electrode layer 205 and a second internal electrode layer 215 in an alternating arrangement. The internal electrode layers 205 and 215 include at least one lead tab 220a~b, 230a~b, 240a~b, 250a~b extending from the upper and lower edges of the main body of the internal electrode layer. The lead tabs 220a~b, 230a~b, 240a~b, 250a~b of the internal electrode layers 205 and 215 extend to the upper and lower surfaces of the capacitor and assist in forming external terminals. In this regard, the lead tabs 220a~b, 230a~b, 240a~b, 250a~b are exposed on the upper and lower surfaces of the capacitor and can enable connections between the main body of the internal electrode layer and the external terminals. For example, lead tabs 220a~b, 230a~b, 240a~b, 250a~b may contain leading edges 223a~b, 233a~b, 243a~b, 253a~b, which extend to the edge of the dielectric layer, enabling the formation of external terminals. Internal electrode layers 205, 215 include at least two lead tabs 220a~b, 230a~b, 240a~b, 250a~b along their upper and bottom edges. The first internal electrode layer 205 includes two lead tabs 220a~b, 230a~b extending from the main body 235 along their respective upper and bottom edges 205c and 205d. The second internal electrode layer 215 includes two lead tabs 240a-b and 250a-b that extend from the main body 245 along their respective upper and bottom edges.

[0045] The lead tabs 220a-b and 230a-b located at the upper edge 205c and bottom edge 205d of the first internal electrode layer 205 can be aligned vertically. That is, the lateral edges 221a and 222a of the first lead tab 220 along the upper edge 205c can be aligned with the lateral edges 231a and 232a of the first lead tab 230 along the bottom edge 205d opposite the upper edge 205c. In addition, such lateral edges 221a and 231a can be aligned with the side edge 205a of the internal electrode layer 205. However, it should be understood that both lateral edges 221a, 222a of the first lead tab 220a along the upper edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230a along the bottom edge 205d opposite the upper edge 205c. In other words, both lateral edges 222a, 232a can be offset by the same distance from the lateral edges 205a-b along the bottom edge 205d and the upper edge 205c. When the upper edge 205c and the bottom edge 205d contain at least two lead tabs 220a-b, 230a-b, at least one lateral edge of each lead tab on the upper edge 205c can be aligned with the corresponding lateral edge of the lead tab on the bottom edge 205d. Furthermore, both lateral edges of each lead tab located at the upper edge 205c can be aligned with the corresponding lateral edges of the lead tabs located at the bottom edge 205d. Similarly, the lead tabs 240a-b and 250a-b located at the upper and bottom edges of the second internal electrode layer 215 can be aligned vertically. That is, the lateral edges 241a and 242a of the first lead tab 240 along the upper edge can be aligned with the lateral edges 251a and 252a of the first lead tab 250 along the bottom edge opposite the upper edge.

[0046] The lateral edges 241a, 242a of the first lead tab 240 along the upper edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite the upper edge. The relationship between the lateral edges of the first lead tab at the upper edge and the lateral edges of the first lead tab at the bottom edge, as described with respect to the internal electrode layer 205, can also be applied to the internal electrode layer 215. Such an arrangement would form a gap between any of the lead tabs along the upper edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, the gap can be formed between any of the lead tabs 220a-b, 240a-b extending from the upper edge of each internal electrode layer. Additionally, the gap can be formed between any of the lead tabs along the bottom edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap can be formed between any of the lead tabs 230a-b and 250a-b extending from the bottom edge of each internal electrode layer. Furthermore, the size of the gap between two tabs extending from the top edge, whether from the same internal electrode layer or from adjacent internal electrode layers, can be substantially the same as the size of the gap between the corresponding two tabs extending from the bottom edge. For example, the gap between lead tab 220a and lead tab 220b can be substantially the same as the gap between lead tab 230a and lead tab 230b. Similarly, the gap between lead tab 220a and lead tab 240a can be substantially the same as the gap between lead tab 230a and lead tab 250a.

[0047] Any or all of the lead tabs 220a-b and 240a-b can be arranged in parallel with the lead tabs 230a-b and 250a-b extending from layers 205 and 215, respectively, so that the lead tabs extending from the alternating electrode layers 205 and 215 can be aligned in their respective rows. For example, the lead tabs 220a-b and 230a-b of the internal electrode layer 205 can be arranged in their respective stacked configurations, while the lead tabs 240a-b and 250a-b of the internal electrode layer 215 can be arranged in their respective stacked configurations. It will be recognized that the lead tabs 220a-b are connected to external terminals 22a-b, respectively, while the lead tabs 240a-b are connected to external terminals 24a-b, respectively. Therefore, each lead tab 220a-b will interlock with each other with each lead tab 240a-b in the same manner as the external terminals 22a-b and 24a-b. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0048] In the embodiments discussed above, the external terminals are arranged in a linear manner in a single dimension (e.g., a 1×2 or 1×4 configuration). Naturally, it should be understood that multidimensional arrays of external terminals are also possible. For example, referring to Figures 7A to 7D, one particular embodiment of a capacitor 10 having a 2×2 array configuration is shown. In such a configuration, the capacitor includes a total of four external terminals (first external terminal 12 and second external terminal 14) on the upper surface and a corresponding number of external terminals (third and fourth external terminals, not shown) on the lower surface. The first external terminal 12 and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) also generally have the same polarity (i.e., negative). Although not always required, a void 1350 can also be formed in the capacitor 10 between external terminals 12 and 14, as described above.

[0049] The capacitor 10 includes alternating dielectric layers and internal electrode layers 110, the internal electrode layers 110 including a first internal electrode layer 105 and a second internal electrode layer 115 in an alternating arrangement. Similar to the embodiments discussed above in Figures 4A to 4B, the internal electrode layers 105, 115 also include at least one lead tab 120, 130, 140, 150 extending from the upper and bottom edges of the main body of the internal electrode layers. However, in contrast to the internal electrodes in Figures 4A to 4B, the lateral edges 121, 122 of the first lead tab 120 along the upper edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c. In other words, the lateral edges 121 and 122 of the first lead tab 120 along the upper edge 105c can be offset from the lateral edges 105a and 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c by the same distance (indicated by "O"). However, it should be understood that both lateral edges 121 and 122 of the first lead tab 120 along the upper edge 105c can be aligned with the lateral edges 131 and 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c. In other words, both lateral edges 121 and 122 of the first lead tab 120 along the upper edge 105c can be offset from the lateral edges 105a and 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c by the same distance.

[0050] Similarly, the lead tabs 140 and 150 at the upper and lower edges of the second internal electrode layer 115 can be aligned vertically. That is, the lateral edges 141 and 142 of the first lead tab 140 along the upper edge can be aligned with the lateral edges 151 and 152 of the first lead tab 150 along the lower edge opposite the upper edge. In one embodiment, both lateral edges 141 and 142 of the first lead tab 140 along the upper edge can be aligned with the lateral edges 151 and 152 of the first lead tab 150 along the lower edge opposite the upper edge. The relationship between the lateral edges of the first lead tabs at the upper edge and the lateral edges of the first lead tabs at the lower edge, as described with respect to the internal electrode layer 105, can also be applied to the internal electrode layer 115. Such an arrangement allows for the formation of a gap between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. A gap can also be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The size of each gap can be substantially the same.

[0051] The lead tabs 120 and 140 can be arranged in parallel with the lead tabs 130 and 150 extending from the internal electrode layers 105 and 115, respectively, so that the lead tabs extending from the alternating electrode layers 105 and 115 can be aligned in their respective rows. For example, the lead tabs 120 and 130 of the internal electrode layer 105 can be arranged in their respective stacked configurations, while the lead tabs 140 and 150 of the internal electrode layer 115 can be arranged in their respective stacked configurations. It will be recognized that the lead tab 120 connects to the external terminal 12, and the lead tab 140 connects to the external terminal 14. Thus, each lead tab 120 will interlock with each other with the respective lead tab 140 in a similar manner to the external terminals 12 and 14. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0052] As shown in Figure 7D, multiple sets 110a and 110b of the internal electrode layer 110 can be used to form an array of external terminals shown in Figure 7A. Typically, the distance "t" between sets 110a and 110b is about 0.2 μm to about 10 μm, in some embodiments about 0.5 μm to about 8 μm, and in some embodiments about 1 μm to about 5 μm. Additionally, the distance "t" can be at least twice as large as the distance between adjacent lead tabs in a given column, in some embodiments at least about three times, and in some embodiments about four times to about eight times, in order to ensure that individual terminals do not mix.

[0053] Referring to Figures 8A to 8D, one embodiment of a capacitor 20 having a 2x4 array configuration is shown. In such a configuration, the capacitor includes a total of eight external terminals (first external terminals 22a, 22b and second external terminals 24a, 24b) on its upper surface and a corresponding number of external terminals (third and fourth external terminals, not shown) on its lower surface. The first external terminals 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminal (not shown) also generally have the same polarity (i.e., negative). Although not always required, voids 1350 can also be formed in the capacitor 20 between the external terminals 22a, 22b, 24a, and / or 24b, as described above.

[0054] Furthermore, the capacitor 20 includes two sets 210a and 210b of alternating internal electrode layers 210, as illustrated in Figure 8D. As illustrated in Figures 8B and 8C, each set of alternating dielectric layers and internal electrode layers 210 includes a first internal electrode layer 205 and a second internal electrode layer 215 in an alternating arrangement. The internal electrode layers 205 and 215 include at least one lead tab 220a~b, 230a~b, 240a~b, and 250a~b extending from the upper and lower edges of the main body of the internal electrode layer. The lead tabs 220a~b, 230a~b, 240a~b, and 250a~b of the internal electrode layers 205 and 215 extend to the upper and lower surfaces of the capacitor and help form external terminals. In this regard, the lead tabs 220a~b, 230a~b, 240a~b, and 250a~b are exposed on the upper and lower surfaces of the capacitor, enabling connection between the main body of the internal electrode layer and the external terminals. For example, the lead tabs 220a~b, 230a~b, 240a~b, and 250a~b may contain leading edges 223a~b, 233a~b, 243a~b, and 253a~b, which extend to the edge of the dielectric layer, enabling the formation of external terminals. The internal electrode layers 205 and 215 include at least two lead tabs 220a~b, 230a~b, 240a~b, and 250a~b along their upper and bottom edges. The first internal electrode layer 205 includes two lead tabs 220a-b and 230a-b extending from the main body 235 along their respective upper edges 205c and bottom edges 205d. The second internal electrode layer 215 includes two lead tabs 240a-b and 250a-b extending from the main body 245 along their respective upper and bottom edges.

[0055] The lead tabs 220a-b and 230a-b located at the upper edge 205c and bottom edge 205d of the first internal electrode layer 205 can be aligned vertically. That is, the lateral edges 221a and 222a of the first lead tab 220 along the upper edge 205c can be aligned with the lateral edges 231a and 232a of the first lead tab 230 along the bottom edge 205d opposite the upper edge 205c. In other words, the lateral edges 221a and 222a of the first lead tab 220 along the upper edge 205c can be offset from the lateral edges 205a-b by the same distance as the lateral edges 231a and 232a of the first lead tab 230 along the bottom edge 205d opposite the upper edge 205c (indicated by "O"). Furthermore, both lateral edges 221a, 222a of the first lead tab 220 along the upper edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230 along the bottom edge 205d opposite the upper edge 205c. That is, both lateral edges can be offset by the same distance from the side edges 205a-b. When the upper edge 205c and the bottom edge 205d contain at least two lead tabs 220a-b, 230a-b, at least one lateral edge of each lead tab on the upper edge 205c can be aligned with the corresponding lateral edge of the lead tab on the bottom edge 205d. Also, both lateral edges of each lead tab on the upper edge 205c can be aligned with the corresponding lateral edges of the lead tab on the bottom edge 205d.

[0056] Similarly, the lead tabs 240a-b and 250a-b located at the upper and lower edges of the second internal electrode layer 215 can be aligned vertically. That is, the lateral edges 241a and 242a of the first lead tab 240 along the upper edge can be aligned with the lateral edges 251a and 252a of the first lead tab 250 along the lower edge opposite the upper edge. Both lateral edges 241a and 242a of the first lead tab 240 along the upper edge can be aligned with the lateral edges 251a and 252a of the first lead tab 250 along the lower edge opposite the upper edge. The relationship between the lateral edges of the first lead tabs at the upper edge and the lateral edges of the first lead tabs at the lower edge, as described for the internal electrode layer 205, can also be applied to the internal electrode layer 215. Such arrangements allow gaps to be formed between any of the lead tabs along the upper edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, gaps can be formed between any of the lead tabs 220a-b, 240a-b extending from the upper edge of each internal electrode layer. Additionally, gaps can be formed between any of the lead tabs along the bottom edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, gaps can be formed between any of the lead tabs 230a-b, 250a-b extending from the bottom edge of each internal electrode layer. Furthermore, the size of the gap between each pair of tabs extending from the upper edge, whether from the same internal electrode layer or from adjacent internal electrode layers, can be substantially the same as the size of the gap between each of the corresponding tabs extending from the bottom edge. For example, the gap between lead tab 220a and lead tab 220b can be substantially the same as the gap between lead tab 230a and lead tab 230b. Similarly, the gap between lead tab 220a and lead tab 240a can be substantially the same as the gap between lead tab 230a and lead tab 250a.

[0057] Any or all of the lead tabs 220a-b and 240a-b can be arranged in parallel with the lead tabs 230a-b and 250a-b extending from layers 205 and 215, respectively, so that the lead tabs extending from the alternating electrode layers 205 and 215 can be aligned in their respective rows. For example, the lead tabs 220a-b and 230a-b of the internal electrode layer 205 can be arranged in their respective stacked configurations, while the lead tabs 240a-b and 250a-b of the internal electrode layer 215 can be arranged in their respective stacked configurations. It will be recognized that the lead tabs 220a-b are connected to external terminals 22a-b, respectively, while the lead tabs 240a-b are connected to external terminals 24a-b, respectively. Therefore, each lead tab 220a-b will interlock with each other with each lead tab 240a-b in the same manner as the external terminals 22a-b and 24a-b. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0058] As shown in Figure 8D, multiple sets 210a and 210b of the internal electrode layer 110 can be used to form an array of external terminals shown in Figure 8A. Typically, the distance "t" between sets 110a and 110b is about 0.2 μm to about 10 μm, in some embodiments about 0.5 μm to about 8 μm, and in some embodiments about 1 μm to about 5 μm. Additionally, the distance "t" can be at least twice as large as the distance between adjacent lead tabs in a given column, in some embodiments at least about three times, and in some embodiments about four times to about eight times, in order to ensure that individual terminals do not mix.

[0059] Referring to Figures 9A and 9B, one embodiment of a capacitor 20 having a 4x4 array configuration is shown. In such a configuration, the capacitor includes a total of 16 external terminals (first external terminals 32a, 32b and second external terminals 34a, 34b) on its upper surface and a corresponding number of external terminals (third and fourth external terminals, not shown) on its lower surface. The first external terminals 32a, 32b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 34a, 34b and the fourth external terminal (not shown) also generally have the same polarity (i.e., negative). Although not always required, voids 1350 can also be formed in the capacitor 20 between the external terminals 32a, 32b, 34a, and / or 34b, as described above. Furthermore, the capacitor 30 includes an internal electrode layer 210 arranged in four sets 210a, 210b, 210c, and 210d, as illustrated in Figure 9B. Similar to the embodiments discussed above, the distances between sets "t1", "t2", and / or "t3" can be from about 0.2 μm to about 10 μm, from about 0.5 μm to about 8 μm in some embodiments, and from about 1 μm to about 5 μm in some embodiments. In addition, the distances "t1", "t2", and / or "t3" can be at least twice as large as the distance between adjacent lead tabs in a given column, from about four times to about eight times in some embodiments, but not limited to, to ensure that individual terminations do not mix.

[0060] In the embodiments referenced above, the internal electrode layers are generally oriented in a vertical configuration. Naturally, this is not always necessary, and other geometric configurations (e.g., a horizontal configuration) are equally appropriate. For example, referring to Figures 10A–10C, a capacitor 20 is shown, which has a 4x4 configuration of external terminals 32 and 34 similar to that in Figures 9A–9B, but uses a horizontal internal electrode configuration. That is, as shown in Figures 10B–10C, the capacitor 20 includes multiple internal electrode layers 205 and 215 and multiple dielectric layers in an alternating arrangement, with the electrode layers interleaved in a relationship where the dielectric layers are positioned opposite each other and spaced apart. The internal electrode layers are electrically connected to the external terminals through conductive vias (e.g., a first conductive via 225 and a second conductive via 285). The conductive vias extend to the upper surface 235 and the lower surface 245 of the capacitor. In this regard, conductive vias can be exposed on the upper surface 235 and the lower surface 245 of the capacitor. This exposure can facilitate the formation of external terminals on the upper and lower surfaces 235 and 245 of the capacitor. Furthermore, the internal electrode layers 205 and 215 have a rectangular configuration and are provided so as not to extend to the side surfaces of the capacitor.

[0061] If desired, the capacitor 20 may also include a first shielding region 255 and a second shielding region 265, each of which may include one or more shielding electrode layers 275. As shown, the shielding regions are provided above and below the active electrode region and active electrode layers 205, 215. Figure 10C similarly illustrates the use of a first anchor electrode 305 and a second anchor electrode 295. The first anchor electrode 305 is provided in the first active electrode layer 205 together with the first active electrode. In this regard, the first active electrode is electrically connected to a first conductive via 225, while the first anchor electrode is connected to a second conductive via 285. Similarly, the second anchor electrode 295 is provided in the second active electrode layer 215 together with the second active electrode. In this regard, the second active electrode is electrically connected to the second conductive via 285, while the second anchor electrode is connected to the first conductive via 225.

[0062] The first conductive via 225 extends through the first plurality of internal electrode layers 205 and is in electrical contact with the first plurality of internal electrode layers 205. However, the first conductive via 225 extends through a non-contact hole 105, and a gap 105 is formed between the first conductive via 225 and the electrodes of the second plurality of internal electrode layers 215. Such a gap 105 allows for insulation of the second plurality of internal electrode layers 215 from the first conductive via 225. Similarly, the second conductive via 285 extends through the second plurality of internal electrode layers 215 and is in electrical contact with the second plurality of internal electrode layers 215. However, the second conductive via 285 extends through a non-contact hole 115, and a gap 115 is formed between the second conductive via 285 and the electrodes of the first plurality of internal electrode layers 205. Such gap 115 allows for the isolation of the first plurality of internal electrode layers 205 from the second conductive via 285. When an anchor (or dummy) electrode is present, as illustrated in Figure 10C, such layers also include gaps 125 and 135. The first conductive via 225 extends through the first plurality of internal electrode layers 205 and is in electrical contact with it and in contact with the second anchor tab 295. However, the second anchor tab 295 is isolated from the active electrode of the second plurality of internal electrode layers 215 through a gap 125 formed between the anchor tab 295 and the active electrode 215. Such gap 125 allows for the isolation of the second plurality of internal electrode layers 215 from the second anchor tab 295 and the first conductive via 225.

[0063] The dielectric layers of the decoupling capacitors described herein are typically formed from ceramic materials. Ceramic materials can have relatively high dielectric constants. For example, the dielectric constant can be 3 or greater, and in some embodiments it can be about 10 to about 20,000, in some embodiments it can be about 50 to about 10,000, in some embodiments it can be about 60 to about 9,000, and in some embodiments it can be about 80 to about 8,000. Particularly suitable examples of ceramic materials with high dielectric constants are those designated as NPO(COG) (up to about 100), X7R (about 3,000 to about 7,000), X7S, Z5U, and / or Y5V, based on the standard classification established by the Electronic Industries Alliance (EIA). Such materials may include perovskites, for example, barium titanate ceramic materials (e.g., barium titanate, barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate, etc.), lead titanate ceramic materials (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), and sodium bismuth titanate. In one particular embodiment, for example, the chemical formula Ba x Sr 1-x Barium strontium titanate ("BSTO") of TiO3 can be used, where x is from 0 to 1, and in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable barium titanate ceramic materials include, for example, Ba x Ca 1-x TiO3 (where x is about 0.2 to about 0.8, and in some embodiments about 0.4 to about 0.6); and barium calcium zirconium titanate (BaCaZrTiO3); A[B1 1 / 3 B2 2 / 3 ]O3 material (where A is Ba x Sr 1-xwhere x can be a value from 0 to 1, and B1 is Mg y Zn 1-y where y can be a value from 0 to 1, and B2 is Ta z Nb 1-z and so on can be included. Other suitable ceramic materials can include, for example, Pb x Zr 1-x TiO3 ("PZT") (where x is in the range of about 0.05 to about 0.4); lead lanthanum zirconium titanate ("PLZT"); and lead titanate (PbTiO3) and so on can be included.

[0064] The internal electrode layer can be formed from any of a variety of different metals as known in the art. The internal electrode layer can be made from a metal such as a conductive metal. The materials can include noble metals (such as silver, gold, palladium, platinum, etc.), base metals (such as copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloy, as well as sputtered layers of chromium, nickel, and gold respectively, may also be suitable. In one particular embodiment, the internal electrode layer can include nickel or an alloy thereof. Similarly, the external terminal can be formed from any of a variety of different metals as known in the art. The external terminal can be made from a metal such as a conductive metal. The materials can include noble metals (such as silver, gold, palladium, platinum, etc.), base metals (such as copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. In one particular embodiment, the external terminal can include copper or an alloy thereof. The external terminal can have an average thickness of about 100 μm or less, in some embodiments, about 1 μm to about 70 μm, and in some embodiments, about 5 μm to about 50 μm.

[0065] External terminals can be formed using any method commonly known in the art. External terminals can be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spray / airbrushing, etc. External terminals can be formed such that they are thin-film platings of metal. Such thin-film platings can be formed by depositing a conductive material (e.g., a conductive metal) onto an exposed portion of an internal electrode layer. For example, the leading edge of the internal electrode layer can be exposed so as to allow for the formation of a plated terminal. Plated terminals can be formed by techniques known in the art (e.g., electroless plating, electroplating, or a combination thereof). When multiple layers are used to form an external terminal, the external terminal can include electroplated and electroless plating layers. For example, electroless plating can be used first to deposit an initial layer of material. The plating technique can then be switched to an electrochemical plating system, which can allow for faster accumulation of the material. When forming terminals plated by any of the plating methods, the leading edges of the lead tabs of the internal electrode layer exposed from the main body of the capacitor are exposed to the plating solution. By exposure, in one embodiment, the capacitor can be immersed in the plating solution.

[0066] The plating solution used in the plating process may contain conductive materials (e.g., conductive metals). For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution, such that the plated layer and external terminals contain nickel. Alternatively, the plating solution may be a copper acid bath or other suitable copper solution, such that the plated layer and external terminals contain copper. Additionally, it should be understood that the plating solution may contain other additives as are commonly known in the art. For example, the additives may include other organic additives and media that can assist the plating process. Additionally, additives may be used to use the plating solution at a desired pH level. In one embodiment, resistance-reducing additives may be used in the solution to assist in complete plating, as well as in the bonding of the plating material to the exposed leading edges of the lead tabs of the capacitor and internal electrode layers. The capacitor may be exposed, submerged, or immersed in the plating solution for a predetermined amount of time. The exposure time is not necessarily limited, but can be a sufficient amount of time to allow sufficient plating material to deposit to form the plated terminals. In this regard, the time should be sufficient to allow the formation of a continuous connection between the desired exposed adjacent leading edges of the lead tabs of a given polarity in each internal electrode layer within the set of alternating dielectric and internal electrode layers.

[0067] The difference between electrolytic plating and electroless plating is that electrolytic plating uses an electrical bias (for example, by using an external power supply). Electrolytic plating solutions typically have a high current density range, e.g., 10 to 15 amp / ft. 2It may be exposed to (rated 9.4 volts). The connection can be formed by a negative connection to the capacitor, which requires the formation of plated terminals, and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased to a polarity opposite to the polarity of the plating solution. Using such a method, the conductive material of the plating solution is attracted to the metal of the exposed leading edge of the lead tab of the internal electrode layer.

[0068] Various pretreatment steps can be used before immersing or exposing the capacitor in a plating solution. Such steps can be performed for a variety of purposes, including catalytically accelerating, and / or improving the adhesion of the plating material to the leading edge of the lead tab. Additionally, an initial cleaning step can be used before plating or any other pretreatment step. This step can be used to remove any oxide accumulations that may form on the exposed lead tab of the internal electrode layer. The cleaning step may be particularly useful in assisting the removal of any nickel oxide accumulations when the internal electrodes or other conductive elements are formed from nickel. Component cleaning can be achieved by complete immersion in a pre-cleaning tank (e.g., one containing an acid cleaner). In one embodiment, the exposure can be over a predetermined time (e.g., on the order of about 10 minutes). Alternatively, cleaning can be achieved by a chemical polishing or hyper-rising step.

[0069] In addition, to promote the deposition of conductive material, a step may be performed to activate the exposed metal leading edge of the lead tab of the internal electrode layer. Activation can be achieved by immersion in a palladium salt, a photo-patterned palladium organometallic precursor (via a mask or laser), a screen-printed or inkjet-deposited palladium compound, or an electrophoretic palladium deposit. It should be recognized that the palladium-based activation is disclosed here merely as an example of an activation solution, which often works well for activating exposed tab portions formed from nickel or its alloys. However, it should be understood that other activation solutions may be used and are therefore not necessarily limited. Also, instead of or in addition to the activation step described above, an activation dopant may be introduced into the conductive material when forming the internal electrode layer of the capacitor. For example, when the internal electrode layer contains nickel and the activation dopant contains palladium, the palladium dopant may be introduced into the nickel ink or composition forming the internal electrode layer. Doing so makes it possible to eliminate the palladium activation step. It should be further recognized that some of the activation methods described above, such as those using organometallic precursors, are also useful for co-deposition of glass-forming agents to improve adhesion to the generally ceramic body of the capacitor. When the activation step is carried out as described above, traces of the activating material may often remain on the exposed conductive parts before and after the terminal plating. In addition, post-treatment steps after plating may be used as desired or as needed. Such steps may be performed for a variety of purposes, including strengthening and / or improving the adhesion of the materials. For example, a heating (or annealing) step may be used after the plating step has been carried out. Such heating may be carried out via baking, laser subjection, UV exposure, microwave exposure, arc welding, etc.

[0070] Therefore, as described above, the external terminals used in the capacitor may contain at least one plated layer. In one embodiment, the external terminal may contain only one plated layer. However, it should be understood that the external terminal may contain multiple plated layers. For example, the external terminal may contain a first plated layer and a second plated layer. In addition, the external terminal may contain a third plated layer. Furthermore, the materials of these plated layers may be any of those described above, or any materials commonly known in the art. For example, one plated layer (e.g., the first plated layer) may contain copper or an alloy thereof. Another plated layer (e.g., the second plated layer) may contain nickel or an alloy thereof. Alternatively, another plated layer (e.g., the second plated layer) may contain copper or an alloy thereof. Another plated layer (e.g., the third plated layer) may contain tin, lead, gold, or a combination thereof (e.g., an alloy). Alternatively, the initial plating layer may contain nickel, followed by a tin or gold plating layer. In another embodiment, an initial copper plating layer may be formed, followed by a nickel layer.

[0071] In one embodiment, the initial plating layer or first plating layer can be a conductive metal (e.g., copper). This area can then be covered by a second layer containing a resistive polymer material for sealing. The area can then be polished to selectively remove the resistive polymer material and then re-plated with a third layer containing a conductive metallic material (e.g., copper). The aforementioned second layer above the initial plating layer can correspond to a solder barrier layer (e.g., a nickel-solder barrier layer). In some embodiments, the aforementioned layer can be formed by electroplating an additional layer of metal (e.g., nickel or copper) on top of an initial electroless or electroplated layer (e.g., plated copper). Other exemplary materials for the layer (the aforementioned solder barrier layer) include nickel-phosphorus, gold, and silver. The third layer above the aforementioned solder barrier layer can correspond in some embodiments to a conductive layer (e.g., plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder). In addition, a layer of metal plating may be formed, followed by an electroplating step to provide a resistant alloy or a higher-resistance metal alloy coating (e.g., electroless Ni-P alloy) on top of such metal plating. However, it should be understood that any metal coating is possible, as will be understood by those skilled in the art from the full disclosure herein. It should be recognized that any of the steps described above can occur as a bulk process, such as barrel plating, fluidized bed plating, and / or flow-through plating termination processes (all of which are commonly known in the art). Such bulk processes allow multiple components to be processed at once, providing an efficient and rapid termination process. This is a particular advantage over conventional termination methods (e.g., printing of thick film terminations, which require processing of individual components).

[0072] V. Decoupling Capacitor Structure One or more decoupling capacitors may be arranged adjacent to at least one interposer to form a decoupling capacitor structure. It will be recognized that the interposer of the decoupling capacitor structure may be different from and separate from the interposer described above (which may be referred to as the assembly interposer). The interposer of the decoupling capacitor structure may provide rigidity to the decoupling capacitor and help prevent warping of the decoupling capacitor, which can destroy or interfere with electrical contact between the decoupling capacitor and other components of the microelectronic assembly. Additionally or alternatively, the interposer may help establish electrical contact with the decoupling capacitor despite any warping of the individual decoupling capacitor, and the interposer may be electrically connected to a desired component of the microelectronic assembly and provide electrical connection between the decoupling capacitor and the microelectronic assembly.

[0073] Generally speaking, a decoupling capacitor structure includes an interposer and a decoupling capacitor as described herein (for example, the decoupling capacitor described with respect to Figures 4A to 10C). The decoupling capacitor is disposed adjacent to the interposer such that its surface is adjacent to the surface of the interposer. One or more external terminals of the decoupling capacitor located on its surface adjacent to the interposer are electrically connected to the interposer.

[0074] For example, referring to Figure 11A, the decoupling capacitor structure 900 includes an interposer 902 and a decoupling capacitor 904 adjacent to the interposer 902. For example, the interposer 902 and the decoupling capacitor 904 can be stacked together such that the decoupling capacitor 904 is positioned adjacent to the interposer 902 along the height or thickness direction Z. The interposer 902 has a first surface 906 and an opposite second surface 908, the second surface 908 being opposite the first surface 906 along the height direction Z. Similarly, the decoupling capacitor 904 has a first surface 910 and an opposite second surface 912, the second surface 912 being opposite the first surface 910 along the height direction Z.

[0075] As described elsewhere in this specification, multiple external terminals can be formed on the first surface 910 and the second surface 912 of the decoupling capacitor. For example, the decoupling capacitor 904 may include alternating dielectric layers and internal electrode layers, as illustrated in Figures 4A to 5C, and comprises a first external terminal 914, a second external terminal 916, a third external terminal 918, and a fourth external terminal 920, wherein the first external terminal 914 is electrically connected to a first internal electrode layer and is located on the first surface 910, the second external terminal 916 is electrically connected to a first internal electrode layer and is located on the second surface 912, the third external terminal 918 is electrically connected to a second internal electrode layer and is located on the first surface 910, and the fourth external terminal 920 is electrically connected to a second internal electrode layer and is located on the second surface 912. However, it will be recognized that the four external terminals 914, 916, 918, and 920 are merely illustrative examples, and the decoupling capacitor 904 can include more than four external terminals, as illustrated, for example, with respect to Figures 4A to 10C.

[0076] As described, in the exemplary embodiment of Figure 11A, the first external terminal 914 and the third external terminal 918 are formed on the first surface 910, and the second external terminal 916 and the fourth external terminal 920 are formed on the second surface 912. The first external terminal 914 and the third external terminal 918 can be electrically connected to the interposer 902. For example, in at least some embodiments, the interposer 902 can define one or more first vias 922 that provide an electrical connection from the decoupling capacitor 904 through the interposer 902.

[0077] Referring to Figure 11A, for example, two first vias 922 extend from a first surface 906 to a second surface 908 of the interposer 902. The first vias 922 can be lined or filled with a conductive material 924 (for example, copper), which contacts the first and third external terminals 914, 918, thereby electrically connecting the first and third external terminals 914, 918 and the interposer 902. For example, the conductive material 924 of one first via 922 can contact the first external terminal 914, and the conductive material 924 of the other first via 922 can contact the third external terminal 918, thereby electrically connecting the first and third external terminals 914, 918 to the interposer 902. In at least some embodiments, four or more external terminals may be formed on the first surface 910 and the second surface 912 of each decoupling capacitor 904 of the decoupling capacitor structure 900, and a first via 922 is defined with respect to each external terminal on the first surface 910 and provides an electrical connection between the decoupling capacitor 904 and the interposer 902, as illustrated in Figure 11D.

[0078] By extending the conductive material 924 through the interposer 902 to each external end of the decoupling capacitor 904, it is recognized that an electrical connection can be established between the decoupling capacitor 904 and another component despite the warping of the decoupling capacitor 904, as shown in Figure 11C. That is, the conductive material 924 in the via 922 can extend to each external end of the decoupling capacitor 904 even if its external end is not positioned in contact with or abutting the interposer 902. As described below, an insulating material 934 (e.g., epoxy resin) can be inserted into the decoupling capacitor structure 900 so that the insulating material 934 surrounds any conductive material 924 that extends beyond or outside the interposer 902 to contact each external end of the decoupling capacitor 904. For example, the insulating material 934 can be injected so as to surround the decoupling capacitor 904, and then one or more vias 922 can be formed through the interposer 902 and the insulating material 934, for example, using a laser or other suitable apparatus for forming the vias 922.

[0079] Looking at Figure 11B, in at least some embodiments, the interposer 902 can be a first interposer 902, and the decoupling capacitor structure 900 can further include a second interposer 926. The second interposer 926 can be positioned on the opposite side of the first interposer 902, such that the decoupling capacitor 904 is sandwiched between the first interposer 902 and the second interposer 926. For example, as shown in Figure 11B, the second interposer 926 has a first surface 928 and a second surface 930 on the opposite side. The decoupling capacitor 904 is disposed between the first interposer 902 and the second interposer 926, with the first surface 910 of the decoupling capacitor 904 adjacent to the second surface 908 of the first interposer 902, and the second surface 912 of the decoupling capacitor 904 adjacent to the first surface 928 of the second interposer 926.

[0080] Furthermore, as illustrated in Figure 11B, the second external terminal 916 and the fourth external terminal 920 of the decoupling capacitor 904 can be electrically connected to the second interposer 926. For example, in at least some embodiments, two second vias 932 extend from the first surface 928 to the second surface 930 of the second interposer 926. The second vias 932 can be lined or filled with a conductive material 924 (e.g., copper), which contacts the second and fourth external terminals 916, 920, thereby electrically connecting the second and fourth external terminals 916, 920 and the second interposer 926. For example, the conductive material 924 of one second via 932 can contact the second external terminal 916, and the conductive material 924 of the other second via 932 can contact the fourth external terminal 920, thereby enabling the second and fourth external terminals 916 and 920 to be electrically connected to the second interposer 926.

[0081] Referring here to Figures 12A and 12B, in some embodiments of the decoupling capacitor structure 900, the decoupling capacitor 904 is one of a plurality of decoupling capacitors 904, and the plurality of decoupling capacitors 904 are arranged adjacent to the first interposer 902. That is, each decoupling capacitor structure 900 can include a plurality of decoupling capacitors 904 stacked with only one interposer 902 (Figure 12B), or a plurality of decoupling capacitors 904 stacked with one first interposer 902 and one second interposer 926 (Figure 12A). The plurality of decoupling capacitors 904 can be arranged within the decoupling capacitor structure 900, spaced apart from each other along the lateral X and longitudinal Y directions.

[0082] As shown in Figure 12A, in some embodiments, the decoupling capacitor structure 900 includes a first interposer 902 and a second interposer 926, and a plurality of decoupling capacitors 904 are sandwiched between the first interposer 902 and the second interposer 926, as described with respect to Figure 11B. In other embodiments, such as as illustrated in Figure 12B, the decoupling capacitor structure 900 may include only the first interposer 902, and the plurality of decoupling capacitors 904 are positioned adjacent to the second surface 908 of the first interposer 902. Each of the plurality of decoupling capacitors 904 may be configured as described herein, with at least two external terminals provided on the first surface 910 of each decoupling capacitor 904 and at least two external terminals provided on the second surface 912 opposite to each decoupling capacitor 904.

[0083] As shown in Figures 12A and 12B, each of the multiple decoupling capacitors 904 is positioned adjacent to the first interposer 902, with the first surface 910 of each decoupling capacitor 904 adjacent to the second surface 908 of the first interposer 902. Similar to the embodiments in Figures 11A and 11B, the first external terminal 914 and the third external terminal 918 of each decoupling capacitor 904 are electrically connected to the first interposer 902. In the embodiment of Figure 12A, each decoupling capacitor 904 is positioned between the first interposer 902 and the second interposer 926, with the second surface 912 of each decoupling capacitor 904 adjacent to the first surface 928 of the second interposer 926. Furthermore, the second external terminal 916 and the fourth external terminal 920 of each decoupling capacitor 904 are electrically connected to the second interposer 926.

[0084] A decoupling capacitor structure 900 having multiple components arranged adjacent to one or two interposers 902 includes multiple decoupling capacitors 904, but it will be recognized that each of the multiple components does not have to be a decoupling capacitor 904. Rather, in some embodiments, one or more of the multiple components arranged adjacent to a single interposer 902 or sandwiched between two interposers 902 can be capacitors, varistors, resistors, inductors, filters, or any other suitable components having configurations different from those described herein. Thus, in some embodiments, a decoupling capacitor structure 900 can include at least one decoupling capacitor 904 and one or more other components, and the one or more other components can be arranged away from and apart from the decoupling capacitors 904, as shown with respect to the multiple decoupling capacitors 904 in Figure 12A or the multiple components in Figure 12B. However, in some embodiments, the multiple components within the decoupling capacitor 904 do not all need to be spaced uniformly apart from one another, as shown in Figures 12A and 12B. For example, two or more components (e.g., two or more decoupling capacitors 904, one decoupling capacitor 904 and one other component) can be positioned immediately adjacent to each other along the lateral X and / or longitudinal Y directions and can be in contact with each other along at least one surface.

[0085] Looking at Figures 15A, 15B, and 15C, in some embodiments, one or more interposers can be sacrificial plates. More specifically, the sacrificial component structure 1200 includes at least one sacrificial plate 1202, with a plurality of components 1204 disposed adjacent to it. After sacrificing at least a portion of at least one sacrificial plate 1202, a reduced component structure 1250 remains. It will be understood that similar reference figures in Figures 15A to 15C refer to similar features described, for example, with respect to the decoupling capacitor structure 900 in Figures 11A to 12B.

[0086] As illustrated with reference to Figures 15A, 15B, and 15C, a resin 1234 (for example, an epoxy resin as described elsewhere in this specification) is coated, injected, or otherwise disposed around the multiple components 1204. In embodiments in which at least one sacrificial plate 1202 includes a first sacrificial plate 1202 and a second sacrificial plate 1202 / 1226, the second sacrificial plate 1202 can be disposed adjacent to the multiple components 1204 after the coating of the resin 1234. However, in other embodiments, the second sacrificial plate 1202 / 1226 can be disposed adjacent to the multiple components 1204 before the coating of the resin 1234. As shown in Figure 15A, the second sacrificial plate 1202 / 1226 is positioned along the Z direction opposite to the first sacrificial plate 1202, and the multiple components 1204 are sandwiched between the first sacrificial plate 1202 and the second sacrificial plate 1202 / 1226.

[0087] Next, one or more vias 1222 are formed through one or more sacrificial plates 1202, for example, as described above with respect to via 922, and filled with a conductive material 1224 (e.g., conductive paste). Then, at least one sacrificial plate 1202 is polished along its first surface 1206 or otherwise reduced in height or thickness along the Z direction, and then the component structure 1200 can be disposed in the assembly, for example, as described below with respect to Figures 13A and 13B. In some embodiments, at least one sacrificial plate 1202 can be reduced in height or thickness after the component structure 1200 has been assembled with other elements of the assembly (for example, after the component structure 1200 has been disposed in a cavity defined in the substrate). Furthermore, at least one sacrificial plate 1202 can be completely removed, or only a portion of at least one sacrificial plate 1202 can be removed. For example, in the embodiment shown in Figure 15B, both of the sacrificial plates 1202 illustrated in Figure 15A are polished down to zero or completely removed. However, in other embodiments, such as those shown in Figure 15C, at least a portion of one or both of the plates 1202 can be retained, with a reduced height H that is not zero along the Z direction. r It is possible to have the initial height H of the sacrificial plate 1202 before reduction. i It is smaller than. As shown in Figure 15C, the first and second sacrificial plates 1202 are reduced in terms of height or thickness, and the reduced height H of the first sacrificial plate 1202 r However, the reduced height H of the second sacrificial plate 1202 / 1226 r Although it appears to differ from this, in other embodiments, the reduced height H of the sacrificial plate 1202 r They can be the same.

[0088] The sacrificial plates 1202 help maintain parallelism between multiple components 1204 during the construction of the component structure 1200. That is, the sacrificial plates 1202 help hold the multiple components 1204 in place such that the first surfaces 1210 of each component 1204 are substantially parallel to each other, and the second surfaces 1212 of each component 1204 are substantially parallel to each other. Therefore, when assembling with the resin 1234, vias 1222, and conductive material 1224, one or more sacrificial plates 1202 can be removed whole or partially by grinding along their respective surfaces 1206, 1230, or by another suitable removal technique. As shown in Figure 15B, removing the sacrificial plates 1202 makes it possible to expose one or more external terminals 1214, 1216, 1218, 1220 of each of the multiple components 1204.

[0089] In the embodiments depicted in Figures 15A and 15B, multiple components 1204 are sandwiched between two sacrificial plates 1202, but it will be recognized that in other embodiments, a single sacrificial plate 1202 may suffice. When worn down, or otherwise removed or reduced in height, one or both sacrificial plates 1202 can be reduced in height along the Z direction. Furthermore, a second sacrificial plate 1202 can be assembled with the first sacrificial plate 1202 and the multiple components 1204 before or after the addition of resin 1234. One or more vias 1222 can be formed through one or both sacrificial plates 1202.

[0090] Furthermore, as described above, the multiple components 1204 can be multiple decoupling capacitors 904, or they can be multiple components that may or may not include at least one decoupling capacitor 904. For example, in some embodiments, the multiple components 1204 include at least one decoupling capacitor 904 and one or more other components (e.g., another type of capacitor, varistor, resistor, inductor, filter, or any other suitable component), and in other embodiments, the multiple components 1204 include at least one of another type of capacitor, varistor, resistor, inductor, filter, or any other suitable component, and do not include a decoupling capacitor 904.

[0091] VI. Decoupling Capacitor Assembly One or more decoupling capacitor structures can be disposed within a substrate to form a decoupling capacitor assembly. The decoupling capacitor assembly can facilitate the insertion of the decoupling capacitor structure into a microelectronic assembly, for example, as described elsewhere herein. For example, the decoupling capacitor structure can be electrically connected to the substrate, and the substrate can include one or more conductive paths to facilitate the electrical connection of the decoupling capacitor assembly to one or more components of the microelectronic assembly. The substrate can also provide additional structural integrity to the decoupling capacitor structure, and the decoupling capacitor structure can be surrounded by a resin (for example, an epoxy resin as described herein) in a cavity of the substrate. Such additional structural integrity can facilitate the establishment of electrical connections with the decoupling capacitor (e.g., through conductive vias extending through the interposer of the resin and decoupling capacitor structure) despite any warping of the decoupling capacitor, otherwise the warping could prevent electrical connections between one or more external ends of the decoupling capacitor (formed on the opposite surface of the decoupling capacitor as described herein) and other components. Furthermore, forming such a decoupling capacitor assembly makes it possible to provide a decoupling capacitor module that includes one or more decoupling capacitors and can be tested for suitability, form, and / or function before integration into a larger assembly, which can help improve the yield of the final product by detecting defective capacitors, incorrectly sized capacitors, or capacitors that have lost their function before integration.

[0092] Referring to Figures 13A and 13B, side cross-sectional views of exemplary decoupling capacitor assemblies 1000 are provided. Each decoupling capacitor assembly 1000 includes a substrate 1002 in which a cavity 1004 is defined. In the embodiments of Figures 13A and 13B, multiple decoupling capacitor structures 900 are disposed within the cavity 1004 of the substrate 1002. However, it will be recognized that in other embodiments, only one decoupling capacitor structure 900 may be disposed within the cavity 1004.

[0093] In some embodiments, a resin (for example, an epoxy resin as described herein) can surround one or more decoupling capacitor structures 900 disposed within a cavity 1004 of a substrate 1002. Furthermore, at least one interposer of each decoupling capacitor structure 900 can be electrically connected to the substrate 1002, and the substrate can be placed in a state where it is electrically connected to, for example, the decoupling capacitor 904 of the decoupling capacitor structure 900. For example, the first interposer 902 of each decoupling capacitor structure 900 can be electrically connected to the substrate 1002. In embodiments in which the decoupling capacitor structure 900 includes both a first interposer 902 and a second interposer 926, both the first interposer 902 and the second interposer 926 can be electrically connected to the substrate 1002, or only one of the first interposer 902 and the second interposer 926 can be electrically connected to the substrate 1002.

[0094] VII. Multilayer Decoupling Capacitor Structures One or more decoupling capacitor structures, or one or more structures containing at least one decoupling capacitor, can be stacked together to form a multilayer decoupling capacitor structure. By arranging at least one decoupling capacitor between interposers to form a decoupling capacitor structure as described above, and by stacking decoupling capacitor structures along the stacking direction with similar structures containing decoupling capacitors and / or other components, it is possible to form, for example, a filter or composite structure that facilitates radio frequency (RF) integration. For example, two or more decoupling capacitor structures can be stacked along the stacking direction or perpendicularly to form a module that can be tested for suitability, form, and / or function before assembly with other components, which can improve the yield of the final product. Such a module can contain a decoupling capacitor structure with the decoupling capacitor positioned therein, which can improve the functionality of the final product, improve the integration of at least one decoupling capacitor into the assembly, and / or improve the yield of the final product.

[0095] Referring to Figures 14A and 14B, the multilayer decoupling capacitor structure 1100 can include a plurality of interposers 1102 and a plurality of decoupling capacitors 1104. Similar reference figures can be used to indicate the same or similar features, and it will be recognized that, for example, an interposer 1102 can generally be configured as an interposer 902 as described with respect to Figures 11A to 13B. Furthermore, it will be recognized that each of the multiple decoupling capacitors 1104, such as the decoupling capacitor 904, can be configured as described herein with respect to exemplary decoupling capacitors, for example, in Figures 4A to 10C. For example, each decoupling capacitor 1104 may include a first surface 1110 and a second surface 1112 on the opposite side, and may include alternating dielectric layers and internal electrode layers, for example, as illustrated in Figures 4A to 5C, and comprises a first external terminal 1114, a second external terminal 1116, a third external terminal 1118, and a fourth external terminal 1120, wherein the first external terminal 1114 is electrically connected to a first internal electrode layer and is located on the first surface 1110, the second external terminal 1116 is electrically connected to a first internal electrode layer and is located on the second surface 1112, the third external terminal 1118 is electrically connected to a second internal electrode layer and is located on the first surface 1110, and the fourth external terminal 1120 is electrically connected to a second internal electrode layer and is located on the second surface 1112. The four external terminals are described merely as examples, and it should be understood that the decoupling capacitor 1104 of the multilayer decoupling capacitor structure 1100 may include more than four external terminals (for example, those described with respect to Figures 4A to 10C), as described in more detail elsewhere in this specification.Furthermore, in Figures 14A and 14B, the location of the decoupling capacitor 1104 with labeled terminals 1114, 1116, 1118, and 1120 is merely illustrative, and it will be recognized that, in embodiments including components other than the decoupling capacitor 1104, the decoupling capacitor 1104 of the multilayer structure 1100 can be included in any suitable location within the multilayer structure 1100.

[0096] As shown in Figures 14A and 14B, the multiple interposers 1102 and multiple decoupling capacitors 1104 of the multilayer decoupling capacitor structure 1100 are arranged within at least two layers 1150. Each layer 1150 includes at least one decoupling capacitor 1104 positioned between two interposers 1102, and the at least two layers 1150 are stacked adjacent to each other such that one interposer 1102 is common to at least two layers 1150.

[0097] For example, referring particularly to Figure 14A, the multilayer decoupling capacitor structure 1100 may include a first layer 1150A and a second layer 1150B. The first layer 1150A and the second layer 1150B are stacked adjacent to each other along the height direction or stacking direction Z, which may be vertical when the multilayer decoupling capacitor structure 1100 is integrated into a product (e.g., a microelectronic assembly as described herein). More specifically, in the embodiment depicted, the first layer 1150A may include a first interposer 1102A, a second interposer 1102B, and a first set 1152A of components disposed between the first interposer 1102A and the second interposer 1102B. The first set of components 1152A can be a plurality of decoupling capacitors 1104 (for example, only decoupling capacitors), or the first set 1152A can include one or more components that are not decoupling capacitors, as described below with respect to other components 1160. The second layer 1150B includes a second interposer 1102B, a third interposer 1102C, and a second set of components 1152B disposed between the second interposer 1102B and the third interposer 1102C. Like the first set 1152A, the second set 1152B of components can be a plurality of decoupling capacitors 1104 (for example, only decoupling capacitors), or the second set 1152B can include one or more components that are not decoupling capacitors, as described below.

[0098] In the embodiment shown in Figure 14A, each component 1104 / 1160 of the first set of components 1152A is aligned with each component 1104 / 1160 of the second set of components 1152B along the stacking direction Z. In other embodiments, such as those shown in Figure 14B, the first layer 1150A and the second layer 1150B are stacked adjacent to each other along the stacking direction Z, and each component 1104 / 1160 of the first set of components 1152A is offset along the longitudinal direction Y from each component 1104 / 1160 of the second set of components 1152B. The longitudinal direction Y is perpendicular to the stacking direction Z.

[0099] As further shown in Figure 14B, the multilayer decoupling capacitor structure 1100 may include an additional layer 1150 (e.g., a third layer 1150C). The third layer 1150C includes a third interposer 1102C and a fourth interposer 1102D, with a third set of components 1152C disposed between the third interposer 1102C and the fourth interposer 1102D. The third set of components 1152C may be a plurality of decoupling capacitors 1104 (e.g., decoupling capacitors only), or the third set 1152C may include one or more components that are not decoupling capacitors, as described below with respect to other components 1160. Each component 1104 / 1160 of the third set of components 1152C is aligned with each individual component 1104 / 1160 of the first set of components 1152A along the stacking direction Z. Thus, each component 1104 / 1160 of the third set of components 1152C is offset along the longitudinal direction Y from each individual component 1104 / 1160 of the second set of components 1152B.

[0100] Returning to Figure 14A, in at least some embodiments, at least one of the multiple interposers 1102 of the multilayer decoupling capacitor structure 1100 includes at least one via 1122 extending from a first surface 1106 of at least one interposer 1102 to a second surface 1108 of at least one interposer 1102. As described with respect to via 922, at least one via 1122 can be filled with a conductive material 1124 (e.g., copper).

[0101] In some embodiments, at least one interposer 1102 includes one via 1122 in contact with a first external terminal 1114 of one decoupling capacitor 1104 and a second via 1122 in contact with a third external terminal 1118 of one decoupling capacitor 1104, thereby electrically connecting the first external terminal 1114 and the third external terminal 1118 to at least one interposer 1102. In other embodiments, multiple decoupling capacitors 1104 can be electrically connected to their respective interposers 1102 through any other suitable electrical connection, and / or one or more of the multiple decoupling capacitors 1104 can be electrically connected through their respective interposers 1102 to another component of an electronic assembly including a multilayer decoupling capacitor assembly 1100 (for example, another component of a microelectronic assembly according to the exemplary embodiments described herein).

[0102] It will be recognized that the components sandwiched between the interposers 1102 are not limited to the decoupling capacitor 1104. For example, one or more other components 1160 (e.g., capacitors configured differently from those described herein) may be included in one or more layers 1150 of the multilayer structure 1100, and varistors, resistors, or inductors (which may form, for example, one or more filters) may be disposed between a pair of interposers 1102, and one or more capacitors, varistors, resistors, inductors, etc. may be part of one or more layers 1150 of the multilayer structure 1100. One or more vias 922 may be formed between layers 1150 to electrically connect, for example, components 1104, 1160 of one layer 1150 to components 1104, 1160 of another layer 1150.

[0103] VIII. Microelectronic Assembly A semiconductor structure, an assembly interposer, a package substrate, and at least one of a decoupling capacitor structure, a decoupling capacitor assembly, or a multilayer decoupling capacitor structure can generally be arranged on a circuit board in a variety of different configurations. Referring to Figure 1, for example, one embodiment of a microelectronic assembly 600 is shown, which includes semiconductor structures 610, 620, and 630 electrically connected to an assembly interposer 650, and a package substrate 680 electrically connected to the assembly interposer 650. The semiconductor structures can be any type of structure as described above. In one embodiment, for example, structures 610 and 630 can be a high-bandwidth memory structure, a field-programmable gate array. The semiconductor structures 610, 620, and 630 can be electrically connected to the assembly interposer 650 via first-level coupling components 611, 621, and 631, respectively, as shown. In the illustrated embodiment, the connecting component 621 may be a solder ball or bump, while the connecting components 611 and 631 may be a conductive adhesive or underfill material. Although not always required, an overmolding material 760 may also be used. The overmolding material may be an insulating material, such as those described above (e.g., epoxy resin material). Similarly, the assembly interposer 650 contains conductive paths 652 formed in an insulating dielectric material 654. The conductive paths 652 allow for the electrical connection of the assembly interposer 650 to the package substrate 680 through a second level connecting component 656 (e.g., a solder ball or bump). The package substrate 680 then contains conductive paths 682 (e.g., vias) in an insulating dielectric material 684.The conductive path 682 allows for the electrical connection of the package substrate 680 to the circuit board 800 (e.g., a printed circuit board) through a third level coupling component 704 (e.g., a solder ball).

[0104] In particular, the decoupling capacitor assembly 10 (see, for example, Figures 12A to 12B) is also positioned between at least a portion of the package substrate 680 and the circuit board 800. As described herein, it should be understood that, naturally, the decoupling capacitor structure 10 may contain only one or more decoupling capacitors, and that one or more decoupling capacitors may be used between the package substrate 680 and the circuit board 800. The external terminals of the decoupling capacitors may each be electrically connected to the current paths of the circuit board 800 and may be connected to the circuit board 800 using any method commonly known in the art. For example, instead of solder balls 704, the decoupling capacitor assembly 10 may be directly electrically connected to the package substrate 680 and the circuit board 800, or at least a smaller coupling component 702 (e.g., a solder bump or ball) than coupling component 704 may be used.

[0105] In addition to the decoupling capacitor assembly 10, or as an alternative to the decoupling capacitor assembly 10, one or more decoupling capacitor structures or multilayer decoupling capacitor structures can be positioned between at least a portion of the package substrate 680 and the circuit board 800, as illustrated with respect to the assembly 10. The decoupling capacitors in such assemblies or structures can allow AC signals to pass or be transmitted while blocking DC signals. That is, decoupling capacitors can be used to block low-frequency signals and transmit high-frequency signals. Furthermore, by arranging the decoupling capacitors in the manner shown in Figure 1, certain conductive paths directly above the decoupling capacitors (e.g., directly above the decoupling capacitor assembly 10) can be eliminated, thereby further improving performance. The use of decoupling capacitors in such a manner can also enable a significant reduction in inductance. In particular, minimizing the distance or path for ground connections can help reduce inductance. For example, the use of a decoupling capacitor can result in an inductance of about 1 nanohenry or less, and in some embodiments, it is possible to result in an inductance of about 25 femtohenry to about 900 picohrenry, in some embodiments, about 100 femtohenry to about 500 picohrenry, and in some embodiments, about 250 femtohenry to about 100 picohrenry. Furthermore, the decoupling capacitor can exhibit a low equivalent series resistance, such as, for example, less than about 100 mOhm, in some embodiments, about 0.01 mOhm to about 50 mOhm, in some embodiments, about 0.1 mOhm to about 40 mOhm, and in some embodiments, about 0.5 mOhm to about 30 mOhm.Low inductance and / or equivalent series resistance can be achieved while still exhibiting tuned capacitance values, such as approximately 1 pF to approximately 1,000 μF, in some embodiments approximately 500 pF to approximately 500 μF, and in some embodiments approximately 1 μF to approximately 100 μF.

[0106] In the embodiment shown in Figure 1, the assembly interposer 650 is generally considered a “passive” interposer in that it does not contain any integrated electronic components. However, it should be understood that an “active” interposer can also be appropriately used in the microelectronic assembly of the present invention. Referring to Figure 2, one embodiment of the microelectronic assembly 100 is shown, which includes semiconductor structures 114-3, 114-1, and 114-2 electrically connected to the assembly interposer 102, and a package substrate 104 electrically connected to the assembly interposer 102. In the illustrated embodiment, a bridge 110 is also embedded within the assembly interposer 102. More specifically, the assembly interposer 102 may have a first surface 170-1 and a second surface 170-2 on the opposite side, and the surface of the bridge 110 may be coplanar with the second surface 170-2 of the assembly interposer 102. The bridge 110 may include a substrate 111a and one or more routing layers 111b, the one or more routing layers 111b having high-density conductive paths 118 (e.g., traces and / or vias) through an insulating material (e.g., a dielectric material formed in multiple layers) for routing electrical signals between dies 114-1 and 114-2. The bridge 110 can be fabricated from any suitable material. For example, in some embodiments, the insulating material can be a semiconductor material (e.g., silicon or germanium), a III-V material (e.g., gallium nitride), silicon oxide, or glass.

[0107] Although not required, the bridge 110 may include one or more integrated electronic components 112 (e.g., resistors and / or capacitors). The bridge 110 may include multiple integrated electronic components 112 disposed on the surface of the bridge 110 at different distances from the surface of the bridge 110 (i.e., in the z-direction) and at different lateral locations within the bridge 110 (e.g., in the x-direction). The bridge 110 may also include conductive paths 115 and 118 through insulating material that connect the integrated electronic components 112 to semiconductor structures 114-3, 114-1, and 114-2. The semiconductor structures may be connected to the second surface 170-2 of the assembly interposer 102 via first level conductive paths 108-1, 108-2, and 108-3, as shown. Furthermore, the assembly interposer 102 may include conductive paths 119 for electrically connecting semiconductor structures 114-3, 114-1, and 114-2 to the package substrate 104 (for example, via first-level interconnects 108-3, 108-1, 108-2 and second-level interconnects 109). Any suitable arrangement of the conductive paths 119 may, as desired, connect the semiconductor structures to each other (for example, a conductive path 117 connecting structure 114-1 to structure 114-3) and connect the structures to the substrate 104. Although not expressly shown herein, the package substrate 104 is also connected to the circuit board and decoupling capacitors in the manner described above.

[0108] Another embodiment of the microelectronic assembly 800, which includes an active assembly interposer 802, is shown in Figure 3. In this embodiment, the assembly interposer 802 is electrically connected to the package substrate 832, and a semiconductor structure 310 (e.g., a coprocessor) is electrically connected to the assembly interposer 802. The semiconductor structure 310 may include an active layer 392 and a bulk semiconductor layer 390 (which may be referred to herein as an inactive layer 390). The active layer 392 may include circuit elements and register files 394, which may act as a central on-die memory for the structure 310. The active assembly interposer 802 may similarly include an active layer 806 and a bulk semiconductor layer 804 (which may be referred to as an inactive layer 804). The active layer 806 may include a plurality of Level 1 (L1) memory elements 808 formed on its active side, which can be used as a memory cache for storing configuration bitstreams for constituting logical sectors in the structure 310. The active assembly interposer 802 may be electrically connected to the package substrate 832 through a linking component 822 (e.g., solder bumps or balls), and the inactive layer 804 may include through-silicon vias (TSVs) 810, which can connect components such as the L1 memory elements 808 in the active layer 806 to the linking component 822. The active layer 806 may face the active layer 392 of the semiconductor structure 310, and can be electrically connected to components in the active layer 392 through a linking component 820 (e.g., solder bumps).

[0109] If desired, additional semiconductor structures 812 (e.g., auxiliary chips) can be electrically connected directly to the substrate 832. Structures 812 may include an active layer 816 and a bulk semiconductor layer 814 (optionally referred to as a deactivating layer 814). The active layer 816 may include a level 2 (L2) memory element 809 formed on the active side, which can be used as a memory cache for storing configuration bitstreams. For example, a configuration bitstream stored in an L1 memory element 808 on the assembly interposer 802 can be transferred to the L2 memory element 809 to make space on the L1 memory element 808 for a new incoming configuration bitstream (e.g., received from a host processor in the L1 memory element 808). The active layer 816 can face the package substrate 832 and be electrically connected to it through connecting components 822 and 824 (e.g., solder balls or bumps). Furthermore, the bridge 826 can be used to connect the semiconductor structure 812 to the assembly interposer 802. The bridge 826 can include an interconnect 828 formed in a silicon substrate embedded in the package substrate 832. The interconnect 828 can electrically connect a portion of the connecting component 824 connected to the semiconductor structure 812 to a portion of the connecting component 824 connected to the assembly interposer 802. Also, the heat sink 830 can be installed in contact with the semiconductor structures 310 and 812, as is known in the art. And, although not expressly shown herein, the package substrate 104 is connected to the circuit board and decoupling capacitor in the manner described above.

[0110] These and other modifications and variations of the present invention can be practiced by those skilled in the art without departing from the spirit and scope of the invention. In addition, it should be understood that the aspects of the various embodiments can be interchanged, both in whole and in part. Furthermore, those skilled in the art will recognize that the foregoing description is merely illustrative and not intended to limit the invention, and that the invention is further described in such appended claims. [Explanation of symbols]

[0111] 10 Decoupling Capacitors 12 First external terminal 14. Second external terminal 20 Capacitors 22a First external terminal 22b First external terminal 24a Second external terminal 24b Second external terminal 30 Capacitors 32 External terminals 32a First external terminal 32b First external terminal 34 External terminals 34a Second external terminal 34b Second external terminal 100 Microelectronic Assembly 102 Assembly Interposer 104 Package substrate 105 First internal electrode layer, alternating electrode layers, non-contact hole, gap 105a Side edge 105b Side edge 105c Upper edge 105d bottom edge 108-1 First Level Conductive Path 108-2 First Level Conductive Path 108-3 First Level Conductive Path 109 Second level interconnect 110 Internal electrode layer, bridge 110a Set of internal electrode layers 110b Set of internal electrode layers 111a substrate 111b Routing Layer 112 Electronic Components 114-1 Semiconductor structures, dies 114-2 Semiconductor structures, dies 114-3 Semiconductor Structures 115 Second set of internal electrode layers, second internal electrode layer, alternating electrode layers, non-contact holes, gap, conductive path 117 Conductive Path 118 Conductive Path 119 Conductive Path 120 First lead tab 121 Lateral edge 122 Lateral edge 123 Front edge 125 Gap 130 First lead tab 131 Lateral edge 132 Lateral edge 133 Front edge 135 Main body, gap 140 First lead tab 141 Lateral edge 142 Lateral edge 143 Front edge 145 Main body 150 First lead tab 151 Lateral edge 152 Lateral edge 153 Front edge 170-1 First surface 170-2 Second surface 205 First internal electrode layer, first active electrode layer 205a Side edge 205c Upper edge 205d bottom edge 210 Internal electrode layer 210a Set of internal electrode layers 210b Set of internal electrode layers 210c internal electrode layer set 210d Internal electrode layer set 215 Second internal electrode layer, second active electrode layer, active electrode 220 First lead tab 220a~b Lead Tabs 221a Lateral edge 222a Lateral edge 223a~b Leading edge 225 First conductive via 230 First lead tab 230a~b Lead Tabs 231a Lateral edge 232a Lateral edge 233a~b Front edge 235 Main body section, upper surface 240 First lead tab 240a~b Lead Tabs 241a Lateral edge 242a Lateral edge 243a~b Front edge 245 Main body, lower surface 250 First lead tab 250a~b Lead Tabs 251a Lateral edge 252a Lateral edge 253a~b Leading edge 255 First Shield Area 265 Second Shield Area 275 Shield electrode layer 285 Second conductive via 295 Second anchor electrode, second anchor tab 305 First anchor electrode 310 Semiconductor Structures 390 Bulk semiconductor layer, inactive layer 392 Active layer 394 Register File 600 Microelectronic Assembly 610 Semiconductor Structures 611 First-level linked components 621 First-level linked components 620 Semiconductor Structures 630 Semiconductor Structures 631 First-level linked components 650 Assembly Interposer 652 Conductive Path 654 Insulating Dielectric Materials 656 Second-level linked components 680 Package Substrates 682 Conductive Path 684 Insulating Dielectric Materials 702 Linked Components 704 Third-level linked components 760 Overmolding Material 800 Circuit boards, microelectronic assemblies 802 Active Assembly Interposer, Assembly Interposer 804 Bulk semiconductor layer, inactive layer 806 Active layer 808 Level 1 (L1) Memory Element 809 Level 2 (L2) memory element 810 Through-Silicon Via (TSV) 812 Semiconductor Structures 814 Bulk semiconductor layer, inactive layer 816 Active layer 820 Linked Components 822 Linking components, solder balls 824 Linking Components, Solder Balls 826 Bridge 828 Interconnection section 830 Heatsink 832 Package substrate 900 Decoupling Capacitor Structure 902 Interposer, First Interposer 904 Decoupling Capacitor 906 First surface 908 Second surface 910 First surface 912 Second surface 914 First external terminal 916 Second external terminal 918 Third external terminal 920 Fourth external terminal 922 First Beer 924 Conductive materials 926 The Second Interposer 928 First surface 930 Second surface 932 Second Beer 934 Insulating materials 1000 Decoupling Capacitor Assembly 1002 circuit board 1004 Cavity 1100 Multilayer Decoupling Capacitor Structure, Multilayer Structure 1102 Interposer 1102A First Interposer 1102B Second Interposer 1102C Third Interposer 1102D The Fourth Interposer 1104 Decoupling Capacitors, Components 1106 First surface 1108 Second surface 1110 First surface 1112 Second surface 1114 First external terminal 1116 Second external terminal 1118 Third external terminal 1120 Fourth external terminal 1122 Second Beer 1150 layers 1150A First layer 1150B Second layer 1150C Third Layer 1152A First set 1152B Second set 1152C Third set 1160 components, other components 1200 Sacrificial Component Structure 1202 Sacrifice Plate, First Sacrifice Plate, Second Sacrifice Plate 1204 Components 1206 First surface 1210 First surface 1212 Second surface 1214 External terminals 1216 External terminals 1218 External terminals 1220 External terminals 1222 Beer 1224 Conductive materials 1226 Second Sacrifice Plate 1230 Surface 1234 Resin 1250 Reduced Component Structures 1350 Void BW External terminal width BL External terminal length BLA External Terminal Length BLB External terminal length H i Initial height H r Reduced height L Length O Offset T thickness t Distance between sets Distance between t1 sets Distance between t2 sets Distance between t3 sets W width X horizontal direction Y-direction (longitudinal direction) Z: Height direction, Thickness direction

Claims

1. A decoupling capacitor structure, wherein the decoupling capacitor structure is A first interposer having a first surface and a second surface on the opposite side; A decoupling capacitor having a first surface and a second surface on the opposite side, wherein the decoupling capacitor includes alternating dielectric layers and internal electrode layers, the internal electrode layers include a first internal electrode layer and a second internal electrode layer, the decoupling capacitor further includes a first external terminal, a second external terminal, a third external terminal, and a fourth external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on the first surface of the decoupling capacitor, the second external terminal being electrically connected to the first internal electrode layer and disposed on the second surface of the decoupling capacitor, the third external terminal being electrically connected to the second internal electrode layer and disposed on the first surface of the decoupling capacitor, and the fourth external terminal being electrically connected to the second internal electrode layer and disposed on the second surface of the decoupling capacitor. Includes, The decoupling capacitor is disposed adjacent to the first interposer such that the first surface of the decoupling capacitor is adjacent to the second surface of the first interposer. A decoupling capacitor structure in which the first external terminal and the third external terminal are electrically connected to the first interposer.

2. The aforementioned decoupling capacitor structure is The present invention further includes a second interposer having a first surface and a second surface on the opposite side. The decoupling capacitor is disposed between the first interposer and the second interposer such that the second surface of the decoupling capacitor is adjacent to the first surface of the second interposer. The decoupling capacitor structure according to claim 1, wherein the second external terminal and the fourth external terminal are electrically connected to the second interposer.

3. The decoupling capacitor is one of a plurality of decoupling capacitors, each of the plurality of decoupling capacitors has a first surface and a second surface on the opposite side, each of the plurality of decoupling capacitors contains alternating dielectric layers and internal electrode layers, the internal electrode layers contain a first internal electrode layer and a second internal electrode layer, each of the plurality of decoupling capacitors further contains a first external terminal, a second external terminal, a third external terminal and a fourth external terminal, and the first external The decoupling capacitor structure according to claim 1, wherein the internal terminal is electrically connected to the first internal electrode layer and disposed on the first surface of the decoupling capacitor, the second external terminal is electrically connected to the first internal electrode layer and disposed on the second surface of the decoupling capacitor, the third external terminal is electrically connected to the second internal electrode layer and disposed on the first surface of the decoupling capacitor, and the fourth external terminal is electrically connected to the second internal electrode layer and disposed on the second surface of the decoupling capacitor.

4. The decoupling capacitor structure according to claim 3, wherein each of the plurality of decoupling capacitors is disposed adjacent to the first interposer such that the first surface of each of the plurality of decoupling capacitors is adjacent to the second surface of the first interposer, and the first external terminal and the third external terminal of each of the plurality of decoupling capacitors are electrically connected to the first interposer.

5. The aforementioned decoupling capacitor structure is The present invention further includes a second interposer having a first surface and a second surface on the opposite side. Each of the plurality of decoupling capacitors is disposed between the first interposer and the second interposer such that the second surface of each of the plurality of decoupling capacitors is adjacent to the first surface of the second interposer. The decoupling capacitor structure according to claim 4, wherein the second external terminal and the fourth external terminal of each of the plurality of decoupling capacitors are electrically connected to the second interposer.

6. The decoupling capacitor structure according to claim 5, wherein the first interposer includes at least one first via extending from the first surface of the first interposer to the second surface of the first interposer, and the second interposer includes at least one second via extending from the first surface of the second interposer to the second surface of the second interposer.

7. The decoupling capacitor structure according to claim 6, wherein the at least one first via and the at least one second via are filled with a conductive material.

8. The decoupling capacitor structure according to claim 6, wherein the at least one first via is in contact with either the first external terminal or the third external terminal of each of the plurality of decoupling capacitors.

9. The decoupling capacitor structure according to claim 6, wherein at least one second via is in contact with either the second external terminal or the fourth external terminal of one of the multiple decoupling capacitors.

10. The decoupling capacitor structure according to claim 6, wherein the at least one first via includes two first vias, one of the two first vias is in contact with a first external terminal of each of the plurality of decoupling capacitors, the other of the two first vias is in contact with a third external terminal of each of the decoupling capacitors, and the first and third external terminals of each of the decoupling capacitors are electrically connected to the first interposer.

11. The decoupling capacitor structure according to claim 10, wherein the at least one second via comprises two second vias, one of which contacts the second external terminal of each of the decoupling capacitors, and the other of which contacts the fourth external terminal of each of the decoupling capacitors, and the second and fourth external terminals of each of the decoupling capacitors are electrically connected to the second interposer.

12. The decoupling capacitor structure according to claim 1, wherein the first interposer includes at least one first via extending from a first surface of the first interposer to a second surface of the first interposer, and the at least one first via is filled with a conductive material.

13. The decoupling capacitor structure according to claim 12, wherein the at least one first via comprises two first vias, one of the two first vias is in contact with the first external terminal, the other of the two first vias is in contact with the third external terminal, and the first external terminal and the third external terminal are electrically connected to the first interposer.

14. The decoupling capacitor structure according to claim 2, wherein the first interposer is a first sacrificial plate, and the second interposer is a second sacrificial plate, and each of the first sacrificial plate and the second sacrificial plate is configured to be polished such that the height of each of the first sacrificial plate and the second sacrificial plate is reduced.

15. A decoupling capacitor assembly, wherein the decoupling capacitor assembly is A substrate defining the cavity within it, A decoupling capacitor structure disposed within the cavity and Includes, The aforementioned decoupling capacitor structure is A first interposer having a first surface and a second surface on the opposite side, A decoupling capacitor having a first surface and a second surface on the opposite side, wherein the decoupling capacitor includes alternating dielectric layers and internal electrode layers, the internal electrode layers include a first internal electrode layer and a second internal electrode layer, the decoupling capacitor further includes a first external terminal, a second external terminal, a third external terminal, and a fourth external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on the first surface of the decoupling capacitor, the second external terminal being electrically connected to the first internal electrode layer and disposed on the second surface of the decoupling capacitor, the third external terminal being electrically connected to the second internal electrode layer and disposed on the first surface of the decoupling capacitor, and the fourth external terminal being electrically connected to the second internal electrode layer and disposed on the second surface of the decoupling capacitor. Includes, The decoupling capacitor is disposed adjacent to the first interposer such that the first surface of the decoupling capacitor is adjacent to the second surface of the first interposer. The first external terminal and the third external terminal are electrically connected to the first interposer in a decoupling capacitor assembly.

16. The decoupling capacitor assembly according to claim 15, further comprising a second interposer having a first surface and a second surface on the opposite side, wherein the decoupling capacitor is disposed between the first interposer and the second interposer such that the second surface of the decoupling capacitor is adjacent to the first surface of the second interposer, and the second external terminal and the fourth external terminal are electrically connected to the second interposer.

17. The decoupling capacitor assembly according to claim 15, wherein the decoupling capacitor structure is one of a plurality of decoupling capacitor structures disposed in the cavity.

18. The decoupling capacitor assembly according to claim 17, wherein the resin surrounds the plurality of decoupling capacitor structures in the cavity.

19. The decoupling capacitor assembly according to claim 15, wherein the first interposer is electrically connected to the substrate.

20. The decoupling capacitor is one of a plurality of decoupling capacitors in the decoupling capacitor structure, each of the plurality of decoupling capacitors has a first surface and a second surface on the opposite side, each of the plurality of decoupling capacitors contains alternating dielectric layers and internal electrode layers, the internal electrode layers contain a first internal electrode layer and a second internal electrode layer, and each of the plurality of decoupling capacitors further contains a first external terminal, a second external terminal, a third external terminal and a fourth external terminal. The decoupling capacitor assembly according to claim 15, wherein the first external terminal is electrically connected to the first internal electrode layer and disposed on the first surface of the decoupling capacitor, the second external terminal is electrically connected to the first internal electrode layer and disposed on the second surface of the decoupling capacitor, the third external terminal is electrically connected to the second internal electrode layer and disposed on the first surface of the decoupling capacitor, and the fourth external terminal is electrically connected to the second internal electrode layer and disposed on the second surface of the decoupling capacitor.

21. A method for forming a reduced component structure, wherein the method is The steps include arranging multiple components adjacent to the first sacrificial plate, The steps include applying resin around the plurality of components, The steps of forming one or more vias through the first sacrificial plate, A step of filling one or more vias with a conductive material, A step of removing at least a portion of the first sacrificial plate along the Z direction, Methods that include...

22. The method according to claim 21, wherein the step of removing at least a portion of the first sacrificial plate includes the step of polishing the first sacrificial plate along a first surface of the first sacrificial plate.

23. The above method, after the step of applying the resin, A step of arranging a second sacrificial plate adjacent to the plurality of components, wherein the second sacrificial plate is located on the opposite side of the first sacrificial plate in the Z direction such that the plurality of components are sandwiched between the first sacrificial plate and the second sacrificial plate. The method according to claim 21, further comprising:

24. A multilayer decoupling capacitor structure, wherein the multilayer decoupling capacitor structure is With multiple interposers; A plurality of decoupling capacitors, each of the plurality of decoupling capacitors having a first surface and a second surface on the opposite side, each decoupling capacitor containing alternating dielectric layers and internal electrode layers, the internal electrode layers containing a first internal electrode layer and a second internal electrode layer, each decoupling capacitor further containing a first external terminal, a second external terminal, a third external terminal and a fourth external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on the first surface of the decoupling capacitor, the second external terminal being electrically connected to the first internal electrode layer and disposed on the second surface of the decoupling capacitor, the third external terminal being electrically connected to the second internal electrode layer and disposed on the first surface of the decoupling capacitor, and the fourth external terminal being electrically connected to the second internal electrode layer and disposed on the second surface of the decoupling capacitor. Includes, The plurality of interposers and the plurality of decoupling capacitors are arranged in at least two layers, each layer including at least one decoupling capacitor of the plurality of decoupling capacitors disposed between two of the plurality of interposers. A multilayer decoupling capacitor structure in which the at least two layers are stacked adjacent to each other such that one of the plurality of interposers is common to the at least two layers.

25. The multilayer decoupling capacitor structure according to claim 24, wherein the at least two layers include a first layer and a second layer, the first layer includes a first interposer of the plurality of interposers, a second interposer of the plurality of interposers, and a first set of the plurality of decoupling capacitors disposed between the first interposer and the second interposer, and the second layer includes a second interposer, a third interposer of the plurality of interposers, and a second set of the plurality of decoupling capacitors disposed between the second interposer and the third interposer.

26. The multilayer decoupling capacitor structure according to claim 25, wherein the first layer and the second layer are stacked adjacent to each other along the stacking direction, and each decoupling capacitor of the first set of the plurality of decoupling capacitors is aligned with each decoupling capacitor of the second set of the plurality of decoupling capacitors along the stacking direction.

27. The multilayer decoupling capacitor structure according to claim 25, wherein the first layer and the second layer are stacked adjacent to each other along the stacking direction, and each decoupling capacitor of the first set of the plurality of decoupling capacitors is offset along the longitudinal direction from each decoupling capacitor of the second set of the plurality of decoupling capacitors, and the longitudinal direction is perpendicular to the stacking direction.

28. The multilayer decoupling capacitor structure according to claim 24, wherein at least one of the plurality of interposers includes at least one via extending from a first surface of the at least one interposer to a second surface of the at least one interposer, and the at least one via is filled with a conductive material.

Images