Analog / digital converter, analog / digital conversion system, digital control device, and digitally controlled power supply

Abstract

In an analog-to-digital converter (90), a first integrating circuit (10) integrates the sum of an analog input signal (Vin) and a first feedback signal (V4) with respect to time, and includes an active element. A second integrating circuit (20) integrates the sum of the integration result of the first integrating circuit (10) and the first feedback signal (V4) with respect to time, and does not include an active element. A first signal generating circuit (34) compares a first output voltage (V5) representing the integration result of the second integrating circuit (20) with a threshold voltage (Vth) in discrete time intervals, generates a 1 as a first digital signal (DS) if the first output voltage (V5) is higher than the threshold voltage (Vth), and generates a 0 as the first digital signal (DS) if the first output voltage (V5) is lower than the threshold voltage (Vth). The first signal generating circuit (34) outputs, as the first feedback signal (V4), a signal obtained by inverting the 1 or 0 of the first digital signal (DS).

Description

Analog-to-digital converter, analog-to-digital conversion system, digital control device, and digitally controlled power supply

[0001] The present disclosure relates to an analog-to-digital converter, an analog-to-digital conversion system, a digital controller, and a digitally controlled power supply.

[0002] In a ΔΣ analog-to-digital (A / D) converter, for example, the technology disclosed in Japanese Patent Laid-Open No. 2019-057937 (Patent Document 1) is known as a technology for improving conversion accuracy with an inexpensive circuit configuration.

[0003] In the delta-sigma A / D converter described in this document, the delta-sigma modulation unit includes a first delta-sigma modulation unit whose input voltage value is the voltage value of the test voltage and a second delta-sigma modulation unit whose input voltage value is the voltage value of a correction reference voltage. The digital filter unit includes a first digital filter that generates N-bit data based on information indicated by the 1-bit data generated by the first delta-sigma modulation unit and a second digital filter that generates N-bit data based on information indicated by the 1-bit data generated by the second delta-sigma modulation unit. The correction calculation unit uses the N-bit data generated by the second digital filter to perform a correction calculation for the N-bit data generated by the first digital filter (see the abstract of Patent Document 1). In addition, in the above delta-sigma modulation unit, the resistor element R1 and the capacitor C1 function as a smoothing circuit, a delay DA conversion circuit, and an integrating circuit (see paragraphs

[0018] and

[0019] of Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2019-057937

[0005] The configuration of the ΔΣ A / D converter disclosed in the above-mentioned Japanese Patent Laid-Open No. 2019-057937 (Patent Document 1) is expected to inexpensively achieve error compensation due to insufficient precision of the reference voltage value. However, no particular consideration is given to reducing quantization errors that occur when converting an analog signal to a digital signal.

[0006] The present disclosure has been made in view of the above-described background art, and one of its objectives is to provide a ΔΣ A / D converter that can achieve higher conversion accuracy than conventional techniques with an inexpensive circuit configuration. Other objectives and features of the present disclosure will be described in the following embodiments.

[0007] In one embodiment, the analog-to-digital converter includes a first integrator circuit, a second integrator circuit, and a first signal generator circuit. The first integrator circuit integrates over time the sum of an analog input signal and a first feedback signal and includes an active element. The second integrator circuit integrates over time the sum of the integration result of the first integrator circuit and the first feedback signal and does not include an active element. The first signal generator circuit compares a first output voltage representing the integration result of the second integrator circuit with a threshold voltage at discrete time intervals, and generates a first digital signal that is 1 if the first output voltage is higher than the threshold voltage, and generates a first digital signal that is 0 if the first output voltage is lower than the threshold voltage. The first signal generator circuit outputs a signal obtained by inverting the 1s and 0s of the first digital signal as the first feedback signal.

[0008] According to the above embodiment, a second-order ΔΣ analog-to-digital converter can be configured using a first integrator circuit including an active element and a second integrator circuit not including an active element, thereby enabling higher conversion accuracy than conventional technology with an inexpensive circuit configuration.

[0009] 1 is a circuit diagram showing a configuration of a ΔΣ A / D converter 90 according to embodiment 1. FIG. 2 is a functional block diagram of a second-order ΔΣ modulator 300 corresponding to the ΔΣ A / D converter 90 of FIG. 1. FIG. 3 is a circuit diagram showing a configuration of a ΔΣ A / D converter 92 according to embodiment 2. FIG. 4 is a circuit diagram showing an example configuration of an A / D conversion system 93 according to embodiment 3. FIG. 5 is a circuit diagram showing the configurations of a digital control device 201 and a digital control power supply 200 using the A / D conversion system 93 of FIG.

[0010] Each embodiment will be described in detail below with reference to the drawings. The same or corresponding parts will be denoted by the same reference characters and description thereof will not be repeated.

[0011] First Embodiment [Configuration of a ΔΣ A / D Converter] FIG. 1 is a circuit diagram showing the configuration of a ΔΣ A / D converter 90 according to the first embodiment. The ΔΣ A / D converter 90 according to the first embodiment includes analog circuit sections (10, 20) and a digital circuit 30. The analog circuit section (10, 20) includes an integrating circuit 10 including an active element and an integrating circuit 20 configured with a passive circuit and not including an active element. The active element may be an operational amplifier or a semiconductor amplifier configured with discrete components. Hereinafter, the integrating circuit 10 will also be referred to as an active integrating circuit 10 or a first integrating circuit 10, and the integrating circuit 20 will also be referred to as a passive integrating circuit 20 or a second integrating circuit 20. First, the configuration of each of the above circuits 10 to 30 and the connections between the components that make up each circuit will be described.

[0012] Active integration circuit 10 is configured to time-integrate the sum of input signal Vin and a digital signal fed back to active integration circuit 10 from digital circuit 30. As shown in Fig. 1, active integration circuit 10 includes resistive elements 11 to 14, capacitors 15 and 16, and semiconductor amplifier 17. Semiconductor amplifier 17 is an operational amplifier having a non-inverting input terminal (+ terminal), an inverting input terminal (- terminal), and an output terminal.

[0013] The resistive element 11 is connected between a node to which an input signal Vin is input and the non-inverting input terminal of the semiconductor amplifier 17. The resistive element 12 is connected between a node 24 on the output side of a buffer element 33 (described later) and the non-inverting input terminal of the semiconductor amplifier 17. The capacitor 16 is connected between the non-inverting input terminal of the semiconductor amplifier 17 and ground GND. The resistive element 13 is connected between the inverting input terminal of the semiconductor amplifier 17 and ground GND. The resistive element 14 is connected between the inverting input terminal of the semiconductor amplifier 17 and a node to which a reference voltage Vref is supplied. The capacitor 15 is connected between the inverting input terminal and output terminal of the semiconductor amplifier 17.

[0014] The passive integrator circuit 20 is configured to time-integrate the sum of the output signal of the active integrator circuit 10 and a digital signal fed back to the passive integrator circuit 20 from the digital circuit 30. As shown in Figure 1, the passive integrator circuit 20 includes resistive elements 21 and 22 and a capacitor 23. The resistive element 22 and the capacitor 23 are connected in series, in this order, between a node 24 on the output side of the buffer element 33 and ground GND. The resistive element 21 is connected between the output terminal of the semiconductor amplifier 17 of the active integrator circuit 10 and a connection node 25 of the resistive element 22 and the capacitor 23.

[0015] The digital circuit 30 compares the output voltage V5 of the passive integrator circuit 20 with the threshold voltage Vth at discrete time intervals (specifically, at each cycle of the clock signal CLK). The digital circuit 30 feeds back to the analog circuit units 10 and 20 a digital signal of "0" if the output voltage V5 is higher than the threshold voltage Vth, and "1" if the output voltage V5 is lower than the threshold voltage Vth. Note that the digital circuit 30 may be configured to feed back either "0" or "1" when the output voltage V5 and the threshold voltage Vth are equal. As shown in FIG. 1 , the digital circuit 30 includes a differential input buffer element 31, a D flip-flop 32, an inverted output buffer element 33, and a low-pass filter (LPF) 35.

[0016] The non-inverting input terminal of the buffer element 31 is connected to the connection node 25 of the passive integration circuit 20. A threshold voltage Vth is input to the inverting input terminal of the buffer element 31. The output signal of the buffer element 31 is input to the D terminal of the D flip-flop 32. The digital signal DS output from the Q terminal of the D flip-flop 32 is input to the low-pass filter 35 and also to the buffer element 33. A clock signal CLK is input to the clock terminal of the D flip-flop 32. The buffer element 33 outputs a signal obtained by inverting 0 / 1 of the input digital signal DS to one end of the resistor element 12 and one end of the resistor element 22.

[0017] In this disclosure, the buffer elements 31, 33 and the D flip-flop 32 are collectively referred to as the signal generation circuit 34. The signal generation circuit 34 generates a digital signal DS according to the input signal Vin, and outputs a signal obtained by inverting the 0 / 1 of the digital signal DS as a feedback signal to the active integration circuit 10 and the passive integration circuit 20. The active integration circuit 10, the passive integration circuit 20, and the signal generation circuit 34 constitute a so-called ΔΣ modulator 91.

[0018] The low-pass filter 35 removes quantization noise that has been shifted to the high-frequency region by the noise shaping function of the ΔΣ modulator 91. As a result, a highly accurate digital signal Dout proportional to the analog input signal Vin is output from the ΔΣ A / D converter 90. Instead of using a low-pass filter, processing such as counting the proportion of 0s or 1s in the digital signal DS output from the signal generation circuit 34 may be performed.

[0019] The digital circuit 30 can be configured using individual semiconductor elements, or can be configured using a programmable logic device or a microprocessor. In particular, FPGAs (Field Programmable Gate Arrays), which are a type of programmable logic device, often include differential input buffers and are suitable for highly integrated implementation of multiple A / D conversion circuits and other digital circuits.

[0020] 1, if the reference voltage Vref and the power supply voltage of the buffer element 33 are set equal, this becomes the reference voltage of the A / D converter. Also, if the threshold voltage Vth is set to 1 / 2 of the reference voltage Vref, the circuit operation becomes symmetrical, which is preferable.

[0021] [Operation of the ΔΣ A / D Converter] Next, a description will be given of the operation of the above-mentioned ΔΣ A / D converter 90. Fig. 2 is a functional block diagram of a second-order ΔΣ modulator 300 corresponding to the ΔΣ A / D converter 90 of Fig. 1.

[0022] 2, the ΔΣ modulator 300 includes integrators 310 and 320, adders 311 and 321, a 1-bit quantizer 331, a delay device 332, a buffer element 333 for inverted output, and a 1-bit digital-to-analog converter (DAC) 334. If the buffer element 333 for inverted output is not provided immediately after the delay device 332, it is necessary to provide a subtractor in place of each of the adders 311 and 321. This embodiment is characterized in that the provision of the buffer element 333 allows the use of an adder instead of a subtractor.

[0023] To briefly explain the operation of FIG. 2 , the adder 311 adds the feedback signal V4 to the input signal Vin (input voltage V1). The integrator 310 time-integrates the result of the addition by the adder 311. The adder 321 adds the feedback signal V4 to a voltage V3 representing the integration result of the integrator 310. The integrator 320 time-integrates the result of the addition by the adder 321. The 1-bit quantizer 331 converts the voltage V5 representing the integration result of the integrator 320 into a binary digital signal by comparing it with a threshold voltage Vth. The delay element 332 generates a digital signal DS by delaying the output of the 1-bit quantizer 331 by one clock cycle. The buffer element 333 inverts the 0 / 1 of the digital signal DS output from the delay element 332. The digital-to-analog converter 334 converts the inverted digital signal output from the buffer element 333 into an analog signal to generate the feedback signal V4.

[0024] The functional blocks in Figure 2 correspond to the circuit in Figure 1 as follows. First, the adder 311 and integrator 310 in Figure 2 correspond to the active integration circuit 10 in Figure 1. The adder 321 and integrator 320 in Figure 2 correspond to the passive integration circuit 20 in Figure 1. The 1-bit quantizer 331 in Figure 2 corresponds to the differential input buffer element 31 in Figure 1. The delay element 332 in Figure 2 corresponds to the D flip-flop 32 in Figure 1. The buffer element 333 and digital-to-analog converter 334 in Figure 2 correspond to the buffer element 33 in Figure 1.

[0025] Note that the digital signal "0" is set to a low level and the digital signal "1" is set to a high level. This allows the negative feedback circuit required for the ΔΣ A / D converter 90 to be configured without a subtractor, and a simple passive integration circuit 20 can be used for the second-stage integrator 320. The digital signal "0" fed back from the digital circuit 30 may be set to a high level and "1" to a low level, but in that case the analog circuit units 10 and 20 will need to have a subtraction function.

[0026] The operation of the active integrator circuit 10 and the passive integrator circuit 20 shown in Figure 1 will now be described in detail. In the active integrator circuit 10, the resistance value of resistors 11 and 13 is Ri1, the resistance value of resistors 12 and 14 is Rf1, and the capacitance value of capacitors 15 and 16 is Ci1. If we assume that V2 = V4 - Vref (1), then the transfer function of the active integrator circuit 10 can be expressed as follows, based on the conditions of a virtual short of the operational amplifier formed by semiconductor amplifier 17 and zero input current: (V1 / Ri1 + V2 / Rf1) / (s Ci1) (2). In other words, the active integrator circuit 10 integrates the sum of a constant multiple of the input voltage V1 and a constant multiple of the feedback voltage V2.

[0027] When the input voltage V1 is in a steady DC state, the output of the active integrator circuit 10 is a constant value. In this case, the input to the active integrator circuit 10 is differentiated from the output to become 0, so the following holds: V1 / Ri1+V2 / Rf1=0 (3)

[0028] Using the above equation (3), it can be seen that the range of the input voltage V1 in the active integration circuit 10 can be set by the ratio of the gain resistors Ri1 and Rf1. For example, in FIG. 1, if the reference voltage Vref and the power supply voltage of the buffer element 33 are equal, the output voltage V4 of the buffer element 33 will be the reference voltage Vref or 0. Therefore, the voltage V2 expressed by the above equation (1) will be 0 or -Vref. By substituting the value of this voltage V2 into the above equation (3), the lower limit of the input voltage V1 becomes 0 V, and the upper limit of the input voltage V1 becomes Vref × Ri1 / Rf1.

[0029] As with a typical differential amplifier circuit, the offset voltage can be adjusted by changing the resistor connections, so the lower limit of the input voltage V1 is not limited to 0 V. For example, a negative voltage can also be input as the input voltage V1.

[0030] 1, the resistance value of resistor 21 is Ri2, the resistance value of resistor 22 is Rf2, and the capacitance value of capacitor 23 is Ci2. In this case, the transfer function of passive integrator circuit 20 is expressed as follows: (V3 / Ri2+V4 / Rf2) / (s·Ci2) (4) In other words, passive integrator circuit 20 integrates the sum of a constant multiple of output voltage V3 of active integrator circuit 10 and a constant multiple of feedback voltage V4.

[0031] However, because the passive integrator circuit 20 is an RC integrator, it can be considered an integrator only in the region where the change in its output voltage V5 is small. Therefore, the time constant of Rf2·Ci2 is set to be sufficiently longer than the delay time (i.e., the clock period) of the delay element 332. This keeps the voltage change of the capacitor 23 small, and realizes an integrator using only passive elements.

[0032] In the steady state, the output of the passive integrator circuit 20 is maintained at a constant value (i.e., the threshold voltage Vth). In this case, the input to the passive integrator circuit 20 is zero as the differential of the output, and therefore the following equation holds: (V3-Vth) / Ri2+(V4-Vth) / Rf2=0 (5)

[0033] Using equation (5) above, it can be seen that the range of input voltage V3 in passive integration circuit 20 can be set by the ratio of gain resistors Ri2 and Rf2. For example, in the circuit of FIG. 1, if reference voltage Vref and the power supply voltage of buffer element 33 are equal, output voltage V4 of buffer element 33 will be reference voltage Vref or 0. By substituting this voltage V4 into equation (4) above, the lower limit of input voltage V3 becomes Vth - (Vref - Vth) × Ri2 / Rf2, and the upper limit of input voltage V3 becomes Vth × (1 + Ri2 / Rf2). This allows the input range of passive integration circuit 20 to be set in accordance with the output characteristics of semiconductor amplifier 17 included in active integration circuit 10.

[0034] 1 outputs a digital signal DS whose ratio of 0 to 1 changes in response to the analog input signal Vin. Specifically, in the circuit configuration of Fig. 1, when the voltage V1 of the analog input signal Vin is equal to or lower than 0 V, the D flip-flop 32 always outputs 0, and the frequency of outputting 1 increases in proportion to the voltage V1 of the analog input signal Vin.

[0035] As described above, according to the first embodiment, the second-order ΔΣ A / D converter 90 can be configured using only one analog semiconductor amplifier as the active component of the analog circuit section. Therefore, a low-cost, high-precision A / D conversion circuit can be provided using general-purpose components.

[0036] Second Embodiment In a second embodiment, a ΔΣ A / D converter 92 will be described, which has improved reliability by adding a failure detection function to the ΔΣ A / D converter 90 of the first embodiment.

[0037] [Configuration of ΔΣ A / D Converter] Fig. 3 is a circuit diagram showing the configuration of a ΔΣ A / D converter 92 according to embodiment 2. The ΔΣ A / D converter 92 of Fig. 3 differs from the ΔΣ A / D converter 90 of Fig. 1 in that it further includes a second passive integrator circuit 20B, and the digital circuit 30 further includes a second signal generating circuit 34B and a deviation detecting circuit 36.

[0038] The second passive integrator circuit 20B has a configuration similar to that of the passive integrator circuit 20 described in Fig. 1, and is an integrator circuit formed of passive circuits and including no active elements. The second passive integrator circuit 20B is configured to time-integrate the sum of the input signal Vin and the digital signal (i.e., the feedback voltage V7) output from the second signal generating circuit 34B of the digital circuit 30. In the present disclosure, the second passive integrator circuit 20B is also referred to as a third integrator circuit.

[0039] More specifically, the second passive integration circuit 20B includes resistive elements 21B and 22B and a capacitor 23B. The resistive element 22B and the capacitor 23B are connected in series in this order between a node 24B on the output side of a buffer element 33B (described later) and ground GND. The resistive element 21B is connected between a node to which an input signal Vin is input and a connection node 25B between the resistive element 22B and the capacitor 23B.

[0040] The second signal generating circuit 34B of the digital circuit 30 compares the output voltage V6 of the second passive integrator circuit 20B with the threshold voltage Vth at discrete time intervals (specifically, at each cycle of the clock signal CLK). The second signal generating circuit 34B feeds back to the second passive integrator circuit 20B a digital signal (i.e., feedback voltage V7) that is "0" if the output voltage V6 is higher than the threshold voltage Vth and "1" if the output voltage V6 is equal to or lower than the threshold voltage Vth. Note that the digital circuit 30 may be configured to feed back either "0" or "1" when the output voltage V6 is equal to the threshold voltage Vth.

[0041] More specifically, the second signal generating circuit 34B, like the signal generating circuit 34 described in FIG. 1, includes a differential input buffer element 31B, a D flip-flop 32B, and an inverting output buffer element 33B. The non-inverting input terminal of the buffer element 31B is connected to the connection node 25B of the second passive integrator circuit 20B. A threshold voltage Vth is input to the inverting input terminal of the buffer element 31B. The output signal of the buffer element 31B is input to the D terminal of the D flip-flop 32B. A digital signal DSB output from the Q terminal of the D flip-flop 32B is input to the deviation detection circuit 36 ​​and also to the buffer element 33B. A clock signal CLK is input to the clock terminal of the D flip-flop 32B. The buffer element 33B outputs a signal (feedback voltage V7) obtained by inverting the input digital signal DSB to one end of the resistor element 22B.

[0042] Here, if the reference voltage Vref and the power supply voltage of the buffer element 33B are set equal, this voltage becomes the reference voltage of the first-order ΔΣ modulator 91B composed of the second passive integrator circuit 20B and the second signal generating circuit 34B. Furthermore, if the threshold voltage Vth is set to Vref / 2, the circuit operation becomes symmetrical, which is preferable.

[0043] The digital signal "0" is set to a low level, and the digital signal "1" is set to a high level. This allows the negative feedback circuit required for the first-order ΔΣ modulator 91B to be configured without a subtractor, making it possible to use a simple passive integrator circuit 20. The digital signal "0" fed back from the second signal generating circuit 34B of the digital circuit 30 may be set to a high level, and "1" to a low level, but in that case, the second passive integrator circuit 20B needs to have a subtraction function.

[0044] The deviation detection circuit 36 ​​receives the digital signal DS output by the D flip-flop 32 of the signal generation circuit 34 and the digital signal DSB output by the D flip-flop 32B of the second signal generation circuit 34B. The signal generation circuit 34 outputs an abnormality detection signal FS when the difference between the time average of the digital signal DS and the time average of the digital signal DSB becomes equal to or greater than a certain threshold value.

[0045] 3 can be configured using individual semiconductor elements, or can be configured using a programmable logic device or a microprocessor. In particular, FPGAs, which are a type of programmable logic device, often include differential input buffers and are suitable for highly integrated implementation of numerous A / D conversion circuits and other digital circuits.

[0046] Other configurations in FIG. 3 are similar to those in FIG. 1, so the same or corresponding parts are designated by the same reference numerals and description thereof will not be repeated.

[0047] [Operation of the ΔΣ A / D Converter] Next, the operation of the ΔΣ A / D converter 92 of Figure 3 will be described. First, the operation of the second-order ΔΣ modulator 91 configured by the active integrator circuit 10, the passive integrator circuit 20, and the signal generator circuit 34 of Figure 3 is the same as that described in the first embodiment, and therefore detailed description will not be repeated. The D flip-flop 32 of the signal generator circuit 34 outputs a digital signal DS whose 0 / 1 ratio changes depending on the analog input signal Vin. Specifically, in the circuit configuration of Figure 3, when the voltage V1 of the analog input signal Vin is 0 V or less, the D flip-flop 32 always outputs 0, and the frequency with which the D flip-flop 32 outputs 1 increases in proportion to the voltage V1 of the analog input signal Vin.

[0048] 3 and the second signal generating circuit 34B, which have been newly added, form a first-order ΔΣ modulator 91B. In the second passive integrating circuit 20B, the resistance value of the resistive element 21B is Ri3, the resistance value of the resistive element 22B is Rf3, and the capacitance value of the capacitor 23B is Ci3. In this case, the transfer function of the second passive integrating circuit 20B is expressed as follows: (V1 / Ri2+V7 / Rf2) / (s·Ci3) (6) That is, the second passive integrating circuit 20B integrates the sum of a constant multiple of the input voltage V1 and a constant multiple of the feedback voltage V7.

[0049] However, because the second passive integrator circuit 20B is an RC integrator, it can be considered an integrator only in the region where the change in its output voltage V6 is small. Therefore, the time constant of Rf3 and Ci3 is set to be sufficiently longer than the delay time (i.e., the clock period) of the delay element. This minimizes the voltage change of capacitor 23B, realizing an integrator using only passive elements.

[0050] In the steady state, the output of the second passive integrator circuit 20B is maintained at a constant value (i.e., the threshold voltage Vth). In this case, the input to the second passive integrator circuit 20B is zero as the differential of the output, and the following equation holds: (V1-Vth) / Ri3+(V7-Vth) / Rf3=0 (7)

[0051] Using equation (7) above, it can be seen that the range of input voltage V1 in second passive integrator circuit 20B can be set by the ratio of gain resistors Ri3 and Rf3. For example, in the circuit of FIG. 3, if reference voltage Vref and the power supply voltage of buffer element 33B are equal, output voltage V7 of buffer element 33B will be reference voltage Vref or 0. By substituting this voltage V7 into equation (7) above, the lower limit of input voltage V1 becomes Vth - (Vref - Vth) × Ri3 / Rf3, and the upper limit of input voltage V1 becomes Vth × (1 + Ri3 / Rf3). Therefore, the input range of second passive integrator circuit 20B can be set to match the input range of active integrator circuit 10 by the ratio of gain resistors Ri3 and Rf3.

[0052] The D flip-flop 32B of the second signal generating circuit 34B outputs a digital signal DSB whose ratio of 0 to 1 changes according to the input signal Vin. Specifically, in the circuit configuration of Fig. 3, when the voltage of the analog input signal Vin is equal to or lower than Vth-(Vref-Vth) x Ri3 / Rf3, the D flip-flop 32B always outputs 0, and the frequency with which the D flip-flop 32B outputs 1 increases in proportion to the voltage of the analog input signal Vin.

[0053] The first ΔΣ modulator 91, which is composed of the active integrator circuit 10, the passive integrator circuit 20, and the signal generator circuit 34, and the second ΔΣ modulator 91B, which is composed of the second passive integrator circuit 20B and the second signal generator circuit 34B, are designed so that the time average values ​​of the digital signals DS and DSB output for the same input signal Vin are equal. Therefore, the input ranges are also designed to be equal. Although it is possible to design them with different input ranges, in that case the deviation detection circuit 36 ​​corrects either the time average of the digital signal DS output from the D flip-flop 32 or the time average of the digital signal DSB output from the D flip-flop 32B using a linear function. This ensures that the time averages of the corrected digital signals DS and DSB for the same input signal Vin are equal to each other.

[0054] As described above, the deviation detection circuit 36 ​​outputs the abnormality detection signal FS when the difference between the time average of the digital signal DS output by the D flip-flop 32 and the time average of the digital signal DSB output by the D flip-flop 32B becomes equal to or greater than a certain threshold. As a result, when the first ΔΣ modulator 91 fails, the difference between the time averages of the digital signals DS and DSB becomes equal to or greater than the threshold and the abnormality detection signal FS is output, allowing the downstream control circuit to recognize that the A / D conversion result is unreliable.

[0055] As described above, according to the second embodiment, the second-order ΔΣ A / D converter 92 with a fault detection function can be configured using only one analog semiconductor amplifier 17 as the active component of the analog circuit section. Therefore, it is possible to provide a low-cost, highly accurate, and highly reliable A / D conversion circuit using general-purpose components.

[0056] Embodiment 3 In embodiment 3, an A / D conversion system 93 including a plurality of ΔΣ A / D converters 92 according to embodiment 2 will be described. If an operating ΔΣ A / D converter fails, the A / D conversion system 93 can switch to another ΔΣ A / D converter. Furthermore, an example will be described in which the A / D conversion system 93 is applied to a digital control device 201 that controls a power conversion circuit 60.

[0057] [Configuration of A / D Conversion System] Figure 4 is a circuit diagram showing an example configuration of an A / D conversion system 93 according to embodiment 3. The A / D conversion system 93 of embodiment 3 includes multiple ΔΣ A / D converters with a configuration similar to that of the ΔΣ A / D converter 92 of Figure 3. Each ΔΣ A / D converter receives a common input signal Vin. A standby redundant system is configured by including multiple A / D converters with the same configuration. Hereinafter, the operating ΔΣ A / D converter will be referred to as the main converter.

[0058] 4 includes, as an example, a first ΔΣ A / D converter 94 and a second ΔΣ A / D converter 194. The digital circuit 30 of the first ΔΣ A / D converter 94 further includes a selection circuit 37 and a buffer element 41, and the digital circuit of the second ΔΣ A / D converter 194 further includes a selection circuit 137 and a buffer element 141. The selection circuit 37 of the first ΔΣ A / D converter 94 and the selection circuit 137 of the second ΔΣ A / D converter 194 are connected to each other via a communication path 50. In the present disclosure, the selection circuit 37 is also referred to as a first selection circuit, and the selection circuit 137 is also referred to as a second selection circuit.

[0059] The selection circuit 37 receives the abnormality detection signal FS from the deviation detection circuit 36. When the first ΔΣ A / D converter 94 is operating as the main converter, the selection circuit 37 of the first ΔΣ A / D converter 94 sends a signal indicating normal operation to the selection circuit 137 of the second ΔΣ A / D converter 194. The selection circuit 37 stops sending the signal indicating normal operation when a power supply abnormality occurs, a clock abnormality occurs, or when the selection circuit 37 receives the abnormality detection signal FS from the deviation detection circuit 36. This allows the selection circuit 37 to notify the selection circuit 137 of an abnormality in the first ΔΣ A / D converter 94.

[0060] The selection circuit 137 of the standby second ΔΣ A / D converter 194 monitors the normal operation signal output from the selection circuit 37 of the first ΔΣ A / D converter 94, which is the main converter. The selection circuit 137 has the function of switching the output of the digital signal resulting from A / D conversion from another converter to its own converter in the event of an abnormality where the normal operation signal cannot be received. In the case of FIG. 4 , the selection circuit 37 of the currently operating first ΔΣ A / D converter 94 disables the output from the buffer element 41, and the selection circuit 137 of the currently standby second ΔΣ A / D converter 194 enables the output from the buffer element 141. While FIG. 4 shows an example in which the selection circuits 37 and 137 operate the output enable signals of the buffer elements 41 and 141, a switching circuit such as a multiplexer or a selector may be provided instead of the buffer elements 41 and 141.

[0061] The normal operation signal output from the selection circuit 37, 137 may be a pulse signal or a serial communication signal instead of a level signal. If a level signal is used, it becomes impossible to distinguish between normal operation and an abnormal state when a failure occurs in a communication circuit element or communication path and the signal becomes stuck (i.e., when the signal no longer changes from a value indicating normal). In contrast, if a pulse signal or a serial communication signal is used as the normal operation signal, it becomes impossible to receive a correct signal when the signal becomes stuck, making it possible to determine that an abnormal state has occurred. Furthermore, using a serial communication signal is even more preferable because it allows other information to be superimposed on it.

[0062] [Configuration of Digitally Controlled Power Supply and Digital Control Device] FIG. 5 is a circuit diagram showing the configuration of a digital control device 201 and a digitally controlled power supply 200 that utilize the A / D conversion system 93 of FIG.

[0063] 5, the digitally controlled power supply 200 includes a power conversion circuit 60 and a digital control device 201 for controlling the power conversion circuit 60. The digital control device 201 further includes a digital controller 42 in the digital circuit 30 of each ΔΣ A / D converter constituting the A / D conversion system 93 of FIG. 4. The digital controller 42 is a feedback controller that performs PWM (Pulse Width Modulation) by feedback control based on the A / D conversion result. Buffer elements 41, 141 are provided downstream of the digital controller 42.

[0064] 5, the digital controller 42 includes a subtractor 43, a compensator 44, a comparator 45, and a carrier oscillator 46. The operation of these components, including the low-pass filter 35, will now be briefly described.

[0065] The low-pass filter 35 generates a multi-bit digital value Dout from the ΔΣ modulated 1-bit digital signal DS. The subtractor 43 compares the digital value Dout with the output command value OCV to determine the deviation between them. The compensator 44 multiplies the deviation determined by the subtractor 43 by an appropriate transfer function to calculate the duty as the manipulated variable. The comparator 45 compares the carrier wave generated by the carrier wave oscillator 46 with the manipulated variable to generate a PWM signal. When the output of the buffer element 41 is enabled by the selection circuit 37, the buffer element 41 outputs the PWM signal generated by the comparator 45 to the downstream power conversion circuit 60.

[0066] Although FIG. 5 shows a general configuration for performing PWM by feedback control, other configurations having similar functions are possible, and the configuration is not limited to that shown in FIG.

[0067] The power conversion circuit 60 controls the voltage and / or current by controlling the ON / OFF of the power semiconductor element 62. A feedback loop is formed by returning the output voltage or output current of the power conversion circuit 60 as an input signal Vin to the A / D conversion system. This makes it possible to configure a switching regulator (digitally controlled power supply 200) that outputs a desired voltage or current through digital control.

[0068] 5 shows a typical step-down chopper (i.e., buck converter) circuit as an example of the power conversion circuit 60. Specifically, the power conversion circuit 60 in FIG. 5 includes a buffer element 61, a power semiconductor element 62, a diode 63, an inductor 64, an input capacitor 65, and an output capacitor 66.

[0069] As shown in Figure 5, a power semiconductor element 62 and an inductor 64 are connected, in this order, between a power supply node that receives a DC voltage Vdc and an output node that outputs an output voltage Vout. The cathode of a diode 63 is connected to a connection node 67 between the power semiconductor element 62 and the inductor 64, and the cathode of the diode 63 is connected to ground GND. A PWM signal is input to the gate of the power semiconductor element 62 via a buffer element 61. An input capacitor 65 is connected between the power supply node and ground GND. An output capacitor 66 is connected between the output node and ground GND. The output voltage Vout is fed back to the digital control device 201 as an input signal Vin.

[0070] The power conversion circuit 60 is not limited to the step-down chopper shown in FIG. 5, and any power conversion circuit 60 can be used in combination with the digital control device 201.

[0071] [Effects and Modifications of Embodiment 3] As described above, according to Embodiment 3, reliability can be further improved by constructing a redundant A / D conversion system 93 including a plurality of the ΔΣ A / D converters 92 of Embodiment 2. Furthermore, the A / D conversion system 93 of Embodiment 3 can be applied to the digital control device 201 and the digital control power supply 200.

[0072] The configurations of the first to third embodiments are merely examples, and the present invention is not limited to these, and any combination including existing known techniques can be used. For example, a digitally controlled power supply can be configured by combining the ΔΣ A / D converter 90 of the first embodiment with the digital controller 42 and power conversion circuit 60 of FIG.

[0073] Furthermore, when configuring a highly reliable system, there is the concept of a single point of failure. A single point of failure refers to an element that will cause the entire system to lose its functionality if it fails at one location. By employing the ΔΣ A / D converter 92 of embodiment 2 or the A / D conversion system 93 of embodiment 3 for signal paths that will become single points of failure, and employing the ΔΣ A / D converter 90 of embodiment 1 for signal paths that will not become single points of failure, it is possible to realize a system that ensures overall fault tolerance at the lowest possible cost.

[0074] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0075] 10 Active integrator circuit (first integrator circuit), 11 to 14, 21, 21B, 22, 22B, R1 Resistor element, 15, 16, 23, 23B, C1 Capacitor, 17 Analog semiconductor amplifier, 20 Passive integrator circuit (second integrator circuit), 20B Second passive integrator circuit (third integrator circuit), 30 Digital circuit, 31, 31B Differential input buffer element, 33, 33B Inverting output buffer element, 32, 32B D flip-flop, 34 Signal generation circuit, 34B Second signal generation circuit, 35 Low-pass filter, 36 Deviation detection circuit, 37, 137 Selection circuit, 42 Digital controller (feedback controller), 43 Subtractor, 44 Compensator, 45 Comparator, 46 Carrier oscillator, 50 Communication path, 60 Power conversion circuit, 62 Power semiconductor element, 63 Diode, 64 Inductor, 65 Input capacitor, 66 Output capacitor, 90, 92 ΔΣ A / D converter, 91 First ΔΣ modulator, 91B Second ΔΣ modulator, 93 A / D conversion system, 94 First ΔΣ A / D converter, 194 Second ΔΣ A / D converter, 200 Digital control power supply, 201 Digital control device, 300 ΔΣ modulator, 310, 320 Integrator, 311, 321 Adder, 331 1-bit quantizer, 332 Delay, 333 Output inversion buffer element, 334 Digital / analog converter, CLK Clock signal, DS, DSB, Dout Digital signal, FS Abnormality detection signal, GND Ground, OCV Output command value, V2, V4, V7 Feedback voltage, V3, V6 Output voltage, Vref Reference voltage, Vth Threshold voltage.

Claims

1. An analog-to-digital converter comprising: a first integrating circuit including an active element that integrates over time the sum of an analog input signal and a first feedback signal; a second integrating circuit not including an active element that integrates over time the sum of the integration result of the first integrating circuit and the first feedback signal; and a first signal generating circuit that compares a first output voltage representing the integration result of the second integrating circuit with a threshold voltage at discrete time intervals, and generates a first digital signal that is 1 if the first output voltage is higher than the threshold voltage, and generates a first digital signal that is 0 if the first output voltage is lower than the threshold voltage, wherein the first signal generating circuit outputs a signal that is the inverse of the 1s and 0s of the first digital signal as the first feedback signal.

2. The analog-to-digital converter according to claim 1, further comprising: a third integrating circuit, not including any active element, that time-integrates the sum of the analog input signal and a second feedback signal; and a second signal generating circuit that compares a second output voltage representing the integration result of the third integrating circuit with the threshold voltage at discrete time intervals, and generates a second digital signal of 1 if the second output voltage is higher than the threshold voltage, and generates a second digital signal of 0 if the second output voltage is lower than the threshold voltage; wherein the second signal generating circuit outputs a signal obtained by inverting the 1s and 0s of the second digital signal as the second feedback signal; and wherein the analog-to-digital converter further comprises a deviation detecting circuit that outputs an abnormality detection signal when a deviation between the time average of the first digital signal and the time average of the second digital signal is equal to or greater than a threshold.

3. An analog / digital conversion system comprising: a first converter and a second converter having the analog / digital converter configuration of claim 2; a first selection circuit that selects whether or not to output the first digital signal, which is the result of A / D conversion of the analog input signal by the first converter, to the outside; and a second selection circuit that selects whether or not to output the first digital signal, which is the result of A / D conversion of the analog input signal by the second converter, to the outside, wherein if the abnormality detection signal is output from the deviation detection circuit of the first converter while the first digital signal is being output from the first converter to the outside, the first selection circuit stops the output of the first digital signal from the first converter and notifies the second selection circuit to output the first digital signal from the second converter.

4. An analog / digital conversion system comprising: a first converter having the configuration of the analog / digital converter described in claim 2; and a second converter including the first integrating circuit, the second integrating circuit, and the first signal generating circuit, but not the third integrating circuit, the second signal generating circuit, or the deviation detecting circuit, wherein the first converter is provided in a signal path that is a single point of failure, and the second converter is provided in a signal path that is not a single point of failure.

5. The analog-to-digital converter of claim 2, wherein at least a portion of the digital circuitry including the first signal generating circuit, the second signal generating circuit, and the deviation detecting circuit is implemented using a programmable logic device or a microprocessor.

6. A digital control device comprising: an analog / digital converter according to claim 2; and a feedback controller that generates an operation signal based on the deviation between the first digital signal and an output command value.

7. A digitally controlled power supply comprising: the digital control device according to claim 6; and a power conversion circuit including a semiconductor switch element controlled by the operation signal, wherein the voltage or current output from the power conversion circuit is used as the analog input signal.

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