Universal Memory for In-Memory Computing

Abstract

To provide a memory device having a high retention property where weights are retained for inference calculation, and an operation method of the same.SOLUTION: A universal memory cell 400 of a universal memory device includes a write transistor 410 and a read transistor 420 coupled to the write transistor 410. The write transistor has a gate terminal 412, a first terminal 414, and a second terminal 416. The read transistor includes a gate terminal 422, a charge trap layer 423, a first terminal 424, and a second terminal 426. The charge trap layer is configured to be unalterable when a first write voltage is applied at the first terminal of the write transistor, and be alterable when a second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure is directed to memory, for example for in-memory computing. [Background technology]

[0002] The operation of the artificial intelligence (AI) model includes a training mode and an inference mode. In the training mode, the memory needs to be repeatedly programmed and erased to change the weights, so a memory with high endurance is desirable. In the inference mode, the memory needs to retain the weights for the inference calculations, so a memory with high retention is desirable. Summary of the Invention

[0003] The present disclosure describes methods, circuits, devices, systems, and techniques for, e.g., in-memory computing, to provide a universal memory, where the universal memory can be configured to operate in both a dynamic random access memory (DRAM)-like mode with high endurance for AI training and a non-volatile memory (NVM)-like mode with high retention for AI inference.

[0004] One aspect of the disclosure features a semiconductor circuit including a first transistor and a second transistor. The first transistor has a gate terminal configured to receive a gate voltage to switch the first transistor on or off, a first terminal configured to receive a write voltage, and a second terminal coupled to the gate terminal of the second transistor. The second transistor has a charge trapping layer at the gate terminal of the second transistor. The charge trapping layer is configured to be: immutable when a first write voltage is applied at the first terminal of the first transistor; and mutable when a second write voltage is applied at the first terminal of the first transistor to modify a threshold voltage of the second transistor, the second write voltage being greater than the first write voltage.

[0005] In some implementations, the second write voltage is high enough to achieve Fowler-Nordheim tunneling and hot carrier injection in the charge trapping layer of the second transistor.

[0006] In some implementations, one of the first terminal and the second terminal is a drain terminal, and the other of the first terminal and the second terminal is a source terminal.

[0007] In some implementations, the semiconductor circuit is configured to: operate in a first mode, where an accumulation potential of a accumulation node between the second terminal of the first transistor and the gate terminal of the second transistor is determined based on the first write voltage applied at the first terminal of the first transistor while the first transistor is switched on, the threshold voltage of the second transistor remains unchanged, and the accumulation potential of the accumulation node is repeatedly alterable based on the first write voltage; and operate in a second mode, where the second transistor is programmed or erased to have a particular threshold voltage based on a second write voltage applied at the first terminal of the first transistor while the first transistor is switched on, and the particular threshold voltage is adjustable based on the second write voltage.

[0008] In some implementations, the first mode includes a training mode or a dynamic random access memory (DRAM)-like mode of an artificial intelligence (AI) model, and the second mode includes an inference mode or a non-volatile memory (NVM)-like mode of the AI ​​model.

[0009] In some implementations, the storage potential of the storage node corresponds to an adjustable weight in the first mode, and the particular threshold voltage of the second transistor corresponds to a fixed weight in the second mode.

[0010] In some implementations, the particular threshold voltage of the second transistor corresponds to a binary weight "1" or "0" in the second mode.

[0011] In some implementations, the particular threshold voltage of the second transistor corresponds to an analog weight in the second mode, and the particular threshold voltage is adjustable between a minimum threshold voltage and a maximum threshold voltage.

[0012] In some implementations, the second transistor is configured to operate in a saturation region, the storage potential of the storage node in the second mode being greater than a saturation voltage associated with the second transistor, and the second transistor is configured to receive a binary input signal at the first terminal of the second transistor, the binary input signal representing a "1" when the binary input signal has a voltage greater than a difference between the storage potential of the storage node and the minimum threshold voltage, and representing a "0" when the binary input signal has a voltage equal to 0V.

[0013] In some implementations, the second transistor is configured to operate in the triode region, the storage potential of the storage node in the second mode is less than a saturation voltage associated with the second transistor, and the second transistor is configured to receive an analog input signal at the first terminal of the second transistor, the analog input signal having a voltage in the range between 0V and a voltage difference between the storage potential and the maximum threshold voltage of the storage node.

[0014] In some implementations, the second transistor comprises a silicon-oxide-nitride-oxide-silicon (SONOS) transistor and the first transistor comprises a metal-oxide-semiconductor (MOS) transistor or a SONOS transistor.

[0015] Another aspect of the disclosure features a semiconductor circuit including a first transistor and a second transistor, the first transistor having a gate terminal configured to receive a gate voltage to switch the first transistor on or off, a first terminal configured to receive a write voltage, and a second terminal coupled to the gate terminal of the second transistor. The semiconductor circuit may be configured to: operate in a first mode, where an accumulation potential of an accumulation node between the second terminal of the first transistor and the gate terminal of the second transistor is determined based on the first write voltage applied at the first terminal of the first transistor while the first transistor is switched on, the threshold voltage of the second transistor remains unchanged, and the accumulation potential of the accumulation node is repeatedly alterable based on the first write voltage; and operate in a second mode, where the second transistor is programmed or erased to have a particular threshold voltage based on a second write voltage applied at the first terminal of the first transistor while the first transistor is switched on, and the particular threshold voltage is adjustable based on the second write voltage.

[0016] Another aspect of the disclosure features a semiconductor device including a plurality of memory cells, at least one of which includes a write transistor and a read transistor. The write transistor has a gate terminal configured to receive a gate voltage to switch the write transistor on or off, a first terminal configured to receive a write voltage, and a second terminal coupled to the gate terminal of the read transistor. The read transistor has a charge trapping layer at the gate terminal of the read transistor, the charge trapping layer configured to: be immutable when a first write voltage is applied at the first terminal of the write transistor; and be mutable when a second write voltage is applied at the first terminal of the write transistor to modify a threshold voltage of the read transistor, the second write voltage being greater than the first write voltage.

[0017] Another aspect of the disclosure features a semiconductor device that includes an array of memory cells; one or more write word lines (WWL); one or more write bit lines (WBL); one or more read word lines (RWL); and one or more read bit lines (RBL). Each memory cell of the array of memory cells includes: a write transistor and a read transistor. The write transistor includes a gate terminal coupled to a corresponding write word line, a first terminal coupled to a corresponding write bit line, and a second terminal coupled to the gate terminal of the read transistor, and the read transistor includes a first terminal coupled to a corresponding read bit line and a second terminal coupled to a corresponding read word line. The read transistor includes a charge trap layer at the gate terminal of the read transistor. The charge trap layer is configured to be: immutable when a first write voltage through the corresponding write bit line is applied at the first terminal of the write transistor; and alterable when a second write voltage through the corresponding write bit line is applied at the first terminal of the write transistor to alter a threshold voltage of the read transistor, the second write voltage being greater than the first write voltage.

[0018] In some implementations, the array of memory cells is arranged in an area defined by a first direction and a second direction perpendicular to the first direction, each of the one or more write word lines is coupled to a gate terminal of a write transistor of a first memory cell along the first direction, each of the one or more write bit lines is coupled to a first terminal of a write transistor of a second memory cell along the second direction, each of the one or more read bit lines is coupled to a first terminal of a read transistor of a third memory cell along the first direction, and each of the one or more read word lines is coupled to a second terminal of a read transistor of a fourth memory cell along the second direction.

[0019] In some implementations, the memory cell is configured to: operate in a first mode, where an accumulation potential of a accumulation node between the second terminal of the write transistor and the gate terminal of the read transistor is determined based on the first write voltage applied at the first terminal of the write transistor while the write transistor is switched on by a gate voltage applied at the gate terminal of the write transistor, the threshold voltage of the read transistor remains unchanged, and the accumulation potential of the accumulation node is repeatedly alterable based on the first write voltage; and operate in a second mode, where the read transistor is programmed or erased to have a particular threshold voltage based on a second write voltage applied at the first terminal of the write transistor while the write transistor is switched on, and the particular threshold voltage is adjustable based on the second write voltage.

[0020] In some implementations, the first mode includes a training mode or a dynamic random access memory (DRAM)-like mode of an artificial intelligence (AI) model, and the second mode includes an inference mode or a non-volatile memory (NVM)-like mode of the AI ​​model.

[0021] In some implementations, the semiconductor device is configured to function as a DRAM in a first mode and as an NVM in a second mode.

[0022] In some implementations, the storage potentials of the storage nodes correspond to adjustable weights in the training mode, and the particular threshold voltages of the readout transistors correspond to fixed weights in the inference mode.

[0023] In some implementations, the particular threshold voltage of the readout transistor corresponds to a binary weight "1" or "0" in the inference mode.

[0024] In some implementations, the particular threshold voltage of the readout transistor corresponds to an analog weight in the inference mode, and the particular threshold voltage is adjustable between a minimum threshold voltage and a maximum threshold voltage.

[0025] In some implementations, the analog weight is related to the difference between the storage potential and the particular threshold voltage of the storage node.

[0026] In some implementations, the readout transistor is configured to operate in a saturation region, and the storage potential of the storage node in the inference mode is greater than a saturation voltage associated with the readout transistor. The readout transistor is configured to receive a binary input signal at the first terminal of the readout transistor through a corresponding read bit line, the binary input signal representing a "1" when the binary input signal has a voltage greater than a difference between the storage potential of the storage node and the minimum threshold voltage, and representing a "0" when the binary input signal has a voltage equal to 0V.

[0027] In some implementations, the readout transistor is configured to operate in the triode region, and the storage potential of the storage node in the inference mode is less than a saturation voltage associated with the readout transistor. The readout transistor is configured to receive an analog input signal at the first terminal of the readout transistor through a corresponding read bit line, the analog input signal having a voltage in the range between 0V and a voltage difference between the storage potential and the maximum threshold voltage of the storage node.

[0028] In some implementations, the semiconductor device is configured to perform a multiply-accumulate (MAC) operation using the array of memory cells. The semiconductor device further comprises a sense amplifier coupled to a corresponding read word line that is coupled to a second terminal of a read transistor of a corresponding memory cell. The sense amplifier is configured to receive a sum current I from the corresponding read word line, the sum current I being:

number

[0029] In some implementations, the read transistor comprises a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, and in some implementations, the write transistor comprises a metal-oxide-semiconductor (MOS) transistor or a SONOS transistor.

[0030] Another aspect of the disclosure features a method of operating a universal memory for in-memory computing (IMC), the method of operation including: executing a training mode of an artificial intelligence (AI) model in the universal memory, where the universal memory comprises at least one memory cell having a write transistor and a read transistor, the write transistor having a gate terminal configured to receive a gate voltage to switch the write transistor on or off, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the read transistor, and during the training mode, a storage potential of a storage node between the second terminal of the write transistor and the gate terminal of the read transistor is increased by the write transistor to the gate terminal of the read transistor, the storage potential of a storage node between the second terminal of the write transistor and the gate terminal of the read transistor being increased by the write transistor to the gate terminal of the read transistor, the storage potential of a storage node ... a threshold voltage of the read transistor is determined based on the first write voltage applied at the first terminal of the write transistor while the write transistor is switched on by a gate voltage applied at the gate terminal of the write transistor, the threshold voltage of the read transistor remains unchanged and the storage potential of the storage node is repeatedly alterable based on the first write voltage; and executing an inference mode of the AI ​​model in the universal memory, where in the inference mode the read transistor is programmed or erased to have a particular threshold voltage based on a second write voltage applied at the first terminal of the write transistor while the write transistor is switched on, the particular threshold voltage being adjustable based on the second write voltage.

[0031] In some implementations, the training mode includes a weight change procedure, a weight hold procedure, and a read operation procedure, and the inference mode includes a weight change procedure, a weight hold procedure, and a read operation procedure.

[0032] In some implementations, the storage potentials of the storage nodes correspond to adjustable weights in the training mode, and the particular threshold voltages of the readout transistors correspond to fixed weights in the inference mode.

[0033] In some implementations, the particular threshold voltage of the readout transistor corresponds to a binary weight "1" or "0" in the inference mode.

[0034] In some implementations, the particular threshold voltage of the readout transistor corresponds to an analog weight in the inference mode, and the particular threshold voltage is adjustable between a minimum threshold voltage and a maximum threshold voltage.

[0035] In some implementations, the analog weight is related to the difference between the storage potential and the particular threshold voltage of the storage node.

[0036] In some implementations, executing the inference mode of the AI ​​model in the universal memory includes: operating the readout transistor in a saturation region, where the storage potential of the storage node in the inference mode is greater than a saturation voltage associated with the readout transistor; and receiving a binary input signal at the first terminal of the readout transistor, where the binary input signal represents a "1" when the binary input signal has a voltage greater than a difference between the storage potential of the storage node and the minimum threshold voltage, and represents a "0" when the binary input signal has a voltage equal to 0V.

[0037] In some implementations, executing the inference mode of the AI ​​model in the universal memory includes: operating the readout transistor in a triode region, where the storage potential of the storage node in the inference mode is less than a saturation voltage associated with the readout transistor; and receiving an analog input signal at the first terminal of the readout transistor, where the analog input signal has a voltage in the range between 0V and a voltage difference between the storage potential of the storage node and the maximum threshold voltage.

[0038] In some implementations, the method of operation includes: performing a multiply-accumulate (MAC) operation of the AI ​​model in the universal memory, the MAC operation being performed separately in a training mode and an inference mode. The performing the MAC operation includes: generating a sum current I from corresponding read word lines serially coupled to a set of memory cells, the sum current I being:

number

[0039] The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0040] [Figure 1A] FIG. 1 illustrates an example of an artificial neural network (ANN). [Figure 1B]An example of an exploded view of a neuron in an ANN is shown.

[0041] [Diagram 2] FIG. 2 illustrates an example memory for performing multiply-accumulate (MAC) operations.

[0042] [Figure 3A] FIG. 1 illustrates an example system for implementing a training mode.

[0043] [Figure 3B] FIG. 1 illustrates an example system for implementing inference mode.

[0044] [Figure 4] FIG. 1 is a diagram showing an example of a universal memory cell.

[0045] [Figure 5A] FIG. 1 illustrates an example universal memory.

[0046] [Figure 5B] FIG. 5B illustrates an implementation of a MAC operation using the universal memory of FIG. 5A.

[0047] [Figure 6] 1 is a flowchart of an example process for operating a universal memory.

[0048] [Figure 7A] FIG. 11 is a characteristic curve diagram of a write transistor in a training mode or a DRAM mode.

[0049] [Figure 7B] FIG. 11 is a characteristic curve diagram of a read transistor in a training mode or a DRAM mode.

[0050] [Figure 8A] FIG. 11 is a characteristic curve diagram of a write transistor in inference mode or NVM mode.

[0051] [Figure 8B] FIG. 13 illustrates a series of characteristic curves of a read transistor in inference mode or NVM mode.

[0052] [Figure 9] FIG. 2 illustrates the relationship between the current and voltage on a read bit line.

[0053] [Figure 10A] 1A-1C illustrate an exemplary operation of a read transistor in the saturation region.

[0054] [Figure 10B] 1A-1C illustrate an example operation of a read transistor in the triode region.

[0055] Like reference numbers and designations in the various drawings indicate like elements. It should also be understood that the various exemplary implementations shown in the figures are illustrative representations only and are not necessarily drawn to scale. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] Implementations of the present disclosure provide methods, circuits, devices, systems, and techniques for providing a universal memory for in-memory computing. In some implementations, the universal memory is configured to operate in both a dynamic random access memory (DRAM)-like mode with high endurance and a non-volatile memory (NVM)-like mode with high non-volatility and high retention. That is, the universal memory can integrate the functions of different types of memory, including a memory with high reliability (e.g., DRAM) and a memory with high retention (e.g., NVM). The universal memory can be applied for in-memory computing (IMC) that enables massively parallel dot products while keeping one set of operands in memory. For example, the universal memory can be configured for computationally demanding artificial intelligence (AI) applications, such as deep neural networks (DNN) and recurrent neural networks (RNN).

[0057] The universal memory can be configured to perform both AI training and AI inference, for example, in multiply-accumulate (MAC) or multiply-add (MAD) operations. All operations can be performed in the universal memory, and no data is transmitted between different memories or computing resources (e.g., computing processing units (CPUs) or processors) and data memories, which reduces or eliminates the von Neumann bottleneck problem, substantially reducing latency and substantially lowering energy dissipation or power consumption, improving processing speed and efficiency, and simplifying the system for AI applications, thereby improving the overall performance of the system for AI applications.

[0058] In some implementations, the universal memory includes an array of memory cells. Each memory cell can be a universal memory cell configured to perform DRAM-like operations such as training in AI computations and NVM functions such as inference in analog mode. The universal memory can have high endurance (e.g., nearly infinite endurance) to meet very large weight updates during training on big data, and can also have non-volatility and high retention to hold the weights in a fixed state with low power consumption.

[0059] The universal memory can be configured to perform dual mode operation in a two-transistor (2T) charge trap memory cell. In some implementations, the universal memory cell includes a write transistor and a read transistor. The write transistor is coupled to a write word line (WWL) and a write bit line (WBL), while the read transistor is coupled to a read word line (RWL) and a read bit line (RBL). The read transistor can be a charge trap transistor (CTT) including a charge trap layer with charge storage capability. In some examples, the read transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) field effect transistor (FET), where the nitride layer is the charge trap layer. The write transistor can be a transistor with charge storage capability, such as a SONOS FET, or a transistor without charge storage capability, such as a metal-oxide semiconductor field effect transistor (MOSFET).

[0060] In some implementations, under the DRAM-like mode, the write transistor is switched on by the write voltage in the WWL to charge or discharge the gate node (or storage node) of the read transistor with the write voltage in the WBL, and the logic state of the memory cell depends on the amount of charge stored at the gate node of the read transistor, which depends on the write voltage in the WBL to the write transistor. The storage mode of the memory cell can be at least partially similar to that of a DRAM memory cell. Because the write voltage in the WBL is low, the charge trap layer is not programmed / erased. Thus, the read transistor can have high endurance, and the memory cell operating in the DRAM-like mode can be used for in-memory computing in AI training.

[0061] In some implementations, under NVM mode, Fowler-Nordheim tunneling and hot carrier injection mechanisms (+FN / -FN) can be used to change the amount of charge in the charge trap layer of the read transistor. Therefore, the read transistor can be programmed / erased (e.g., using +FN / -FN with high voltage) to have a multi-level threshold voltage Vt with non-volatile capability, e.g., Vt can be adjustable. Various Vt levels can be used to determine the logic state of the memory cell. The memory cell operating in NVM mode can be used in in-memory computing for AI inference, where Vt can be used as a fixed weight. The read transistor can operate in both triode and saturation regions. The write bit line (WBL) read voltage can be constant at the same level under the condition of adjustable Vt for the read transistor.

[0062] The logic state in the universal memory cell operating in DRAM mode can be determined by accumulating charge at the sense node of the memory cell for short-term storage (e.g., with retention less than 10^4 seconds) with low voltage operation (e.g., less than 3V). Therefore, the universal memory cell can function like a DRAM memory cell. Compared with a conventional DRAM memory cell with a one transistor one capacitor (1T1C) structure, the universal memory cell has a two transistor zero capacitor (2T0C) structure, which has a more compact structure, a simpler manufacturing process, and can be cost-effective. The logic state can be stored by FN programming / erasing in the read transistor (and / or write transistor) for NVM operation. Furthermore, the universal memory cell can be applied to AI model training by in-memory computing (IMC) in DRAM mode and inference by IMC in NVM mode with fixed weights. The Vt value in the read transistor (and / or write transistor) can serve as a weight for MAC operation, which can be realized in a memory array of the universal memory cell by Ohm's law and Kirchhoff's law.

[0063] In some implementations, the universal memory cell has an analog IV curve or characteristic at the read transistor, which allows analog operations (e.g., analog training or inference) at the universal memory cell. Analog training or inference can be more efficient than binary training or inference. In some cases, the universal memory cell has an analog weight Vt and a binary input (the voltage V at the read bit line for the read transistor). RBL , and the read transistor operates in the saturation region. In some cases, the universal memory cell is configured for operation with an analog weight Vt and an analog input V RBL, with the readout transistor operating in the triode region.

[0064] These techniques can be applied to any suitable charge trapping based memory device, for example, silicon-oxide-nitride-oxide-silicon (SONOS) memory devices. These techniques can be applied to two-dimensional (2D) memory devices or three-dimensional (3D) memory devices. These techniques can be applied to various memory types, such as SLC (single level cell) devices, bi-level cell devices, TLC (triple level cell) devices, QLC (quad level cell) devices, or MLC (multi-level cell) devices, such as PLC (penta-level cell) devices.

[0065] These techniques can be applied to various types of storage systems, such as storage class memories (SCM), various types of memory devices, such as storage systems based on static random access memories (SRAM), dynamic random access memories (DRAM), resistive random access memories (ReRAM), magnetoresistive random access memories (MRAM), or phase change memories (PCM), among others. Additionally or alternatively, these techniques can be applied to systems based on, for example, NAND flash memories or NOR flash memories, such as universal flash storage (UFS), peripheral component interconnect express (PCIe) storage, embedded multimedia card (eMMC) storage, storage on dual in-line memory modules (DIMM), among others. These techniques can also be applied to magnetic or optical disks, among others. These techniques can be applied to any suitable application, such as applications using AI mechanisms, such as ANNs for deep learning. These applications can include, among others, gaming, natural language processing, expert systems, vision systems, speech recognition, handwriting recognition, intelligent robots, data centers, cloud computing services, and automotive applications.

[0066] 1A and 1B respectively show an example of an artificial neural network (ANN) 100 and an exploded view of a neuron N6 of the ANN 100. As shown in FIG. 1A, the ANN 100 is a collection of connected units or nodes, e.g., N0, N1, N2, N3, N4, N5, N6, N7, and N8, which are called artificial neurons. The artificial neurons are organized in layers. For example, layer L0 includes artificial neurons N0, N1, and N2; layer L1 includes artificial neurons N3, N4, N5, and N6; and layer L2 includes artificial neurons N7 and N8.

[0067] In some implementations, different layers of the ANN perform different types of transformations on their inputs. One of the layers is the first or input layer of the ANN, e.g., layer L0, while another layer is the last or output layer of the ANN, e.g., layer L2. The ANN includes one or more internal layers between the input layer and the output layer, e.g., layer L1. From the input layer, a signal proceeds to the output layer after traversing the internal layers one or more times.

[0068] In some implementations, each connection between artificial neurons, for example, the connection from N2 to N6 or the connection from N6 to N8, can send a signal to each other. The artificial neuron that receives the signal can process it and then signal the artificial neuron connected to it. In some implementations, the signals at the connections between artificial neurons are real, and the output of each artificial neuron is calculated by a nonlinear function of the sum of its inputs. Each connection can have a weight that adjusts as learning progresses. The weight increases or decreases the strength of the signal at the connection.

[0069] In some implementations, a set of input data (e.g., from each sample) is presented to the ANN at an input layer, e.g., L0. A series of calculations is performed at each subsequent layer, e.g., L1. In the fully connected network shown in FIG. 1A, the output calculations from each node are presented to all nodes in the subsequent layers. The final layer, e.g., L2, of the trained ANN may be associated with determining classification matches to the input data, e.g., from a fixed set of labeled candidates, which may be referred to as "supervised learning."

[0070] 1B shows an exploded view of the computations performed in artificial neuron N6, an example of an artificial neuron in an ANN. Input signals x0, x1, x2 from other artificial neurons of the ANN 100, e.g., artificial neurons N0, N1, and N2, respectively, are sent to artificial neuron N6. Each input signal is weighted by a weight associated with the corresponding connection, and the weighted signals are received and processed by the artificial neuron. For example, the connection from artificial neuron N0 to artificial neuron N6 has a weight w0 that weights the signal x0 sent from N0 to N6 via that connection, such that the value of the signal received and processed by N6 is w0x0. Similarly, the connections from artificial neurons N1 and N2 to artificial neuron N6 have weights w1 and w2, respectively, such that the values ​​of the signals received by N6 from N1 and N2 are w1x1 and w2x2, respectively.

[0071] An artificial neuron processes the weighted input signals internally, for example by modifying its internal state (called activation) according to the input, and generates an output signal depending on the input and activation. For example, artificial neuron N6 generates an output signal that is the result of an output function f applied to a weighted combination of the input signals received by artificial neuron N6. In this way, the artificial neurons of ANN 100 form a weighted directed graph that connects the outputs of some neurons to the inputs of other neurons. In some implementations, the weights, activation functions, output functions, or any combination of these parameters of an artificial neuron can be modified by a learning process, for example deep learning.

[0072] In some implementations, the calculation is a multiply-accumulate (MAC) calculation, which may be an action in an AI operation. As shown in FIG. 1B, for each data value x of the multiple input signals, i is its associated weight w i Then, it is multiplied by Σ i w i x i The final bias value b is added to the calculated value z = (Σ i w i x i +b) may be obtained. The calculated value z may then be passed through an activation function f to obtain the output value a=f(Σ i w i x i +b) is obtained. The output value a can be provided as a node output (or output signal) to the next layer as an input.

[0073] An AI model, for example, the ANN 100, can operate in a training mode and an inference mode. In order for the AI ​​model to provide an answer to a problem, the connection between the answer and the problem can be addressed by repeatedly performing network training. In the training mode, the AI ​​model is first given a set of test data with a correct answer label, known as training data. Then, the inferences of the AI ​​model generated by the set of test data are monitored, to which the AI ​​model may respond correctly or incorrectly. The goal of the learning method is to detect patterns, and what the AI ​​model does in this case is to explore and group data according to their similarity. The AI ​​training mode can be similar to training in multimedia data processing. Mathematically, in the training mode, the weights in the AI ​​model are adjusted to obtain a maximized output. In the inference mode, the AI ​​model puts into practice based on what the AI ​​model has learned in training. The AI ​​model can create an inference model using the training weights and the fixed weights to classify, solve, and / or answer problems.

[0074] FIG. 2 illustrates an example memory 200 for performing multiply-accumulate calculations (MAC). The memory 200 can be a universal memory as described in this disclosure, for example, the universal memory in FIG. 5A-5B. The memory 200 includes, for example, a number of memory cells 210, 220, 230, 240. The memory cells can include, for example, universal memory cells as described in more detail in FIG. 4A-4B. The memory cells 210, 220, 230, 240 include, for example, resistors 211, 221, 231, 241, respectively. The resistors 211, 221, 231, 241 have conductances G1, G2, G3, G4, respectively.

[0075] When voltages V1, V2, V3, and V4 are input to bit line BL2, a plurality of respective read currents I1, I2, I3, and I4 flow through word line WL2. Read current I1 is equal to the product of voltage V1 and conductance G1; read current I2 is equal to the product of voltage V2 and conductance G2; read current I3 is equal to the product of voltage V3 and conductance G3; and read current I4 is equal to the product of voltage V4 and conductance G4. The total current I is equal to the sum of the products of voltages V1, V2, V3, and V4 and conductances G1, G2, G3, and G4. When voltages V1, V2, V3, and V4 are input to input signal x i and the conductances G1, G2, G3, and G4 have weights w i , the total current I is expressed as the input signal x i and weight w i Represents the sum of products of:

number

[0076] 3A illustrates an example system 300 for implementing the training mode. The system 300 includes a plurality of memory cells 320 arranged, for example, in a matrix. ijThe system 300 further comprises a plurality of digital-to-analog converters (DACs) 302, each coupled to a respective bit line 303 (e.g., bit line BL2 in FIG. 2). Each DAC 302 is configured to convert an input digital signal, e.g., a voltage such as V1, V2, V3, V4 in FIG. 2, into an analog voltage signal. The system 300 may also comprise a plurality of sample and hold (SH) units 304, each coupled to a respective word line 305 (e.g., word line WL2 in FIG. 2), and an analog-to-digital converter (ADC) 306 coupled to the plurality of SH units 304. Each SH unit 304 may have one or more logic units and / or circuits configured to sample and hold a summed current analog signal (e.g., I in FIG. 2) along the respective word line 305, and the ADC 306 may be configured to sum the summed current analog signals from each word line 305 and convert the final summation result from the analog signal into a digital signal for further processing.

[0077] Memory cell 320 ij Each of the adjustable registers 322 may be, for example, ij The adjustable resistor 322 may have ij Each of these has a conductance G ij , for example, G1 211, G2 221, G3 231, or G4 241 in FIG. ij is the weight w ij For example, as shown in FIG. i When the memory 310 is in training mode, the weights w ij must be continually updated, so the adjustable register 322 ij The memory 310 having the above-mentioned durability can be used to smoothly execute the training mode. Therefore, it is desirable to have the memory 310 having the nearly infinite durability to meet the very large weight updates during training of the big data for AI training.

[0078] 3B illustrates an example system 350 for implementing the inference mode. System 350 is similar to system 300 and includes a DAC 302, a S&H unit 304, and an ADC 306. Unlike system 300 of FIG. 3A, system 350 includes a memory 360 that is different from memory 310. Memory 360 may include, for example, a number of memory cells 370 arranged in a matrix. ij The memory cell 370 ij Each of the resistors 372 ij For example, this may be achieved by adjusting the adjustable resistor 322. ij The memory cell 320ij has a fixed resistor 322. ij Each of these has a fixed conductance G ij These conductances G ij is the fixed weight w ij In the process of running the inference mode, the weights w ij is already set, and for example, the trained G in Figure 3A ij Since it has not been arbitrarily changed based on the fixed resistor 372 ij A memory 360 having volatile and good retention can be used to smoothly run the inference mode. Therefore, it is desirable to have a memory 360 with non-volatility and good retention to keep the weights in a fixed state with low power consumption for AI inference.

[0079] As explained above, the requirements for the training and inference modes are different. For example, the memory 310 for running the training mode may store the weights w ij The memory 360 that runs the inference mode must be highly durable to satisfy the large number of update actions for the weights w ij These two types of memories are usually completely different. For example, memory 310 in FIG. 3A and memory 360 in FIG. 3B use completely different resistors (adjustable resistor 322 and adjustable resistor 330). ij and fixed resistor 372 ij ) to use the

[0080] As described in further detail below, implementations of the present disclosure provide a universal memory configured to operate in both a dynamic random access memory (DRAM)-like mode with high endurance and a non-volatile memory (NVM)-like mode with high non-volatility and high retention. That is, the universal memory can integrate the functions of different types of memory, including a memory with high reliability and a memory with high retention. The universal memory can be applied for in-memory computing (IMC). In-memory computing can also be referred to as computing in memory, in-memory processing, or processing in-memory (PIM) or processing in memory (PIM).

[0081] In some implementations, the universal memory comprises a plurality of universal memory cells. As discussed in more detail below, each universal memory cell can be configured to have a first parameter (e.g., a voltage at a storage node) that can be adjustable for a training mode, and a second parameter (e.g., a threshold voltage of a read transistor) that can be fixed for an inference mode. The second parameter can be based on the first parameter.

[0082] 4 shows an example of a universal memory cell 400. The universal memory cell 400 can be used for in-memory computing (IMC). In some implementations, as shown in FIG. 4, the universal memory cell 400 includes a write transistor 410 and a read transistor 420 coupled to the write transistor 410. The universal memory cell 400 can also be called a 2T structure because it is composed of two transistors.

[0083] The write transistor 410 has a gate terminal 412, a first terminal 414, and a second terminal 416. One of the first terminal 414 and the second terminal 416 is a drain terminal, and the other of the first terminal 414 and the second terminal 416 is a source terminal. Similarly, the read transistor 420 has a gate terminal 422, a first terminal 424, and a second terminal 426. One of the first terminal 424 and the second terminal 426 is a drain terminal, and the other of the first terminal 424 and the second terminal 426 is a source terminal. The second terminal 416 of the write transistor 410 is coupled to a gate terminal 422 of the read transistor 420. A storage node (SN) 402 is coupled between the second terminal 416 and the gate terminal 422.

[0084] Unlike a typical memory cell having one transistor coupled to a write line and a bit line, the universal memory cell 400 has two transistors coupled to two write lines and two bit lines. For example, as shown in FIG. 4, the gate terminal 412 of the write transistor 410 is coupled to a write word line (WWL) and has a gate voltage V WWL A first terminal 414 of the write transistor 410 is coupled to a write bit line (WBL) and configured to receive a write voltage (or read voltage) V WBL A first terminal 424 of the read transistor 420 is coupled to a read bit line (RBL) and is configured to receive a read voltage V RBL A second terminal 426 of the read transistor 420 is coupled to a read word line (RWL) and configured to receive a write voltage (or read voltage) V RWL is configured to receive

[0085] The read transistor 420 can be configured to have an adjustable threshold voltage so that the universal memory cell 400 can be used to set a fixed weight in the inference mode at any time. In some implementations, the read transistor 420 has a charge trap layer 423 at the gate terminal 422. The charge trap layer 423 can be referred to as a charge storage layer or a charge trapping layer. According to the Fowler-Nordheim (FN) tunneling and hot carrier injection mechanism, when a high voltage (e.g., a positive voltage such as +FN or a negative voltage such as -FN) is applied at the gate terminal 422, the high voltage (e.g., +FN / -FN) can change the amount of charge stored in the charge trap layer 423, thereby changing the threshold voltage of the read transistor 420. The threshold voltage of the read transistor 420 can be changed based on the value of the applied high voltage and the duration of applying the high voltage on the gate terminal 422. That is, the threshold voltage of the read transistor 420 is set to a minimum threshold voltage V (e.g., as shown in FIG. 8B ). tmin to the highest threshold voltage V tmax As discussed below, with the charge trapping layer 423, the read transistor 420 can be programmed or erased to have different Vt levels to determine the corresponding logic gate and / or set different fixed weights (e.g., digital weights or analog weights).

[0086] In some implementations, the read transistor 420 includes a silicon-oxide-nitride-oxide-silicon (SONOS) field effect transistor (FET), where a nitride layer (e.g., a silicon nitride SiN layer) is a charge trapping layer 423. In some implementations, the write transistor 410 is a transistor that does not have charge storage capability, such as a metal oxide semiconductor field effect transistor (MOSFET). That is, the threshold voltage of the write transistor 410 is fixed and / or predetermined and cannot be changed. In some implementations, the write transistor 410 also includes a charge trapping layer 413, for example as shown in FIG. 4, and the threshold voltage of the write transistor 410 can be adjusted based on the operation. The write transistor 410 can also be a SONOS FET transistor.

[0087] The read transistor 420 can have a low off-current to ensure good data retention. In some examples, the channel layer of the read transistor 420 can include indium gallium zinc oxide (IGZO), indium oxide (In2O3), silicon (Si), germanium (Ge), or a III-V material. In some examples, the write transistor 410 has a high on-current to ensure read accuracy. The channel layer of the write transistor 410 can include indium gallium zinc oxide (IGZO), indium oxide (In2O3), silicon (Si), germanium (Ge), or a III-V material.

[0088] Figure 5A illustrates an example universal memory 500 comprising an array of universal memory cells 400 of Figure 4. Each universal memory cell 400 comprises a write transistor 410 and a read transistor 420 coupled to each other. The universal memory 500 comprises one or more write word lines WWL 512, one or more read word lines RWL 522, one or more write bit lines WBL 514, and one or more read bit lines RBL 524.

[0089] For each universal memory cell 400, the gate terminal 412 of the write transistor 410 is connected to a corresponding write word line WWL 512, the first terminal 414 (one of the drain and source terminals) of the write transistor 410 is connected to a corresponding write bit line WBL 514, and the second terminal 416 (the other of the drain and source terminals) of the write transistor 410 is connected to a gate terminal 422 of the read transistor 420. The first terminal 424 (one of the drain and source terminals of the read transistor 420) is connected to a corresponding read bit line 524, and the second terminal 426 (the other of the drain and source terminals of the read transistor 420) is connected to a read word line RWL 522.

[0090] Each write word line WWL 512 is connected to a plurality of gate terminals 412 of the write transistors 410 of the corresponding universal memory cells 400 along a first direction, and each write bit line WBL 514 is connected to a plurality of first terminals 414 of the write transistors 410 of the corresponding universal memory cells 400 along a second direction that may be perpendicular to the first direction. Similarly, each read bit line RBL 524 is connected to a plurality of first terminals 424 of the read transistors 420 of the corresponding universal memory cells 400 along a first direction parallel to the write word line 512, and each read word line RWL 522 is connected to a plurality of second terminals 426 of the read transistors 420 of the corresponding universal memory cells 400 along a second direction parallel to the write bit line 514.

[0091] In some implementations, the universal memory 500 includes a plurality of sense amplifiers (SAs) 502. Each SA 502 is coupled to a corresponding RWL 522 and configured to receive a sum of read currents from memory cells coupled to the corresponding RWL 522, for example as shown in FIG.

[0092] In some implementations, the universal memory 500 is applicable to both training and inference modes of an artificial intelligence (AI) model. When the universal memory 500 is executed in the training mode, it can provide high reliability similar to or the same as a dynamic random access memory (DRAM) to satisfy a large number of update actions on the weights. The universal memory 500 in the training mode can be implemented as the memory 310 of FIG. 3A. When the universal memory 500 is executed in the inference mode, it can provide non-volatility and high retention similar to or the same as a non-volatile memory (NVM) to allow the weights to be well retained with low power consumption. The universal memory 500 in the inference mode can be implemented as the memory 360 of FIG. 3B.

[0093] The universal memory 500 can be applied to realize one or more operations of an AI model, such as a multiply-accumulate (MAC) operation. The MAC operation is based on Ohm's law and Kirchhoff's law. Figure 5B shows an implementation of the MAC operation using the universal memory 500. Given a set of input signals x i , e.g., V1, V2, ..., Vn are applied on corresponding read bit lines RBL1, RBL2, ..., RBLn, respectively. The amount of read current Ii from each universal memory cell 400 (e.g., 0 or 1) is determined by the input signal x i and weight w i (e.g., 0 or 1). Accordingly, for each read word line 522, the total current I received by the SA 502 can be calculated based on equation (1) above:

number

[0094] As discussed below, the weights w of the universal memory cells 400 ican be digital or binary weights, e.g., "1" or "0". In some cases, the weights w i is the storage potential V at the storage node SN402 between the write transistor 410 and the read transistor 420 in a training mode or a DRAM mode, for example as described in FIGS. 7A-7B. SN In some cases, the weight w of the universal memory cell 400 is represented by i can be represented by the threshold voltage of the read transistor 420 in inference mode or NVM mode, for example, as illustrated in FIGS. 8A-8B.

[0095] Weight w of universal memory cell 400 i can be analog weights represented by, for example, an adjustable threshold voltage of the read transistor 420, for example, in an inference mode or an NVM mode as illustrated in Figures 10A-10B. In some cases, the universal memory cell 400 can operate with analog weights and a binary (1 or 0) input signal in the saturation region, for example, as illustrated in Figure 10A. In some cases, the universal memory cell 400 can operate with analog weights and an analog input signal in the triode region, for example, as illustrated in Figure 10B.

[0096] FIG. 6 is a flow chart of an example process 600 for operating a universal memory, for example, for training and inference of an artificial intelligence (AI) model. The universal memory may be the universal memory 500 of FIGS. 5A-5B. The universal memory comprises an array of universal memory cells (e.g., the universal memory cell 400 of FIG. 4). Each universal memory cell comprises a write transistor (e.g., the write transistor 410 of FIG. 4) and a read transistor (e.g., the read transistor 420 of FIG. 4). As described above, in the training mode 610, the universal memory (and the universal memory cells) are configured to operate in a DRAM mode or a DRAM-like mode; in the inference mode 620, the universal memory (and the universal memory cells) are configured to operate in an NVM mode or an NVM-like mode.

[0097] 6, the training mode 610 includes a weight change procedure 612, a weight hold procedure 614, and a read operation procedure 616. The weight change procedure 612 changes the weights w i (For example, the conductance G in Fig. 2 i or G in FIG. 3A ij ) is used to change the weights w i The read operation step 616 is used to temporarily store the weights w i In the training mode 610, the weight change procedure 612, the weight hold procedure 614, and the read operation procedure 616 read the weights w i can be run iteratively to optimize the AI ​​model by continually adjusting

[0098] 6, the inference mode 620 includes a weight setting procedure 622, a weight retention procedure 624, and a read operation procedure 626. The weight setting procedure 622 sets the fixed weights w based on the training mode 610. iThe weight maintenance procedure 624 is used to set the weights w i The read operation step 626 is used to hold the weights w i In inference mode 620, the weights w i is fixed and does not change frequently.

[0099] In the following, the operation of the write transistor and the read transistor of the universal memory cell of the universal memory in the training mode 610 (or DRAM mode) will be described with reference to Figures 7A-7B, respectively. For illustrative purposes, the universal memory, the universal memory cell, the write transistor, and the read transistor will be described with reference to the universal memory 500, the universal memory cell 400, the write transistor 410, and the read transistor 420, respectively.

[0100] 7A shows a characteristic curve diagram 700 of the write transistor 410 in the training mode 610 or DRAM mode. As shown in FIG. 7A, the lower voltage V G =V WWL When a higher gate voltage V is applied to the gate terminal 412 of the write transistor 410, the write transistor 410 can be switched off, for example, during the weight retention procedure 614 and the read operation procedure 616. G =V WWL When a voltage is applied to the gate terminal 412 of the write transistor 410, the write transistor 410 can be switched on, for example during a weight change procedure 612, and a voltage can be applied to the first terminal 414 of the write transistor 410 to charge or discharge a storage node SN402 coupled between the second terminal 416 of the write transistor 410 and the gate terminal 422 of the read transistor 420.

[0101] 7B shows a characteristic curve diagram 710 of the read transistor 420 in the training mode 610 or DRAM mode. In the training mode 610, the threshold voltage Vt of the read transistor 420 remains unchanged since the charge trap layer 423 of the read transistor 420 remains unchanged. The gate terminal 422 of the read transistor 420 is charged with a higher storage potential Vt that is higher than the threshold voltage Vt. SN The readout transistor 420 can be switched on when the gate terminal 422 of the readout transistor 420 has a lower storage potential V that is lower than the threshold voltage Vt. SN , the readout transistor 420 can be switched off.

[0102] In training mode 610, a high voltage signal (e.g., V RBL ) can be applied at the first terminal 424 of the readout transistor 420, and a low voltage (e.g., V ss ) or ground (e.g., 0) can be applied at the second terminal 426 of the read transistor 420. When the read transistor 420 is switched on, the logic state of the data stored in the storage node 402 can be read as a bit "1". When the read transistor 420 is switched off, the logic state of the data stored in the storage node 402 can be read as a bit "0". Therefore, in the training mode 610, the storage node 402 can be instantly charged or discharged to a higher or lower storage potential, which further determines the logic state of the read data, which can be used as a weight value of the universal memory cell 400. Moreover, the charge trap layer 423 of the read transistor 420 remains unchanged. Therefore, the universal memory cell 400 can have high endurance (e.g., nearly infinite endurance), which is suitable for training an AI model.

[0103] The operation of the universal memory cell 400 in the training mode 610 is to set the weights w iIn the training mode 610, the weights W i are stored in the storage node SN 402 between the write transistor 410 and the read transistor 420.

[0104] If the universal memory cell 400 changes the weight w of “0” during the weight change procedure 612 of the training mode 610, i When a write transistor 410 is to be written, the write word line WWL is driven to a higher voltage V WWL (e.g., 3V) is applied to the write bit line WBL, and a lower bias voltage V WBL0 (e.g., 0V) is applied to the write transistor 410. Since the write transistor 410 is switched on, the voltage V WBL can be input to the storage node SN402, which in turn provides the storage node SN402 with a storage potential V that is lower than the threshold voltage Vt of the read transistor 420. SN0 (e.g., 0 V). The storage potential V SN0 is the weight w of “0” of the universal memory cell 400 i can be represented as:

[0105] During a weight retention step 614 of the training mode 610, the memory cell 400 stores the weights w i It is intended to temporarily hold the lower voltage V WWL (e.g., 0V) is applied to the write word line WWL to switch off the write transistor 410. With the write transistor 410 switched off, the storage potential V SN0 remains unchanged.

[0106] During the read operation procedure 616 of the training mode 610, the weights w i If is to be read and then multiplied, the write word line WWL is driven to a lower voltage V to switch off the write transistor 410. WWL(e.g., 0V) is applied to the read bit line RBL, and an input voltage signal Vi (e.g., 0.8V) is applied to the read bit line RBL. i The corresponding stored potential V SN Since V is lower than the threshold voltage Vt of the read transistor 420, the read transistor 420 is switched off and no read current Ii is generated on the read bit line RBL. The amount of the read current Ii (e.g., 0) is determined by the input signal Vi and the weight w of "0". i is equivalent to the product of

[0107] When the universal memory cell 400 changes the weight w of “1” during the weight change procedure 612 of the training mode 610, i When a write transistor 410 is to be written, the write word line WWL is driven to a higher voltage V WWL (e.g., 3V) is applied to the write bit line WBL, and a high voltage V WBL (e.g., 1V) is applied to the write transistor 410. Since the write transistor 410 is switched on, the voltage V WBL can be input to the storage node SN402, which in turn provides the storage node SN402 with a storage potential V that is higher than the threshold voltage Vt of the read transistor 420. SN1 (e.g., 1 V). The storage potential V SN1 is the weight w of the "1" in the universal memory cell 400. i As mentioned above, in the weight change step 612 of the training mode 610, the weights w i is changed, the threshold voltage Vt of the read transistor 420 is not changed.

[0108] During a weight retention step 614 of the training mode 610, the memory cell 400 is intended to temporarily retain the weights wi during the training mode 610 and is driven at a lower voltage V WWL(e.g., 0V) is applied to the write word line WWL to switch off the write transistor 410. With the write transistor 410 switched off, the storage potential V SN1 remains unchanged.

[0109] During a read operation step 616 of the training mode 610, when the weights wi of the universal memory cells 400 are to be read and then multiplied, the write word line WWL is driven to a lower voltage V WWL (e.g., 0V) is applied to the read bit line RBL, and an input voltage signal Vi (e.g., 0.8V) is applied to the read bit line RBL. i The corresponding stored potential V SN Since V is greater than the threshold voltage Vt of the read transistor 420, the read transistor 420 is switched on and a read current Ii is generated on the read bit line RBL. The amount of the read current Ii (e.g., 0) is determined by the input signal Vi and the weight of "1" w i is equivalent to the product of

[0110] The above-mentioned operations of the universal memory cell 400 in the training mode 610 or the DRAM mode may be organized in the following Table I. Note that Table I is only an example of values ​​and is not intended to limit the present disclosure. Table I. Values ​​for DRAM Operation [Table 1]

[0111] The operation of the write and read transistors of the universal memory cells of the universal memory in the speculation mode 620 (or NVM mode) is described below with respect to Figures 8A-8B, respectively. For illustrative purposes, the universal memory, universal memory cell, write transistor, and read transistor are described with respect to the universal memory 500, the universal memory cell 400, the write transistor 410, and the read transistor 420, respectively.

[0112] In the inference mode 620 or NVM mode, a high voltage (e.g., +FN / -FN) can be applied on the gate terminal 422 of the read transistor 420 to charge or discharge the charge trap layer 423 of the read transistor 420, thereby changing the threshold voltage Vt of the read transistor 420. The threshold voltage Vt can be fixed, for example, for a long retention time, to set a specific weight value for the universal memory cell 400, which can be applied in the inference mode 620 for the AI ​​model. The weight value can be reconfigured by changing the threshold voltage Vt with a high voltage (e.g., +FN / -FN) applied on the gate terminal 422 of the read transistor 420, for example, based on the value of the high voltage and the duration of applying the high voltage.

[0113] 8A illustrates a characteristic curve diagram 800 of the write transistor 410 in the inference mode 620 or NVM mode. As shown in FIG. G =V WWL When a higher gate voltage V is applied to the gate terminal 412 of the write transistor 410, the write transistor 410 can be switched off. G =V WWLThe write transistor 410 can be switched on when a FN high voltage (e.g., +FN / -FN, such as +20V / -20V) is applied to the gate terminal 412 of the write transistor 410. During a weight setting procedure 622 of the inference mode 620, a FN high voltage (e.g., +FN / -FN, such as +20V / -20V) is applied to the first terminal 414 of the write transistor 410 such that the storage potential at the storage node SN402 can be charged or discharged to correspond to (e.g., be the same as) the high voltage (e.g., +FN / -FN). The voltage at the gate terminal 422 of the read transistor 420 is a voltage VFN high voltage (e.g., +FN / -FN, such as +20V / -20V) at the storage node SN402. SN Therefore, the FN high voltage can change the threshold voltage Vt of the read transistor 420. During a read operation procedure 626 of the inference mode 620, a read voltage Vread (e.g., 0.8V) is applied to the first terminal 414 of the write transistor 410, which can be used as an input signal for the universal memory cell 400, for example, as described in more detail in FIG.

[0114] FIG. 8B is a diagram 810 showing a series of characteristic curves of the read transistor 420 in the inference mode 620 or the NVM mode. Each characteristic curve corresponds to a threshold voltage Vt of the read transistor 420, for example, the characteristic curve shown in FIG. 710 of the read transistor 420. As described above, the threshold voltage Vt can be set by a high voltage (e.g., +FN / -FN) applied on the write bit line. The value of the threshold voltage Vt can be based on the amount of charge in the charge trap layer 423 of the read transistor 420 based on the value of the high voltage and the duration of applying the high voltage. Therefore, the value of the threshold voltage Vt can be adjustable, for example, between a minimum threshold voltage Vtmin and a maximum threshold voltage Vtmax as shown in FIG. 8B.

[0115] After the threshold voltage Vt is set during the weight setting procedure 622, a read voltage Vread (e.g., 0.8V) is applied to the first terminal 414 of the write transistor 410, which corresponds to a high storage potential V SNThe storage node SN 402 can be charged to a storage potential V SN When the storage potential V at the gate terminal 422 is higher than the set threshold voltage V of the read transistor 420, the read transistor 420 can be switched on and the supply voltage V applied at the first terminal 424 of the read transistor 420 can generate a higher current I corresponding to data "1". SN If the weight w of the universal memory cell 400 is lower than the set threshold voltage Vt, the read transistor 420 can be switched off, which corresponds to data "0". The read voltage Vread applied on the write bit line WBL can be between the minimum threshold voltage Vtmin and the maximum threshold voltage Vtmax. Therefore, in the inference mode 620, the weight w of the universal memory cell 400 can be switched off, which corresponds to data "0". i is represented by the set threshold voltage Vt of the read transistor 420.

[0116] The operation of the universal memory cell 400 in the inference mode 620 is described in more detail below with respect to the weights W of “0” and “1”. The read transistor 420 includes a charge trap layer 423 that can be charged or discharged to adjust the threshold voltage Vt of the read transistor 420.

[0117] If the universal memory cell 400 has a weight w of “0” during the weight setting step 622 of the inference mode 620, i When a write transistor 410 is to be written, the write word line WWL is driven with a voltage V higher than the threshold voltage of the write transistor 410 to switch the write transistor 410 on. ON (e.g., 1V) is applied to the write bit line WBL, and a positive high FN voltage (e.g., +FN) is applied to the write transistor 410. Since the write transistor 410 is switched on, the positive high FN voltage applied by the write bit line WBL can be applied to the storage node SN402, which in turn supplies the storage node SN402 with a high storage potential V SN0(e.g., +FN), which can charge the charge trap layer 423 of the read transistor 420, causing the threshold voltage Vt of the read transistor 420 to change, e.g., to a higher Vt. The higher Vt of the read transistor 420 causes the weight w of the universal memory cell 400 “0” to change. i can be represented as:

[0118] During a weight retention step 624 of the speculation mode 620, the memory cell 400 stores the weights w i The lower voltage V WWL (eg, 0V) is applied to the write word line WWL to switch the write transistor 410 off.

[0119] During the read operation step 626 of the inference mode 620, the weight w i If is to be read and then multiplied, the write word line WWL is driven to a voltage V higher than the threshold voltage of the write transistor 410 to switch the write transistor 410 on. on (e.g., 1V) is applied to the read bit line RBL, and an input voltage signal Vi (e.g., V DD ) is applied to the write bit line WBL. read (e.g., 1 V) is applied to the read transistor 420. Since the read transistor 420 is set to have a higher Vt, which may be higher than the read voltage Vread, the read transistor 420 is switched off and no read current Ii is generated on the read bit line RBL. The amount of the read current Ii (e.g., 0) is determined by the input signal Vi and the weight of "0" w i is equivalent to the product of

[0120] If the universal memory cell 400 assigns a weight w of “1” during the weight setting step 622 of the inference mode 620, iWhen a write transistor 410 is to be written, the write word line WWL is applied with a voltage Von higher than the threshold voltage of the write transistor 410 to switch on the write transistor 410, and the write bit line WBL is applied with a negative high FN voltage (e.g., −FN). Because the write transistor 410 is switched on, the negative high FN voltage input by the write bit line WBL can be input to the storage node SN402, which in turn can be driven to a negative high storage potential V SN1 (e.g., −FN), which can discharge the charge trap layer 423 of the read transistor 420, for example, to change the threshold voltage Vt of the read transistor 420, which is reduced to a lower Vt. The lower Vt of the read transistor 420 reduces the weight w of the “1” of the universal memory cell 400. i can be represented as:

[0121] During a weight retention step 624 of the speculation mode 620, the memory cell 400 stores the weights w i The lower voltage V WWL (eg, 0V) is applied to the write word line WWL to switch the write transistor 410 off.

[0122] During the read operation step 626 of the inference mode 620, the weight w i If is to be read and then multiplied, the write word line WWL is driven to a voltage V higher than the threshold voltage of the write transistor 410 to switch the write transistor 410 on. on (e.g., 1V) is applied to the read bit line RBL, and an input voltage signal Vi (e.g., V DD ) is applied to the write bit line WBL. read (for example, 1 V) is applied to the read transistor 420. readSince the read transistor 420 is set to have a lower Vt, which may be lower than Vt, the read transistor 420 is switched on and a read current Ii is generated on the read bit line RBL. The amount of the read current Ii is determined by the input signal Vi and the "1" weight w i is equivalent to the product of

[0123] The above-mentioned operation of the universal memory cell 400 in the inference mode 620 or NVM mode can be organized in the following Table II. Note that Table II shows only an example of values ​​and is not intended to limit the present disclosure. Note that the Vread applied on the write bit line is between the minimum threshold voltage Vtmin and the maximum threshold voltage Vtmax of the read transistor 420. Table II Values ​​for NVM Mode Operation [Table 2]

[0124] The universal memory 500 can be applied to realize one or more operations of the AI ​​model, such as a multiply-accumulate (MAC) operation. The MAC operation is based on Ohm's law and Kirchhoff's law. As shown in FIG. 5B, in the inference mode 620, a series of input voltages V1, V2, ... Vn are applied on corresponding read bit lines RBL1, RBL2, ..., RBLn, respectively. As described above, the weights w for each universal memory cell 400 are calculated. i is represented by the threshold voltage Vt of the read transistor 420 of the universal memory cell 400. The amount (e.g., 0 or 1) of the read current Ii from each universal memory cell 400 is represented by the input signal Vi and the weight w i (e.g., 0 or 1). Accordingly, for each read word line 522, the total current I received by the SA 502 can be calculated based on equation (1) above:

number

[0125] The weights mentioned above i is represented by taking the two-bit values ​​of "0" and "1" as an example. In some other implementations, the weight w i may be analog values. As discussed in more detail below, the read transistor 420 can operate in the triode region or the saturation region. The universal memory cell 400 can operate with analog weights and a binary (1 or 0) input signal, for example in the saturation region, or with analog weights and an analog input signal, for example in the triode region.

[0126] 9 shows a diagram 900 illustrating the relationship between the current and the voltage on the read bit line RBL. The current-voltage curves CVi correspond to different gate overdrive voltages Vd. The gate overdrive voltage Vd is proportional to the storage potential V of the read transistor 420. SN and the threshold voltage Vt. Different degrees of gate overdrive voltage Vd can be formed corresponding to different threshold voltages Vt. The upper curve CVi in FIG. 9 corresponds to a higher gate overdrive voltage Vd. The current formed on the read bit line RBL depends on the gate overdrive voltage Vd, e.g.

number

[0127] The current-voltage curve CVi represents the voltage at the gate terminal 422 of the readout transistor 420 (e.g., VSN ) and can be divided based on the relationship with the saturation voltage Vsat. For example, as described in FIG. 10A, when V SN >Vsat, the read transistor 420 operates in the saturation region, and the universal memory cell 400 can operate with the analog weight w i and a binary (1 or 0) input signal. For example, as described in FIG. 10B, when V SN <Vsat, the read transistor 420 operates in the triode region, and the universal memory cell 400 can operate with an analog weight and an analog input signal.

[0128] FIG. 10A shows an exemplary operation in the saturation region of the read transistor 420, as shown in the shaded part, for example, where V SN >Vsat. The threshold voltage Vt of the read transistor 420 can be analog, and the voltage V RBL is the input signal applied to the read bit line, which can have a bit value of "1" or "0". When the voltage V RBL corresponds to bit "0", for example 0V, no current is formed. When the voltage V RBL corresponds to bit "1", a current is formed and is proportional to (V SN -V t ). To ensure input "1", the voltage V RBL is greater than or equal to the maximum value of (V SN -V t ). Since V SN is the same as V WBL applied to the write bit line that can be held constant, the maximum value of (V SN -V t ) is equivalent to (V SN -Vtmin), where Vtmin is the minimum threshold voltage of the read transistor 420 in the saturation region, as shown in FIG. 10A, for example.

[0129] The operation of the universal memory cell 400 in inference mode 620 or NVM mode and the saturation region of the read transistor 420 can be organized in Table III below. Note that Table III shows only an example of values ​​and is not intended to limit the present disclosure. Table III. Values ​​for NVM mode operation in the saturation region [Table 3]

[0130] As Table III shows, during the set weight procedure 622 of the inference mode 620, for a Vt rise, the write transistor 410 is switched on and a voltage Von higher than the threshold voltage of the write transistor 410 is applied at the write word line WWL. In some cases, a positive high FN voltage (e.g., +FN) is applied on the write bit line, and a V RWL and V RBL are both equal to 0V, therefore the storage potential in SN 402 increases to a positive high FN voltage, which may charge the charge trap layer 423 of the read transistor 420 and increase the threshold voltage Vt of the read transistor 420. In some cases, a low voltage (e.g., 0) is applied on the write bit line (V WBL =0V), and V applied to the read word line RWL and the read bit line RBL. RWL and V RBL are both equal to -FN, and the potential between the gate terminal 422 and the second terminal 426 is +FN, which in turn can charge the charge trap layer 423 of the read transistor 420 and increase the threshold voltage Vt of the read transistor 420.

[0131] Similarly, during the weight setting procedure 622 of the inference mode 620, for a Vt drop, the write transistor 410 is switched on and a voltage Von higher than the threshold voltage of the write transistor 410 is applied at the write word line WWL. In some cases, a negative high FN voltage (e.g., −FN) is applied on the write bit line, and V RWL and V RBL are both equal to 0V, so the stored potential in the SN 402 is reduced to a negative high FN voltage (e.g., -FN), which can discharge the charge trap layer 423 of the read transistor 420 and reduce the threshold voltage Vt of the read transistor 420. In some cases, a low voltage (e.g., 0) is applied on the write bit line (V WBL =0V), and V applied to the read word line RWL and the read bit line RBL. RWL and V RBL are both equal to +FN, and the potential between the first terminal 424 and the gate terminal 422 is +FN, which in turn can discharge the charge trap layer 423 of the read transistor 420 and reduce the threshold voltage Vt of the read transistor 420.

[0132] During the weight retention step 624 of the inference mode 620, V WWL = 0V, and V WBL can be any value, for example 0V. RWL and V RBL can both be equal to 0V, therefore no current is formed and the analog threshold voltage Vt of the read transistor 420 remains unchanged and can be fixed for a long retention time to determine the specific weight value of the universal memory cell 400.

[0133] During a read operation step 626 of the inference mode 620, the write transistor 410 is switched on and a voltage Von, which is higher than the threshold voltage of the write transistor 410, is applied on the write word line WWL.WBL is applied at the write bit line WBL, which is the supply voltage V DD The second terminal 426 of the readout transistor 420 is coupled to ground, e.g., 0V, and the first terminal 424 of the readout transistor 420 is coupled to V dd -V tmin An input signal greater than V RBL is applied.

[0134] The universal memory 500 can be applied to realize one or more operations of the AI ​​model, such as a multiply-accumulate (MAC) operation. The MAC operation is based on Ohm's law and Kirchhoff's law. As shown in FIG. 5B, in the inference mode 620, a series of input voltages V1, V2, ... Vn are applied on corresponding read bit lines RBL1, RBL2, ..., RBLn, respectively. As described above, the weights w for each universal memory cell 400 are calculated. i is represented by the threshold voltage Vt of the read transistor 420 of the analog universal memory cell 400. The amount of read current Ii from each universal memory cell 400 is determined by the input signal Vi (e.g., 0 or 1) and the analog weight w i Accordingly, for each read word line 522, the total current I received by the SA 502 can be calculated based on equation (1) above:

number

[0135] FIG. 10B illustrates an example operation of the readout transistor 420 in the triode region, for example as shown in the shaded area, where V SNIt is Vsat. The threshold voltage Vt of the read transistor 420 can be analog, and various Vts can function as analog weights. The voltage V RBL is the input signal applied on the read bit line and satisfies the requirements for ensuring that the read transistor 420 is within the triode region. Therefore, V RBL can also be within the analog input range 0 <= V RBL <= V SN -V tmax for example, as shown in FIG. 10B.

[0136] The operation of the universal memory cell 400 in the inference mode 620 or the NVM mode and in the triode region of the read transistor 420 can be compiled in Table IV below. Note that Table IV only shows an example of values and is not intended to limit the present disclosure. Table IV Values for NVM Mode Operation in the Triode Region

Table 4

[0137] As shown in Table IV, during the weight setting procedure 622 of the inference mode 620, for the Vt increase, the write transistor 410 is switched on, and a voltage Von higher than the threshold voltage of the write transistor 410 is applied on the write word line WWL. In some cases, a positive high FN voltage (e.g., +FN) is applied on the write bit line, and V RWL and V RBL applied on the read word line RWL and the read bit line RBL are both the same as 0V. Therefore, the storage potential in the SN402 increases to the positive high FN voltage, whereby the charge trap layer 423 of the read transistor 420 is charged and the threshold voltage Vt of the read transistor 420 can be increased. In some cases, a low voltage (e.g., 0) is applied on the write bit line (V WBL = 0V), and V RWLand V RBL are both equal to -FN, and the potential between the gate terminal 422 and the second terminal 426 is +FN, which in turn can charge the charge trap layer 423 of the read transistor 420 and increase the threshold voltage Vt of the read transistor 420.

[0138] Similarly, during the weight setting procedure 622 of the inference mode 620, for a Vt drop, the write transistor 410 is switched on and a voltage Von higher than the threshold voltage of the write transistor 410 is applied at the write word line WWL. In some cases, a negative high FN voltage (e.g., −FN) is applied on the write bit line, and V RWL and V RBL are both equal to 0V, so the stored potential in the SN 402 is reduced to a negative high FN voltage (e.g., -FN), which can discharge the charge trap layer 423 of the read transistor 420 and reduce the threshold voltage Vt of the read transistor 420. In some cases, a low voltage (e.g., 0) is applied on the write bit line (V WBL =0V), and V applied to the read word line RWL and the read bit line RBL. RWL and V RBL are both equal to +FN, and the potential between the first terminal 424 and the gate terminal 422 is +FN, which in turn can discharge the charge trap layer 423 of the read transistor 420 and reduce the threshold voltage Vt of the read transistor 420.

[0139] During the weight retention step 624 of the inference mode 620, V WWL = 0V, and V WBL can be any value, for example 0V. RWL and V RBLcan both be equal to 0V, therefore no current is formed and the analog threshold voltage Vt of the read transistor 420 remains unchanged and can be fixed for a long retention time to determine the specific weight value of the universal memory cell 400.

[0140] During a read operation step 626 of the inference mode 620, the write transistor 410 is switched on and a voltage Von, which is higher than the threshold voltage of the write transistor 410, is applied on the write word line WWL. WBL is applied at the write bit line WBL, which is the supply voltage V DD The second terminal 426 of the readout transistor 420 is coupled to ground, e.g., 0V, and the first terminal 424 of the readout transistor 420 is coupled to V dd -V tmax An input signal V that is smaller than RBL is applied.

[0141] The universal memory 500 can be applied to realize one or more operations of the AI ​​model, such as a multiply-accumulate (MAC) operation. The MAC operation is based on Ohm's law and Kirchhoff's law. As shown in FIG. 5B, in the inference mode 620, a series of input voltages V1, V2, ... Vn are applied on corresponding read bit lines RBL1, RBL2, ..., RBLn, respectively. As described above, the weights w for each universal memory cell 400 are calculated. i is represented by the threshold voltage Vt of the read transistor 420 of the analog universal memory cell 400. The amount of read current Ii from each universal memory cell 400 is expressed by the analog input signal V i (For example, 0 and V dd -V tmax range) and analog weight w iAccordingly, for each read word line 522, the total current I received by the SA 502 can be calculated based on equation (1) above:

number

[0142] The disclosed and other examples may be implemented as one or more computer program products, e.g., one or more modules of computer program instructions encoded on a computer-readable medium for execution by or to control the operation of a data processing apparatus. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or one or more combinations thereof. The term "data processing apparatus" encompasses all apparatus, devices, and machines that process data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, an apparatus may include code that creates an execution environment for the computer program, e.g., code that constitutes a processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations of these.

[0143] A system may encompass all apparatus, devices, and machines that process data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, a system may include code that creates an execution environment for the computer program, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these.

[0144] A computer program (also known as a program, software, software application, script, or code) can be written in any type of programming language, including compiled or interpreted languages, and it can be deployed in any form, including a stand-alone program, or a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated files (e.g., files that store one or more modules, subprograms, or code portions). A computer program can be deployed for execution on one computer, or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0145] The processes and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The processes and logic flows may also be performed by, and apparatus may be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0146] Processors suitable for executing computer programs include, by way of example, both general purpose and special purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, a processor receives instructions and data from a read-only memory or a random access memory, or both. The essential elements of a computer may include a processor for executing instructions, and one or more memory devices for storing instructions and data. Typically, a computer may include one or more mass storage devices, such as magnetic disks, magneto-optical disks, or optical disks, for storing data, or may be operatively coupled to receive data from or transfer data to them, or both. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data may include all types of non-volatile memory, media, and memory devices, including, by way of example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices, and magnetic disks. The processor and memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0147] Although the specification may describe many specific examples, these should not be construed as limitations on the scope of the claimed invention or what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features described in the context of separate embodiments herein may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as operating in a particular combination, and even initially claimed as such, in some cases one or more features from a claimed combination may be deleted from the combination, and the claimed combination may be directed to a subcombination, or a variation of the subcombination. Similarly, although operations are shown in a particular order in the figures, this should not be understood as requiring that such operations be performed in the particular order or sequential order shown, or that all of the shown operations be performed, to achieve desired results.

[0148] Only a few examples and implementations are disclosed. Variations, modifications, and enhancements to the described examples and implementations and other implementations may be made based on what is disclosed.

Claims

1. a first transistor; and Second Transistor a first transistor having a gate terminal configured to receive a gate voltage to switch the first transistor on or off, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the second transistor; the second transistor having a charge trapping layer at the gate terminal of the second transistor, the charge trapping layer comprising: is immutable when a first write voltage is applied at the first terminal of the first transistor; A second write voltage is modifiable when applied at the first terminal of the first transistor to modify the threshold voltage of the second transistor. the second write voltage is greater than the first write voltage; During execution of a training mode of an artificial intelligence (AI) model in the semiconductor circuit, an accumulation potential of an accumulation node between the second terminal of the first transistor and the gate terminal of the second transistor is determined based on the first write voltage applied at the first terminal of the first transistor while the first transistor is switched on by the gate voltage applied to the gate terminal of the first transistor, the threshold voltage of the second transistor remains unchanged, and the accumulation potential of the accumulation node is repeatedly changeable based on the first write voltage; A semiconductor circuit, wherein while executing an inference mode of the AI ​​model in the semiconductor circuit, the second transistor is programmed or erased to have a particular threshold voltage based on the second write voltage applied at the first terminal of the first transistor while the first transistor is switched on, and the particular threshold voltage is adjustable based on the second write voltage.

2. 2. The semiconductor circuit of claim 1, wherein the training mode of the AI ​​model includes a dynamic random access memory (DRAM)-like mode, and the inference mode of the AI ​​model includes a non-volatile memory (NVM)-like mode.

3. 2. The semiconductor circuit of claim 1, wherein the storage potential of the storage node corresponds to an adjustable weight in the training mode of the AI ​​model, and the particular threshold voltage of the second transistor corresponds to a fixed weight in the inference mode of the AI ​​model.

4. 2. The semiconductor circuit of claim 1, wherein the particular threshold voltage of the second transistor corresponds to a binary weight "1" or "0" in the inference mode of the AI ​​model.

5. 2. The semiconductor circuit of claim 1, wherein the particular threshold voltage of the second transistor corresponds to an analog weight in the inference mode of the AI ​​model, and the particular threshold voltage is adjustable between a minimum threshold voltage and a maximum threshold voltage.

6. the second transistor is configured to operate in a saturation region, and the storage potential of the storage node in the inference mode of the AI ​​model is greater than a saturation voltage associated with the second transistor; 6. The semiconductor circuit of claim 5, wherein the second transistor is configured to receive a binary input signal at the first terminal of the second transistor, the binary input signal representing a "1" when the binary input signal has a voltage greater than a difference between the storage potential of the storage node and the minimum threshold voltage, and representing a "0" when the binary input signal has a voltage equal to 0V.

7. the second transistor is configured to operate in the triode region, and the storage potential of the storage node in the inference mode of the AI ​​model is less than a saturation voltage associated with the second transistor; 6. The semiconductor circuit of claim 5, wherein the second transistor is configured to receive an analog input signal at the first terminal of the second transistor, the analog input signal having a voltage in a range between 0V and a voltage difference between the storage potential and the maximum threshold voltage of the storage node.

8. the second transistor comprises a silicon-oxide-nitride-oxide-silicon (SONOS) transistor; The semiconductor circuit of claim 1 , wherein the first transistor comprises a metal-oxide-semiconductor (MOS) transistor or a SONOS transistor.

9. an array of memory cells; One or more write word lines (WWL); One or more write bit lines (WBLs); One or more read word lines (RWLs); and One or more read bit lines (RBLs) 11. A semiconductor device comprising: A write transistor; and Readout Transistor the write transistor includes a gate terminal coupled to a corresponding write word line, a first terminal coupled to a corresponding write bit line, and a second terminal coupled to a gate terminal of the read transistor, the read transistor includes a first terminal coupled to a corresponding read bit line and a second terminal coupled to a corresponding read word line; The readout transistor includes a charge trapping layer at the gate terminal of the readout transistor, the charge trapping layer comprising: a first write voltage through the corresponding write bit line is immutable when applied at the first terminal of the write transistor; A second write voltage through the corresponding write bit line is modifiable when applied at the first terminal of the write transistor to change the threshold voltage of the read transistor. the second write voltage is greater than the first write voltage; During execution of a training mode of an artificial intelligence (AI) model in the semiconductor device, an accumulation potential of an accumulation node between the second terminal of the write transistor and the gate terminal of the read transistor is determined based on the first write voltage applied at the first terminal of the write transistor while the write transistor is switched on by a gate voltage applied to the gate terminal of the write transistor, the threshold voltage of the read transistor remains unchanged, and the accumulation potential of the accumulation node is repeatedly variable based on the first write voltage; A semiconductor device, wherein while executing an inference mode of the AI ​​model in the semiconductor device, the read transistor is programmed or erased to have a particular threshold voltage based on the second write voltage applied at the first terminal of the write transistor while the write transistor is switched on, and the particular threshold voltage is adjustable based on the second write voltage.

10. the array of memory cells is arranged in an area defined by a first direction and a second direction perpendicular to the first direction; each of the one or more write word lines is coupled along the first direction to a gate terminal of a write transistor of a first memory cell; each of the one or more write bit lines is coupled along the second direction to a first terminal of a write transistor of a second memory cell; each of the one or more read bit lines is coupled along the first direction to a first terminal of a read transistor of a third memory cell; 10. The semiconductor device of claim 9, wherein each of the one or more read word lines is coupled to a second terminal of a read transistor of a fourth memory cell along the second direction.

11. 10. The semiconductor device of claim 9, wherein the training mode of the AI ​​model includes a dynamic random access memory (DRAM)-like mode, and the inference mode of the AI ​​model includes a non-volatile memory (NVM)-like mode.

12. 12. The semiconductor device of claim 11, wherein the storage potential of the storage node corresponds to an adjustable weight in the training mode, and the particular threshold voltage of the readout transistor corresponds to a fixed weight in the inference mode.

13. The semiconductor device of claim 12 , wherein the particular threshold voltage of the readout transistor corresponds to a binary weight “1” or “0” in the inference mode.

14. 13. The semiconductor device of claim 12, wherein the particular threshold voltage of the readout transistor corresponds to an analog weight in the inference mode, and the particular threshold voltage is adjustable between a minimum threshold voltage and a maximum threshold voltage.

15. the readout transistor is configured to operate in a saturation region, the storage potential of the storage node in the inference mode being greater than a saturation voltage associated with the readout transistor; 15. The semiconductor device of claim 14, wherein the read transistor is configured to receive a binary input signal through a corresponding read bit line at the first terminal of the read transistor, the binary input signal representing a "1" when the binary input signal has a voltage greater than a difference between the storage potential and the minimum threshold voltage of the storage node, and a "0" when the binary input signal has a voltage equal to 0V.

16. the readout transistor is configured to operate in the triode region, and the storage potential of the storage node in the inference mode is less than a saturation voltage associated with the readout transistor; 15. The semiconductor device of claim 14, wherein the read transistor is configured to receive an analog input signal through a corresponding read bit line at the first terminal of the read transistor, the analog input signal having a voltage in a range between 0V and a voltage difference between the storage potential and the maximum threshold voltage of the storage node.

17. the semiconductor device is configured to perform a multiply-accumulate (MAC) operation using the array of memory cells; the semiconductor device further comprising a sense amplifier coupled to a corresponding read word line that is coupled to the second terminal of the read transistor of the corresponding memory cell; the sense amplifier is configured to receive a sum current I from the corresponding read word line; The total current I is [0097] where x ｉ represents the input signal received at the corresponding memory cell i, and w ｉ represents the weight of the memory cell i, and G ｉ represents the conductance of the read transistor of the memory cell i, and V ｉ 10. The semiconductor device of claim 9, wherein i represents an input voltage across a corresponding read bit line at the first terminal of the read transistor of the memory cell i.

18. 1. A method of operating a universal memory for in-memory computing (IMC), the method comprising: running a training mode of an artificial intelligence (AI) model in the universal memory; wherein the universal memory comprises at least one memory cell having a write transistor and a read transistor; the write transistor having a gate terminal configured to receive a gate voltage to switch the write transistor on or off, a first terminal configured to receive a write voltage, and a second terminal coupled to the gate terminal of the read transistor; During the training mode, an accumulation potential of a storage node between the second terminal of the write transistor and the gate terminal of the read transistor is determined based on a first write voltage applied at the first terminal of the write transistor while the write transistor is switched on by a gate voltage applied at the gate terminal of the write transistor, a threshold voltage of the read transistor remains unchanged, and the accumulation potential of the storage node is repeatedly alterable based on the first write voltage; and executing an inference mode of the AI ​​model in the universal memory, where in the inference mode, the read transistor is programmed or erased to have a particular threshold voltage based on a second write voltage applied at the first terminal of the write transistor while the write transistor is switched on, the particular threshold voltage being adjustable based on the second write voltage. A method of operation comprising:

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