Semiconductor Device

Abstract

To provide a fine transistor, a transistor with small parasitic capacitance, a transistor with high frequency characteristics, a transistor with good electrical characteristics, a transistor with stable electrical characteristics, a transistor with small current when turned off, a semiconductor device having the transistor, a module having the semiconductor device, and an electronic device having these.SOLUTION: A transistor includes a semiconductor 406b on a semiconductor substrate 400, a first conductor 416a and a second conductor 416b on the semiconductor, a first insulator 410 on the first conductor and the second conductor, a second insulator 406c on the semiconductor, a third insulator 412 on the second insulator, and a third conductor 404 on the third insulator, and the third insulator is in contact with the side surface of the first insulator, and a length t1 between the top surface of the semiconductor and the bottom surface of the third conductor is larger than a length L1 between a region of the semiconductor that overlaps with the bottom surface of the first conductor and a region that overlaps with the bottom surface of the third conductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device, and a method for manufacturing the same. Alternatively, the present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a camera, The present invention relates to an image device, a processor, and an electronic device. Or, a display device, a liquid crystal display device, a light emitting device, The present invention relates to a method for manufacturing a storage device, an imaging device, and an electronic device. The present invention relates to a liquid crystal display device, a light emitting device, a storage device, and a method for driving electronic equipment.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It is about the nature of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices may include a semiconductor device. [Background technology]

[0004] In recent years, transistors using oxide semiconductors have been attracting attention. It is known that a transistor has an extremely small leakage current when it is in a non-conducting state. For example, a low-power transistor using an oxide semiconductor is proposed, which utilizes the low leakage current of the transistor. A power CPU and the like have been disclosed (see Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2012-257187 A Summary of the Invention [Problem to be solved by the invention]

[0006] One of the objects is to provide a fine transistor. One of the objectives is to provide a transistor with high frequency characteristics. Another object of the present invention is to provide a transistor having favorable electrical characteristics. Another object of the present invention is to provide a transistor having stable electrical characteristics. Another object of the present invention is to provide a transistor with a small current when off. Another object of the present invention is to provide a novel transistor. Another object of the present invention is to provide a semiconductor device having a high operating speed. Another object of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a module including the semiconductor device. It is an object of the present invention to provide an electronic device having the semiconductor device or the module. do.

[0007] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, and a second conductor. A first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, and a second insulator a third insulator on the edge and a third conductor on the third insulator, the third insulator being a first The semiconductor is in contact with the side surface of the first insulator, and the semiconductor is in contact with the bottom surface of the first conductor. a second region overlapping the semiconductor and a bottom surface of the second conductor; and a third region overlapping the top surface of the semiconductor and the bottom surface of the third conductor. a length between the first region and the third region is greater than a length between the first region and the third region. .

[0009] One aspect of the present invention is a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, and a second conductor. A first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, and a second insulator a third insulator on the edge, a third conductor on the third insulator, and a first insulator and a third conductor on the third insulator. a fourth conductor on the first insulator, a third insulator contacting a side of the first insulator, and a semiconductor The conductor and the bottom surface of the first conductor overlap in a first region, and the semiconductor and the bottom surface of the second conductor a second region overlapping the bottom surface of the semiconductor and a third conductor overlapping the bottom surface of the third conductor; The length between the top surface of the semiconductor and the bottom surface of the third conductor is The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first conductor or the second conductor and the fourth conductor. The length between the first region and the second region is greater than the length between the first region and the second region.

[0010] One aspect of the present invention is a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, and a second conductor. A first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, and a second insulator a third insulator on the conductor, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. the fourth insulator is in contact with a side surface of the first insulator, and the semiconductor is a semiconductor and a first a first region overlapping the bottom surface of the first conductor, and a semiconductor and a bottom surface of the second conductor overlapping the first region; a third region in which the semiconductor and a bottom surface of the third conductor overlap; The length between the top surface of the semiconductor and the bottom surface of the third conductor is the length between the first region and the third region. It is a larger semiconductor device.

[0011] One aspect of the present invention is a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, and a second conductor. A first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, and a second insulator a third insulator on the conductor, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. a fourth conductor on the first insulator and the third conductor, the fourth insulator being in contact with the first The semiconductor is in contact with the side surface of the insulator, and the semiconductor is in a first region where the semiconductor and the bottom surface of the first conductor overlap. a second region where the semiconductor and the bottom surface of the second conductor overlap, and a third region where the semiconductor and the bottom surface of the second conductor overlap, and a third region overlapping the bottom surface of the conductor, and the upper surface of the semiconductor and the bottom surface of the third conductor are The length between the first region and the third region is greater than the length between the first region and the third region, and the first conductor or The length between the second conductor and the fourth conductor is longer than the length between the first region and the second region. It is a larger semiconductor device.

[0012] In one aspect of the present invention, the length between the first conductor or the second conductor and the fourth conductor is The length is 1.5 times or more and 2 times or less than the length between the first region and the second region. Effect of the Invention

[0013] It is possible to provide a fine transistor or a transistor with a small parasitic capacitance. Alternatively, a transistor having high frequency characteristics can be provided. Alternatively, a transistor having good electrical characteristics can be provided. It is possible to provide a stable transistor. Or, it is possible to provide a transistor with a small current when off. Alternatively, a novel transistor can be provided. Alternatively, a semiconductor device having the transistor can be provided. It is possible to provide a fast semiconductor device. Alternatively, it is possible to provide a novel semiconductor device. Alternatively, a module having the semiconductor device can be provided. It is possible to provide a semiconductor device or an electronic device having the module.

[0014] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0015] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 2]1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 3] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 5] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 7] FIG. 1 is a cross-sectional view illustrating a part of a transistor according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view illustrating a part of a transistor according to one embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view illustrating a part of a transistor according to one embodiment of the present invention. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 18] FIG. 1 is a cross-sectional view illustrating a part of a transistor according to one embodiment of the present invention. [Figure 19] FIG. 1 is a cross-sectional view illustrating a part of a transistor according to one embodiment of the present invention. [Figure 20] FIG. 1 is a cross-sectional view illustrating a part of a transistor according to one embodiment of the present invention. [Figure 21] FIG. 1 is a cross-sectional view showing a part of a sputtering apparatus. [Figure 22] FIG. 1 is a cross-sectional view showing a part of a sputtering apparatus. [Figure 23] FIG. 2 is a top view showing an example of a film forming apparatus. [Figure 24] FIG. 1 is a diagram showing an example of the configuration of a film forming apparatus. [Diagram 25] FIG. 2 is a top view illustrating a manufacturing apparatus according to one embodiment of the present invention. [Figure 26] FIG. 2 is a top view showing a chamber according to one embodiment of the present invention. [Figure 27] FIG. 2 is a top view showing a chamber according to one embodiment of the present invention. [Figure 28] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 29] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Diagram 30] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Diagram 31] Electron diffraction pattern of CAAC-OS. [Diagram 32] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 33] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 34] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 35] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 36] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 38] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 39] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 40] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 41]FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 42] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 43] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 44] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 45] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 46] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 47] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 48] 1A and 1B are a perspective view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 49] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 50] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 51] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 52] 1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 53] FIG. 1 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Figure 54] 1 is a surface profile image of a sample according to one embodiment of the present invention. [Figure 55] 1 is a bright-field image by a scanning transmission electron microscope of a sample according to one embodiment of the present invention. [Figure 56] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and detail can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used in different The hatch pattern is used in common among drawings. In some cases, no particular symbol is attached.

[0017] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where

[0018] In this specification, the shape of an object may be expressed, for example, as a "diameter," "particle size," "size," or "diameter." When specifying the size or width of an object, the length of one side of the smallest cube that the object can fit into, or may be read as the equivalent circle diameter in a cross section of an object. refers to the diameter of a perfect circle whose area is equal to that of a cross-section of an object.

[0019] Note that a voltage is a voltage between a certain potential and a reference potential (such as the ground potential (GND) or source potential). Therefore, it is possible to say "voltage" as "potential". .

[0020] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "the first" should not be changed to "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. However, the ordinal numbers used to identify an aspect of the present invention may not be consistent.

[0021] The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor. For example, Elements with a concentration of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the body and the carrier mobility In some cases, the semiconductor may become an oxide semiconductor, or the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, There are elements, group 13 elements, group 14 elements, group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (which is also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, for example, impurities such as hydrogen can be mixed in. In addition, when the semiconductor is silicon, the properties of the semiconductor may be affected. The impurities to be changed include, for example, oxygen, group 1 elements excluding hydrogen, group 2 elements, and group 13 elements. Group 1 elements, Group 15 elements, etc.

[0022] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode (the part of the semiconductor through which current flows) overlaps with the The source region or source potential in the region where the This refers to the distance between the drain (drain region or drain electrode) and the In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is defined as any one value, maximum value, or The minimum or average value.

[0023] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. This refers to the length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0024] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in transistors with a fine, three-dimensional structure, In some cases, the proportion of the channel region formed may be large. In that case, The effective channel width of the channel is smaller than the apparent channel width. The larger the size, the larger the

[0025] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0026] In this specification, therefore, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length of the overlapping area between the source and drain The channel width of the In this specification, it is sometimes referred to as the "channel width". In some cases, this may refer to the enclosed channel width or apparent channel width; or In this specification, when simply referring to a channel width, it may refer to an effective channel width. In addition, the channel length, channel width, effective channel width, apparent channel width, and enclosure The width of the inclusion channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0027] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0028] In this specification, when it is stated that A has a shape protruding from B, it is to be understood that the shape is not limited to a top view. or in a cross-sectional view, at least one end of A is outside at least one end of B. Therefore, it may be described as having a shape in which A protrudes more than B. For example, in the top view, one end of A is outside one end of B. It can be read as having.

[0029] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0030] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0031] In the present specification, the term "semiconductor" may be interpreted as an oxide semiconductor. Semiconductors include group 14 semiconductors such as silicon and germanium, silicon carbide, and silicon Germanium arsenide, gallium arsenide, indium phosphide, zinc selenide, cadmium sulfide, etc. Compound semiconductors, carbon nanotubes, graphene, organic semiconductors, etc. can be done.

[0032] In this specification and the like, a silicon oxynitride film is a film having a composition containing more oxygen than nitrogen. A silicon nitride oxide film is a film that contains more nitrogen than oxygen. This refers to a film with a high content.

[0033] In this specification, etc., in a drawing or text described in a certain embodiment, When at least one specific example is described, it is not possible to derive a generic concept of that specific example. It will be easily understood by those skilled in the art. When at least one specific example is described in a figure or text, the general outline of that specific example is The invention is also disclosed as an embodiment of the invention and may constitute an embodiment of the invention. And one aspect of the invention can be said to be clear.

[0034] In this specification, at least the contents shown in the drawings (or even a part of the drawings) This is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if something is shown in a diagram, it does not need to be explained in words. However, the contents are disclosed as one aspect of the invention and constitute one aspect of the invention. Similarly, a part of the drawings may be regarded as an embodiment of the invention. This is disclosed as one embodiment of the present invention. It can be said that one aspect of the invention is clear.

[0035] In addition, regarding the contents not specified in the text or drawings in the specification, Alternatively, the upper limit of a certain value may be set. If a numerical range is listed, such as a lower limit, you can narrow the range arbitrarily. Or, by excluding one point within the scope, a mode of the invention that excludes a part of the scope is specified. As a result, for example, the prior art can be considered to be within the technical scope of one aspect of the present invention. It may be stipulated that no entry will be allowed.

[0036] (Embodiment 1) <Transistor structure 1> A structure of a transistor included in a semiconductor device according to one embodiment of the present invention will be described below. do.

[0037] 1A, 1B, and 1C are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 1(A) is a top view. FIG. 1(B) is a cross-sectional view of the one-dot chain line A1 shown in FIG. 1(A). FIG. 1(C) is a cross-sectional view corresponding to the cross-sectional view taken along line A2 of FIG. 1, showing the cross-sectional shape in the channel length direction. FIG. 2 is a cross-sectional view corresponding to the dashed line A3-A4 shown in (A), and shows the cross-sectional shape in the channel width direction. In the top view of FIG. 1(A), some elements are omitted for clarity. There are.

[0038] The transistor shown in FIG. 1 includes a conductor 413 and an insulator 401 on a substrate 400, and a conductor 413, an insulator 402 on the insulator 401, an insulator 406a on the insulator 402, and an insulator A semiconductor 406b on the insulating layer 406a and a conductor having a region in contact with the upper surface of the semiconductor 406b 416a and conductor 416b, the upper surface of insulator 402, the upper surface of conductor 416a, and conductor The insulator 410 is in contact with the top surface of the conductor 416b and has an opening. The side surface of the conductor 416a and the semiconductor An insulator 406c contacts the upper surface and side surface of the insulator 406b, and an insulator 406c contacts the upper surface and side surface of the insulator 406b. The insulator 412 contacting the side of the opening of the edge member 410, the insulator 412 and the insulator 406c A conductor having a conductor 404a and a conductor 404b disposed on a semiconductor 406b through a The conductor 404b is connected to the conductor 404a via the insulator 412. The conductor 40 is disposed on the transistor so as to face the side of the opening of the insulator 410. 4a and conductor 420 on conductor 404b, and insulator 412 and insulator 420 on conductor 420. The edge member 408 is also shown in FIG. 56(A), FIG. 56(B), and FIG. 56(C). As shown in FIG. 1, the conductor 413 and the insulator 401 are not essential components. A configuration without the insulator 401 may also be used.

[0039] The insulator 406c contains at least one element other than oxygen contained in the semiconductor 406b. This is preferable. In addition, the crystallinity of the insulator 406c can be improved. .

[0040] The semiconductor 406b and the insulator 406c preferably include a CAAC-OS, which will be described later. In addition, the insulator 406a also preferably includes a CAAC-OS.

[0041] In this transistor, the conductors 404a and 404b function as a first gate electrode. In addition, at least one of the conductors 404a and 404b is impermeable to oxygen. For example, the lower layer conductor is preferably a conductor that is less permeable to oxygen. By forming the conductive material 404a, it is possible to prevent a decrease in the conductivity due to oxidation of the conductive material 404b. The insulator 412 also functions as a first gate insulator.

[0042] The conductor 413 also functions as a second gate electrode. It is also possible to use a laminated structure including a conductor having a function of being difficult for oxygen to permeate. By forming a layered structure including a conductor that is difficult to oxidize, the conductivity of the conductor 413 is reduced. The insulator 402 functions as a second gate insulator. The threshold voltage of the transistor can be controlled by the potential applied to the body 413. In addition, by electrically connecting the first gate electrode and the second gate electrode, the current The function of the first gate electrode and the function of the second gate electrode can be increased. The functions of the electrodes may be interchanged.

[0043] The conductor 416a and the conductor 416b serve as a source electrode and a drain electrode. The conductivity of a conductor can be measured using the two-terminal method, for example.

[0044] The resistance of the semiconductor 406b can be controlled by applying a potential to the conductor 404. That is, the potential applied to the conductor 404 causes a voltage between the conductor 416a and the conductor 416b. Conduction / non-conduction can be controlled.

[0045] As shown in FIG. 1B, the top surface of the semiconductor 406b is In addition, the semiconductor 4 is in contact with the conductor 404, which functions as a gate electrode. The electric field of the gate electrode electrically surrounds the semiconductor. The surrounding transistor structure is called the surrounded channel (s-channel Therefore, a channel may be formed in the entire semiconductor 406b. In the s-channel structure, a large current flows between the source and drain of the transistor. This allows the current (on-state current) to be increased when the semiconductor 40 is turned on. 6b is surrounded by the electric field of the conductor 404, the current when it is not conducting (OFF The current) can be reduced.

[0046] In the transistor of this embodiment, a region functioning as a gate electrode is formed on the insulator 410. It is self-aligned to fill the openings formed by the above. Therefore, TGSA s-channel FET (Trench Gate Select f Align s-channel FET).

[0047] In FIG. 1B, the upper surface of the semiconductor 406b in the region overlapping with the conductor 404 and the conductor The length between the bottom surface of the semiconductor 406b and the bottom surface of the semiconductor 406b is t1. In the above, a region overlapping with the bottom surface of the conductor 416a and a region overlapping with the bottom surface of the conductor 404 are The length between the area overlapping the bottom surface of the conductor 416b and the area overlapping the bottom surface of the conductor 404 is L1. The length between the area overlapping with the bottom surface is L1.

[0048] In the transistor, the region in which the channel is formed in the semiconductor 406b (the conductor 40 4 and the semiconductor 406b) and a source region or a drain region (conductor 416 a or a region where the conductor 416b and the semiconductor 406b overlap each other) and a region L1 is formed between the conductor 416b and the semiconductor 406b. By providing this region, the off-state current of the transistor can be reduced. If the area is too large, it will reduce the on-current of the transistor.

[0049] In addition, the region in which the channel of the semiconductor 406b is to be formed is covered with the insulator 406c. The elements other than oxygen (hydrogen, silicon) that make up the adjacent insulator are introduced into the region where the channel is formed. Therefore, the insulator 406c is small. Both may be formed on the semiconductor 406b.

[0050] Therefore, the insulator 406c is not provided on the side of the conductor 404 via the insulator 412. Alternatively, the region where the insulator 406c covers the side surface of the conductor 404 via the insulator 412 is The area 406c overlaps the bottom surface of the conductor 404 with the insulator 412 interposed therebetween. By making 406c thin, L1 can be made small. Therefore, t1 is L is greater than 1, and L1 / t1 is less than 1.

[0051] In addition, in FIG. 1B, the conductor 416a or the conductor 416b and the conductor 420 The length between the conductor 416a and the conductor 416b is denoted by t2. The length between them is L2.

[0052] As transistors become smaller, the parasitic capacitance near the transistor becomes too large to be ignored. For example, between the conductor 420 and the conductor 416a or conductor 416b The parasitic capacitance may be formed near the region where the channel is formed. If the parasitic capacitance is not charged, the transistor operation requires time. This reduces the response of the transistor and therefore the response of the semiconductor device. In circuits that use multiple transistors, unnecessary power is consumed to supply power. Therefore, for t2, the parasitic capacitance is negligible compared to the gate capacitance. It is preferable that the length is sufficient so that the

[0053] In addition, as transistors are miniaturized, L2 becomes smaller, and the conductor 404a and However, it becomes difficult to apply a sufficient voltage to the conductor 404b. By designing the length of the conductor 404a and the conductor 404b to be appropriate, the resistance of the conductor 404a and the conductor 404b can be reduced. Therefore, t2 should be greater than L2, and preferably t2 / L2 should be 1.5 or greater. It is recommended to set it to 2 or less.

[0054] The substrate 400 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, and a stabilized zirconia substrate. There are also semiconductor substrates, such as zirconia substrates stabilized with yttria, and resin substrates. The substrate may be, for example, a single semiconductor substrate such as silicon or germanium, or a silicon carbide substrate. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates made of insulating material. A semiconductor substrate having, for example, an SOI (Silicon On Insulator) substrate Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. Further, a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or a semiconductor is provided on a semiconductor substrate, There are substrates with an insulator, and substrates with a semiconductor or insulator on a conductor substrate. Alternatively, a substrate having elements provided thereon may be used. Examples of the elements include a capacitance element, a resistance element, a switch element, a light-emitting element, and a memory element.

[0055] A flexible substrate may be used as the substrate 400. The method of providing the transistor is to fabricate the transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to the flexible substrate 400. A peeling layer may be provided between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil having woven fibers may be used. The substrate 400 may be stretchable. Also, the substrate 400 may be designed to retain its original shape when the bending or pulling is stopped. The substrate 4 may have a property of returning to its original shape. Alternatively, the substrate 4 may have a property of not returning to its original shape. 00 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less; More preferably, the substrate 400 has a region having a thickness of 15 μm or more and 300 μm or less. By making the substrate thinner, the weight of the semiconductor device having the transistor can be reduced. By making 00 thinner, it can be stretched even when using glass, and can be easily folded or folded. It may have the property of returning to its original shape when you stop pulling it. Therefore, it is possible to reduce the impact applied to the semiconductor device on the substrate 400. It is possible to provide a semiconductor device.

[0056] The substrate 400, which is a flexible substrate, may be made of, for example, a metal, an alloy, a resin, or a glass. The substrate 400, which is a flexible substrate, has a linear expansion coefficient of 1.0. The lower the coefficient of thermal expansion, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester or polystyrene. Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, so it is suitable for flexible substrates. 400 is preferable.

[0057] The transistor is made of an insulator that has a function of blocking impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator, the electrical characteristics of the transistor can be stabilized. 408 is an insulator that has the function of blocking impurities such as hydrogen and oxygen. Good.

[0058] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in a single layer or in a multilayer.

[0059] For example, the insulator 408 may be aluminum oxide, magnesium oxide, or nitride oxide. Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide The material may be zinc oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide. The insulator 408 preferably contains aluminum oxide. The insulator 408 is formed by depositing an insulating film that serves as a base layer for the insulator 408 using plasma containing oxygen. Oxygen can be added to the body 410 or to the side of the insulator 412. The added oxygen can be excess oxygen in the insulator 410 or in the insulator 412. The insulator 408 contains aluminum oxide, which prevents impurities such as hydrogen from entering the semiconductor 406b. In addition, for example, if the insulator 408 is made of aluminum oxide, the insulator 408 can be prevented from being contaminated by foreign matter. By having the insulator, the excess oxygen added to the insulator 410 and the insulator 412 can be prevented from being outwardly dispersed. Diffusion can be reduced.

[0060] The insulator 402 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 402 may be made of silicon oxide or oxide. It is preferable to have silicon nitride.

[0061] It is preferable that the insulator 410 has a low dielectric constant. 410 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with , silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the material includes silicon, silicon oxide having voids, or resin. Alternatively, The insulator 410 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide The laminated structure may include a silicon oxide layer or a silicon oxide layer having voids, and a resin layer. Silicon oxide and silicon oxynitride are preferred because they are thermally stable and can be easily combined with resin. By combining these resins, it is possible to obtain a laminated structure that is thermally stable and has a low relative dielectric constant. For example, polyester, polyolefin, polyamide (nylon, aramid, etc.) , polyimide, polycarbonate or acrylic.

[0062] The insulator 412 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 412 may be a silicon oxide or an oxide film. It is preferable to have silicon nitride.

[0063] It is preferable that the insulator 412 has a high relative dielectric constant. For example, 412 is a gallium oxide, hafnium oxide, and oxide with aluminum and hafnium. oxide nitrides with aluminum and hafnium, oxide nitrides with silicon and hafnium It is preferred to have a silicon oxide having hafnium or an oxide nitride having silicon and hafnium. Alternatively, the insulator 412 may be a material having a dielectric constant of silicon oxide or silicon oxynitride. It is preferable to have a laminate structure of silicon oxide and silicon oxynitride. Since PO is thermally stable, it can be combined with an insulator with a high dielectric constant to produce a thermally stable For example, aluminum oxide, gallium oxide, etc. By having hafnium or hafnium oxide on the insulator 406c side, silicon oxide or oxide The silicon contained in the silicon nitride can be prevented from being mixed into the semiconductor 406b. Also, for example, silicon oxide or silicon oxynitride may be provided on the insulator 406c side. By this, aluminum oxide, gallium oxide or hafnium oxide and silicon oxide or In some cases, trap centers are formed at the interface between the silicon oxide and the silicon nitride. The boost center shifts the threshold voltage of the transistor in the positive direction by capturing electrons. It may be possible to do so.

[0064] The conductor 416a and the conductor 416b may be, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver Conductors containing one or more of indium, tin, tantalum and tungsten are used in a single layer or in a For example, an alloy film or a compound film may be used, and a film containing aluminum may be used. Conductors containing copper and titanium, conductors containing copper and manganese, indium, Conductors containing tin and oxygen, or conductors containing titanium and nitrogen, etc. may also be used. .

[0065] The conductor 404, the conductor 413, and the conductor 420 may include, for example, boron, nitrogen, oxygen, etc. , fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel Kel, Copper, Zinc, Gallium, Yttrium, Zirconium, Molybdenum, Ruthenium, Silver Conductors containing one or more of indium, tin, tantalum and tungsten are used in a single layer or in a For example, an alloy film or a compound film may be used, and a film containing aluminum may be used. Conductors containing copper and titanium, conductors containing copper and manganese, indium, Conductors containing tin and oxygen, or conductors containing titanium and nitrogen, etc. may also be used. .

[0066] The semiconductor 406b is preferably an oxide semiconductor. (including silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, Aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors There are cases where this is acceptable.

[0067] The insulators 406a and 406c are made of an element other than oxygen that constitutes the semiconductor 406b. It is preferable to use an oxide composed of one or more kinds of materials. (including strained silicon), germanium, silicon germanium, silicon carbide, gallium Arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride or organic semiconductors, etc. There are cases where it is acceptable to use

[0068] The semiconductor 406b is, for example, an oxide semiconductor. When the semiconductor 406b contains the element Zn, the carrier mobility (electron mobility) increases. It is preferable to include M. The element M is preferably aluminum, gallium, yttrium or the like. Other elements that can be used for element M include boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, The element M may be a combination of the above elements. For example, the element M may be For example, indium has a high bond energy with oxygen. Alternatively, the element M may be, for example, an element having an energy gap of an oxide semiconductor. The semiconductor 406b preferably contains zinc. When an oxide semiconductor contains zinc, it may be easily crystallized.

[0069] However, the semiconductor 406b is not limited to an oxide semiconductor. Indium-free, zinc-containing oxide semiconductors such as zinc tin oxide and gallium tin oxide A conductor, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like may be used.

[0070] The semiconductor 406b is made of, for example, an oxide having a large energy gap. The energy gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 The excitation voltage is preferably from 3 eV to 3.5 eV, and more preferably from 3 eV to 3.8 eV.

[0071] The insulators 406a and 406c are each made of an element other than oxygen that constitutes the semiconductor 406b. The oxide is composed of one or more kinds of oxides, or two or more kinds of oxides. Since the insulators 406a and 406c are composed of one or more other elements, Therefore, the interface between the insulator 406a and the semiconductor 406b and the interface between the semiconductor 406b and the insulator 406c At the interface with the silicon, defect levels are unlikely to be formed.

[0072] The semiconductor 406b is an oxide having a higher electron affinity than the insulators 406a and 406c. For example, a semiconductor 406b having a higher electron affinity than the insulators 406a and 406c is used. The force is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and Preferably, an oxide having an electron affinity of 0.15 eV or more and 0.4 eV or less is used. is the energy difference between the vacuum level and the conduction band minimum.

[0073] In this way, a transistor in which an insulator 406a and an insulator 406c are arranged above and below a semiconductor 406b is When a gate voltage is applied to the transistor, the insulator 406a, the semiconductor 406b, and the insulator 406c are A channel is formed in the semiconductor 406b having a large electron affinity out of the semiconductor 406c. , a so-called buried channel structure can be formed.

[0074] Here, between the insulator 406a and the semiconductor 406b, In addition, between the semiconductor 406b and the insulator 406c, The mixed region may have a semiconductor 406b and an insulator 406c. Therefore, the stacked layer of the insulator 406a, the semiconductor 406b, and the insulator 406c is The body has a continuous change in energy near each interface (also called a continuous junction). The interfaces of the insulator 406a, the semiconductor 406b, and the insulator 406c are clearly shown. It may not be possible to determine with certainty.

[0075] At this time, the electrons are mainly in the semiconductor 406b, not in the insulator 406a or the insulator 406c. and move.

[0076] The on-current of a transistor can be increased by reducing the factors that inhibit the movement of electrons. The movement of electrons is also hindered, for example, when the channel formation region has large physical irregularities. will be done.

[0077] In order to increase the on-current of the transistor, for example, the upper or lower surface of the semiconductor 406b (the surface to be formed, here the upper surface of the insulator 406a) Root mean square (RMS) roughness less than 1 nm, preferably It is preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in an area of ​​1 μm × 1 μm is 1 nm. less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably 0 The maximum height difference (PV and ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, The RMS roughness, Ra and PV are preferably less than 7 nm. Using a scanning probe microscope system SPA-500 manufactured by Nano Technology Co., Ltd. It can be measured.

[0078] The above-mentioned three-layer structure is an example. For example, the upper or lower layer of the insulator 406a or the lower layer of the insulator 406b may be Above or below 06c, any of the insulators exemplified as insulator 406a or insulator 406c may be provided. A laminated structure having one or more of these may also be used.

[0079] Note that an oxide semiconductor that can be used as a semiconductor will be described in detail in other embodiments. I will explain in detail.

[0080] <Transistor manufacturing method 1> A method for manufacturing the transistor of FIG. 1 according to the present invention will be described below with reference to FIGS. .

[0081] First, a substrate 400 is prepared.

[0082] Next, as shown in FIG. 7(A) and FIG. 7(B), an insulator 401 is formed on the substrate 400. An opening is formed in the insulator 401, and a conductor that becomes a conductor 413 is formed on the insulator 401. The conductive material to be the conductive material 413 is formed by sputtering, CVD, MBE, or the like. The conductor 413 can be formed by a deposition method, a PLD method, an ALD method, or the like. As a multilayer structure containing a conductor that is difficult to penetrate (or has high oxidation resistance) Next, Chemical Mechanical Polishing The conductor 413 may be embedded in the opening of the insulator 401 by using a chemical vapor deposition (CMP) or the like. Another method for forming the conductor 413 is to form a conductor film and then apply a photolithography method or the like. The conductor 413 may be formed by processing using a material such as a silicon dioxide film.

[0083] In the photolithography method, first, the resist is exposed to light through a mask. The exposed areas are removed or left behind using a developer to form a resist mask. Then, a conductor, a semiconductor, or an insulator is formed by etching the resist mask. For example, KrF excimer laser light, ArF excimer laser light, etc. can be processed into the desired shape. Using laser light, extreme ultraviolet (EUV) light, etc. A resist mask may be formed by exposing the resist. A liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the light source for exposure. Instead of light, an electron beam or an ion beam may be used. If a mask is used, the mask is not necessary. Dry etching such as dipping, wet etching, or After dry etching, wet etching is performed, or wet etching is performed. After the treatment, a dry etching treatment can be performed.

[0084] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. Capacitively Coupled Plasma (CAP) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be A high-frequency power source may be applied to one of the electrodes. A configuration in which a plurality of different high frequency power sources are applied to the electrodes may be used. Alternatively, a high-frequency power source having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a high-frequency power source having a high-density plasma source may be used. Dry etching equipment with a high density plasma source can be used. The device is, for example, an inductively coupled plasma (ICP) d Plasma etching equipment or the like can be used.

[0085] Next, a high-density plasma treatment may be performed as shown by the arrows in FIG. 7(A) or (B). The high density plasma treatment is preferably carried out in an oxygen atmosphere or a nitrogen atmosphere. is a gas atmosphere containing oxygen atoms, such as oxygen, ozone or nitrogen oxides (nitric oxide, Nitrogen dioxide, nitrous oxide, dinitrogen trioxide, dinitrogen tetroxide, dinitrogen pentoxide, etc.) atmosphere In addition, in an oxygen atmosphere, the inert gases such as nitrogen or rare gases (helium, argon, etc.) The active gas may be included. By performing high density plasma processing in such an oxygen atmosphere, Therefore, for example, carbon, hydrogen, etc. can be desorbed. By using plasma treatment, organic compounds such as hydrocarbons can be easily desorbed from the material to be treated. stomach.

[0086] The high density plasma treatment in a nitrogen atmosphere may be carried out in an atmosphere containing nitrogen and a rare gas, or in an atmosphere containing nitrogen, hydrogen and a rare gas, or in an atmosphere containing ammonia and a rare gas. The high-density plasma treatment can be performed by using the above-mentioned high-density plasma. The area to be nitrided can be formed very thinly on the surface side of the workpiece. Moreover, the nitrided region can suppress the diffusion of impurities.

[0087] The high-density plasma treatment may be performed in an oxygen atmosphere and then in a nitrogen atmosphere. After the treatment in the nitrogen atmosphere, the treatment in the oxygen atmosphere may be performed. Annealing may be performed before or after the treatment. In some cases, it may be preferable to flow an adequate amount of gas. If the amount of gas is not sufficient, radical generation may occur. For example, if the gas is 100 sccm or more and 30 Flows of 0 sccm or more or 800 sccm or more may be preferred.

[0088] High-density plasma processing is performed, for example, at frequencies of 0.3 GHz to 3.0 GHz, 0.7 GHz, etc. z or higher and up to 1.1 GHz, or 2.2 GHz or higher and up to 2.8 GHz (typically 2.4 The microwave generated by a high frequency generator (5 GHz) can be used. The pressure is 10 Pa or more and 5000 Pa or less, preferably 200 Pa or more and 1500 Pa or less, and Preferably, the pressure is 300 Pa or more and 1000 Pa or less, and the substrate temperature is 100° C. or more and 600° C. or less ( Typically, the reaction can be performed at a temperature of 400° C. using a mixed gas of oxygen and argon.

[0089] The high-density plasma is generated by using, for example, 2.45 GHz microwaves. Electron density is 1×10 11 / cm 3 More than 1×10 13 / cm 3 Below, electron temperature is 2 eV or less It is preferable to carry out such a high-density plasma treatment with an ion energy of 5 eV or less. The kinetic energy of radicals is small, and the plasma treatment is more effective than conventional plasma treatment. This results in less damage to the film, which has fewer defects. The distance from the generating antenna to the object to be treated is 5 mm or more and 120 mm or less, preferably 20 It is recommended that the thickness be between 60 mm and 60 mm.

[0090] Alternatively, a plasma that applies an RF (Radio Frequency) bias to the substrate side The frequency of the RF bias may be, for example, 13.56 MHz or 27.1 By using high-density plasma, high-density oxygen ions can be generated. By applying an RF bias to the substrate, the device is generated by high-density plasma. The oxygen ions can be efficiently guided to the workpiece. It is preferable to perform high density plasma treatment while applying heat.

[0091] In addition, after the high-density plasma treatment, annealing was performed continuously without exposure to the atmosphere. In addition, the high-density plasma treatment may be performed continuously after the annealing treatment without exposing the substrate to the atmosphere. The high density plasma treatment and the annealing treatment may be performed in succession. This can prevent impurities from being mixed in during processing. After the treatment, an annealing treatment is performed to remove the oxygen from the workpiece. It is possible to eliminate unnecessary oxygen that has not been used to compensate for the oxygen vacancies. The annealing process may be performed by, for example, lamp annealing.

[0092] In addition, the processing time for high-density plasma treatment is from 30 seconds to 120 minutes, or from 1 minute to 90 minutes. , preferably from 2 to 30 minutes, or from 3 to 15 minutes.

[0093] Annealing should be performed at temperatures between 250°C and 800°C, between 300°C and 700°C, or between 400°C and 800°C. Treatment time at 00°C or higher and 600°C or lower is 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less, It is preferable to set the time to between 2 and 30 minutes, or between 3 and 15 minutes.

[0094] Next, the insulator 402 is formed. The insulator 402 is formed by a sputtering method, a chemical vapor deposition method, or the like. Chemical Vapor Deposition (CVD) method, molecular beam epitaxy Molecular Beam Epitaxy (MBE) method or pulse laser Pulsed Laser Deposition (PLD), Atomic Layer Deposition ( This can be done using methods such as ALD (Atomic Layer Deposition). can.

[0095] The CVD method is a method that uses plasma CVD (PECVD: Plasma ECVD). enhanced CVD method, and thermal CVD (TCVD: Thermal CVD) method D) method, photo CVD method, etc. Depending on the source gas, metal CVD (MCVD) method, metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0096] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device etc. may become charged up by receiving an electric charge from the plasma. Accumulated electric charges can destroy wiring, electrodes, elements, etc., contained in semiconductor devices. On the other hand, in the case of the thermal CVD method that does not use plasma, the above-mentioned exposure to plasma Since no damage caused by the above-mentioned occurs, the yield of semiconductor devices can be increased. In addition, with thermal CVD, the film is not exposed to plasma during deposition, so the film has fewer defects. Easy to obtain.

[0097] In addition, the ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. Obtained.

[0098] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less susceptible to the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of films with high aspect ratios. It is suitable for coating the surface of a high opening. However, the ALD method has a slow film formation speed. Therefore, it is preferable to use it in combination with other film formation methods such as CVD, which has a high film formation rate. In some cases, this is not possible.

[0099] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0100] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0101] Further, a treatment for adding oxygen to the insulator 402 may be performed. The method includes, for example, an ion implantation method and a plasma treatment method. The oxygen removed becomes excess oxygen.

[0102] Next, as shown in FIG. 7(C) and FIG. 7(D), the insulator 406a and the semiconductor 4 A semiconductor to be 06b and a resist mask 430 are formed.

[0103] First, an insulator that will become the insulator 406a is formed over the insulator 402. The insulator film is formed by sputtering, CVD, MBE, PLD, ALD, etc. In particular, the deposition can be performed using a facing target sputtering device. In this specification and the like, the term "facing target type sputtering apparatus" is used. The deposition method using this method is also called VDSP (vapor deposition SP). can.

[0104] By depositing an insulator using a facing target sputtering device, This reduces plasma damage in the film, thereby reducing oxygen vacancies in the film. In addition, by using a facing target sputtering device, film formation in a high vacuum is possible. This allows the concentration of impurities (e.g. hydrogen, rare gas (argon, etc.)) in the deposited insulator to be ), water, etc.) can be reduced.

[0105] Also, a sputtering device having an inductively coupled antenna conductor plate may be used. This allows for a high film formation speed and the formation of a film with a large area and high uniformity.

[0106] The film is preferably formed using a gas containing oxygen, a rare gas, a gas containing nitrogen, or the like. Gases that contain nitrogen (N2), nitrous oxide (N2O), ammonia (NH3 ) etc. can be used.

[0107] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0108] In addition, a process of adding oxygen to the insulator that will become the insulator 406a may be performed. The treatment for adding the insulating material 406a includes ion implantation and plasma treatment. The oxygen added to the insulator becomes excess oxygen.

[0109] Next, a semiconductor film that will become the semiconductor 406b is formed on the insulator that will become the insulator 406a. The film is formed by sputtering, CVD, MBE, PLD, ALD, etc. In particular, it is possible to form a film using a facing target sputtering apparatus. preferable.

[0110] By depositing semiconductor films using a facing target sputtering device, This reduces plasma damage in the film, thereby reducing oxygen vacancies in the film. In addition, by using a facing target sputtering device, film formation in a high vacuum is possible. This allows the concentration of impurities (e.g. hydrogen, rare gas (argon, etc.)) in the deposited semiconductor to be ), water, etc.) can be reduced.

[0111] Also, a sputtering device having an inductively coupled antenna conductor plate may be used. This allows for a high film formation speed and the formation of a film with a large area and high uniformity.

[0112] The film is preferably formed using a gas containing oxygen, a rare gas, a gas containing nitrogen, or the like. Gases that contain nitrogen (N2), nitrous oxide (N2O), ammonia (NH3 ) etc. can be used.

[0113] Next, a first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. The first heat treatment is preferably performed at a temperature of 450° C. or higher and 600° C. or lower. or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed under an inert gas atmosphere. After heat treatment in an atmosphere, oxidizing gas is added at 10 ppm or more and 1 % or more, or 10% or more. This can improve the crystallinity of a semiconductor and remove impurities such as hydrogen and water. Alternatively, the first heat treatment may be performed using a plasma treatment containing oxygen under reduced pressure. The plasma treatment includes, for example, a power source that generates high-density plasma using microwaves. It is preferable to use a device that can perform the same process as the above. y) A plasma power supply for applying a voltage may be provided. By using high density plasma, By applying RF voltage to the substrate, high density printing can be achieved. The oxygen radicals generated by the plasma can be efficiently guided into the semiconductor 406b. Alternatively, the apparatus can be used to supplement the oxygen released after plasma treatment containing an inert gas. In order to achieve this, a plasma treatment containing oxygen may be performed.

[0114] Next, as shown in FIG. 7(E) and FIG. 7(F), the insulator 406a and the semiconductor A semiconductor that will become the body 406b is formed by a photolithography method using a resist mask 430. The multilayer film having the insulator 406a and the semiconductor 406b is formed. When forming a multilayer film, the insulator 402 may also be etched, resulting in some areas becoming thinner. That is, the insulator 402 may have a protrusion in the region in contact with the multilayer film.

[0115] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0116] Next, as shown in FIG. 7(G) and FIG. 7(H), the conductor 416 and the insulator 410 are Form an insulator.

[0117] First, the conductor 416 is formed. The conductor 416 can be formed by a sputtering method, a CVD method, or the like. This can be carried out by using the MBE method, the PLD method, the ALD method, or the like.

[0118] The conductor 416 is formed to cover the multilayer film. Damage was caused to the side surface of 406a, the top surface of semiconductor 406b, and a part of the side surface of semiconductor 406b. By providing the insulating material 406a, a region having a low resistance may be formed. Since a part of the semiconductor 406b has a region with reduced resistance, the conductor 416 and the semiconductor 40 The contact resistance between 6b and can be reduced.

[0119] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0120] Then, the conductive material 416a and the conductive material 416b are processed by photolithography or the like. Form 6b.

[0121] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0122] Next, a film of an insulator that will become the insulator 410 is formed. The film of the insulator that will become the insulator 410 is formed by a spat This can be done using methods such as CVD, MBE, PLD, and ALD. Alternatively, it can be applied by spin coating, dipping, droplet ejection (inkjet method, etc.), printing, etc. Printing method (screen printing, offset printing, etc.), doctor knife method, roll coater method, etc. Alternatively, a curtain coater method or the like can be used.

[0123] The insulator that becomes the insulator 410 may be formed so as to have a flat upper surface. For example, The insulating material that becomes the edge 410 may have a flat upper surface immediately after deposition. For example, the insulator that becomes the insulator 410 is insulated so as to be parallel to a reference plane such as the back surface of the substrate after film formation. The planarization may be achieved by removing the substrate from the top surface. The planarization process is called "processing". Examples of planarization processes include chemical mechanical polishing and dry etching. However, the top surface of the insulator that will become insulator 410 does not need to be flat.

[0124] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0125] Next, a resist mask is formed on the insulator 410 by photolithography or the like. Here, a gap 431 is formed between the upper surface of the insulator 410 and the resist mask. In order to improve adhesion, for example, an organic coating film is formed on the insulator 410 and the resist. It may be provided between the masks.

[0126] Next, as shown in FIGS. 8(A) and 8(B), an opening is formed in the insulator 410 and the conductor 416. First, a resist mask 431 is formed on an insulator that will become an insulator 410, and then A first process is performed using a dry etching method or the like until the top surface of the conductor 416 is reached. The dry etching method can use the dry etching equipment described above, but Use of a dry etching device in which high-frequency power sources with different frequencies are connected to each electrode is preferred.

[0127] Next, the conductor 416 is subjected to a second process using a dry etching method or the like to form a conductive The insulator 410 is separated into a conductor 416a and a conductor 416b. The process for forming the conductive material 416 and the process for forming the conductive material 416 may be performed in a common photolithography process. No problem. By standardizing the photolithography process, the number of steps can be reduced. Therefore, the productivity of a semiconductor device having a transistor can be increased. Cut.

[0128] At this time, the semiconductor 406b has an exposed area. A portion of the exposed semiconductor 406b may be removed by the second process described above. Impurity elements such as residual components of the etching gas may adhere to the surface of the substrate. If chlorine gas is used as the etching gas, chlorine and other substances may adhere to the surface. If a hydrocarbon gas is used, carbon, hydrogen, etc. may adhere to the gas. In this case, it is preferable to reduce impurity elements attached to the exposed surface of the semiconductor 406b. The reduction of impurities can be achieved by, for example, cleaning using dilute hydrofluoric acid or cleaning using ozone. Alternatively, a cleaning process using ultraviolet light or the like may be used. This may form an exposed surface of the semiconductor 406b, in other words, a channel. The area where the current is applied becomes highly resistive.

[0129] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0130] Next, as shown in FIG. 8(C) and FIG. 8(D), at least the side surface of the insulator 410 is removed. , the top and side surfaces of the semiconductor 406b, the side surfaces of the insulator 406a, the top surface of the insulator 402, and The insulator 406c is deposited on the top surface of the insulator 410. The insulator 406c is deposited by sputtering. This can be done using the gelling method.

[0131] Here, a sputtering apparatus used for forming the insulator 406c will be described with reference to FIGS. 21 and 22. This will be explained using:

[0132] FIG. 21 is a cross-sectional view showing a part of the sputtering apparatus 101. The ring device 101 includes a member 190, a collimator 150 disposed on the member 190, and a A target holder 120 and a backing plate 110 disposed on the target holder 120 10, a target 100 arranged on a backing plate 110, and A magnet 130N and a magnet 140N are disposed under the target 100 via a port 110. A magnet unit 130 including a magnet holder 130S and a magnet holder 130 for supporting the magnet unit 130 and a magnet holder 132. In this specification, a magnet holder The combination of these is called a magnet unit. A magnet unit consists of a cathode, a cathode It can also be called a sword magnet, magnetic member, magnetic part, etc.

[0133] The substrate stage 170 is disposed facing the target 100. Also shown is the substrate 160 supported by the magnet unit 170. 1 shows magnetic field lines 180a and 180b.

[0134] The target holder 120 and the backing plate 110 are secured together using screws (bolts, etc.). The target holder 120 is fixed to the backing plate 122 and is equipotential. It has the function of supporting the target 100 via 110.

[0135] The backing plate 110 has a function of fixing the target 100 .

[0136] The sputtering device 101 has a water channel inside or under the backing plate 110. And, a fluid (air, nitrogen, rare gas, water, oil, etc.) is made to flow through the waterway. During sputtering, the temperature of the target 100 may rise, causing discharge abnormalities. This can prevent damage to the sputtering device 101 caused by deformation of any of the members. At this time, the backing plate 110 and the target 100 are in close contact with each other via a bonding material. This is preferable because it improves the cooling performance.

[0137] A gasket is provided between the target holder 120 and the backing plate 110. This makes it difficult for impurities originating from the outside or water channels to get into the sputtering apparatus 101. Therefore, it is preferable.

[0138] In the magnet unit 130, the magnet 130N and the magnet 130S are The magnets are arranged with different polarities facing the target 100. The magnet 130N is placed so that the target 100 side is the north pole, and the magnet 130S is placed The following describes the case where the magnet is arranged so that the target 100 side is the south pole. The arrangement of the magnets and the polarities in the magnet unit 130 is not limited to that shown in FIG. It is not.

[0139] The magnetic field line 180a is one of the magnetic field lines that form a horizontal magnetic field in the vicinity of the upper surface of the target 100. The vicinity of the upper surface of the target 100 is, for example, a region perpendicular to the target 100. This is the region between 0 mm and 5 mm, in particular between 0 mm and 5 mm.

[0140] The magnetic field lines 180b form a horizontal magnetic field at a vertical distance d from the top surface of the magnet unit 130. The vertical distance d is, for example, 0 mm or more and 20 mm or less, or Between 5mm and 15mm.

[0141] During film formation, the potential V1 applied to the target holder 120 is, for example, The potential V2 applied to the substrate stage 170 is lower than the potential V3 applied to the substrate stage 170. The potential V2 is, for example, a ground potential. The potential V1, the potential V2, and the potential V3 are the above potentials. In addition, the target holder 120, the substrate stage 170, the magnet holder For example, if the substrate stage 170 is electrically It doesn't matter if it's floating on the target.

[0142] In addition, in FIG. 21, the backing plate 110, the target holder 120, and the magnet In this example, the magnet unit 130 and the magnet holder 132 are not electrically connected. For example, the backing plate 110 and the target holder 120 is electrically connected to the magnet unit 130 and the magnet holder 132. The potentials may be equipotential.

[0143] A deposition gas (for example, a rare gas such as argon, oxygen, nitrogen, etc.) is placed in the sputtering device 101. The pressure is kept constant (for example, 0.05 Pa or more and 10 Pa or less, preferably 0.1 When a potential V1 is applied to the target holder 120, Plasma is generated in the magnetic field generated by the net unit 130. The potential becomes Vp, which is higher than the potential V1. At this time, the positive ions in the plasma The potential difference between Vp and potential V1 accelerates the positive ion beam toward the target 100. The collision of the ions with the target 100 releases sputter particles. Of the sputtered particles, those that reach the substrate 160 are deposited as a film.

[0144] In general, in sputtering equipment, the bottom of a small opening with a large aspect ratio is filled with sputtering gas. In addition, the sputter particles flying at an angle to the substrate are difficult to reach. However, it may accumulate near the top of the opening, narrowing the opening, and preventing the film from being formed inside the opening.

[0145] On the other hand, by using the sputtering apparatus having the above configuration, among the emitted sputtered particles, The sputtered particles flying in an oblique direction with respect to the surface of the substrate 160 are collimated by the collimator 150. That is, by installing the collimator 150, the target 100 and the substrate 160 The collimator 150 is disposed between the substrate 160 and the substrate 160. The sputtering particles reach the substrate and are deposited on a surface parallel to the substrate. Particles do not accumulate on surfaces perpendicular to the substrate, or accumulate less on surfaces parallel to the substrate. Therefore, by using the above sputtering device, it is possible to obtain the results shown in Figs. 8(C) and 8(D). As shown, insulator 406c can be deposited on all surfaces except those perpendicular to the substrate.

[0146] In addition, the target 100 and the collimator 150, or the substrate 160 and the collimator 150 The vertical distance may be changed as appropriate depending on the quality of the film to be formed. As shown in FIG. 22, the movable portion 151 and the movable portion 152 may be provided. By having the collimator 150, it is possible to easily select whether or not to use the collimator 150. By having the movable portion 152, the collimator 150, the substrate 160 and the target 100 The vertical distance can be easily adjusted.

[0147] Also, a long-throw sputtering method can be used. In the dipping method, the vertical distance between the target 100 and the substrate 160 is increased, so that the sputtered particles The incident direction of the light on the substrate 160 can be made closer to perpendicular. Even if not used, the insulator 406c can be deposited on surfaces other than those perpendicular to the substrate. The vertical distance between the substrate 160 and the target 100 is set to 150 mm or more and 500 mm or less. Also, the collimator 150 may be combined with the long throw sputtering method. stomach.

[0148] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0149] Next, as shown in FIG. 8(E) and FIG. 8(F), the insulator that will become the insulator 412 and the conductor 40 A conductor that will become 4a and a conductor that will become 404b are formed.

[0150] First, an insulator to become the insulator 412 is formed over the insulator 410 and the insulator 406c. The insulating film that becomes the insulating layer 412 is formed by sputtering, CVD, MBE, or PLD. The deposition can be performed by using a deposition method, an ALD method, or the like.

[0151] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0152] Next, a conductor that will become the conductor 404a and the conductor 404b is formed. The conductive material to be the conductive material 404b may be formed by a sputtering method, a CVD method, an MBE method, or the like. The deposition can be performed by using a PLD method, an ALD method, or the like. The conductor that becomes 4b is formed so as to fill the opening formed by the insulator 410 etc. Therefore, it is preferable to use the CVD method (particularly the MCVD method). In order to improve the adhesion of the conductor formed by the ALD method, It may be preferable to laminate the conductive material with a CVD method. For example, titanium nitride A laminated film in which a layer of tungsten and a layer of silicon may be formed in this order may be used.

[0153] Next, as shown in FIG. 9(A) and FIG. 9(B), the insulator 410 is removed by a CMP process or the like. conductor 404a, conductor 404b, insulator 412, and insulator 406c are removed until In this case, the insulator 410 can be used as a stopper layer. Therefore, the thickness of the conductor 404a may be reduced in the completed transistor. The thickness of the insulator 410 is set to be sufficient so that the conductor 404b has a sufficiently low resistance. By designing the transistors in advance, it is possible to create multiple transistors with little variation. .

[0154] The CMP process may be performed once or multiple times. When performing MP processing, first polishing with a high polishing rate is performed, followed by finishing with a low polishing rate. It is preferable to perform polishing in this manner. This can further improve the flatness of the polished surface.

[0155] Next, a film of a conductor is formed to become the conductor 420. The conductor 420 may have a laminated structure. The conductive material to be the conductive material 420 may be formed by sputtering, CVD, MBE, or the like. This can be done using a PLD method, an ALD method, or the like. Then, a photolithography method or the like can be used. The conductive material 420 is formed by processing the conductive material 420 .

[0156] Next, as shown in FIG. 9(C) and FIG. 9(D), The insulator 408 is deposited. The insulator 408 can be deposited by a sputtering method, a CVD method, or an MBE method. The insulator 408 can be formed by a method such as a PLD method, an ALD method, or the like. By forming an aluminum oxide film using plasma containing oxygen as a The oxygen in the insulating layer 410 can be added to the top surface of the insulating layer 410 as excess oxygen (exO). In addition, excess oxygen is added to the insulator 408 by oxygen diffusing through the insulator 410. Therefore, at this time, excess is present near the film interface between the insulator 408 and the insulator 410. Oxygen-rich intermixed regions may form.

[0157] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0158] In addition, at some point after the formation of the insulator 408, a second heat treatment is performed. By performing the second heat treatment, the insulator 410 and the mixed region 414 may be heated. The excess oxygen contained in the insulator 412, the insulator 402, the insulator 406c, and the insulator 406a In this way, the excess oxygen passes through the semiconductor 406b and moves to the semiconductor 406b. Therefore, defects (oxygen vacancies) in the semiconductor 406b can be reduced.

[0159] The second heat treatment is performed to convert excess oxygen contained in the insulator 410 and the mixed region 414 into semiconductors. The temperature may be set to a temperature at which the fluorine-containing gas diffuses to the substrate 406b. For example, see the description of the first heat treatment. Alternatively, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20° C. or more and 150° C. or less, preferably The temperature is set to 40° C. or higher and 100° C. or lower. This allows excess oxygen to be released from the insulator 402 and the like. The second heat treatment can suppress the formation of each layer by performing the same heat treatment. In some cases, this step may not be necessary if the above-mentioned function can be achieved by heating during film formation.

[0160] Although not shown, the insulator 408 and the insulator 410 are provided with a conductor 416a and a conductor The openings are formed so as to reach the conductive body 416b, and conductive bodies that function as wiring are provided in the respective openings. Alternatively, an opening may be formed in the insulator 408 to reach the conductor 404, and the opening may be used as a wiring. The conductive material may be formed to function as a conductor.

[0161] In the above manner, the transistor shown in FIG. 1 can be manufactured.

[0162] Note that in this embodiment, one embodiment of the present invention has been described. In other words, in this and other embodiments, various Since clear embodiments have been described, the present invention is not limited to any particular embodiment. For example, In one embodiment of the present invention, an example in which an oxide semiconductor is used as a semiconductor is described. One aspect of the invention is not limited to this. In some cases or depending on the situation, the present invention One embodiment of the present invention is silicon, germanium, silicon germanium, silicon carbide, gallium. Arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc. This is also fine.

[0163] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0164] (Embodiment 2) <Transistor structure 2> In the following, a transistor with a different structure from that shown in FIG. 1 and a method for manufacturing the same will be described with reference to FIG. 2. FIG. 2 is a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 2(A) is a top view. FIG. 2(B) corresponds to the dashed line A1-A2 shown in FIG. FIG. 2(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 2(A). In the top view of FIG. 2(A), some elements are omitted for clarity. There are.

[0165] In this transistor, in FIG. 2B, the side surface of the insulator 410 is in contact with the top surface of the conductor 416a. 410 has an angle θ greater than 0 degrees and less than 90 degrees with respect to the The angle θ is 75 degrees or more and less than 90 degrees, preferably 80 degrees or more. The angle is preferably less than 90 degrees, more preferably 85 degrees or more and less than 90 degrees. In the region where the insulator 406c covers the side surface of the conductor 404 via the insulator 412, the insulator 406c covers the conductor 4 The insulator 406c is provided thinner than the area overlapping with the bottom surface of the insulating film 404. The other configurations are the same as those shown in FIG. Consider the transistor shown below.

[0166] <Transistor manufacturing method 2> First, the same steps are carried out up to FIG. 7 shown in the first embodiment.

[0167] Next, the side surface of the insulator 410 is rotated to an angle of 90 degrees, which is greater than 0 degrees, relative to the top surface of the conductor 416a. Next, the film forming apparatus described in the first embodiment is used to form the film having an angle θ of less than 100 nm. At this time, for example, the smaller the angle θ, the more the sputtered particles The probability of deposition increases, and the insulator 406c is formed thickly on the side of the insulator 410. In addition, the larger the angle θ, the thinner the insulator 406c is formed on the side surface of the insulator 410. Therefore, the thickness of the insulator 406c formed on the side of the insulator 410 is adjusted by the angle θ. In other words, by reducing L1, which is the width of the offset region to be formed, t1 is greater than L1, and L1 / t1 is less than 1.

[0168] The subsequent steps are the same as those in the manufacturing method 1 of the transistor described in Embodiment 1. Just do it.

[0169] In the above manner, the transistor shown in FIG. 2 can be manufactured.

[0170] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0171] (Embodiment 3) <Transistor structures 3 and 4> In the following, a transistor having a different structure from that shown in FIG. 1 and a method for manufacturing the same will be described with reference to FIG. 3 and 4 are top views and diagrams of a semiconductor device according to one embodiment of the present invention. A cross-sectional view is shown.

[0172] The transistors shown in FIGS. 3 and 4 will be described. Note that FIGS. 3(A) and 4(A) are FIG. 3(B) is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. FIG. 3(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 3(A). In the top view of FIG. 3(A), some elements are omitted for clarity.

[0173] FIG. 4B is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 4(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. In the top view of (A), some elements are omitted for clarity.

[0174] The transistors shown in FIGS. 3 and 4 include an insulator 406c2 (insulator 406c in FIG. 4), The edge 412, the conductor 404a, and the conductor 404b are disposed on a partial area of ​​the upper surface of the insulator 410. The other configurations are the same as those of the transistor shown in FIG.

[0175] The transistor shown in FIG. 3 and FIG. 4 includes a conductor 404a serving as a gate electrode and a conductor A part of the insulator 404b may function as a wiring. The conductor 404a and the conductor 404b are formed on the insulator 410 through the insulator 412. 04b corresponds to the conductor 420 in the transistor structure 1. In this case, t2 is the distance between the conductor 416a or the conductor 416b and the conductor 404 on the insulator 410. The vertical distance between the insulator 406c2, the insulator 412, and the conductor 404a Since the upper surface of the insulator 410 and the conductor 404b are formed at the same time, Between the conductor 404a formed on the upper side, an insulator 406c2 (insulator 406c in FIG. 4) is provided. and insulator 412. Therefore, t2 is the thickness of insulator 410 plus insulator 406 c2 (insulator 406c in FIG. 4) and the thickness of insulator 412 are added, Therefore, a sufficient distance can be provided, and parasitic capacitance can be suppressed.

[0176] <Transistor manufacturing methods 3 and 4> A method for manufacturing the transistor shown in FIGS.

[0177] First, the steps are carried out in the same manner as those shown in FIG. 8 in the first embodiment.

[0178] Next, the insulator 406c, the insulator 412, and the conductor 4 By using this structure, the transistor structure 1 is formed. The conductor corresponding to the conductor 420 in the above is formed by using the conductor 404a and the conductor 404b. , can be formed simultaneously.

[0179] Next, the insulator 408 is formed.

[0180] In the above manner, the transistor shown in FIG. 3 can be manufactured.

[0181] The transistor shown in FIG. 4 is manufactured by the same process as the transistor shown in FIG. The edge 406c, the insulator 412, the conductor 404a, and the conductor 404b are then deposited. , and the insulator 406c, the insulator 412, and the like having desired shapes are formed by using a photolithography method or the like. The conductor 404a and the conductor 404b are formed. The conductors corresponding to the conductor 420 in the structure 1 are conductor 404a and conductor 404b. can be simultaneously formed using

[0182] In the above manner, the transistor shown in FIG. 4 can be manufactured.

[0183] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0184] (Embodiment 4) <Transistor structures 5 and 6> In the following, a transistor having a different structure from that shown in FIG. 1 and a method for manufacturing the same will be described with reference to FIG. 5 and 6 are top views and diagrams of a semiconductor device according to one embodiment of the present invention. A cross-sectional view is shown.

[0185] The transistors shown in FIGS. 5 and 6 will be described. Note that FIGS. 5(A) and 6(A) are 5(B) is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. FIG. 5(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 5(A). In the top view of FIG. 5(A), some elements are omitted for clarity.

[0186] FIG. 6B is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 6(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. In the top view of (A), some elements are omitted for clarity.

[0187] In the transistor illustrated in FIG. 5 and FIG. 6, the conductor 416a and the conductor 416b are semiconductor 4 The other configurations are shown in Fig. 1 or Fig. 2. To pour drinks.

[0188] <Transistor manufacturing methods 5 and 6> A method for manufacturing the transistor shown in FIGS.

[0189] First, the steps are carried out similarly up to FIGS. 7(A) and 7(B) shown in the first embodiment.

[0190] Next, the insulator 406a and the semiconductor 406b are formed, and then the conductor 416 is formed. Then, a resist is formed on the conductor 416 by photolithography or the like, and the resist is Using the resist as a mask, a first etching is performed on the conductor 416. Next, the resist is removed. After the etching, a second etching is performed using the conductor 416 as a mask. , insulator 406a, and semiconductor 406b.

[0191] The subsequent steps are similar to those in the first embodiment shown in FIG. 7(G) and FIG. 7(H) and subsequent steps. In the above manner, the transistor shown in FIG. 5 can be manufactured.

[0192] 6 also includes an insulator 406a, as in the transistor shown in FIG. , a semiconductor 406b, and a conductor 416 are formed. The transistor may be manufactured using the process described above.

[0193] In the above manner, the transistor shown in FIG. 6 can be manufactured.

[0194] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0195] (Embodiment 5) <Transistor structure 7> A structure of a transistor included in a semiconductor device according to one embodiment of the present invention will be described below. do.

[0196] 10A, 10B, and 10C are top views of a semiconductor device according to one embodiment of the present invention. 10(A) is a cross-sectional view. FIG. 10(B) is a top view. FIG. 10(A) is a cross-sectional view. FIG. 10(C) is a cross-sectional view corresponding to the dashed line A1-A2, showing the cross-sectional shape in the channel length direction. 10(A) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 10(A), and is a cross-sectional view in the channel width direction. In the top view of FIG. 10(A), some elements are shown in order to clarify the drawing. It is omitted in the illustration.

[0197] The transistor shown in FIG. 10 includes a conductor 413 and an insulator 401 on a substrate 400, and a conductive an insulator 402 on the body 413 and the insulator 401; and an insulator 406a on the insulator 402. A semiconductor 406b on an insulator 406a and a conductive layer having a region in contact with the upper surface of the semiconductor 406b. The upper surface of the insulator 402, the upper surface of the conductor 416a, and the conductor 416b. The insulator 410 having an opening and in contact with the upper surface of the conductor 416b, the side surface of the conductor 416a, the semiconductor An insulator 406c is in contact with the top and side surfaces of the conductor 406b, and an insulator 406c is on the insulator 406c. 06d, and an insulator 412 in contact with the upper surface of the insulator 406d and the side surface of the opening of the insulator 410. and on the semiconductor 406b via the insulator 412, the insulator 406c, and the insulator 406d. The conductor 404 has a conductor 404a and a conductor 404b. The conductor 404b is connected to the opening of the insulator 410 via the conductor 404a and the insulator 412. In addition, the conductor 404a and the conductor 404b are disposed on the transistor. 4, has a conductor 420 on top, and an insulator 412 and an insulator 408 on the conductor 420 . As shown in FIG. 56(A), FIG. 56(B), and FIG. 56(C), the conductor 413 and The conductor 413 and the insulator 401 are not essential components, and a configuration without the conductor 413 and the insulator 401 may be used. You may do so.

[0198] The insulators 406c and 406d are each an insulator containing an element other than oxygen that is included in the semiconductor 406b. It is preferable to have at least one of the semiconductor 406b and the insulator 406c. , and at the interfaces of the insulator 406c and the insulator 406d, defects are generated. In addition, the crystallinity of the insulators 406c and 406d can be improved. It can be done.

[0199] The semiconductor 406b and the insulator 406c preferably include a CAAC-OS, which will be described later. Furthermore, the insulator 406d also preferably has a CAAC-OS. It is preferred that 06a also has CAAC-OS.

[0200] In this transistor, the conductors 404a and 404b function as a first gate electrode. In addition, at least one of the conductors 404a and 404b is impermeable to oxygen. For example, the lower layer conductor 404 is preferably made of a conductor that is less permeable to oxygen. By forming the conductive material 404b as a, it is possible to prevent a decrease in the conductivity due to oxidation of the conductive material 404b. The insulator 412 also functions as a first gate insulator.

[0201] The conductor 413 also functions as a second gate electrode. It is also possible to use a laminated structure including a conductive material that is difficult for oxygen to permeate. By using a layered structure including a conductor with low oxidation properties, the decrease in conductivity due to oxidation of the conductor 413 can be prevented. The insulator 402 functions as a second gate insulator. The threshold voltage of the transistor can be controlled by the potential applied to 3. By electrically connecting the first gate electrode and the second gate electrode, the current (ON The current (current) can be increased. It is acceptable for the functions of and to be interchangeable.

[0202] The conductor 416a and the conductor 416b serve as a source electrode and a drain electrode. The conductivity of a conductor can be measured using the two-terminal method, for example.

[0203] The resistance of the semiconductor 406b can be controlled by applying a potential to the conductor 404. That is, the potential applied to the conductor 404 causes a conduction between the conductor 416a and the conductor 416b. Conduction / non-conduction can be controlled.

[0204] As shown in FIG. 10B, the top surface of the semiconductor 406b is covered with the conductor 416a and the conductor 416b. In addition, the electric field of the conductor 404, which functions as a gate electrode, The electric field of the gate electrode electrically surrounds the semiconductor 406b. The structure of the transistor that surrounds the Therefore, a channel may be formed in the entire semiconductor 406b. In the s-channel structure, a large current flows between the source and drain of the transistor. This allows the current flow when the semiconductor is conductive (ON current) to be increased. Since 06b is surrounded by the electric field of the conductor 404, the current (O The current (f) can be reduced.

[0205] In the transistor of this embodiment, a region functioning as a gate electrode is formed on the insulator 410. It is self-aligned to fill the openings formed by the above. Therefore, TGSA s-channel FET (Trench Gate Select f Align s-channel FET).

[0206] In FIG. 10B, the upper surface of the semiconductor 406b in the region overlapping with the conductor 404 and the conductor The length between the bottom surface of the semiconductor 404 and the bottom surface of the semiconductor 404 is t1. 6b, the area overlapping the bottom surface of the conductor 416a and the area overlapping the bottom surface of the conductor 404. The length between the area overlapping the bottom surface of the conductor 416b and the area overlapping the bottom surface of the conductor 416c is L1. The length between the area overlapping with the bottom surface of 04 is L1.

[0207] In the transistor, the region in which the channel is formed in the semiconductor 406b (the conductor 40 4 and the semiconductor 406b) and a source region or a drain region (conductor 416 a or a region where the conductor 416b and the semiconductor 406b overlap each other) and a region L1 is formed between the conductor 416b and the semiconductor 406b. By providing this region, the off-state current of the transistor can be reduced. If the area is too large, it will reduce the on-current of the transistor.

[0208] The region in which the channel of the semiconductor 406b is to be formed is surrounded by the insulator 406c and the insulator 406b. By covering the region where the channel is to be formed with 06d, the oxygen that constitutes the adjacent insulator is not absorbed into the region. It can block elements (hydrogen, silicon, etc.) from entering. The insulator 406c and the insulator 406d are formed on at least the semiconductor 406b. Good.

[0209] Therefore, the insulator 406c and the insulator 406d are connected to the conductor 404 via the insulator 412. Alternatively, the insulator 406c and the insulator 406d may be provided on the insulator 412. The region covering the side of the conductor 404 is covered by the insulator 406c and the insulator 406d. The insulators 406c and 406b are arranged in a region overlapping the bottom surface of the body 404 through the insulator 412. By making the insulator 406d thin, L1 can be made small. is greater than L1, and L1 / t1 is less than 1.

[0210] In addition, in FIG. 10B and FIG. 11A, the conductor 416a or the conductor 416b The length between the conductor 41 and the conductor 420 is t2. The length between 6a and the conductor 416b is L2.

[0211] As transistors become smaller, the parasitic capacitance near the transistor becomes too large to be ignored. For example, between the conductor 420 and the conductor 416a or conductor 416b The parasitic capacitance may be formed near the region where the channel is formed. If the parasitic capacitance is not charged, the transistor operation requires time. This reduces the response of the transistor and therefore the response of the semiconductor device. In circuits that use multiple transistors, unnecessary power is consumed to supply power. Therefore, for t2, the parasitic capacitance is negligible compared to the gate capacitance. It is preferable that the length is sufficient so that the

[0212] In addition, as transistors are miniaturized, L2 becomes smaller, and the conductor 404a and However, it becomes difficult to apply a sufficient voltage to the conductor 404b. By designing the length of the conductor 404a and the conductor 404b to be appropriate, the resistance of the conductor 404a and the conductor 404b can be reduced. Therefore, t2 should be greater than L2, and preferably t2 / L2 should be 1.5 or greater. It is recommended to set it to 2 or less.

[0213] The transistor according to the present embodiment shown in FIG. 11(A) and FIG. 11(B) has an insulator 41 4 shows an enlarged view of an opening provided in the insulating body 406d. The height of the upper surface of the insulating body 406d is the same as that of the conductor 416a. The height of the insulator 406d may be the same as the top surface of the conductor 416b. The top surface is the area where the insulator 406d overlaps with the bottom surfaces of the conductor 404a and the conductor 404b. In this case, the surface is the surface close to the conductor 404a. Ideally, as shown in FIG. The upper surface of the body 406d is at the same height as the upper surfaces of the conductors 416a and 416b. is preferred.

[0214] The height of the top surface of the insulator 406c is the height of the semiconductor 406b, the conductor 416a, and the conductor It is preferable that the height of the upper surface of the insulator 406c is about the same as the interface of the insulator 406b. In the region where the insulator 406c overlaps with the bottom surfaces of the conductor 404a and the conductor 404b, Ideally, the top surface of the insulator 406c is the surface closest to the semiconductor 404a. 6b is preferably at the same height as the interface between the conductor 416a and the conductor 416b. However, the insulator 406c is at least partially removed by over-etching the semiconductor 406b. As shown in FIG. 11(B), the upper surface of the insulator 406c is a semiconductor. The conductor 406b may be located above the interface between the conductor 416a and the conductor 416b. It won't turn.

[0215] In the transistor of this embodiment, the insulator 406c is formed on the semiconductor 406b. In the above embodiment, two layers of the insulating material 406a and the insulating material 406b are provided. However, the present invention is not limited to this, and may be applied to a laminated structure of three or more layers. It may also be of this structure.

[0216] The substrate 400 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, and a stabilized zirconia substrate. There are also semiconductor substrates, such as zirconia substrates stabilized with yttria, and resin substrates. The substrate may be, for example, a single semiconductor substrate such as silicon or germanium, or a silicon carbide substrate. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates made of insulating material. A semiconductor substrate having, for example, an SOI (Silicon On Insulator) substrate Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. Further, a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or a semiconductor is provided on a semiconductor substrate, There are substrates with an insulator, and substrates with a semiconductor or insulator on a conductor substrate. Alternatively, a substrate having elements provided thereon may be used. Examples of the elements include a capacitance element, a resistance element, a switch element, a light-emitting element, and a memory element.

[0217] A flexible substrate may be used as the substrate 400. The method of providing the transistor is to fabricate the transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to the flexible substrate 400. A peeling layer may be provided between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil having woven fibers may be used. The substrate 400 may be stretchable. Also, the substrate 400 may be designed to retain its original shape when the bending or pulling is stopped. The substrate 4 may have a property of returning to its original shape. Alternatively, the substrate 4 may have a property of not returning to its original shape. 00 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less; More preferably, the substrate 400 has a region having a thickness of 15 μm or more and 300 μm or less. By making the substrate thinner, the weight of the semiconductor device having the transistor can be reduced. By making 00 thinner, it can be stretched even when using glass, and can be easily folded or folded. It may have the property of returning to its original shape when you stop pulling it. Therefore, it is possible to reduce the impact applied to the semiconductor device on the substrate 400. It is possible to provide a semiconductor device.

[0218] The substrate 400, which is a flexible substrate, may be made of, for example, a metal, an alloy, a resin, or a glass. The substrate 400, which is a flexible substrate, has a linear expansion coefficient of 1.0. The lower the coefficient of thermal expansion, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester or polystyrene. Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, so it is suitable for flexible substrates. 400 is preferable.

[0219] The transistor is made of an insulator that has a function of blocking impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator, the electrical characteristics of the transistor can be stabilized. 408 is an insulator that has the function of blocking impurities such as hydrogen and oxygen. Good.

[0220] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in a single layer or in a multilayer.

[0221] For example, the insulator 408 may be aluminum oxide, magnesium oxide, or nitride oxide. Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide The material may be zinc oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide. The insulator 408 preferably contains aluminum oxide. The insulator 408 is formed by depositing an insulating film that serves as a base layer for the insulator 408 using plasma containing oxygen. Oxygen can be added to the body 410 or to the side of the insulator 412. The added oxygen can be excess oxygen in the insulator 410 or in the insulator 412. The insulator 408 contains aluminum oxide, which prevents impurities such as hydrogen from entering the semiconductor 406b. In addition, for example, if the insulator 408 is made of aluminum oxide, the insulator 408 can be prevented from being contaminated by foreign matter. By having the insulator, the excess oxygen added to the insulator 410 and the insulator 412 can be prevented from being outwardly dispersed. Diffusion can be reduced.

[0222] The insulator 402 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 402 may be made of silicon oxide or oxide. It is preferable to have silicon nitride.

[0223] It is preferable that the insulator 410 has a low dielectric constant. 410 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with , silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the material includes silicon, silicon oxide having voids, or resin. Alternatively, The insulator 410 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide The laminated structure may include a silicon oxide layer or a silicon oxide layer having voids, and a resin layer. Silicon oxide and silicon oxynitride are preferred because they are thermally stable and can be easily combined with resin. By combining these resins, it is possible to obtain a laminated structure that is thermally stable and has a low relative dielectric constant. For example, polyester, polyolefin, polyamide (nylon, aramid, etc.) , polyimide, polycarbonate or acrylic.

[0224] The insulator 412 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 412 may be a silicon oxide or an oxide film. It is preferable to have silicon nitride.

[0225] It is preferable that the insulator 412 has a high relative dielectric constant. For example, 412 is a gallium oxide, hafnium oxide, and oxide with aluminum and hafnium. oxide nitrides with aluminum and hafnium, oxide nitrides with silicon and hafnium It is preferred to have a silicon oxide having hafnium or an oxide nitride having silicon and hafnium. Alternatively, the insulator 412 may be a material having a dielectric constant of silicon oxide or silicon oxynitride. It is preferable to have a laminate structure of silicon oxide and silicon oxynitride. Since PO is thermally stable, it can be combined with an insulator with a high dielectric constant to produce a thermally stable For example, aluminum oxide, gallium oxide, etc. By providing hafnium oxide or hafnium oxide on the insulator 406c and the insulator 406d side, Silicon contained in silicon oxide or silicon oxynitride is mixed into the semiconductor 406b. In addition, for example, silicon oxide or silicon oxynitride can be used. By providing the insulating layer 406c and the insulating layer 406d, the aluminum oxide and the gas oxide can be effectively prevented from being deteriorated. A tracer is formed at the interface between hafnium or hafnium oxide and silicon oxide or silicon oxynitride. A trap center may be formed. The trap center can trap electrons. In some cases, the threshold voltage of a transistor can be shifted in the positive direction.

[0226] The conductor 416a and the conductor 416b may be, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver Conductors containing one or more of indium, tin, tantalum and tungsten are used in a single layer or in a For example, an alloy film or a compound film may be used, and a film containing aluminum may be used. Conductors containing copper and titanium, conductors containing copper and manganese, indium, Conductors containing tin and oxygen, or conductors containing titanium and nitrogen, etc. may also be used. .

[0227] The conductor 404, the conductor 413, and the conductor 420 may include, for example, boron, nitrogen, oxygen, etc. , fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel Kel, Copper, Zinc, Gallium, Yttrium, Zirconium, Molybdenum, Ruthenium, Silver Conductors containing one or more of indium, tin, tantalum and tungsten are used in a single layer or in a For example, an alloy film or a compound film may be used, and a film containing aluminum may be used. Conductors containing copper and titanium, conductors containing copper and manganese, indium, Conductors containing tin and oxygen, or conductors containing titanium and nitrogen, etc. may also be used. .

[0228] The semiconductor 406b is preferably an oxide semiconductor. (including silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, Aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors There are cases where this is acceptable.

[0229] The insulators 406a, 406c, and 406d are made of the semiconductor 406b. It is preferable to use an oxide composed of one or more elements other than oxygen that constitutes the oxide. However, silicon (including strained silicon), germanium, silicon germanium, Silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride In some cases, a polymer or organic semiconductor may be used.

[0230] The semiconductor 406b is, for example, an oxide semiconductor containing indium. For example, the inclusion of indium increases carrier mobility (electron mobility). 406b preferably contains the element M. The element M is preferably aluminum, gallium, or the like. , yttrium, or tin. Other elements that can be used for M include ho, Uranium, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, la Tantalum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, as the element M, a combination of two or more of the above elements may be used in some cases. The element M is, for example, an element having a high bond energy with oxygen. The element M is an element having a higher energy than indium. Alternatively, the element M is, for example, an oxide semiconductor. The semiconductor 406b is an element that has the function of increasing the energy gap of the It is preferable that the oxide semiconductor contains zinc. When the oxide semiconductor contains zinc, it may be easily crystallized.

[0231] However, the semiconductor 406b is not limited to an oxide semiconductor containing indium. 6b is a zinc-free oxide such as zinc tin oxide or gallium tin oxide. Oxide semiconductors containing lead, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. That's okay.

[0232] The semiconductor 406b is made of, for example, an oxide having a large energy gap. The energy gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 The excitation voltage is preferably from 3 eV to 3.5 eV, and more preferably from 3 eV to 3.8 eV.

[0233] The insulators 406a, 406c, and 406d constitute the semiconductor 406b. Semiconductors are oxides that consist of one or more elements other than oxygen. 06b, one or more elements other than oxygen, or two or more elements, which constitute the insulator 406a, insulator Since the insulator 406a, the semiconductor 406b, and the insulator 406c are formed, the interface between the semiconductor 406b and the insulator 406c, the interface between the insulator 406c and the insulator 406d Defect levels are unlikely to be formed at the interface.

[0234] The semiconductor 406b has higher electronic conductivity than the insulators 406a, 406c, and 406d. For example, an oxide having a high affinity is used as the semiconductor 406b. the electron affinity is 0.07 eV or more and 1.3 eV or less than that of the body 406c and the insulator 406d; Preferably, the voltage is 0.1 eV or more and 0.7 eV or less, and more preferably, the voltage is 0.15 eV or more and 0.4 eV or less. V or less. The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band. In addition, the insulator 406c has a larger electron affinity than the insulator 406d. preferable.

[0235] In this manner, the insulator 406a, the insulator 406c, and the insulator 406b are disposed above and below the semiconductor 406b. When a gate voltage is applied to the transistor having the insulator 406a and the semiconductor Among the conductor 406b, the insulator 406c, and the insulator 406d, the semiconductor having the larger electron affinity is A channel is formed in the body 406b. In this way, a so-called buried channel structure is formed. It is possible.

[0236] Here, between the insulator 406a and the semiconductor 406b, In addition, between the semiconductor 406b and the insulator 406c, In some cases, the semiconductor 406b and the insulator 406c are mixed. Between the insulator 406c and the insulator 406d, there is a mixed region of the insulator 406c and the insulator 406d. In some cases, the mixed region has a low defect level density. The laminate of the insulating layer 406b, the insulating layer 406c, and the insulating layer 406d has the following characteristics in the vicinity of the interface between the insulating layer 406b, the insulating layer 406c, and the insulating layer 406d: The energy changes continuously (also called a continuous junction). The interfaces of the insulating material 406b, the insulating material 406c, and the insulating material 406d can be clearly distinguished. There may not be.

[0237] At this time, the electrons are not in the insulators 406a, 406c, and 406d, but in the It moves mainly through semiconductor 406b.

[0238] The on-current of a transistor can be increased by reducing the factors that inhibit the movement of electrons. The movement of electrons is also hindered, for example, when the channel formation region has large physical irregularities. will be done.

[0239] In order to increase the on-current of the transistor, for example, the upper or lower surface of the semiconductor 406b (the surface to be formed, here the upper surface of the insulator 406a) Root mean square (RMS) roughness less than 1 nm, preferably It is preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in an area of ​​1 μm × 1 μm is 1 nm. less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably 0 The maximum height difference (PV and ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, The RMS roughness, Ra and PV are preferably less than 7 nm. Using a scanning probe microscope system SPA-500 manufactured by Nano Technology Co., Ltd. It can be measured.

[0240] The four-layer structure described above is an example. For example, the upper or lower layer of the insulator 406a or the lower layer of the insulator 406b may be 06d, as insulator 406a, insulator 406c, and insulator 406d. A laminated structure having one or more of the insulators exemplified above may also be used.

[0241] Note that an oxide semiconductor that can be used as a semiconductor will be described in detail in other embodiments. I will explain in detail.

[0242] <Transistor manufacturing method 7> A method for manufacturing the transistor of FIG. 10 according to the present invention will be described below with reference to FIGS. Reveal.

[0243] First, a substrate 400 is prepared.

[0244] Next, as shown in FIG. 18(A) and FIG. 18(B), an insulating film that will become an insulator 401 is formed on the substrate 400. An opening is formed in the insulator 401, and a conductor that becomes the conductor 413 is formed on the insulator 401. The conductive material to be the conductive material 413 is formed by a sputtering method, a CVD method, a M method, etc. The deposition can be performed by using a BE method, a PLD method, an ALD method, or the like. It may be a multi-layer structure including a conductive material that is difficult for oxygen to permeate. Chemical Mechanical Polishing (CMP) and other techniques are used. The conductor 413 may be embedded in the opening of the insulator 401. The method is to form a conductor film and process it using a photolithography method or the like. may be formed.

[0245] In the photolithography method, first, the resist is exposed to light through a mask. The exposed areas are removed or left behind using a developer to form a resist mask. Then, a conductor, a semiconductor, or an insulator is formed by etching the resist mask. For example, KrF excimer laser light, ArF excimer laser light, etc. can be processed into the desired shape. Using laser light, extreme ultraviolet (EUV) light, etc. A resist mask may be formed by exposing the resist. A liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the light source for exposure. Instead of light, an electron beam or an ion beam may be used. If a mask is used, the mask is not necessary. Dry etching such as dipping, wet etching, or After dry etching, wet etching is performed, or wet etching is performed. After the treatment, a dry etching treatment can be performed.

[0246] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. Capacitively Coupled Plasma (CAP) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be A high-frequency power source may be applied to one of the electrodes. A configuration in which a plurality of different high frequency power sources are applied to the electrodes may be used. Alternatively, a high-frequency power source having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a high-frequency power source having a high-density plasma source may be used. Dry etching equipment with a high density plasma source can be used. The device is, for example, an inductively coupled plasma (ICP) d Plasma etching equipment or the like can be used.

[0247] Next, as shown by the arrows in FIG. 18(A) or (B), a high-density plasma treatment may be performed. The high-density plasma treatment is preferably carried out in an oxygen atmosphere or a nitrogen atmosphere. is a gas atmosphere containing oxygen atoms, such as oxygen, ozone or nitrogen oxides (nitric oxide). , nitrogen dioxide, nitrous oxide, dinitrogen trioxide, dinitrogen tetroxide, dinitrogen pentoxide, etc.) atmosphere In addition, in an oxygen atmosphere, nitrogen or rare gas (helium, argon, etc.) Inert gas may be included. In this way, high density plasma processing in an oxygen atmosphere is performed. For example, carbon, hydrogen, etc. can be desorbed by the above method. By performing plasma treatment, organic compounds such as hydrocarbons can be easily desorbed from the object to be treated. water.

[0248] The high density plasma treatment in a nitrogen atmosphere may be carried out in an atmosphere containing nitrogen and a rare gas, or in an atmosphere containing nitrogen, hydrogen and a rare gas, or in an atmosphere containing ammonia and a rare gas. The high-density plasma treatment can be performed by using the above-mentioned high-density plasma. The area to be nitrided can be formed very thinly on the surface side of the workpiece. Moreover, the nitrided region can suppress the diffusion of impurities.

[0249] The high-density plasma treatment may be performed in an oxygen atmosphere and then in a nitrogen atmosphere. After the treatment in the nitrogen atmosphere, the treatment in the oxygen atmosphere may be performed. Annealing may be performed before or after the treatment. In some cases, it may be preferable to flow an adequate amount of gas. If the amount of gas is not sufficient, radical generation may occur. For example, if the gas is 100 sccm or more and 30 Flows of 0 sccm or more or 800 sccm or more may be preferred.

[0250] High-density plasma processing is performed, for example, at frequencies of 0.3 GHz to 3.0 GHz, 0.7 GHz, etc. z or higher and up to 1.1 GHz, or 2.2 GHz or higher and up to 2.8 GHz (typically 2.4 The microwave generated by a high frequency generator (5 GHz) can be used. The pressure is 10 Pa or more and 5000 Pa or less, preferably 200 Pa or more and 1500 Pa or less, and Preferably, the pressure is 300 Pa or more and 1000 Pa or less, and the substrate temperature is 100° C. or more and 600° C. or less ( Typically, the reaction can be performed at a temperature of 400° C. using a mixed gas of oxygen and argon.

[0251] The high-density plasma is generated by using, for example, 2.45 GHz microwaves. Electron density is 1×10 11 / cm 3 More than 1×10 13 / cm 3 Below, electron temperature is 2 eV or less It is preferable to carry out such a high-density plasma treatment with an ion energy of 5 eV or less. The kinetic energy of radicals is small, and the plasma treatment is more effective than conventional plasma treatment. This results in less damage to the film, which has fewer defects. The distance from the generating antenna to the object to be treated is 5 mm or more and 120 mm or less, preferably 20 It is recommended that the thickness be between 60 mm and 60 mm.

[0252] Alternatively, a plasma that applies an RF (Radio Frequency) bias to the substrate side The frequency of the RF bias may be, for example, 13.56 MHz or 27.1 By using high-density plasma, high-density oxygen ions can be generated. By applying an RF bias to the substrate, the device is generated by high-density plasma. The oxygen ions can be efficiently guided to the workpiece. It is preferable to perform high density plasma treatment while applying heat.

[0253] In addition, after the high-density plasma treatment, annealing was performed continuously without exposure to the atmosphere. In addition, the high-density plasma treatment may be performed continuously after the annealing treatment without exposing the substrate to the atmosphere. The high density plasma treatment and the annealing treatment may be performed in succession. This can prevent impurities from being mixed in during processing. After the treatment, an annealing treatment is performed to remove the oxygen from the workpiece. It is possible to eliminate unnecessary oxygen that has not been used to compensate for the oxygen vacancies. The annealing process may be performed by, for example, lamp annealing.

[0254] In addition, the processing time for high-density plasma treatment is from 30 seconds to 120 minutes, or from 1 minute to 90 minutes. , preferably from 2 to 30 minutes, or from 3 to 15 minutes.

[0255] Annealing should be performed at temperatures between 250°C and 800°C, between 300°C and 700°C, or between 400°C and 800°C. Treatment time at 00°C or higher and 600°C or lower is 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less, It is preferable to set the time to between 2 and 30 minutes, or between 3 and 15 minutes.

[0256] Next, the insulator 402 is formed. The insulator 402 is formed by a sputtering method, a chemical vapor deposition method, or the like. Chemical Vapor Deposition (CVD) method, molecular beam epitaxy Molecular Beam Epitaxy (MBE) method or pulse laser Pulsed Laser Deposition (PLD), Atomic Layer Deposition ( This can be done using methods such as ALD (Atomic Layer Deposition). can.

[0257] The CVD method is a method that uses plasma CVD (PECVD: Plasma ECVD). enhanced CVD method, and thermal CVD (TCVD: Thermal CVD) method D) method, photo CVD method, etc. Depending on the source gas, metal CVD (MCVD) method, metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0258] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device etc. may become charged up by receiving an electric charge from the plasma. Accumulated electric charges can destroy wiring, electrodes, elements, etc., contained in semiconductor devices. On the other hand, in the case of the thermal CVD method that does not use plasma, the above-mentioned exposure to plasma Since no damage caused by the above-mentioned occurs, the yield of semiconductor devices can be increased. In addition, with thermal CVD, the film is not exposed to plasma during deposition, so the film has fewer defects. Easy to obtain.

[0259] In addition, the ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. Obtained.

[0260] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less susceptible to the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of films with high aspect ratios. It is suitable for coating the surface of a high opening. However, the ALD method has a slow film formation speed. Therefore, it is preferable to use it in combination with other film formation methods such as CVD, which has a high film formation rate. In some cases, this is not possible.

[0261] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0262] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0263] Further, a treatment for adding oxygen to the insulator 402 may be performed. The method includes, for example, an ion implantation method and a plasma treatment method. The oxygen removed becomes excess oxygen.

[0264] Next, as shown in FIG. 18(C) and FIG. 18(D), the insulator 406a, the semiconductor A semiconductor that will become the body 406b and a resist mask 430 are formed.

[0265] First, an insulator that will become the insulator 406a is formed over the insulator 402. The insulator film is formed by sputtering, CVD, MBE, PLD, ALD, etc. In particular, the deposition can be performed using a facing target sputtering device. In this specification and the like, the term "facing target type sputtering apparatus" is used. The deposition method using this method is also called VDSP (vapor deposition SP). can.

[0266] By depositing an insulator using a facing target sputtering device, This reduces plasma damage in the film, thereby reducing oxygen vacancies in the film. In addition, by using a facing target sputtering device, film formation in a high vacuum is possible. This allows the concentration of impurities (e.g. hydrogen, rare gas (argon, etc.)) in the deposited insulator to be ), water, etc.) can be reduced.

[0267] Also, a sputtering device having an inductively coupled antenna conductor plate may be used. This allows for a high film formation speed and the formation of a film with a large area and high uniformity.

[0268] The film is preferably formed using a gas containing oxygen, a rare gas, a gas containing nitrogen, or the like. Gases that contain nitrogen (N2), nitrous oxide (N2O), ammonia (NH3 ) etc. can be used.

[0269] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0270] In addition, a process of adding oxygen to the insulator that will become the insulator 406a may be performed. The treatment for adding the insulating material 406a includes ion implantation and plasma treatment. The oxygen added to the insulator becomes excess oxygen.

[0271] Next, a semiconductor film that will become the semiconductor 406b is formed on the insulator that will become the insulator 406a. The film is formed by sputtering, CVD, MBE, PLD, ALD, etc. In particular, it is possible to form a film using a facing target sputtering apparatus. preferable.

[0272] By depositing semiconductor films using a facing target sputtering device, This reduces plasma damage in the film, thereby reducing oxygen vacancies in the film. In addition, by using a facing target sputtering device, film formation in a high vacuum is possible. This allows the concentration of impurities (e.g. hydrogen, rare gas (argon, etc.)) in the deposited semiconductor to be ), water, etc.) can be reduced.

[0273] Also, a sputtering device having an inductively coupled antenna conductor plate may be used. This allows for a high film formation speed and the formation of a film with a large area and high uniformity.

[0274] The film is preferably formed using a gas containing oxygen, a rare gas, a gas containing nitrogen, or the like. Gases that contain nitrogen (N2), nitrous oxide (N2O), ammonia (NH3 ) etc. can be used.

[0275] Next, a first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. The first heat treatment is preferably performed at a temperature of 450° C. or higher and 600° C. or lower. or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed under an inert gas atmosphere. After heat treatment in an atmosphere, oxidizing gas is added at 10 ppm or more and 1 % or more, or 10% or more. This can improve the crystallinity of a semiconductor and remove impurities such as hydrogen and water. Alternatively, the first heat treatment may be performed using a plasma treatment containing oxygen under reduced pressure. The plasma treatment includes, for example, a power source that generates high-density plasma using microwaves. It is preferable to use a device that can perform the same process as the above. y) A plasma power supply for applying a voltage may be provided. By using high density plasma, By applying RF voltage to the substrate, high density printing can be achieved. The oxygen radicals generated by the plasma can be efficiently guided into the semiconductor 406b. Alternatively, the apparatus can be used to supplement the oxygen released after plasma treatment containing an inert gas. In order to achieve this, a plasma treatment containing oxygen may be performed.

[0276] Next, as shown in FIG. 18(E) and FIG. 18(F), the insulator that will become the insulator 406a and A semiconductor to be a semiconductor 406b is formed by photolithography using a resist mask 430. For example, a multilayer film having an insulator 406a and a semiconductor 406b is formed. When forming a multilayer film, the insulator 402 may also be etched and some regions may become thin. That is, the insulator 402 may have a shape having a protrusion in the region in contact with the multilayer film. do.

[0277] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0278] Next, as shown in FIG. 18(G) and FIG. 18(H), the conductor 416 and the insulator 410 are This forms an insulator.

[0279] First, the conductor 416 is formed. The conductor 416 can be formed by a sputtering method, a CVD method, or the like. This can be carried out by using the MBE method, the PLD method, the ALD method, or the like.

[0280] The conductor 416 is formed to cover the multilayer film. Damage was caused to the side surface of 406a, the top surface of semiconductor 406b, and a part of the side surface of semiconductor 406b. By providing the insulating material 406a, a region having a low resistance may be formed. Since a part of the semiconductor 406b has a region with reduced resistance, the conductor 416 and the semiconductor 40 The contact resistance between 6b and can be reduced.

[0281] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0282] Then, the conductive material 416a and the conductive material 416b are processed by photolithography or the like. Form 6b.

[0283] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0284] Next, a film of an insulator that will become the insulator 410 is formed. The film of the insulator that will become the insulator 410 is formed by a spat This can be done using methods such as CVD, MBE, PLD, and ALD. Alternatively, it can be applied by spin coating, dipping, droplet ejection (inkjet method, etc.), printing, etc. Printing method (screen printing, offset printing, etc.), doctor knife method, roll coater method, etc. Alternatively, a curtain coater method or the like can be used.

[0285] The insulator that becomes the insulator 410 may be formed so as to have a flat upper surface. For example, The insulating material that becomes the edge 410 may have a flat upper surface immediately after deposition. For example, the insulator that becomes the insulator 410 is insulated so as to be parallel to a reference plane such as the back surface of the substrate after film formation. The planarization may be achieved by removing the substrate from the top surface. The planarization process is called "processing". Examples of planarization processes include chemical mechanical polishing and dry etching. However, the top surface of the insulator that will become insulator 410 does not need to be flat.

[0286] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0287] Next, a resist mask is formed on the insulator 410 by photolithography or the like. Here, a gap 431 is formed between the upper surface of the insulator 410 and the resist mask. In order to improve adhesion, for example, an organic coating film is formed on the insulator 410 and the resist. It may be provided between the masks.

[0288] Next, as shown in FIG. 19(A) and FIG. 19(B), the insulator 410 and the conductor 416 are First, the insulator that will become the insulator 410 is etched by a method such as dry etching. The first process is performed until the top surface of the conductor 416 is reached. An etching device can be used, but the parallel plate electrodes are each equipped with high-frequency It is preferable to use a dry etching device that is connected to a frequency power source.

[0289] Next, the conductor 416 is subjected to a second process using a dry etching method or the like to form a conductive The insulator 410 is separated into a conductor 416a and a conductor 416b. The process for forming the conductive material 416 and the process for forming the conductive material 416 may be performed in a common photolithography process. No problem. By standardizing the photolithography process, the number of steps can be reduced. Therefore, the productivity of a semiconductor device having a transistor can be increased. Cut.

[0290] At this time, the semiconductor 406b has an exposed area. A portion of the exposed semiconductor 406b may be removed by the second process described above. Impurity elements such as residual components of the etching gas may adhere to the surface of the substrate. If chlorine gas is used as the etching gas, chlorine and other substances may adhere to the surface. If a hydrocarbon gas is used, carbon, hydrogen, etc. may adhere to the gas. In this case, it is preferable to reduce impurity elements attached to the exposed surface of the semiconductor 406b. The reduction of impurities can be achieved by, for example, cleaning using dilute hydrofluoric acid or cleaning using ozone. Alternatively, a cleaning process using ultraviolet light or the like may be used. This may form an exposed surface of the semiconductor 406b, in other words, a channel. The area where the current is applied becomes highly resistive.

[0291] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0292] Next, as shown in FIG. 19(C) and FIG. 19(D), at least the side surface of the insulator 410 is removed. The top and side surfaces of the semiconductor 406b, the side surface of the insulator 406a, the top surface of the insulator 402, An insulator 406c is formed on the top surface of the insulator 410. Note that the insulator 406c is a semiconductor It is preferable to form the insulator 406c so as to fill the recess formed in the insulator 406b. The film can be formed by sputtering.

[0293] Here, a sputtering apparatus used for depositing the insulators 406c and 406d will be described. This will be described with reference to FIG. 21 and FIG.

[0294] FIG. 21 is a cross-sectional view showing a part of the sputtering apparatus 101. The ring device 101 includes a member 190, a collimator 150 disposed on the member 190, and a A target holder 120 and a backing plate 110 disposed on the target holder 120 10, a target 100 arranged on a backing plate 110, and A magnet 130N and a magnet 140N are disposed under the target 100 via a port 110. A magnet unit 130 including a magnet holder 130S and a magnet holder 130 for supporting the magnet unit 130 and a magnet holder 132. In this specification, a magnet holder The combination of these is called a magnet unit. A magnet unit consists of a cathode, a cathode It can also be called a sword magnet, magnetic member, magnetic part, etc.

[0295] The substrate stage 170 is disposed facing the target 100. Also shown is the substrate 160 supported by the magnet unit 170. 1 shows magnetic field lines 180a and 180b.

[0296] The target holder 120 and the backing plate 110 are secured together using screws (bolts, etc.). The target holder 120 is fixed to the backing plate 122 and is equipotential. It has the function of supporting the target 100 via 110.

[0297] The backing plate 110 has a function of fixing the target 100 .

[0298] The sputtering device 101 has a water channel inside or under the backing plate 110. And, a fluid (air, nitrogen, rare gas, water, oil, etc.) is made to flow through the waterway. During sputtering, the temperature of the target 100 may rise, causing discharge abnormalities. This can prevent damage to the sputtering device 101 caused by deformation of any of the members. At this time, the backing plate 110 and the target 100 are in close contact with each other via a bonding material. This is preferable because it improves the cooling performance.

[0299] A gasket is provided between the target holder 120 and the backing plate 110. This makes it difficult for impurities originating from the outside or water channels to get into the sputtering apparatus 101. Therefore, it is preferable.

[0300] In the magnet unit 130, the magnet 130N and the magnet 130S are The magnets are arranged with different polarities facing the target 100. The magnet 130N is placed so that the target 100 side is the north pole, and the magnet 130S is placed The following describes the case where the magnet is arranged so that the target 100 side is the south pole. The arrangement of the magnets and the polarities in the magnet unit 130 is not limited to that shown in FIG. It is not.

[0301] The magnetic field line 180a is one of the magnetic field lines that form a horizontal magnetic field in the vicinity of the upper surface of the target 100. The vicinity of the upper surface of the target 100 is, for example, a region perpendicular to the target 100. This is the region between 0 mm and 5 mm, in particular between 0 mm and 5 mm.

[0302] The magnetic field lines 180b form a horizontal magnetic field at a vertical distance d from the top surface of the magnet unit 130. The vertical distance d is, for example, 0 mm or more and 20 mm or less, or Between 5mm and 15mm.

[0303] During film formation, the potential V1 applied to the target holder 120 is, for example, The potential V2 applied to the substrate stage 170 is lower than the potential V3 applied to the substrate stage 170. The potential V2 is, for example, a ground potential. The potential V1, the potential V2, and the potential V3 are the above potentials. In addition, the target holder 120, the substrate stage 170, the magnet holder For example, if the substrate stage 170 is electrically It doesn't matter if it's floating on the target.

[0304] In addition, in FIG. 21, the backing plate 110, the target holder 120, and the magnet In this example, the magnet unit 130 and the magnet holder 132 are not electrically connected. For example, the backing plate 110 and the target holder 120 is electrically connected to the magnet unit 130 and the magnet holder 132. The potentials may be equipotential.

[0305] A deposition gas (for example, a rare gas such as argon, oxygen, nitrogen, etc.) is placed in the sputtering device 101. The pressure is kept constant (for example, 0.05 Pa or more and 10 Pa or less, preferably 0.1 When a potential V1 is applied to the target holder 120, Plasma is generated in the magnetic field generated by the net unit 130. The potential becomes Vp, which is higher than the potential V1. At this time, the positive ions in the plasma The potential difference between Vp and potential V1 accelerates the positive ion beam toward the target 100. The collision of the ions with the target 100 releases sputter particles. Of the sputtered particles, those that reach the substrate 160 are deposited as a film.

[0306] In general, in sputtering equipment, the bottom of a small opening with a large aspect ratio is filled with sputtering gas. In addition, the sputter particles flying at an angle to the substrate are difficult to reach. However, it may accumulate near the top of the opening, narrowing the opening, and preventing the film from being formed inside the opening.

[0307] On the other hand, by using the sputtering apparatus having the above configuration, among the emitted sputtered particles, The sputtered particles flying in an oblique direction with respect to the surface of the substrate 160 are collimated by the collimator 150. That is, by installing the collimator 150, the target 100 and the substrate 160 The collimator 150 is disposed between the substrate 160 and the substrate 160. The sputtering particles reach the substrate and are deposited on a surface parallel to the substrate. Particles do not accumulate on surfaces perpendicular to the substrate, or accumulate less on surfaces parallel to the substrate. Therefore, by using the above sputtering device, the following can be obtained: As shown in FIG. 1, the insulator 406c can be deposited except on the surface perpendicular to the substrate. .

[0308] In addition, the target 100 and the collimator 150, or the substrate 160 and the collimator 150 The vertical distance may be changed as appropriate depending on the quality of the film to be formed. As shown in FIG. 22, the movable portion 151 and the movable portion 152 may be provided. By having the collimator 150, it is possible to easily select whether or not to use the collimator 150. By having the movable portion 152, the collimator 150, the substrate 160 and the target 100 The vertical distance can be easily adjusted.

[0309] Also, a long-throw sputtering method can be used. In the dipping method, the vertical distance between the target 100 and the substrate 160 is increased, so that the sputtered particles The incident direction of the light on the substrate 160 can be made closer to perpendicular. Even if not used, the insulator 406c can be deposited on surfaces other than those perpendicular to the substrate. The vertical distance between the substrate 160 and the target 100 is set to 150 mm or more and 500 mm or less. Also, the collimator 150 may be combined with the long throw sputtering method. stomach.

[0310] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0311] Next, as shown in FIG. 19(E) and FIG. 19(F), the insulator 406d is formed. The insulator 406d can be formed in a similar process to that for the insulator 406c.

[0312] Next, as shown in FIG. 20(A) and FIG. 20(B), the insulator that will become the insulator 412, the conductor A conductor that becomes conductor 404a and a conductor that becomes conductor 404b are formed.

[0313] First, an insulator to be the insulator 412 is formed over the insulator 410 and the insulator 406d. The insulating film that becomes the insulating layer 412 is formed by sputtering, CVD, MBE, or PLD. The deposition can be performed by using a deposition method, an ALD method, or the like.

[0314] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0315] Next, a conductor that will become the conductor 404a and the conductor 404b is formed. The conductive material to be the conductive material 404b may be formed by a sputtering method, a CVD method, an MBE method, or the like. The deposition can be performed by using a PLD method, an ALD method, or the like. The conductor that becomes 4b is formed so as to fill the opening formed by the insulator 410 etc. Therefore, it is preferable to use the CVD method (particularly the MCVD method). In order to improve the adhesion of the conductor formed by the ALD method, It may be preferable to laminate the conductive material with a CVD method. For example, titanium nitride A laminated film in which a layer of tungsten and a layer of silicon may be formed in this order may be used.

[0316] Next, as shown in FIG. 20(C) and FIG. 20(D), the insulator 4 is removed by a CMP process or the like. 10 is exposed, the conductor 404a, the conductor 404b, the insulator 412, and the insulator 406c. Then, the insulator 406d is removed. At this time, the insulator 410 is used as a stopper layer. This may reduce the thickness of the insulator 410. In the saturation, the conductors 404a and 404b are insulated so that their resistance is sufficiently low. By designing the thickness of the insulator 410 with a certain margin, a transistor with little variation can be produced. You can create multiple.

[0317] The CMP process may be performed once or multiple times. When performing MP processing, first polishing with a high polishing rate is performed, followed by finishing with a low polishing rate. It is preferable to perform polishing in this manner. This can further improve the flatness of the polished surface.

[0318] Next, a film of a conductor is formed to become the conductor 420. The conductor 420 may have a laminated structure. The conductive material to be the conductive material 420 may be formed by sputtering, CVD, MBE, or the like. This can be done using a PLD method, an ALD method, or the like. Then, a photolithography method or the like can be used. The conductive material 420 is formed by processing the conductive material 420 .

[0319] Next, as shown in FIG. 20(E) and FIG. 20(F), the insulator 410 and the conductor 420 are The insulator 408 is formed on the insulating layer 404 by a method such as sputtering, CVD, M, etc. The deposition can be performed by using a BE method, a PLD method, an ALD method, or the like. 08, a film of aluminum oxide is formed using plasma containing oxygen, and the film The oxygen in the semiconductor can be added to the top surface of the insulator 410 as excess oxygen (exO). In addition, excess oxygen is added to the insulator 408 by oxygen diffusing through the insulator 410. Therefore, at this time, in the vicinity of the film interface between the insulator 408 and the insulator 410, A mixed region rich in excess oxygen may form.

[0320] Next, the above-mentioned high density plasma treatment may be performed to remove carbon, hydrogen, and the like. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances are removed from the treated object. The organic compounds can also be eliminated.

[0321] In addition, at some point after the formation of the insulator 408, a second heat treatment is performed. By performing the second heat treatment, the insulator 410 and the mixed region 414 may be heated. The excess oxygen contained in the insulator 412, the insulator 402, the insulator 406d, the insulator 406c, and The excess oxygen migrates through the insulator 406a to the semiconductor 406b. Since the oxygen ions move to 406b, defects (oxygen vacancies) in the semiconductor 406b can be reduced. .

[0322] The second heat treatment is performed to convert excess oxygen contained in the insulator 410 and the mixed region 414 into semiconductors. The temperature may be set to a temperature at which the fluorine-containing gas diffuses to the substrate 406b. For example, see the description of the first heat treatment. Alternatively, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20° C. or more and 150° C. or less, preferably The temperature is set to 40° C. or higher and 100° C. or lower. This allows excess oxygen to be released from the insulator 402 and the like. The second heat treatment can suppress the formation of each layer by performing the same heat treatment. In some cases, this step may not be necessary if the above-mentioned function can be achieved by heating during film formation.

[0323] Although not shown, the insulator 408 and the insulator 410 are provided with a conductor 416a and a conductor The openings are formed so as to reach the conductive body 416b, and conductive bodies that function as wiring are provided in the respective openings. Alternatively, an opening may be formed in the insulator 408 to reach the conductor 404, and the opening may be used as a wiring. The conductive material may be formed to function as a conductor.

[0324] In the above manner, the transistor shown in FIG. 10 can be manufactured.

[0325] Note that in this embodiment, one embodiment of the present invention has been described. In other words, in this and other embodiments, various Since clear embodiments have been described, the present invention is not limited to any particular embodiment. For example, In one embodiment of the present invention, an example in which an oxide semiconductor is used as a semiconductor is described. One aspect of the invention is not limited to this. In some cases or depending on the situation, the present invention One embodiment of the present invention is silicon, germanium, silicon germanium, silicon carbide, gallium. Arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc. This is also fine.

[0326] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0327] (Embodiment 6) <Transistor structure 8> A transistor having a structure different from that in FIG. 10 and a method for manufacturing the same will be described below with reference to FIGS. The description will be given with reference to FIG. 13. FIG. 12 is a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 12(A) is a top view. FIG. 12(B) is a dot-chain diagram of FIG. 12(A). FIG. 12(C) is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 12(A) is a cross-sectional view corresponding to 3-A4. Note that in the top view of FIG. 12(A), FIG. 13 is an enlarged view of the cross-sectional view shown in FIG. 12. vinegar.

[0328] In this transistor, in FIG. 12B, the side surface of the insulator 410 is on the conductor 416a. The insulator 410 has an angle θ of greater than 0 degrees and less than 90 degrees with respect to the surface. An insulator 406d is formed via 406c. The angle θ is 75 degrees or more and less than 90 degrees. 80 degrees or more and less than 90 degrees, and more preferably 85 degrees or more and less than 90 degrees. Note that the insulators 406c and 406d are connected to the conductor 404 via the insulator 412. The region covering the side surface of the conductor 404 is where the insulator 406c and the insulator 406d overlap with the bottom surface of the conductor 404. The insulators 406c and 406d are provided thinner than the regions where the insulators 406a and 406b are provided. Consider the transistor shown in FIG.

[0329] It is sufficient that t1 is greater than L1 and L1 / t1 is less than 1. Only one of the insulators 406a and 406b is formed thinly in a region covering the side surface of the insulator 410. Furthermore, only one of the insulator 406c and the insulator 406d may be used. It is formed in the area covering the side of 0, and the other side may be absent.

[0330] The transistor according to this embodiment shown in FIGS. 13A and 13B is provided on an insulator 410. The height of the top surface of the insulator 406d is the same as that of the conductor 416a and The height of the upper surface of the conductor 416b may be the same as that of the upper surface of the insulator 406d. In the region where the insulator 406d overlaps with the bottom surfaces of the conductors 404a and 404b, 13A, the surface of the insulator 404a is closer to the conductor 404a. The upper surface of 6d is preferably at the same height as the upper surfaces of conductors 416a and 416b. It is.

[0331] The height of the top surface of the insulator 406c is the height of the semiconductor 406b, the conductor 416a, and the conductor It is preferable that the height of the upper surface of the insulator 406c is about the same as the interface of the insulator 406b. In the region where the insulator 406c overlaps with the bottom surfaces of the conductor 404a and the conductor 404b, Ideally, the top surface of the insulator 406c is the surface closest to the semiconductor 404a. 6b is preferably at the same height as the interface between the conductor 416a and the conductor 416b. However, the insulator 406c is at least partially etched away from the semiconductor 406b. As shown in FIG. 13(B), the upper surface of the insulator 406c is a semiconductor. The conductor 406b may be located above the interface between the conductor 416a and the conductor 416b. It won't turn.

[0332] In the transistor of this embodiment, the insulator 406c is formed on the semiconductor 406b. In the above embodiment, two layers of the insulating material 406a and the insulating material 406b are provided. However, the present invention is not limited to this, and may be applied to a laminated structure of three or more layers. It may also be of this structure.

[0333] <Transistor manufacturing method 8> First, the same steps are carried out up to FIG. 18 shown in the fifth embodiment.

[0334] Next, the side surface of the insulator 410 is rotated to an angle of 90 degrees, which is greater than 0 degrees, relative to the top surface of the conductor 416a. Next, the film forming apparatus described in the fifth embodiment is used to form the film having an angle θ of less than 100 nm. In this case, for example, the angle θ is small. The probability of sputtered particles accumulating increases as the thickness of the insulator 410 increases. The larger the angle θ, the thicker the insulator 410 is. The insulators 406c and 406d are formed thin on the sides of the insulator 41. The thickness of the insulator 406c and the insulator 406d formed on the side of the substrate 0 is adjusted by the angle θ. In other words, by reducing L1, which is the width of the offset region to be formed, t1 is greater than L1, and L1 / t1 is less than 1.

[0335] The subsequent steps are the same as those in the manufacturing method 1 of the transistor described in Embodiment 5. Just do it.

[0336] In the above manner, the transistor shown in FIG. 12 can be manufactured.

[0337] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0338] (Embodiment 7) <Transistor Structures 9 and 10> In the following, a transistor having a different structure from that shown in FIG. 10 and a method for manufacturing the same will be described with reference to FIG. 14 and 15 show a semiconductor device according to one embodiment of the present invention. Top view and cross-sectional view are shown.

[0339] The transistors shown in FIGS. 14A and 15 will be described. FIG. 14(B) corresponds to the dashed line A1-A2 shown in FIG. 14(A). Fig. 14(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in Fig. 14(A). In the top view of FIG. 14(A), some elements are omitted for clarity. The figure shows the

[0340] FIG. 15B is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. FIG. 15(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 15(A). In the top view of FIG. 15(A), some elements are omitted for clarity.

[0341] The transistor shown in FIG. 14 and FIG. 15 has an insulator 406c2 (insulator 406c in FIG. 4). , insulator 406d2 (insulator 406d in FIG. 4), insulator 412, conductor 404a, and The conductor 404b is also formed on a partial area of ​​the upper surface of the insulator 410. Consider the transistor shown in FIG. 10 or FIG.

[0342] The transistor shown in FIG. 14 and FIG. 15 includes a conductor 404a serving as a gate electrode, In other words, the insulator 406 and a part of the conductor 404b may function as wiring. c2 (insulator 406c in FIG. 4), insulator 406d2 (insulator 406d in FIG. 4), and A conductor 404a and a conductor 404b are formed on an insulator 410 with an insulator 412 interposed therebetween. b corresponds to the conductor 420 in the transistor structure 1. , t2 is the distance between the conductor 416a or conductor 416b and the conductor 404a on the insulator 410. The vertical distance is set to 1.0 mm. Note that the insulator 406c2 (insulator 406c in FIG. 4) and the insulator 406d2 (insulator 406d in FIG. 4), insulator 412, conductor 404a, and conductor 4 Since the insulating layer 410 and the insulating layer 410 are formed at the same time, the insulating layer 410 and the insulating layer 410 are formed at the same time. Between the conductor 404a, an insulator 406c and an insulator 406d2 (insulator 406d in FIG. 4) are provided. ) and insulator 412 are interposed. Therefore, t2 is the thickness of insulator 410 plus the thickness of insulator 4 06c2 (insulator 406c in FIG. 4), insulator 406d2 (insulator 406d in FIG. 4) By adding thickness, it is possible to provide sufficient distance and suppress parasitic capacitance. Cut.

[0343] <Transistor manufacturing methods 9 and 10> A method for manufacturing the transistor shown in FIGS.

[0344] First, the same steps are carried out up to FIG. 19 shown in the fifth embodiment.

[0345] Next, the insulators 406c, 406d, and 412, a conductor 404a, and a conductor 404b are formed. The conductor corresponding to the conductor 420 in the transistor structure 1 is a conductor 404a and a conductor 404b can be used to form them simultaneously.

[0346] Next, the insulator 408 is formed.

[0347] In the above manner, the transistor shown in FIG. 14 can be manufactured.

[0348] The transistor shown in FIG. 15 was manufactured using the same process as the transistor shown in FIG. , insulator 406c, insulator 406d, insulator 412, conductor 404a, and conductor 404 Then, a desired shape of the insulator 40 is formed by using a photolithography method or the like. 6c, an insulator 406d, an insulator 412, a conductor 404a, and a conductor 404b are formed. With this configuration, a conductor corresponding to the conductor 420 in the transistor structure 1 is , conductor 404a, and conductor 404b can be formed simultaneously.

[0349] In the above manner, the transistor shown in FIG. 15 can be manufactured.

[0350] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0351] (Embodiment 8) <Transistor structures 11 and 12> In the following, a transistor having a structure different from that in FIG. 10 and a method for manufacturing the same will be described with reference to FIG. 16 and 17 show a semiconductor device according to one embodiment of the present invention. Top view and cross-sectional view are shown.

[0352] The transistors shown in FIGS. 16A and 17 will be described. FIG. 16(B) corresponds to the dashed line A1-A2 shown in FIG. 16(A). Fig. 16(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in Fig. 16(A). In the top view of FIG. 16(A), some elements are omitted for clarity. The figure shows the

[0353] FIG. 17B is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. FIG. 17(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 17(A). In the top view of FIG. 17(A), some elements are omitted for clarity.

[0354] In the transistors shown in FIGS. 16 and 17, the conductor 416a and the conductor 416b are semiconductor The other configurations are the same as those of the transistors shown in FIG. Please take Sta into consideration.

[0355] <Transistor manufacturing methods 11 and 12> A method for manufacturing the transistor shown in FIGS.

[0356] First, the steps are carried out similarly up to the steps shown in FIG. 18(A) and FIG. 18(B) in the fifth embodiment.

[0357] Next, the insulator 406a and the semiconductor 406b are formed, and then the conductor 416 is formed. Then, a resist is formed on the conductor 416 by photolithography or the like, and the resist is Using the resist as a mask, a first etching is performed on the conductor 416. Next, the resist is removed. After the etching, a second etching is performed using the conductor 416 as a mask. , insulator 406a, and semiconductor 406b.

[0358] The subsequent steps are the same as those shown in FIG. 18(G) and FIG. 18(H) and subsequent steps. 16 can be manufactured.

[0359] 17 also has an insulator 40, similar to the transistor shown in FIG. 6a, semiconductor 406b, and conductor 416 are formed. Then, the transistor shown in FIG. A transistor may be manufactured using a process similar to that described above.

[0360] In the above manner, the transistor shown in FIG. 17 can be manufactured.

[0361] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0362] (Embodiment 9) <Film forming equipment> The configuration of a film forming apparatus including the above-mentioned sputtering apparatus will be described below. The structure of a film forming apparatus that reduces the amount of impurities mixed in the film will be described with reference to FIGS. 23 and 24. do.

[0363] FIG. 23 is a schematic top view of a single-wafer multi-chamber film forming apparatus 1700. As shown in FIG. The film forming apparatus 1700 includes a cassette port 1761 for accommodating a substrate and a and an atmosphere-side substrate supply chamber 1701 having an alignment port 1762 for performing alignment. The substrate is loaded from the supply chamber 1701 to the atmospheric substrate transfer chamber 1702, A load lock chamber 1 for switching the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure. 703a, the substrate is removed, and the pressure in the chamber is reduced from reduced pressure to atmospheric pressure, or reduced from atmospheric pressure to atmospheric pressure. and a transfer chamber 1703b for transferring substrates in a vacuum. 04, a substrate heating chamber 1705 for heating the substrate, and a film forming chamber 1706a, 170 The deposition chambers 1706a, 1706b, and 1706c are The above-mentioned sputtering apparatus 101 can be applied to all or part of the above.

[0364] In addition, the cassette port 1761 may have multiple ports (three in the figure) as shown in FIG. good.

[0365] The atmospheric substrate transfer chamber 1702 is provided with a load lock chamber 1703a and an unload lock The load lock chamber 1703a and the unload lock chamber 1703b are connected to the b is connected to a transfer chamber 1704, which is connected to a substrate heating chamber 1705, a film forming chamber 1706, and a 06a, and is connected to the film formation chamber 1706b and the film formation chamber 1706c.

[0366] A gate valve 1764 is provided at the connection between the chambers, and the atmosphere side substrate supply chamber 17 Except for the atmospheric side substrate transfer chamber 1701 and the atmospheric side substrate transfer chamber 1702, the pressure of each chamber can be controlled independently. The atmospheric substrate transfer chamber 1702 and the transfer chamber 1704 are each equipped with a transfer robot 1763a. , a transfer robot 1763b is provided, and the substrate can be transferred.

[0367] In addition, it is preferable that the substrate heating chamber 1705 also serves as a plasma processing chamber. Since the substrate can be transported between processes without being exposed to the atmosphere, This allows the adsorption of impurities from the substrate to be suppressed. In addition, the order of film formation and heat treatment can be freely configured. In addition, the transfer chamber, film formation chamber, load lock chamber, unload lock chamber, and The substrate heating chamber and the substrate heating chamber are not limited to the above configuration, and may be appropriately selected according to the installation space and process conditions. It is possible to provide an optimal configuration.

[0368] Next, the dashed line X1-X2, the dashed line Y1-Y2, and the dashed line Y1-Y2 of the film forming apparatus 1700 shown in FIG. A cross section corresponding to the dashed line Y2-Y3 is shown in FIG.

[0369] FIG. 24(A) shows a cross section of the substrate heating chamber 1705 and the transfer chamber 1704. The chamber 1705 has a number of heated stages 1765 capable of housing substrates. In addition, in FIG. 24(A), a configuration in which seven heating stages 1765 are provided is shown. However, the present invention is not limited to this, and may be configured with 1 to 7 stages or 8 or more stages. By increasing the number of stages in the 1765, multiple substrates can be heat treated simultaneously, improving productivity. The substrate heating chamber 1705 is connected to a vacuum pump 1770 via a valve. The vacuum pump 1770 may be, for example, a dry pump or a mechanical pump. A booster pump or the like can be used.

[0370] In addition, the substrate heating chamber 1705 is provided with a heating mechanism that uses, for example, a resistance heating element. Alternatively, the heat may be transferred by heat conduction or radiation from a medium such as a heated gas. A heating mechanism that heats the gas may be used. For example, a GRTA (Gas Rapid Therma l Anneal), LRTA(Lamp Rapid Thermal Anneal) ) or other RTA (Rapid Thermal Anneal) can be used. LRTA is compatible with halogen lamps, metal halide lamps, xenon arc lamps, and Light emitted from lamps such as bon arc lamps, high pressure sodium lamps, and high pressure mercury lamps The object to be treated is heated by radiation (electromagnetic waves). GRTA also uses high-temperature gas Heat treatment is performed using an inert gas.

[0371] The substrate heating chamber 1705 is connected to a refiner 178 via a mass flow controller 1780. The mass flow controller 1780 and the refiner 1781 are connected to the gas Although the number of the types of the substrates is equal, only one is shown for ease of understanding. The gas to be put in must have a dew point of -80°C or less, preferably -100°C or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) are used.

[0372] The transfer chamber 1704 includes a transfer robot 1763b. The transfer robot 1763b The apparatus has a plurality of movable parts and an arm for holding a substrate, and can transport the substrate to each chamber. The transfer chamber 1704 is connected to a vacuum pump 1770 and a cryopump 1771 via valves. 71. With this configuration, the transfer chamber 1704 is Use the vacuum pump 1770 to evacuate to low or medium vacuum (0.1 to several hundred Pa). By switching the valve, the vacuum can be changed from medium to high or ultra-high vacuum (0.1 Pa to 1×10 -7 The pressure is evacuated to 100 MPa using a cryopump 1771.

[0373] In addition, for example, two or more cryopumps 1771 are connected in parallel to the transfer chamber 1704. With this configuration, even if one cryopump is in regeneration, The remaining cryopumps can be used to pump the remaining gas. This is the process of releasing molecules (or atoms) stored in the cryopump. If the ion pump accumulates too many molecules (or atoms), its pumping capacity decreases. Regeneration will occur periodically.

[0374] FIG. 24B shows the film forming chamber 1706b, the transfer chamber 1704, and the load lock chamber 1703a. A cross section is shown.

[0375] Here, the details of each film formation chamber will be described with reference to FIG. The structure of the sputtering apparatus 101 shown in FIG. 21 will be referred to. The deposition chamber 1706b shown in FIG. The target 100, the substrate stage 170, and the control unit 160 installed between the target and the substrate stage. In this embodiment, a substrate is placed on the substrate stage 170. The substrate stage 170 includes a substrate holding mechanism (not shown) for holding the substrate and a back surface of the substrate. A back heater that heats from the outside may also be provided.

[0376] The deposition chamber 1706b is connected to a mass flow controller 1782 via a gas heating mechanism 1782. 80, and the gas heating mechanism 1782 is purified via the mass flow controller 1780. The deposition gas is heated to a temperature of 40° C. or higher (400° C.) by a gas heating mechanism 1782. The gas can be heated to a temperature of preferably 50° C. or higher and 200° C. or lower. 1782, mass flow controller 1780, and purifier 1781 are provided for each gas type. For ease of understanding, only one is shown. The deposition gas has a dew point of -80°C or less. It is preferable to use a gas having a temperature of -100°C or lower.

[0377] In addition, the film formation chamber 1706b is equipped with a parallel plate sputtering device, an ion beam sputtering device, A gadget may also be applied.

[0378] In addition, when a refiner is provided immediately before the gas inlet, the gas is passed through the refiner 1781 and the deposition chamber 1706b. The length of the piping at is 10 m or less, preferably 5 m or less, and more preferably 1 m or less. By limiting the length of the piping to 10m or less, 5m or less, or 1m or less, the amount of gas released from the piping can be reduced. The effect can be reduced according to the length. In addition, iron fluoride and aluminum oxide are used for gas piping. It is advisable to use metal piping with the inside coated with chromium oxide or the like. Compared with US316L-EP piping, the amount of gas containing impurities released is small, and it is less susceptible to deposition gases, etc. This reduces the intrusion of impurities. In addition, high-performance ultra-small metal gaskets are used for pipe joints. It is recommended to use fittings (UPG fittings). Also, by constructing the piping entirely from metal, resin, etc. can be avoided. This is preferable because it can reduce the effects of released gas and external leakage compared to the case where a conductive material is used.

[0379] The deposition chamber 1706b is connected to a turbo molecular pump 1772 and a vacuum pump 1773 via a valve. 1770. The film forming chamber 1706b preferably has a cryotrap. stomach.

[0380] The Cryotrap 1751 adsorbs molecules (or atoms) with relatively high melting points, such as water. The turbomolecular pump 1772 is a mechanism that can pump large molecules (or atoms). ) and requires little maintenance, making it highly productive. The pumping capacity for water is low. Therefore, in order to increase the pumping capacity for water, etc., a cryotrap is used. The cryotrap 1751 is connected to the film forming chamber 1706b. The temperature of the refrigerator is set to 100 K or less, preferably 80 K or less. If the 751 has multiple refrigerators, changing the temperature of each refrigerator will allow for more efficient exhaust. For example, the temperature of the first stage refrigerator is set to 100K or less, and the second stage refrigerator is set to 100K or less. The temperature of the first refrigerator should be set to 20K or less.

[0381] The method of exhausting the film forming chamber 1706b is not limited to this, and may be the same as that of the transport chamber 1704. The same configuration as the evacuation method (the evacuation method of a cryopump and a vacuum pump) may be used. The exhaust method for the transfer chamber 1704 is the same as that for the film forming chamber 1706b (a turbo molecular pump and a It is also possible to use an empty pump as an exhaust method.

[0382] In addition, the back pressure ( It is preferable that the total pressure and the partial pressure of each gas molecule (atom) are as follows. Since there is a possibility that impurities may be mixed into the film being formed, the back pressure of the film forming chamber 1706b, etc. It is also necessary to pay attention to the partial pressure of each gas molecule (atom).

[0383] The back pressure (total pressure) of each of the above mentioned chambers is 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, and more preferably 1×10 -5 The mass-to-charge ratio (m / z The partial pressure of a gas molecule (atom) with a mass of 18 is 3 × 10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less. In addition, the m The partial pressure of a gas molecule (atom) with z = 28 is 3 x 10 -5 Pa or less, preferably 1×1 0 -5 Pa or less, more preferably 3×10 -6 In addition, the above-mentioned The partial pressure of a gas molecule (atom) with m / z 44 is 3 x 10 -5 Pa or less, preferably 1× 10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0384] The total pressure and partial pressure in the vacuum chamber can be measured using a mass spectrometer. For example, the quadrupole mass spectrometer (also called Q-mass) manufactured by ULVAC, Inc. ee Just use CGM-051.

[0385] The above-mentioned transfer chamber 1704, substrate heating chamber 1705, and film forming chamber 1706b are externally It is desirable to have a configuration with little leakage or internal leakage.

[0386] For example, the above-mentioned transfer chamber 1704, the substrate heating chamber 1705, and the film forming chamber 1706b The crate is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s The leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. The leak rate of a gas molecule (atom) with a mass of 28 is 1×10 -5 Pa·m 3 / s or less, preferred Or 1×10 -6 Pa·m 3 / s or less. Also, gas molecules with m / z of 44 (atomic child) leak rate is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa. m 3 / s or less.

[0387] The leak rate was calculated from the total and partial pressures measured using the mass spectrometer mentioned above. It can be derived.

[0388] The leak rate depends on external and internal leaks. External leaks occur due to tiny holes or seals. An internal leak is when gas flows into the vacuum system from outside due to a valve failure or other reasons. This is caused by leakage from partitions such as valves and gas released from internal components. In order to keep the above values ​​or less, measures must be taken to prevent both external and internal leaks. There is.

[0389] For example, the opening and closing part of the deposition chamber 1706b may be sealed with a metal gasket. Sketches are metals coated with iron fluoride, aluminum oxide, or chromium oxide. It is recommended to use a metal gasket. Metal gaskets have a higher adhesion than O-rings and reduce external leakage. Also, metals coated with iron fluoride, aluminum oxide, chromium oxide, etc. By using a passivation material, gas emissions containing impurities released from the metal gasket are suppressed. This makes it possible to reduce internal leakage.

[0390] In addition, the film forming apparatus 1700 is made of aluminum, which emits less gas containing impurities. Cr, Ti, Zr, Ni or Vanadium is used. The above members may be coated with an alloy containing iron, chromium, nickel, etc. The alloys containing copper, nickel, etc. are strong, heat resistant, and easy to machine. In order to reduce the surface area, the surface irregularities of the component can be reduced by polishing, etc. Gas can be reduced.

[0391] Alternatively, the components of the film forming apparatus 1700 may be replaced with iron fluoride, aluminum oxide, chromium oxide, etc. It may be coated with

[0392] The members of the film forming apparatus 1700 are preferably made of metal, for example, quartz. When installing a viewing window, the surface is treated with iron fluoride or acid to suppress gas emission. It is advisable to thinly coat the surface with aluminum oxide or chromium oxide.

[0393] The adsorbates present in the deposition chamber are adsorbed to the inner walls, etc., and do not affect the pressure in the deposition chamber. This causes gas emission when the deposition chamber is evacuated. Therefore, the leak rate is proportional to the evacuation speed. Although there is no relation between the amount of adsorbed matter and the amount of the adsorbed matter, it is recommended to use a pump with high exhaust capacity to remove as much of the adsorbed matter as possible from the deposition chamber. It is important to desorb the adsorbed material and evacuate the gas beforehand. The deposition chamber may be baked. This will increase the desorption rate of adsorbed substances by about 10 times. Baking can be performed at temperatures between 100℃ and 450℃. If the adsorbed substances are removed while injecting an inert gas into the deposition chamber, they are difficult to remove by simply evacuating the chamber. The desorption rate of water and other substances can be further increased. The desorption rate of the adsorbed substances can be further increased by heating the adsorbent to about the same temperature. It is preferable to use a rare gas as the active gas. Depending on the type of film to be formed, an inert gas may be used. Instead, oxygen or the like may be used. For example, when forming an oxide film, the main component In some cases it may be preferable to use oxygen.

[0394] Alternatively, the pressure in the deposition chamber can be reduced by using an inert gas such as a heated rare gas or oxygen. It is preferable to increase the pressure in the deposition chamber and evacuate the deposition chamber again after a certain period of time has elapsed. This allows the adsorbed substances in the film formation chamber to be desorbed, and the amount of impurities present in the film formation chamber to be reduced. This treatment can be carried out in the range of 2 to 30 times, preferably 5 to 15 times. It is effective to repeat the process within the range of 40°C to 400°C. By introducing inert gas or oxygen, etc., the temperature in the deposition chamber is increased by 50℃ to 200℃. The pressure is set to 0.1 Pa or more and 10 kPa or less, preferably 1 Pa or more and 1 kPa or less, and more preferably The pressure is preferably 5 Pa or more and 100 Pa or less, and the pressure is maintained for 1 minute or more and 300 minutes or less. The time may be 5 minutes or more and 120 minutes or less. After that, the film formation chamber is cooled for 5 minutes or more and 300 minutes or less, preferably. or for a period of 10 minutes or more and 120 minutes or less.

[0395] Also, the desorption speed of the adsorbed substances can be further increased by forming a dummy film. The film formation is performed by forming a film on a dummy substrate using a method such as sputtering. A film is deposited on the plate and the inner wall of the deposition chamber, and impurities in the deposition chamber and substances adsorbed on the inner wall of the deposition chamber are removed from the film. It is preferable to use a dummy substrate that emits less gas. By performing the above, it is possible to reduce the impurity concentration in the film to be formed later. The film formation may be performed simultaneously with baking.

[0396] Next, the transfer chamber 1704 and the load lock chamber 1703a shown in FIG. The details of the atmospheric substrate transfer chamber 1702 and the atmospheric substrate supply chamber 1701 shown in FIG. In addition, FIG. 24(C) shows the atmospheric side substrate transfer chamber 1702 and the atmospheric side substrate A cross section of the plate supply chamber 1701 is shown.

[0397] The transfer chamber 1704 shown in FIG. 24(B) is similar to the transfer chamber 1704 shown in FIG. 24(A). Please refer to the above.

[0398] The load lock chamber 1703a includes a substrate transfer stage 1752. 1703a increases the pressure from a reduced pressure state to atmospheric pressure, and the pressure in the load lock chamber 1703a When the pressure in the atmosphere side substrate transfer chamber 1702 becomes atmospheric pressure, the transfer robot 176 3a to the substrate transfer stage 1752. After the vacuum is drawn in the transfer chamber 1703a to create a reduced pressure state, the transfer robot installed in the transfer chamber 1704 The stage 1763b receives the substrate from the substrate transfer stage 1752.

[0399] The load lock chamber 1703a is connected to a vacuum pump 1770 and a cryogenic It is connected to the vacuum pump 1770 and the cryopump 177 The exhaust system of 1 can be connected by referring to the connection method of the transfer chamber 1704. The unload lock chamber 1703b shown in FIG. It may have a similar configuration to the lock chamber 1703a.

[0400] The atmospheric substrate transfer chamber 1702 includes a transfer robot 1763a. The substrate is transferred between the cassette port 1761 and the load lock chamber 1703a by a. In addition, the atmosphere side substrate transfer chamber 1702 and the atmosphere side substrate supply chamber 1701 A HEPA filter (High Efficiency Particulate Air Filter) is installed on the top. Even if a mechanism for cleaning dust or particles such as an air filter is installed, good.

[0401] The atmosphere side substrate supply chamber 1701 has a plurality of cassette ports 1761. The 1761 can accommodate multiple substrates.

[0402] The target surface temperature is 100° C. or less, preferably 50° C. or less, and more preferably room temperature. In sputtering equipment that can handle large-area substrates, the temperature is set to about 25°C. However, targets of a size corresponding to a large area are often used. It is difficult to fabricate the targets without any seams. Although they are arranged in a large shape, there are inevitably small gaps. As the surface temperature of the target rises, zinc and other substances evaporate from the tiny gaps, gradually filling the gaps. If the gap widens, the backing plate or the metal used for bonding may break. The metal may be sputtered, which increases the impurity concentration. The target is preferably sufficiently cooled.

[0403] Specifically, a metal having high electrical conductivity and high heat dissipation properties (e.g., In addition, a water channel is formed in the backing plate, and a sufficient amount of By flowing cooling water, the target can be cooled efficiently.

[0404] In addition, when the target contains zinc, the plasma damage is reduced by forming the film in an oxygen gas atmosphere. In this way, an oxide semiconductor can be obtained in which the image is reduced and zinc volatilization is less likely to occur.

[0405] By using the above-described film forming apparatus, it is possible to suppress the inclusion of impurities in the film being formed.

[0406] (Embodiment 10) <Manufacturing equipment> A manufacturing apparatus for performing high density plasma processing according to one embodiment of the present invention will be described below.

[0407] First, let us consider the configuration of a manufacturing device that minimizes the inclusion of impurities during the manufacture of semiconductor devices. This will be explained using Figures 26 and 27.

[0408] FIG. 25 is a schematic top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing equipment 2700 includes a cassette port 2761 for accommodating substrates and a and an atmosphere-side substrate supply chamber 2701 having an alignment port 2762 for performing alignment. The substrate is loaded from the supply chamber 2701 to the atmospheric substrate transfer chamber 2702, A load lock chamber 2 that switches the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure. 703a, the substrate is removed, and the pressure in the chamber is reduced from reduced pressure to atmospheric pressure, or reduced from atmospheric pressure to atmospheric pressure. and a transfer chamber 2703b for transferring substrates in a vacuum. 04, chamber 2706a, chamber 2706b, and chamber 2706c, and a chamber 2706d.

[0409] The atmospheric substrate transfer chamber 2702 is provided with a load lock chamber 2703a and an unload lock The load lock chamber 2703a and the unload lock chamber 2703b are connected to each other. b is connected to the transfer chamber 2704, which is connected to the chamber 2706a, the chamber -2706b, connected to chamber 2706c and chamber 2706d.

[0410] In addition, a gate valve GV is provided at the connection between each chamber, and the atmosphere side substrate supply chamber 2701 Each chamber can be independently maintained in a vacuum state except for the atmospheric substrate transfer chamber 2702. In addition, a transfer robot 2763a is provided in the atmospheric substrate transfer chamber 2702. The chamber 2704 is provided with a transport robot 2763b. The substrate can be transported within the manufacturing apparatus 2700 by the transport robot 2763b. .

[0411] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Below Pa, Preferably 3 x 10 -5 Pa or less, more preferably 1×10 -5 Pa or less. Also, The transfer chamber 2704 and each chamber are filled with gas molecules (atoms) having a mass-to-charge ratio (m / z) of 18. The partial pressure of the electrons is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, Preferably 3 x 10 -6 In addition, the transfer chamber 2704 and each chamber The partial pressure of a gas molecule (atom) with m / z of 28 is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less. The partial pressure of gas molecules (atoms) with m / z of 44 in the chamber 2704 and each chamber is, for example, , 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0412] The total pressure and partial pressure in the transfer chamber 2704 and each chamber were measured using a mass spectrometer. For example, a quadrupole mass spectrometer (Q-mass (Also known as Qulee CGM-051) can be used.

[0413] In addition, the transfer chamber 2704 and each chamber are configured to have little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is preferably set as follows: 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. For example, m / z 28 gas molecule (atom) leak rate is 1×10 -5 Pa·m 3 / s or less, Preferably 1 x 10 -6 Pa·m 3 / s or less. For example, if the m / z is 44, The leak rate of gas molecules (atoms) is 3×10 -6 Pa·m 3 / s or less, preferably 1×1 0 -6 Pa·m 3 / s or less.

[0414] The leak rate was calculated from the total and partial pressures measured using the mass spectrometer mentioned above. The leak rate depends on the external leak and the internal leak. The reason is that gas enters from outside the vacuum system due to a small hole or a defective seal. The gas leak is caused by leakage from valves and other partitions in the vacuum system or by gas released from internal components. In order to keep the leak rate below the above values, both external and internal leaks must be prevented. Therefore, measures need to be taken.

[0415] For example, the opening and closing parts of the transfer chamber 2704 and each chamber are sealed with metal gaskets. Metal gaskets are protected by iron fluoride, aluminum oxide, or chromium oxide. It is preferable to use a coated metal. Metal gaskets have a higher adhesion than O-rings, It can reduce external leakage. In addition, iron fluoride, aluminum oxide, chromium oxide, etc. By using a passivation coating, the metal gasket is protected from impurities The released gas is suppressed, and internal leakage can be reduced.

[0416] In addition, the components constituting the manufacturing apparatus 2700 are aluminum, which emits less gas including impurities. Cr, Ti, Zr, Ni or Vanadium is used. The above members may be coated with an alloy containing iron, chromium, nickel, etc. The alloys containing copper, nickel, etc. are strong, heat resistant, and easy to machine. In order to reduce the surface area, the surface irregularities of the component can be reduced by polishing, etc. Gas can be reduced.

[0417] Alternatively, the components of the manufacturing apparatus 2700 may be made of iron fluoride, aluminum oxide, chromium oxide, etc. It may be coated with

[0418] It is preferable that the members of the manufacturing apparatus 2700 are made of metal as much as possible, for example, quartz. When installing a viewing window, the surface is treated with iron fluoride or acid to suppress gas emission. It is advisable to thinly coat the surface with aluminum oxide or chromium oxide.

[0419] The adsorbents present in the transfer chamber 2704 and each chamber are adsorbed to the inner walls, etc. It does not affect the pressure in the transfer chamber 2704 and each chamber, but This causes gas emission when exhausting the nozzle. Therefore, there is a correlation between the leak rate and the pumping speed. Although there is no exhaust gas, the transfer chamber 2704 and each chamber are filled with the gas using a pump with high exhaust capacity. It is important to remove as much of the adsorbed matter as possible and evacuate the air in advance. To facilitate the removal of adhesions, the transfer chamber 2704 and each of the chambers may be baked. Baking can increase the desorption rate of adsorbed substances by about 10 times. The heating may be performed at a temperature of 100° C. or more and 450° C. or less. By removing the adsorbed substances while introducing them into each chamber, it is difficult to remove them by simply evacuating the gas. The desorption rate of water and the like can be further increased. By heating the catalyst to a temperature similar to that of the catalyst, the desorption rate of the adsorbed substances can be further increased. Here, it is preferable to use a rare gas as the inert gas.

[0420] Alternatively, an inert gas such as a heated rare gas or oxygen may be introduced into the transfer chamber 270 The pressure in the transfer chamber 2704 and each chamber is increased, and after a certain period of time, the transfer chamber 2704 and each chamber are It is preferable to perform a process of evacuating the chamber. The adsorbed substances in the transfer chamber 2704 and each chamber can be desorbed. This treatment can be repeated 2 to 30 times to reduce impurities present in the water. It is effective to repeat the process 5 to 15 times. or an inert gas having a temperature of 40° C. or higher and 400° C. or lower, preferably 50° C. or higher and 200° C. or lower; By introducing oxygen, etc., the pressure in the transfer chamber 2704 and each chamber is kept at 0.1 Pa or more. 10 kPa or less, preferably 1 Pa or more and 1 kPa or less, and more preferably 5 Pa or more and 10 0 Pa or less, and the pressure is maintained for 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. After that, the transfer chamber 2704 and each chamber are cooled for 5 minutes to 300 minutes. The evacuation is preferably performed for a period of 10 minutes or more and 120 minutes or less.

[0421] Next, the chamber 2706b and the chamber 2706c are shown in a cross-sectional schematic diagram in FIG. The following explains using the diagram.

[0422] The chambers 2706b and 2706c are, for example, for applying high-density plasma to a workpiece. The chambers 2706b and 2706c are chambers in which the laser processing can be performed. The only difference between the 2706c and the 2706c is the atmosphere during high-density plasma treatment. Since the configurations of the above are the same, they will be described together below.

[0423] The chambers 2706b and 2706c each include a slot antenna plate 2808; The device includes a dielectric plate 2809, a substrate stage 2812, and an exhaust port 2819. Outside the chambers 2706b and 2706c, a gas supply source 2801 and A valve 2802, a high frequency generator 2803, a waveguide 2804, and a mode converter 2805. , a gas pipe 2806, a waveguide 2807, a matching box 2815, and a high frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0424] The high frequency generator 2803 is connected to the mode converter 2805 via the waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with the dielectric plate 2809. The gas source 2801 is connected to the mode converter 2805 via a valve 2802. Then, a gas tube passes through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. 2806 delivers gas to chamber 2706b and chamber 2706c. The vacuum pump 2817 also supplies the chamber with air via a valve 2818 and an exhaust port 2819. It has a function of exhausting gases and the like from the bar 2706b and the chamber 2706c. A high frequency power supply 2816 is connected to the substrate stage 2812 via a matching box 2815. Connected.

[0425] The substrate stage 2812 has a function of holding the substrate 2811. For example, It has the function of holding the electrodes by static electricity or mechanically. It also functions as an electrode to which power is supplied from the heater 2813. and has a function of heating the substrate 2811.

[0426] The vacuum pump 2817 may be, for example, a dry pump, a mechanical booster pump, an On-pump, titanium sublimation pump, cryopump or turbomolecular pump In addition to the vacuum pump 2817, a cryotrap can be used. Cryopumps and cryotraps can be used to efficiently pump out water. Particularly preferred.

[0427] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like. Alternatively, the heat can be transferred by heat conduction or radiation from a medium such as a heated gas. For example, a heating mechanism such as a GRTA or LRTA may be used. GRTA uses high-temperature gas for heat treatment. The gas is an inert gas. is used.

[0428] In addition, the gas supply source 2801 is connected to a refiner via a mass flow controller. The gas used has a dew point of -80°C or less, preferably -100°C or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) are used. That's good.

[0429] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (aluminum The dielectric plate 280 may be made of yttrium oxide (yttria). Another protective layer may be formed on the surface of the substrate 9. The protective layer may be made of magnesium oxide. titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, Silicon oxide, aluminum oxide, yttrium oxide, etc. may be used. 809 is exposed to a particularly high-density region of the high-density plasma 2810 described later. The damage can be mitigated by providing a protective layer. It is possible to suppress the increase in

[0430] The high frequency generator 2803 may be, for example, 0.3 GHz or more and 3.0 GHz or less, 0.7 GHz or less. Generates microwaves of 1.1GHz or more, or 2.2GHz or more, but not exceeding 2.8GHz. The microwave generated by the high frequency generator 2803 passes through the waveguide 2804. The mode converter 2805 transmits the TE mode. The microwaves are then converted into TEM mode and propagated through a waveguide 2807. The slot antenna plate 2808 is connected to a plurality of A slot hole is provided, and the microwave passes through the slot hole and the dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, generating a high-density plasma 2810. The high density plasma 2810 is generated by gas supplied from a gas supply source 2801. There are ions and radicals depending on the gas species. For example, oxygen radicals or nitrogen radicals Cal etc. exist.

[0431] At this time, the ions and radicals generated by the high density plasma 2810 cause the substrate 2 The film on the substrate 811 can be modified. It may be preferable to apply a bias to the 811 side. RF (Radio Frequency) By applying a bias to the substrate, a high density plasma 28 The ions in the nozzle 10 can be efficiently guided to the depth of the opening in the film on the substrate 2811. Cut.

[0432] For example, in the chamber 2706b, oxygen is introduced from the gas supply source 2801 to form a high density The oxygen radical treatment is performed using the high-temperature plasma 2810, and the gas Nitrogen radicals using high-density plasma 2810 by introducing nitrogen from a supply source 2801 Processing can be performed.

[0433] Next, the chamber 2706a and the chamber 2706d are shown in a cross-sectional schematic diagram in FIG. The following explains using the diagram.

[0434] The chambers 2706a and 2706d are used for, for example, irradiating the object to be treated with electromagnetic waves. In addition, the chamber 2706a and the chamber 27 The only difference between the 06d and the 06i is the type of electromagnetic wave. The rest of the configuration is the same. Because there are many, we will explain them together below.

[0435] Chamber 2706a and chamber 2706d may include one or more lamps 2820. , a substrate stage 2825, a gas inlet 2823, and an exhaust port 2830. , outside chamber 2706a and chamber 2706d, a gas supply source 2821 , a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0436] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The air pump 2828 is connected to an exhaust port 2830 via a valve 2829. The substrate stage 2825 is disposed opposite the substrate stage 2820. The substrate stage 2825 has a function of holding the substrate 2824. It has a mechanism 2826 and has a function of heating the substrate 2824 .

[0437] The lamp 2820 has a function of emitting electromagnetic waves such as visible light or ultraviolet light. For example, a light source having a wavelength of 10 nm or more and 2500 nm or less, or a light source having a wavelength of 500 nm or more and 2500 nm or less, may be used. Emitting electromagnetic waves with a peak of 2000 nm or less, or between 40 nm and 340 nm It is sufficient to use a light source having such a function.

[0438] For example, the lamp 2820 may be a halogen lamp, a metal halide lamp, a xenon lamp, or a -lamp, carbon arc lamp, high pressure sodium lamp or high pressure mercury lamp A light source may be used.

[0439] For example, electromagnetic waves emitted from the lamp 2820 may be partially or completely transmitted to the substrate 2824. The absorption can modify the film on the substrate 2824. For example, the generation of defects The substrate 2824 can be heated while: By irradiating electromagnetic waves, it is possible to efficiently create or reduce defects, or remove impurities. can.

[0440] Alternatively, for example, the substrate stage 2825 may be moved by electromagnetic waves emitted from the lamp 2820. In this case, the inside of the substrate stage 2825 may be heated. The heating mechanism 2826 may not be included.

[0441] For the vacuum pump 2828, see the description of the vacuum pump 2817. 2826 refers to the description of the heating mechanism 2813. Also, the gas supply source 2821 , see the description of gas source 2801.

[0442] By using the above manufacturing equipment, it is possible to suppress the inclusion of impurities in the processed object while modifying the film, etc. This becomes possible.

[0443] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0444] (Embodiment 11) <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0445] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline oxide semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li ke oxide semiconductor), and amorphous oxide semiconductor.

[0446] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, and nc-OS.

[0447] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angles are flexible and the bond length is short. In other words, it is a structure that has order but does not have long-range order.

[0448] On the other hand, in the case of an essentially stable oxide semiconductor, It cannot be called an oxide semiconductor. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is transformed into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a periodic Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0449] <caac-os> First, let me explain about CAAC-OS.

[0450] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0451] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0452] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration corrector function was used. In particular, it is called a Cs-corrected high-resolution TEM image. This was carried out using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by Nippon Denki Co., Ltd. This can be done.

[0453] FIG. 28(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 28(A). From FIG. 28(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0454] As shown in Figure 28(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 28(B) and Figure 28(C). Therefore, the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). In addition, CAAC-OS is also used as a C-Axis Aligned Nanocry The semiconductor may also be referred to as an oxide semiconductor having a stals structure.

[0455] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 28(D)). The inclination between the pellets observed in FIG. 28(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0456] FIG. 29(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in FIG. 29(A). The enlarged Cs-corrected high-resolution TEM images are shown in Fig. 29(B), Fig. 29(C), and Fig. 29(D). From Fig. 29(B), Fig. 29(C) and Fig. 29(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0457] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When the structure is analyzed using the out-of-plane method, the result is as shown in Figure 30(A). A peak may appear at a diffraction angle (2θ) of about 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0458] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0459] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ shift is When scanning was performed, the peaks attributable to the crystal plane equivalent to the (110) plane were as shown in FIG. Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0460] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in FIG. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. The first ring in FIG. 31(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and other factors. The second ring in Figure 31(B) This is thought to be due to the (110) plane, etc.

[0461] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so the opposite view is taken. CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0462] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0463] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0464] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 pieces / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be a high-purity intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and is a substantially high-purity intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0465] <nc-os> Next, we will explain nc-OS.

[0466] In the high-resolution TEM image, the nc-OS is divided into two groups: one where the crystals can be confirmed, and the other where the crystals can be clearly confirmed. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In addition, the nanocrystals are different from the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is called pellets. There may be cases where this happens.

[0467] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be considered to be a-like OS or amorphous oxide semiconductor. For example, for nc-OS, the X-shaped pellets with a diameter larger than that of the pellets may not be distinguishable. When using the line, the peaks showing the crystal planes were not detected by the out-of-plane method. In addition, for nc-OS, a probe diameter larger than the pellet (e.g. 50n When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than that of the pellet. When performing nanobeam electron diffraction using an electron beam with a diameter of n When nanobeam electron diffraction is performed on c-OS, bright spots appear in a circular (ring-like) pattern. In some cases, a ring-shaped area may be observed. In addition, multiple spots may be observed within the ring-shaped area. There are cases.

[0468] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0469] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0470] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0471] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen and areas where crystals cannot be seen. and areas where it is not possible to

[0472] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0473] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0474] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0475] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0476] Figure 32 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Figure 32, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2×10 in size, but the cumulative irradiation dose was 4.2×10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the nanoparticles grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 32, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are about 1.4 nm and 2.1 nm, respectively. I realize something.

[0477] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0478] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0479] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0480] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be determined by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0481] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0482] (Embodiment 12) In this embodiment, a semiconductor device including a transistor according to one embodiment of the present invention is An example of the circuit will be described.

[0483] <CMOSインバータ> The circuit diagram shown in FIG. 33(A) includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected. 4 shows the configuration of an S inverter.

[0484] <Semiconductor device structure 1> 34 is a cross-sectional view of the semiconductor device corresponding to FIG. 33(A). The transistor 2200 includes a transistor 2100. The transistor 2100 is disposed above the transistor 2200. Therefore, the transistors described in the above embodiments can be used. For the transistor 2100, the above description of the transistor can be referred to as appropriate. This can be done.

[0485] A transistor 2200 shown in FIG. 34 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472 a in the semiconductor substrate 450 and a It has a region 472b, an insulator 462, and a conductor 454.

[0486] In transistor 2200, regions 472a and 472b are source and The insulator 462 functions as a gate insulator. The conductor 454 also functions as a gate electrode. The resistance of the channel forming region can be controlled by applying a potential to the body 454. That is, the electric potential applied to the conductor 454 causes a conduction line between the region 472a and the region 472b. The non-conduction can be controlled.

[0487] The semiconductor substrate 450 may be, for example, a single semiconductor substrate such as silicon or germanium. or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A semiconductor substrate such as a gallium oxide substrate may be used. A single crystal silicon substrate is used.

[0488] The semiconductor substrate 450 is a semiconductor substrate having impurities that impart n-type conductivity. The semiconductor substrate 450 is a semiconductor substrate having an impurity that imparts p-type conductivity. In that case, the region that will become the transistor 2200 is given n-type conductivity. Alternatively, even if the semiconductor substrate 450 is an i-type, That's fine.

[0489] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The on-characteristics of the transistor 2200 can be improved.

[0490] Regions 472a and 472b are regions having impurities that impart p-type conductivity. In this manner, transistor 2200 constitutes a p-channel transistor.

[0491] Note that transistor 2200 is isolated from adjacent transistors by regions 460, etc. The region 460 is an insulating region.

[0492] The semiconductor device shown in FIG. 34 includes an insulator 464, an insulator 466, an insulator 468, and a conductor. 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b. , conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, and insulator An insulator 489, an insulator 490, an insulator 492, an insulator 493, an insulator 494, and an insulator and an edge body 495.

[0493] The insulator 464 is disposed on the transistor 2200. The insulator 466 is disposed on the insulator 4 64. Insulator 468 is disposed on insulator 466. Insulator 4 89 is disposed on the insulator 468. Also, the transistor 2100 is disposed on the insulator 489. Also, an insulator 493 is disposed on the transistor 2100. Also, an insulator 4 94 is disposed on the insulator 493 .

[0494] The insulator 464 has an opening reaching the region 472a, an opening reaching the region 472b, and a conductive The openings each include a conductor 480a, a conductor 480b, and an opening that reaches the conductor 454. The conductive body 480b or the conductive body 480c is embedded therein.

[0495] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0496] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0497] The insulator 489 has an opening overlapping with a channel formation region of the transistor 2100 and a conductive The opening reaches the conductor 476a and the opening reaches the conductor 476b. The mouths are embedded with conductors 474a, 474b, and 474c, respectively. is.

[0498] The conductor 474a may function as a gate electrode of the transistor 2100. Alternatively, for example, a constant potential may be applied to the conductor 474a to turn on the transistor 210. Alternatively, the electrical properties of the conductor 474 may be controlled, such as the threshold voltage of 0. a and the conductor 504 functioning as the gate electrode of the transistor 2100 are electrically This can increase the on-state current of the transistor 2100. In addition, since the punch-through phenomenon can be suppressed, the transistor 210 The electrical characteristics in the saturated region of 0 can be stabilized. Since this corresponds to the conductor 413 in the embodiment, the description of the conductor 413 should be referred to for details. It is possible.

[0499] The insulator 490 has an opening that reaches the conductor 474b. Since this corresponds to the insulator 402 in the above embodiment, for details, refer to the description of the insulator 402. I can pour drinks.

[0500] Also, the insulator 495 is a conductive layer that is either the source or the drain of the transistor 2100. An opening through body 507b to conductor 474b and the source of transistor 2100 An opening reaching the conductor 507a, which is the other of the drains, and An opening reaching the conductor 504, which is the gate electrode, and an opening reaching the conductor 474c are provided. Note that the insulator 495 corresponds to the insulator 410 in the above embodiment, and therefore will not be described in detail. For details, the description of the insulator 410 can be referred to.

[0501] The insulator 493 is a conductive layer that is either the source or the drain of the transistor 2100. An opening through body 507b to conductor 474b and the source of transistor 2100 An opening reaching the conductor 507a, which is the other of the drains, and An opening reaching the conductor 504, which is the gate electrode, and an opening reaching the conductor 474c are provided. The openings are provided with a conductor 496a, a conductor 496b, and a conductor 496c. and conductor 496d are embedded in the openings. This may be through an opening in one of the components, such as resistor 2100.

[0502] The insulator 494 has an opening that reaches the conductor 496a, and a conductor 496b and a The opening reaches the conductor 496d, and the opening reaches the conductor 496c. The conductive body 498a, the conductive body 498b, and the conductive body 498c are embedded in the conductive body 498a, the conductive body 498b, and the conductive body 498c, respectively. do.

[0503] Insulator 464, Insulator 466, Insulator 468, Insulator 489, Insulator 493 and Insulator Examples of 494 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in a single layer or in Alternatively, the film may be used in a laminated form.

[0504] Insulator 464, Insulator 466, Insulator 468, Insulator 489, Insulator 493 or Insulator At least one of 494 has an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to add impurities such as hydrogen and oxygen to the vicinity of the transistor 2100. By disposing an insulator having a locking function, the electrical characteristics of the transistor 2100 are It can stabilize the sex.

[0505] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in a single layer or in a multilayer.

[0506] Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, Conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, Conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, The conductor 498a, the conductor 498b, and the conductor 498c may be, for example, boron, nitrogen, or the like. , oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt , nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium A conductor containing one or more of aluminum, silver, indium, tin, tantalum and tungsten is formed in a single layer. For example, the material may be an alloy or a compound, and aluminum may be used. Conductor containing copper and titanium Conductor containing copper and manganese Conductor containing indium Alternatively, a conductor containing tin and oxygen, or a conductor containing titanium and nitrogen may be used.

[0507] The semiconductor device shown in FIG. 35 is the same as the transistor 2200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The transistor 2200 is a Fin type. As a result, the effective channel width is increased, improving the on-characteristics of the transistor 2200. In addition, the contribution of the electric field of the gate electrode can be increased, The off characteristics of the transistor 2200 can be improved.

[0508] 36 is a semiconductor device in which the transistor 2200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 200 is provided on a semiconductor substrate 450 which is an SOI substrate. 1 shows a structure in which region 456 is separated from semiconductor substrate 450 by insulator 452. By using an SOI substrate as the conductive substrate 450, punch-through phenomenon and the like can be suppressed. Therefore, the off-state characteristics of the transistor 2200 can be improved. The insulator 452 can be formed by insulating the semiconductor substrate 450. For example, the insulator 452 can be silicon oxide.

[0509] The semiconductor device shown in FIG. 34 to FIG. 36 is a semiconductor substrate having a p-channel transistor. By fabricating a MOSFET and fabricating an n-channel transistor above it, the area occupied by the device is reduced. In other words, the integration density of the semiconductor device can be increased. A p-channel transistor and a p-channel transistor were fabricated using the same semiconductor substrate. Since the process can be simplified compared to the conventional method, the productivity of the semiconductor device can be increased. In addition, the yield of the semiconductor device can be increased. The transistor is in the LDD (Lightly Doped Drain) region, shallow trench In some cases, complex processes such as ch-structure and distortion design can be omitted. Compared to manufacturing transistors using a semiconductor substrate, the productivity and yield are improved. It may be possible to reduce the

[0510] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 33B is that of a transistor 2100 and a transistor 2200. The source and drain of each transistor are connected. It can function as a so-called CMOS analog switch.

[0511] <Storage device 1> A transistor according to one embodiment of the present invention is used to retain stored contents even when power is not supplied FIG. 37 shows an example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written. As shown in.

[0512] The semiconductor device shown in FIG. 37A includes a transistor 3200 using a first semiconductor and a The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 is the same as the transistor 2100 described above. It is possible.

[0513] The transistor 3300 is preferably a transistor having a low off-state current. For example, a transistor including an oxide semiconductor can be used as the transistor 00. The small off-state current of the capacitor 3300 allows for long-term recording at a specific node of the semiconductor device. The contents of the memory can be retained, i.e., no refresh operation is required, or This allows the frequency of refresh operations to be reduced significantly, resulting in a semiconductor with low power consumption. It becomes a body device.

[0514] In FIG. 37A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitor 3400 .

[0515] The semiconductor device shown in FIG. 37A is capable of holding a gate potential of the transistor 3200. This property makes it possible to write, hold, and read information, as shown below. do.

[0516] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is set to a potential at which the transistor 3300 is turned on. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and the The signal is applied to a node FG that is electrically connected to one of the electrodes of the capacitance element 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). Charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) Then, the potential of the fourth wiring 3004 is applied to the transistor. By setting the potential at which the transistor 3300 is in a non-conducting state, the transistor 3300 is in a non-conducting state. As a result, charge is held at the node FG (retention).

[0517] Since the off-state current of the transistor 3300 is small, the charge of the node FG is retained for a long period of time. It will be held.

[0518] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, 3002 takes a potential according to the amount of charge held in the node FG. This is the transistor If 3200 is an n-channel type, a high-level charge is applied to the gate of transistor 3200. The apparent threshold voltage V th_H is the transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is This refers to the potential of the fifth wiring 3005 required to make it in a "conductive state." Then, the potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential between For example, in a write, the charge applied to node FG can be determined. When a high-level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 is in a "conducting state." On the other hand, the node FG When a low-level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." By determining the potential of the second wiring 3002, the data stored in the node FG is read. It can be put out.

[0519] When memory cells are arranged in an array, the information of a desired memory cell is read. For example, in memory cells that do not read information, The voltage applied to the FG terminal is such that the transistor 3200 is in a "non-conducting state." V th_H By applying a lower potential to the fifth wiring 3005, a desired memory It is sufficient to have a configuration in which only the information in the cell can be read. Alternatively, the memory cell from which information is not read can be configured. In this case, the transistor 3200 is in a "conducting state" regardless of the charge applied to the node FG. That is, V th_L Applying a higher potential to the fifth wiring 3005 It is only necessary to have a configuration in which only the information in a desired memory cell can be read out.

[0520] In the above, an example in which two types of charges are held in the node FG is shown. The semiconductor device according to the present invention is not limited to this. For example, It may be configured to hold three or more types of charges. The semiconductor device can be made multi-valued to increase the memory capacity.

[0521] <Memory device structure 1> 38 is a cross-sectional view of the semiconductor device corresponding to FIG. 37(A). The semiconductor memory device includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are disposed above the transistor 3200. The transistor 3300 is arranged in the same manner as the transistor 2100 described above. In addition, the transistor 3200 may be the transistor shown in FIG. Please refer to the description of transistor 2200 in FIG. The case where the transistor 3200 is an n-channel transistor has been described. A transistor of a channel type may also be used.

[0522] A transistor 2200 shown in FIG. 38 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472 a in the semiconductor substrate 450 and a It has a region 472b, an insulator 462, and a conductor 454.

[0523] The semiconductor device shown in FIG. 38 includes an insulator 464, an insulator 466, an insulator 468, and a conductor. 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b. , conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, and insulator An insulator 489, an insulator 490, an insulator 492, an insulator 493, an insulator 494, and an insulator and an edge 495.

[0524] An insulator 464 is disposed on the transistor 3200. Also, an insulator 466 is disposed on the insulator 4 64. Insulator 468 is disposed on insulator 466. Insulator 4 89 is disposed on the insulator 468. Also, the transistor 2100 is disposed on the insulator 489. Also, an insulator 493 is disposed on the transistor 2100. Also, an insulator 4 94 is disposed on the insulator 493 .

[0525] The insulator 464 has an opening reaching the region 472a, an opening reaching the region 472b, and a conductive The openings each include a conductor 480a, a conductor 480b, and an opening that reaches the conductor 454. The conductive body 480b or the conductive body 480c is embedded therein.

[0526] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0527] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0528] The insulator 489 has an opening overlapping with a channel formation region of the transistor 3300 and a conductor The opening reaches the conductor 476a and the opening reaches the conductor 476b. The mouths are embedded with conductors 474a, 474b, and 474c, respectively. is.

[0529] The conductor 474a may function as a bottom gate electrode of the transistor 3300. Alternatively, for example, applying a constant potential to the conductor 474a may cause the transistor It is also possible to control electrical properties such as the threshold voltage of 3300. 474a is electrically connected to the conductor 504 which is the top gate electrode of the transistor 3300. This can increase the on-current of the transistor 3300. In addition, the punch-through phenomenon can be suppressed, so the transistor 3300 The electrical characteristics in the saturation region can be stabilized.

[0530] In addition, the insulator 490 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. Note that the insulator 490 corresponds to the insulator 402 in the above embodiment, For details, the description of the insulator 402 can be referred to.

[0531] Also, the insulator 495 is a conductive layer that is either the source or the drain of the transistor 3300. An opening through body 507b to conductor 474b and the source of transistor 3300 An opening extending from the other conductor 507a, which is the drain, to the conductor 515, and a transistor The other of the source and drain of the transistor 3300 is connected to the conductor 4 The insulator 495 has an opening reaching the insulator 74c. 0, so for details, the description of the insulator 410 can be referred to.

[0532] The insulator 493 reaches the conductor 514 that overlaps the conductor 515 through the insulator 511. An opening that reaches the conductor that is the gate electrode of transistor 3300, and an opening that reaches the conductor that is the gate electrode of transistor 3300. 3300. The openings each have an opening that reaches the conductor 516. The openings also have an opening that reaches the conductor 496e. , conductor 496b, and conductor 496f are embedded in the openings. The portion may also be connected through an opening in any of the components, such as the transistor 3300. There is a match.

[0533] In addition, the insulator 494 has an opening that reaches the conductor 496e and an opening that reaches the conductor 496b. The openings each have a conductor 496f. 498a, conductor 498b or conductor 498c is embedded.

[0534] Insulator 464, Insulator 466, Insulator 468, Insulator 489, Insulator 493 or Insulator At least one of 494 has an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to add impurities such as hydrogen and oxygen to the vicinity of the transistor 3300. By disposing an insulator having a locking function, the electrical characteristics of the transistor 3300 are It can stabilize the sex.

[0535] The source or drain of transistor 3200 is connected to conductor 480b and conductor 478b. , the conductor 476a, the conductor 474b, and the conductor 496c. 00, which is either the source or drain of the conductor 507b. The conductor 454, which is the gate electrode of the transistor 3200, is connected to the conductor 480c and the conductor 47 8c, the conductor 476b, the conductor 474c, and the conductor 496d. The source and drain of the transistor 3300 are electrically connected to the conductor 507a.

[0536] The capacitor 3400 includes a conductor 515 , a conductor 514 , and an insulator 511 .

[0537] For other structures, please refer to the descriptions in Figure 34 etc. as appropriate.

[0538] The semiconductor device shown in FIG. 39 is the same as the transistor 3200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The figure shows a case where the transistor 200 is a fin type. For details, refer to the description of the transistor 2200 shown in FIG. The transistor 2200 is a p-channel transistor. The transistor 3200 may be an n-channel transistor.

[0539] 40 is a semiconductor device having a transistor 3200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 200 is provided on a semiconductor substrate 450 which is an SOI substrate. The transistor 3200 provided on the semiconductor substrate 450 is shown in FIG. Please refer to the description of the transistor 2200. Note that in FIG. The case where the transistor 3200 is an n-channel transistor has been described. A transistor of a channel type may also be used.

[0540] <Storage device 2> The semiconductor device shown in FIG. 37B differs from the semiconductor device shown in FIG. 37A in that it does not include a transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This makes it possible to write and retain information more easily.

[0541] The reading of data in the semiconductor device shown in FIG. When the capacitor 3300 is turned on, the third wiring 3003 and the capacitor element 3400, which are in a floating state, The third wiring 3003 and the capacitor 3400 are electrically connected to each other, and electric charges are redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is expressed by the capacitance The potential of one of the electrodes of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0542] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× VB0+CV) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes of 3400 can take two states, V1 and V0 (V1>V0), then The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+CV1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=(C B×VB0+CV0) / (CB+C)).

[0543] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0544] In this case, the transistor in which the first semiconductor is applied to a driving circuit for driving the memory cell. A transistor in which a second semiconductor is applied is used as the transistor 3300. The structure may be such that the electrodes are stacked on the driving circuit.

[0545] The above-described semiconductor device uses a transistor including an oxide semiconductor and has low off-state current. By doing so, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store the potential for a long period of time. It is possible to maintain the capacity.

[0546] In addition, the semiconductor device does not require a high voltage to write information, so that deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, injection of electrons into the floating gate Since electrons are not introduced or removed from the floating gate, there is no risk of degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the problem of a conventional nonvolatile memory. A semiconductor device with dramatically improved reliability, without the problematic limit on the number of times it can be rewritten Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This enables high-speed operation.

[0547] <Storage device 3> Regarding a modification of the semiconductor device (memory device) shown in FIG. 37(A), a circuit diagram shown in FIG. I will explain this in more detail.

[0548] The semiconductor device illustrated in FIG. 41 includes transistors 4100 to 4400 and a capacitor. The transistor 4100 includes a transistor 4500 and a capacitor 4600. A transistor similar to the transistor 3200 can be used, and the transistor 4200 The transistors 4400 to 4400 can be similar to the transistor 3300 described above. The semiconductor device shown in FIG. 41 is a multi-layered semiconductor device arranged in a matrix, which is not shown in FIG. The semiconductor device shown in FIG. 4009 to control writing and reading of data voltage according to a signal or potential applied to the It is possible.

[0549] One of the source and the drain of the transistor 4100 is connected to a wiring 4003. The other of the source and the drain of the transistor 4100 is connected to a wiring 4001. In FIG. 1, the conductivity type of the transistor 4100 is shown as a p-channel type, but it may also be an n-channel type. good.

[0550] The semiconductor device shown in FIG. 41 has two data storage units. For example, the first data storage unit is , one of the source and drain of the transistor 4400 connected to the node FG1, Between one electrode of the transistor 4600 and one of the source or drain of the transistor 4200 The second data storage unit is a transistor connected to the node FG2. The gate of transistor 4100, the other of the source or drain of transistor 4200, A charge is stored between one of the source or drain of the capacitor 300 and one of the electrodes of the capacitor element 4500. Hold.

[0551] The other of the source and the drain of the transistor 4300 is connected to a wiring 4003. The other of the source and the drain of the transistor 4400 is connected to a wiring 4001. The gate of the transistor 4400 is connected to the wiring 4005. The gate of the transistor 4200 is The gate of the transistor 4300 is connected to a wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode is connected to a wiring 4009 .

[0552] The transistors 4200 to 4400 are transistors that control writing of data voltages and retention of electric charges. Note that the transistors 4200 to 4400 are in a non-conducting state. In this case, a transistor with a low current (off-state current) that flows between the source and drain is used. As a transistor with a low off-state current, a transistor having an oxidized layer in a channel formation region is preferably used. Preferably, the transistor is an OS transistor having an organic semiconductor. The advantages of a silicon-based transistor include a low off-state current and the ability to be stacked with a silicon-based transistor. In FIG. 41, the conductivity type of the transistors 4200 to 4400 is an n-channel type. However, a p-channel type may also be used.

[0553] The transistor 4200, the transistor 4300, and the transistor 4400 are made of an oxide Even if a transistor is made of a semiconductor, it is preferable to provide it in a separate layer. The semiconductor device shown in FIG. 41 includes a first layer 40 having a transistor 4100. 21, a second layer 4022 having a transistor 4200 and a transistor 4300, and a third layer 4023 having a transistor 4400. By stacking layers having transistors, the circuit area can be reduced, and the semiconductor device This allows the device to be made more compact.

[0554] Next, the operation of writing information into the semiconductor device shown in FIG. 41 will be described.

[0555] First, a data voltage is written to the data storage unit connected to node FG1 (hereinafter, In the following, the write operation 1 will be described. The data voltage to be written to the data storage unit is V D1 The threshold voltage of the transistor 4100 is The voltage is Vth.

[0556] In write operation 1, the line 4003 is connected to V D1 Then, after setting the wiring 4001 to the ground potential, The wirings 4005 and 4006 are set to a high level. 007 to 4009 are set to a low level. Then, the node FG2, which is in an electrically floating state, The potential of the wiring 40 increases, and a current flows through the transistor 4100. The potential of the transistor 4400 and the transistor 4200 are turned on. Therefore, as the potential of the wiring 4001 increases, the potentials of the nodes FG1 and FG2 also increase. The potential of the node FG2 rises, and a potential difference between the gate and source of the transistor 4100 increases. When the voltage (Vgs) reaches the threshold voltage Vth of the transistor 4100, the transistor 410 Therefore, the potential of the wiring 4001, the nodes FG1 and FG2 The rise stopped, and V D1 Vth has dropped from D1 -Vth".

[0557] In other words, the V given to wire 4003 D1 When a current flows through the transistor 4100, The potential is applied to the wiring 4001, and the potentials of the nodes FG1 and FG2 increase. , the potential of node FG2 is "V D1 -Vth", the Vgs of transistor 4100 is Vth is reached and the current stops.

[0558] Next, a data voltage is written to the data storage unit connected to node FG2 (hereinafter, “write”). The data retention operation connected to node FG2 is called write operation 2. The data voltage written to the section is V D2 This is explained as follows.

[0559] In write operation 2, the line 4001 is connected to V D2 Then, after setting the wiring 4003 to the ground potential, The wiring 4007 is set to a high level. 006, 4008, and 4009 are set to low level. Transistor 4300 is set to a conductive state. Therefore, the potential of the node FG2 is also set to a low level. The voltage Vcc of the wiring 4003 decreases, and a current flows through the transistor 4100. The potential of the wiring 4003 increases. In addition, the transistor 4300 is turned on. As the potential rises, the potential at node FG2 rises. When Vgs of transistor 4100 becomes Vth of transistor 4100, The current flowing through 100 is reduced. As a result, the potential of the wiring 4003 and the node FG2 increases. stops, V D2 Vth has dropped from D2 -Vth".

[0560] In other words, the V given to wire 4001 D2 When a current flows through the transistor 4100, The potential of the node FG2 is increased by the increase in the potential. The potential of FG2 is "V D2 -Vth", the Vgs of transistor 4100 is Vth. At this time, the potential of the node FG1 is the same as that of the transistors 4200 and 4201. 400 are in a non-conducting state, and the "V D1 -Vth" is maintained can be.

[0561] In the semiconductor device shown in FIG. 41, after writing data voltages to a plurality of data holding units, By setting 4009 to a high level, the potentials of the nodes FG1 and FG2 are raised. The transistor is put into a non-conductive state, preventing the movement of charge and retaining the written data voltage. .

[0562] By the above-described data voltage write operation to the nodes FG1 and FG2, multiple data The data voltage can be stored in the data storage section. D 1-Vth" or "V D2 -Vth" was used as an example, but these are multi-value data. Therefore, each data storage section stores 4 bits of data. When holding, 16 values ​​of "V D1 -Vth" or "V D2 -Vth".

[0563] Next, the operation of reading information from the semiconductor device shown in FIG. 41 will be described.

[0564] First, a data voltage is read from the data storage unit connected to node FG2 (hereinafter, This operation is called read operation 1.

[0565] In the read operation 1, the wiring 4003, which is precharged and then put into an electrically floating state, The wirings 4005 to 4008 are set to a low level. The potential of the electrically floating node FG2 is set to "V D2 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. The current flows, and the potential of the wiring 4003, which is in an electrically floating state, drops. As the voltage Vgs of transistor 4100 decreases, the voltage Vgs of transistor 4100 decreases. When Vgs becomes the Vth of the transistor 4100, the current flowing through the transistor 4100 becomes That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2 “V D2 -Vth” Vth is larger than Vth. D2 The potential of the wiring 4003 is The data voltage of the data storage section connected to G2 corresponds to the data of the analog value that is read out. The voltage of the capacitor is converted into digital data and the data is acquired from the data storage section connected to node FG2. .

[0566] In other words, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. By switching the input from high to low, current flows through transistor 4100. As a result, the potential of the wiring 4003, which was in a floating state, drops to "V D2 " Tran In register 4100, the "V D2 -Vth" is Vth. The current stops. Then, the wiring 4003 is connected to the "V D2 " is read out.

[0567] After acquiring the data of the data storage section connected to the node FG2, the transistor 4300 is In the conductive state, the "V D2 -Vth" is discharged.

[0568] Next, the charge held at node FG1 is distributed to node FG2, and the The data voltage of the data storage unit connected to node FG1 is transferred to the data storage unit connected to node FG2. Then, the wirings 4001 and 4003 are set to low level, and the wiring 4006 is set to high level. , the wiring 4005 and the wirings 4007 to 4009 are set to low level. When the node FG1 is turned on, the charge of the node FG1 is shared with the node FG2.

[0569] Here, the potential after the charge distribution is the written potential "V D1 -Vth". Therefore, the capacitance value of the capacitance element 4600 is set to be larger than the capacitance value of the capacitance element 4500. Alternatively, the potential "V D1 -Vth" is the same data The potential "V D2 It is preferable to set the capacitance value to be larger than "-Vth". By changing the ratio of the potential and increasing the potential to be written in advance, the potential after the charge distribution can be reduced. The change in potential due to the distribution of charge will be described later.

[0570] Next, a data voltage is read from the data storage unit connected to the node FG1 (hereinafter, read This is called read-out operation 2.

[0571] In the read operation 2, the wiring 4003, which is precharged and then put into an electrically floating state, The wirings 4005 to 4008 are set to a low level. The signal is set to high level during precharge and then to low level. By making the node FG2 in an electrically floating state into a potential of "V D1 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. As a result, the potential of the wiring 4003, which is in an electrically floating state, is reduced. As the voltage Vgs of transistor 4100 decreases, the voltage Vgs of transistor 4100 decreases. When gs becomes the Vth of the transistor 4100, the current flowing through the transistor 4100 becomes small. That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2 “V D1 -Vth" or Vth is larger than the D1 The potential of the wiring 4003 is the node FG The analog value data read out corresponds to the data voltage of the data storage section connected to 1. The voltage undergoes A / D conversion, and data is acquired from a data storage section connected to node FG1. The above is the operation of reading out the data voltage to the data holding unit connected to node FG1.

[0572] In other words, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. By switching the input from high to low, current flows through transistor 4100. As a result, the potential of the wiring 4003, which was in a floating state, drops to "V D1 " Tran In register 4100, the "V D1 -Vth" is Vth. The current stops. And the wiring 4003 is connected to the "V D1 " is read out.

[0573] By the above-described operation of reading the data voltages from the nodes FG1 and FG2, multiple data For example, the data voltages at nodes FG1 and FG2 can be read out from the data storage unit. G2 stores 4 bits (16 values) of data, for a total of 8 bits (256 values). In FIG. 41, the first layer 4021 to the third layer The semiconductor device is configured with a layer 4023, but by forming further layers, the area of ​​the semiconductor device can be increased. It is possible to increase the storage capacity without increasing the memory capacity.

[0574] The potential that is read out is a voltage that is Vth higher than the written data voltage. Therefore, the "V D1 -Vth" or "V D2 - As a result, the Vth of the memory cell can be offset. This improves the memory capacity per memory and makes the read data closer to the correct data. This makes it possible to obtain data with excellent reliability.

[0575] FIG. 42 is a cross-sectional view of the semiconductor device corresponding to FIG. 41. The semiconductor device shown in FIG. , transistors 4100 to 4400, a capacitor 4500, and a capacitor 4 600. Here, the transistor 4100 is formed in the first layer 4021, The transistors 4200 and 4300 and the capacitor element 4500 are formed in the second layer 4022. The transistor 4400 and the capacitor 4600 are formed in the third layer 4023 .

[0576] Here, the description of the transistor 3300 is used as the transistors 4200 to 4400. The transistor 4100 can be described with reference to the description of the transistor 3200. The description in Figure 38 can also be taken into consideration as appropriate for other wiring, insulators, etc.

[0577] In the capacitance element 3400 of the semiconductor device shown in FIG. 38, the conductive layer is provided parallel to the substrate. In the capacitor elements 4500 and 4600, a conductive layer is formed in a trench shape. By using such a configuration, the occupied area is the same. Even if the capacitance is large, a large capacitance value can be ensured.

[0578] <fpga> Another aspect of the present invention is a field programmable gate array (FPGA). This can also be applied to LSIs such as MOS Arrays.

[0579] FIG. 43(A) shows an example of a block diagram of an FPGA. The logic element 522 is a switch element 521. The clock element 522 reads the configuration data stored in the configuration memory. Depending on the application data, the logic circuit functions as a combinational circuit or a sequential circuit. You can switch functions.

[0580] FIG. 43B is a schematic diagram for explaining the role of the routing switch element 521. The routing switch element 521 includes a configuration memory 52 3, the connections between the logic elements 522 are determined according to the configuration data stored in the In FIG. 43(B), one switch is shown, with terminals IN and The diagram shows how to switch the connections between the OUT terminals. A switch is provided between the components 522.

[0581] FIG. 43C shows an example of a circuit configuration that functions as the configuration memory 523. The configuration memory 523 is a transistor configured with OS transistors. The transistor M11 is a Si transistor, and the transistor M12 is a Si transistor. Node FN SW The configuration data is transferred to the D SW This configuration data D SW The potential of the transistor The configuration can be retained by making M11 non-conductive. Data D SW The potential of the terminal The connection between IN and terminal OUT can be switched.

[0582] FIG. 43D is a schematic diagram for explaining the role of the logic element 522. The block element 522 stores the configuration data stored in the configuration memory 527. Depending on the configuration data, the terminal OUT mem The potential of the The up-table 524 is connected to the terminal OUT mem The signal at the terminal IN is processed according to the potential of The function of the combinational circuit can be switched. The first circuit is a register 525 and a selector 526 for switching the signal at the terminal OUT. The selector 526 receives a terminal O output from the configuration memory 527. U.T. mem Depending on the potential of You can choose between outputting 5 signals.

[0583] FIG. 43E shows an example of a circuit configuration that functions as the configuration memory 527. The configuration memory 527 is a transistor configured with OS transistors. A transistor M13, a transistor M14, and a transistor M1 5, and transistor M16. Node FN LE The transistor M Configuration data D through 13 LE is given. Node FNB LE for , the configuration data DB via transistor M14 LE is given. Configuration Data DB LE is the configuration data D LE The logic of This corresponds to the inverted potential. LE , configuration Sales data DB LE The potential of the transistor M13 and the transistor M14 are turned off. The configuration data D can be stored by doing the following. LE , Configuration Data DB LE The potential of transistor M15 or transistor The conductive state of one of the transistors M16 is switched, and the terminal OUT mem The potential VDD or can provide the potential VSS.

[0584] The configurations described in the above embodiments can be applied to the configurations of FIGS. For example, the transistors M12, M15, and M16 can be made of Si. The transistors are transistor M11, transistor M13, and transistor M14. In this case, the wiring that connects the lower layer Si transistors is The lines can be made of low-resistance conductive materials, which improves access speed and reduces power consumption. This makes it possible to provide a circuit with excellent power efficiency.

[0585] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0586] (Embodiment 13) In this embodiment, an imaging device using a transistor according to one embodiment of the present invention An example will be described.

[0587] <Configuration of imaging device> FIG. 44A is a plan view showing an example of an imaging device 200 according to one embodiment of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral circuit The pixel section 210 has p rows and q columns. (p and q are integers of 2 or more) have a plurality of pixels 211 arranged in a matrix. The peripheral circuits 260, 270, 280, and 290 each include a plurality of The pixel 211 is connected to the pixel 211 and has a function of supplying a signal for driving the pixel 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 may be considered a part of the peripheral circuit.

[0588] The imaging device 200 preferably also includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0589] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel portion 210 is formed. In addition, a part or the whole of the peripheral circuits may be made of semiconductor devices such as ICs. The peripheral circuits are a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. Any one or more of these may be omitted.

[0590] Also, as shown in FIG. 44B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel size in the row direction and the pixel size in the pixel area can be increased. The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the captured images.

[0591] <Pixel configuration example 1> The imaging device 200 has a pixel 211 that is composed of a plurality of sub-pixels 212. By combining a filter (color filter) that transmits light of a specific wavelength range with the pixel 212, In this way, information required to realize a color image display can be obtained.

[0592] FIG. 45(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 45(A) is provided with a color filter that transmits light in the red (R) wavelength range. The subpixel 212 (hereinafter also referred to as "subpixel 212R") transmits light in the green (G) wavelength range. A subpixel 212 (hereinafter also referred to as "subpixel 212G") is provided with a color filter that transmits light through the and a subpixel 212 (hereinafter referred to as The subpixel 212 functions as a photosensor. It is possible to do so.

[0593] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, The wiring 248 and the wiring 249 are respectively represented as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the mth column is designated as wiring 253[m]. In FIG. 45A, the sub-pixel 212R of the pixel 211 in the m-th column is written as follows: The wiring 253 connected to the subpixel 212G is disposed as wiring 253[m]R. The wiring 253 connected to the line 253[m]G and the subpixel 212B is referred to as a wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuitry via the wiring.

[0594] In addition, the imaging device 200 has color filters that transmit light of the same wavelength range for adjacent pixels 211. The sub-pixels 212 in which the filters are provided are electrically connected to each other via the switches. In Figure 45(B), the matrix is ​​arranged in n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). A sub-pixel 212 of a pixel 211 arranged in the n+1th row and the mth column adjacent to the pixel 211 is arranged in the n+1th row and the mth column. 45B shows an example of a connection of the sub-pixels 212 of the pixel 211 arranged in the nth row. The sub-pixel 212R arranged in the mth column and the sub-pixel 212R arranged in the n+1th row and the mth column are switched. In addition, the sub-pixels 212G arranged in the nth row and the mth column are connected via the n+ The sub-pixels 212G arranged in the first row and the mth column are connected via the switches 202. The sub-pixels 212B arranged in the nth row and the mth column and the sub-pixels 212B arranged in the n+1th row and the mth column are 203.

[0595] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light respectively. A single pixel 211 may have sub-pixels 211 for detecting light of three different wavelength ranges. By providing 12, a full color image can be obtained.

[0596] Alternatively, color filters that transmit red (R), green (G) and blue (B) light are provided. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Alternatively, pixel 211 may be used with pixel 212, or with cyan (C), yellow (Y In addition to the subpixel 212 provided with a color filter that transmits light of red (A) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. A pixel 211 may include sub-pixels 21 that detect light in four different wavelength ranges. By providing 2, the color reproducibility of the captured image can be further improved.

[0597] For example, in FIG. 45A, a subpixel 212 detects light in the red wavelength range, and a subpixel 213 detects light in the green wavelength range. A pixel of the subpixel 212 that detects light in the long wavelength range and a pixel of the subpixel 212 that detects light in the blue wavelength range. The ratio of the number of pixels (or the ratio of the light receiving areas) does not have to be 1:1:1. The area ratio may be a Bayer array with red:green:blue=1:2:1. The ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0598] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. By providing two or more sub-pixels 212 that detect light in the same wavelength range, redundancy is increased and imaging The reliability of the device 200 can be improved.

[0599] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0600] In addition, ND (Neutral Density) filters are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows the dynamic range of the device to be increased.

[0601] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described with reference to a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 46(A), a lens 255 and a filter 25 formed in a pixel 211 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0602] However, as shown in the area surrounded by the dashed line, a part of the light 256 indicated by the arrow is Therefore, as shown in Figure 46(B), A lens 255 and a filter 254 are disposed on the conversion element 220 side. It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, the imaging device 200 with high detection sensitivity is provided. can be done.

[0603] As the photoelectric conversion element 220 shown in FIG. 46, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0604] In addition, the photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating electric charges may be a sintered material. Iron, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0605] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 22 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 0 can be achieved.

[0606] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2, may include a subpixel 212 having a first filter.

[0607] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of forming a pixel using the above will be described.

[0608] 47(A) and 47(B) are cross-sectional views of elements constituting an imaging device. The imaging device shown in FIG. 1 includes a silicon transistor 35 provided on a silicon substrate 300. 1. Transistor 35 using an oxide semiconductor stacked over transistor 351 2 and a transistor 353, and a photodiode provided on the silicon substrate 300. Each transistor and photodiode 360 ​​is connected to a different plug 370. and is electrically connected to the wiring 371. 61 has an electrical connection to plug 370 through low resistance region 363 .

[0609] The imaging device includes a transistor 351 and a photodiode 352 disposed on a silicon substrate 300. A layer 310 having an electrode 360 ​​and a layer 371 provided in contact with the layer 310. 20 and in contact with layer 320, and includes transistors 352 and 353. A layer 330 is provided in contact with the layer 330 and has wiring 372 and wiring 373. It has 40.

[0610] In the example of the cross-sectional view of FIG. 47(A), the transistor 35 is disposed on the silicon substrate 300. The light receiving surfa...

Claims

1. A semiconductor device having a first transistor and a second transistor, A substrate; a first insulator above the substrate; a channel forming region of a first transistor above the first insulator; a second insulator above the channel forming region of the first transistor; a first conductor above the second insulator; a third insulator above the first conductor and the second insulator; a second conductor above the third insulator; and a fourth insulator over the second conductor; and a layer including a channel formation region of the second transistor above the fourth insulator; a third conductor and a fourth conductor having a region in contact with an upper surface of the layer including a channel formation region of the second transistor; a fifth insulator above a layer including a channel forming region of the second transistor; a fifth conductor above the fifth insulator and overlapping a channel formation region of the second transistor; a sixth insulator above the fifth conductor; and a sixth conductor above the sixth insulator; a channel formation region of the first transistor includes silicon; the first conductor functions as a gate electrode of the first transistor; the second conductor functions as a first gate electrode of the second transistor; a channel formation region of the second transistor includes an oxide semiconductor containing indium, gallium, and zinc; the third conductor functions as one of a source electrode and a drain electrode of the second transistor; the fourth conductor functions as the other of the source electrode and the drain electrode of the second transistor; the fifth conductor functions as a second gate electrode of the second transistor; the sixth conductor functions as a first electrode of a capacitance; In a cross-sectional view of the second transistor in a channel length direction, the first conductor does not overlap with the second conductor, the third conductor is electrically connected to one of the source and the drain of the first transistor; the fourth conductor is electrically connected to a gate electrode of the first transistor; the sixth conductor has a region overlapping with a first gate electrode of the first transistor and a region overlapping with a layer including a channel formation region of the second transistor.

2. A semiconductor device having a first transistor and a second transistor, A substrate; a first insulator above the substrate; a channel forming region of a first transistor above the first insulator; a second insulator above the channel forming region of the first transistor; a first conductor above the second insulator; a third insulator above the first conductor and the second insulator; a second conductor above the third insulator; and a fourth insulator over the second conductor; and a layer including a channel formation region of the second transistor above the fourth insulator; a third conductor and a fourth conductor having a region in contact with an upper surface of the layer including a channel formation region of the second transistor; a fifth insulator above a layer including a channel forming region of the second transistor; a fifth conductor above the fifth insulator and overlapping a channel formation region of the second transistor; a sixth insulator above the fifth conductor; and a sixth conductor above the sixth insulator; a channel formation region of the first transistor includes silicon; the first conductor functions as a gate electrode of the first transistor; the second conductor functions as a first gate electrode of the second transistor; a channel formation region of the second transistor includes an oxide semiconductor containing indium, gallium, and zinc; the third conductor functions as one of a source electrode and a drain electrode of the second transistor; the fourth conductor functions as the other of the source electrode and the drain electrode of the second transistor; the fifth conductor functions as a second gate electrode of the second transistor; the sixth conductor functions as a first electrode of a capacitance; In a cross-sectional view of the second transistor in a channel length direction, the first conductor does not overlap with the second conductor, the third conductor is electrically connected to one of the source and the drain of the first transistor; the fourth conductor is electrically connected to a gate electrode of the first transistor; the sixth conductor has a region overlapping with a first gate electrode of the first transistor and a region overlapping with a layer including a channel formation region of the second transistor; a lower surface of the fifth conductor is lower than a lower surface of a layer including a channel formation region of the second transistor in a cross-sectional view taken in a channel width direction of the second transistor.

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