Sampling circuit, analog-to-digital conversion circuit, and semiconductor integrated circuit

Abstract

A sampling circuit that has: a first capacitor (CP0) that has a first terminal and a second terminal; a second capacitor (CN0) that has a third terminal and a fourth terminal; a first input node (VINP) that has a first input voltage input thereto that is one of the differential voltages; a second input node (VINN) that has a second input voltage input thereto that is the other of the differential voltages; a first switching circuit (SW1) provided between the first input node and the first terminal; a second switching circuit (SW2) that is provided between the second input node and the third terminal; a third switching circuit (SW3) that is provided between the first terminal and the third terminal; and a fourth switching circuit (SW5) that is provided between the second terminal and the fourth terminal. During reset operation, the first switching circuit and the second switching circuit are turned off and the third switching circuit and the fourth switching circuit are turned on.

Description

[Technical field]

[0001] The present invention relates to a sampling circuit, an analog-to-digital conversion circuit, and a semiconductor integrated circuit. [Background technology]

[0002] Patent Document 1 describes an analog-to-digital conversion circuit having a first digital-to-analog converter and a second digital-to-analog converter. The first digital-to-analog converter takes in and holds sample data of a first analog signal, and generates a comparison signal to be compared with the first analog signal. The second digital-to-analog converter takes in and holds sample data of a second analog signal, and generates a comparison signal to be compared with the second analog signal. A first switch connects the output sides of the first digital-to-analog converter and the second digital converter to each other so as to be openable and closable. When the first switch is opened, the comparator compares a difference value between the first analog signal and the second analog signal with a difference value between an output signal of the first digital-to-analog converter and an output signal of the second digital-to-analog converter. A potential control circuit controls potential fluctuations of the first analog terminal and the second analog terminal.

[0003] Patent Document 2 describes an analog-to-digital converter having a capacitive main DAC, a resistive sub-DAC, and a resistive correction DAC. The capacitive main DAC has a positive side capacitive main DAC and a negative side capacitive main DAC that operate complementarily, and receives a differential signal to convert the most significant bits. The resistive sub-DAC converts the least significant bits. The resistive correction DAC corrects the capacitive main DAC. The comparator has a plurality of differential circuits and compares the output potentials of the positive side capacitive main DAC and the negative side capacitive main DAC. The positive side capacitive main DAC and the negative side capacitive main DAC each have a first capacitive element formed by wiring layers excluding the uppermost wiring layer. The comparator has a second capacitive element provided between adjacent differential circuits and formed by wiring layers including the uppermost wiring layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-142863 A [Patent Document 2] JP 2014-42358 A Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Documents 1 and 2, prior to a sampling operation, a reset operation is performed in which charges accumulated in a capacitive element in a digital-to-analog converter are discharged and the initial charge is set to zero.

[0006] If the equivalent input resistance of the analog-to-digital conversion circuit is not high enough, the digital code converted by the analog-to-digital conversion circuit will be smaller than the normal value. Therefore, it is desirable that the equivalent input resistance of the analog-to-digital conversion circuit is sufficiently high. However, in Patent Documents 1 and 2, it is difficult to make the equivalent input resistance of the analog-to-digital conversion circuit sufficiently high.

[0007] An object of the present invention is to provide a sampling circuit and an analog-to-digital conversion circuit that can provide a sufficiently high equivalent input resistance. [Means for solving the problem]

[0008] According to one aspect of the present invention, there is provided a sampling circuit that repeats a series of operations including a reset operation and a sampling operation, and samples a differential input voltage in the sampling operation, the sampling circuit comprising: a first capacitor having a first terminal and a second terminal; a second capacitor having a third terminal and a fourth terminal; a first input node to which a first input voltage that is one of the differential input voltages is input; a second input node to which a second input voltage that is the other of the differential input voltages is input; a first switch circuit provided between the first input node and the first terminal; a second switch circuit provided between the second input node and the third terminal; a third switch circuit provided between the first terminal and the third terminal; and a fourth switch circuit provided between the second terminal and the fourth terminal, and in the reset operation, the first switch circuit and the second switch circuit are turned off, and the third switch circuit and the fourth switch circuit are turned on. In the sampling operation, the third switch circuit is turned off, and the first, second and fourth switch circuits are turned on. A sampling circuit is provided. Effect of the Invention

[0009] It is possible to provide a sampling circuit and an analog-to-digital conversion circuit that can provide a sufficiently high equivalent input resistance. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of an analog-to-digital converter according to the first embodiment. [Diagram 2] FIG. 2 is a flowchart showing a processing method of the analog-to-digital conversion circuit. [Diagram 3] FIG. 3 is a diagram showing an equivalent circuit of the analog-to-digital conversion circuit. [Figure 4] FIG. 4 is an equivalent circuit diagram including an equivalent input resistance, a signal source voltage, and a signal source resistance of the analog-to-digital conversion circuit. [Diagram 5] FIG. 5 is a diagram illustrating an example of the configuration of an analog-to-digital converter according to the second embodiment. [Figure 6]FIG. 6 is a diagram showing an example of the configuration of a semiconductor integrated circuit according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (First embodiment) 1 is a diagram showing an example of the configuration of an analog-to-digital converter 100 according to a first embodiment. The analog-to-digital converter 100 is a 4-bit analog-to-digital converter that includes a sampling circuit 101, switch circuits SW8 to SW11, resistors R1 and R2, a comparator CMP, and a control circuit SAR, and converts an analog input voltage into a 4-bit digital code.

[0012] The sampling circuit 101 has switch circuits SW1 to SW3, SW5, switch circuits SP0A, SP0 to SP4, capacitors CP0A, CP0 to CP4, switch circuits SN0A, SN0 to SN4, and capacitors CN0A, CN0 to CN4.

[0013] The relative capacitance value of capacitors CP0A, CP0, CN0A, and CN0 is 1C. The relative capacitance value of capacitors CP1 and CN1 is 2C. The relative capacitance value of capacitors CP2 and CN2 is 4C. The relative capacitance value of capacitors CP3 and CN3 is 8C. The relative capacitance value of capacitors CP4 and CN4 is 16C.

[0014] The switch circuits SP0A, SP0 to SP4 and the capacitors CP0A, CP0 to CP4 form a 4-bit digital-to-analog conversion circuit. The switch circuits SN0A, SN0 to SN4 and the capacitors CN0A, CN0 to CN4 also form a 4-bit digital-to-analog conversion circuit.

[0015] Each of the plurality of capacitors CP0A and CP0 to CP4 has a first terminal and a second terminal, and each of the plurality of capacitors CN0A and CN0 to CN4 has a third terminal and a fourth terminal.

[0016] The top node TOPP is connected to second terminals of the plurality of capacitors CP0A and CP0 to CP4, and the top node TOPN is connected to fourth terminals of the plurality of capacitors CN0A and CN0 to CN4.

[0017] A first input voltage, which is one of the differential input voltages, is input to the input node VINP. A second input voltage, which is the other of the differential input voltages, is input to the input node VINN. The analog-to-digital converter 100 converts this analog differential input voltage into a digital code.

[0018] The switch circuit SW1 is provided between the input node VINP and the bottom node BTP. The switch circuit SW2 is provided between the input node VINN and the bottom node BTN. The switch circuit SW3 is provided between the bottom node BTP and the bottom node BTN. The switch circuit SW5 is provided between the top node TOPP and the top node TOPN.

[0019] The multiple switch circuits SP0A and SP0 to SP4 connect the first terminals of the multiple capacitors CP0A and CP0 to CP4 to the bottom node BTP, the reference voltage node Vrefp, or the reference voltage node Vrefn, respectively. The reference voltage node Vrefp is, for example, 3V. The reference voltage node Vrefn is, for example, 0V.

[0020] The multiple switch circuits SN0A and SN0 to SN4 connect the third terminals of the multiple capacitors CN0A and CN0 to CN4 to the bottom node BTN, the reference voltage node Vrefp, or the reference voltage node Vrefn, respectively.

[0021] The comparator CMP is a differential comparator and has a pair of input terminals. The switch circuit SW8 is provided between the top node TOPP and a comparison input node CIP connected to one input terminal of the comparator CMP. The switch circuit SW9 is provided between the top node TOPN and a comparison input node CIN connected to the other input terminal of the comparator CMP. In successive approximation operation, the comparator CMP receives the voltage of the top node TOPP via the switch SW8 and the comparison input node CIP, and receives the voltage of the top node TOPN via the switch SW9 and the comparison input node CIN. In successive approximation operation, the comparator CMP compares the voltage of the top node TOPP with the voltage of the top node TOPN.

[0022] Resistor R1 is connected between the 3V node and the bias voltage node VCM. Resistor R2 is connected between the bias voltage node VCM and the 0V node. The bias voltage node VCM is 1.5V.

[0023] The switch circuit SW10 is provided between the bias voltage node VCM and the comparison input node CIP, and the switch circuit SW11 is provided between the bias voltage node VCM and the comparison input node CIN.

[0024] In the successive approximation operation, the control circuit SAR controls the multiple switch circuits SP0A and SP0 to SP4 and the multiple switch circuits SN0A and SN0 to SN4 based on the output signal CPO of the comparator CMP.

[0025] Fig. 2 is a flowchart showing a processing method of the analog-to-digital converter 100 of Fig. 1. The analog-to-digital converter 100 repeats a series of operations including a reset operation in step S201, a sampling operation in step S202, and a successive approximation operation in step S203.

[0026] In step S201, the analog-to-digital converter 100 performs a reset operation. The switch circuits SW1 and SW2 are turned off. The switch circuits SW3 and SW5 are turned on.

[0027] The switch circuits SP0A and SP0 to SP4 connect the first terminals of the capacitors CP0A and CP0 to CP4 to the bottom node BTP, respectively. The switch circuits SN0A and SN0 to SN4 connect the third terminals of the capacitors CN0A and CN0 to CN4 to the bottom node BTN, respectively.

[0028] The switch circuits SW8 and SW9 are turned off, and the switch circuits SW10 and SW11 are turned on.

[0029] Initial charges remain in the capacitors CP0A, CP0 to CP4 and the capacitors CN0A, CN0 to CN4. The initial charges are the charges sampled in the previous sampling operation in step S202.

[0030] This reset operation redistributes the initial charges of capacitors CP0A, CP0 to CP4, and capacitors CN0A, CN0 to CN4, rather than resetting them to 0. Because switch circuits SW3 and SW5 are on, the charges of capacitors CP0A, CP0 to CP4, and capacitors CN0A, CN0 to CN4 become equal.

[0031] Next, in step S202, the analog-to-digital converter circuit 100 performs a sampling operation of the differential input voltage. The switch circuit SW3 is turned off. The switch circuit SW5 is kept on. The switch circuits SW1 and SW2 are turned on.

[0032] The switch circuits SP0A and SP0 to SP4 connect the first terminals of the capacitors CP0A and CP0 to CP4 to the bottom node BTP, respectively. The switch circuits SN0A and SN0 to SN4 connect the third terminals of the capacitors CN0A and CN0 to CN4 to the bottom node BTN, respectively.

[0033] The switch circuits SW8 and SW9 are turned off, and the switch circuits SW10 and SW11 are turned on.

[0034] The input voltage of the input node VINP is applied to the first terminals of the capacitors CP0A and CP0 to CP4. The input voltage of the input node VINN is applied to the third terminals of the capacitors CN0A and CN0 to CN4. Since the switch circuit SW5 is on, the top nodes TOPP and TOPN are at the common potential of the input voltage of the input node VINP and the input voltage of the input node VINN.

[0035] In this embodiment, the input node VI N The input voltage of P is input node VI N A case where it is known in advance that the input voltage is equal to or higher than N will be described.

[0036] The capacitors CP0A and CP0 to CP4 store electric charges based on the input voltage of the input node VINP. The capacitors CN0A and CN0 to CN4 store electric charges based on the input voltage of the input node VINN. Since the switch circuit SW5 is on, the top nodes TOPP and TOPN are at the common potential of the input voltages of the input nodes VINP and VINN.

[0037] Fig. 3 is a diagram showing an equivalent circuit of the analog-to-digital converter circuit 100 of Fig. 1 in the reset operation of step S201 of Fig. 2. Capacitor CP in Fig. 3 corresponds to capacitors CP0A and CP0 to CP4 in Fig. 1. Capacitor CN in Fig. 3 corresponds to capacitors CN0A and CN0 to CN4 in Fig. 1.

[0038] The capacitor CP is connected between the top node TOPP and the bottom node BTP, and the capacitor CN is connected between the top node TOPN and the bottom node BTN.

[0039] The switch circuit SW1 disconnects the input node VINP from the bottom node BTP. The switch circuit SW2 disconnects the input node VINN from the bottom node BTN. The switch circuit SW3 connects the bottom nodes BTP and BTN. The switch circuit SW5 connects the top nodes TOPP and TOPN.

[0040] Before the reset operation in step S201, an initial charge remains in the capacitors CP and CN. The initial charge is the charge accumulated in the previous sampling operation in step S202.

[0041] In the reset operation in step S201, the switch circuits SW1 and SW2 are turned off, and the switch circuits SW3 and SW5 are turned on. Since the capacitance values ​​of the capacitors CP and CN are the same, the initial charges of the capacitors CP and CN are evenly distributed to the capacitors CP and CN.

[0042] In the sampling operation in step S202, the switch circuit SW3 is turned off and the switch circuits SW1 and SW2 are turned on. Then, the bottom node B TP is connected to the input node VINP. The bottom node BTN is connected to the input node VINN. The top nodes TOPP and TOPN are at a common potential (VINP+VINN) / 2 of the input voltages of the input nodes VINP and VINN.

[0043] 4 is an equivalent circuit diagram including an equivalent input resistance RIN, a signal source voltage Vs, and a signal source resistance Rs of the analog-to-digital converter 100 of FIG. 1. The input node VIN of FIG. 4 corresponds to the input nodes VINP and VINN of FIG. 1. The equivalent input resistance RIN is N The signal source voltage Vs is the voltage of the signal source of the input voltage of the input node VIN. The signal source resistance Rs is connected between the input node VI N is the resistance of the signal source for the input voltage of . The equivalent input resistance RIN is in series with the signal source resistance Rs.

[0044] The voltage of the input node VIN is the signal source voltage Vs divided by the signal source resistance Rs and the equivalent input resistance RIN. Therefore, if the equivalent input resistance RIN is sufficiently high, the voltage of the input node VIN will be approximately the same as the signal source voltage Vs, and the conversion result of the analog-to-digital conversion circuit 100 will be an appropriate value.

[0045] However, if the equivalent input resistance RIN is low, the voltage of the input node VIN will be low relative to the signal source voltage Vs, resulting in a small conversion result from the analog-to-digital conversion circuit 110. Therefore, it is desirable for the equivalent input resistance RIN to be sufficiently high.

[0046] In the sampling operation of step S202, the amount of charge that the capacitors CP and CN are charged with from the input nodes VINP and VINN is the difference between the amount of charge of the capacitors CP and CN based on the input voltages of the input nodes VINP and VINN in the previous sampling operation and the amount of charge of the capacitors CP and CN based on the input voltages of the input nodes VINP and VINN in the current sampling operation. Therefore, the amount of charge that the capacitors CP and CN are charged with from the input nodes VINP and VINN is small, so that the equivalent input resistance RIN of the analog-to-digital conversion circuit 100 can be made sufficiently high, and the sampling operation time can be shortened.

[0047] In contrast to this, a case will be described where the charge amounts of the capacitors CP and CN are reset to 0 in step S201. In this case, in step S202, the capacitors CP and CN start charging from a state in which the charge amount is 0. Therefore, the amount of charge charged to the capacitors CP and CN from the input nodes VINP and VINN increases, so that the equivalent input resistance RIN of the analog-to-digital conversion circuit 100 decreases, and the sampling operation time becomes longer.

[0048] The sampling operation in step S202 will be described. The total capacitance of the capacitors CP0A and CP0 to CP4 is 1C+1C+2C+4C+8C+16C=32C. The total capacitance of the capacitors CN0A and CN0 to CN4 is also 32C, which is the same as the total capacitance of the capacitors CP0A and CP0 to CP4.

[0049] Since the switch circuit SW5 is turned on, the potentials of the top nodes TOPP and TOPN become the input common potential ((VINP+VINN) / 2), where VINP and VINN represent the potential of the input node VINP and the potential of the input node VINN, respectively.

[0050] The amount of charge QSAMPP stored in the top nodes TOPP of the capacitors CP0A and CP0 to CP4 is expressed by equation (1). QSAMPP=-32C(VINP-(VINP+VINN) / 2) =-32C(VINP-VINN) / 2 (1)

[0051] The amount of charge QSAMPN stored in the top nodes TOPN of the capacitors CN0A and CN0 to CN4 is expressed by equation (2). QSAMPN=-32C(-VINP+VINN) / 2 ···(2)

[0052] In other words, by setting the potentials of the top nodes TOPP and TOPN to the input common potential (VINP+VINN) / 2, the absolute values ​​of the electric charges QSAMPP and QSAMPN are equal and the signs are opposite.

[0053] 2, the analog-to-digital conversion circuit 100 performs a successive approximation operation. The switch circuit SW5 is turned off. After that, the switch circuits SW1 and SW2 are also turned off. Since the switch circuit SW5 is turned off first, the top nodes TOPP and TOPN are in a floating state, so that the charges of the top node TOPP of the capacitors CP0A and CP0 to CP4 and the top node TOPN of the capacitors CN0A and CN0 to CN4 are preserved.

[0054] Next, switch circuits SP0A and SP0 to SP4 are put into a floating state. Switch circuits SN0A and SN0 to SN4 are also put into a floating state. Switch circuit SW3 is turned on. Switch circuits SW10 and SW11 are turned off. Switch circuits SW8 and SW9 are turned on. This prepares comparator CMP for successive approximation.

[0055] During the sampling operation, the switch circuits SW10 and SW11 apply the bias voltage of 1.5 V of the bias voltage node VCM to the comparison input nodes CIP and CIN of the comparator CMP.

[0056] Since VINP-VINN>=0, the switch circuit SP4 connects the first terminal of the capacitor CP4 to the reference voltage node Vrefp. The switch circuit SN4 connects the third terminal of the capacitor CN4 to the reference voltage node Vrefn.

[0057] The switch circuits SP0 to SP3 connect to the reference voltage node Vrefp if the corresponding bit of the digital code is 1, and connect to the reference voltage node Vrefn if the corresponding bit of the digital code is 0. To generate two's complement, the switch circuit SP0A, which generates a 1-bit addend, connects to the reference voltage node Vrefn (corresponding to the bit value "0" of the digital code). This is because there is no need to generate two's complement data.

[0058] The switch circuits SN0 to SN3 connect to the reference voltage node Vrefn if the corresponding bit of the digital code is 1, and connect to the reference voltage node Vrefp if the corresponding bit of the digital code is 0. Since VINP-VINN>=0, the switch circuit SN0A connects to the reference voltage node Vrefp (corresponding to the bit value "0" of the digital code). This is to constantly generate two's complement data.

[0059] Since VINP>VINN, the potential of the top node TOPP is always positive. Therefore, the switch circuit SP0A connects to the reference voltage node Vrefn. Similarly, since the top node TOPN is always negative, the switch circuit SN0A connects to the reference voltage node Vrefp.

[0060] Since it is assumed that VINP>VINN, the comparison by the comparator CMP starts with, for example, a comparison with VINP>VINN and reference voltage / 2, and if (VINP-VINN) is greater than reference voltage / 2, it compares (VINP-VINN) with reference voltage×3 / 4. If (VINP-VINN) is less than reference voltage / 2, it compares (VINP-VINN) with reference voltage×1 / 4. Furthermore, if (VINP-VINN) is greater than reference voltage×1 / 4, it compares (VINP-VINN) with reference voltage×3 / 8. Alternatively, if (VINP-VINN) is less than reference voltage×1 / 4, it compares (VINP-VINN) with reference voltage×1 / 8. In other words, the magnitude relationship between the potential difference (VINP-VINN) and the potential obtained by dividing the reference voltage (Vrefp-Vrefn) is determined, and the range of the sampled potential difference (VINP-VINN) is gradually narrowed to determine the final digital code.

[0061] Next, a method for determining the MSB (Most Significant Bit) of the digital code will be described. The switch circuit SP4 is connected to the reference voltage node Vrefp. The switch circuits SP0-SP2 and SP0A are connected to the reference voltage node Vrefn. The switch circuit SP3 is connected to the reference voltage node Vrefp. A first terminal of the capacitors CP0A and CP0-CP2, which have a total capacitance of 8C, is connected to the reference voltage node Vrefn. A first terminal of the capacitors CP3 and CP4, which have a total capacitance of 24C, is connected to the reference voltage node Vrefp. Since the charge amount QSAMPP of the formula (1) is preserved, the potential Vtp of the top node TOPP at this time is given by the formula (3). Here, Vrefp and Vrefn represent the potentials of the reference voltage nodes Vrefp and Vrefn, respectively. -24C(Vrefp-Vtp)+8C(Vtp-Vrefn)=-32C(VINP-VINN) / 2 Vtp=-(VINP-VINN) / 2+(Vrefp+Vrefn) / 2+(Vrefp-Vrefn) / (2×2) ···(3)

[0062] The switch circuit SN4 is connected to the reference voltage node Vrefn. S N0A is connected to the reference voltage node Vrefp. Switch circuit SN3 is connected to the reference voltage node Vrefn. A third terminal of the capacitors CN0A and CN0 to CN2, which have a total capacitance of 8C, is connected to the reference voltage node Vrefp. A third terminal of the capacitors CN3 and CN4, which have a total capacitance of 24C, is connected to the reference voltage node Vrefn. Since the charge amount QSAMPN of equation (2) is conserved, the potential Vtn of the top node TOPN at this time is given by equation (4). -8C(Vrefp-Vtp)+24C(Vtp-Vrefn)=32C(VINP-VINN) / 2 Vtn=(VINP-VINN) / 2+(Vrefp+Vrefn) / 2-(Vrefp-Vrefn) / (2×2) ···(4)

[0063] The potential of the comparison input node CIP becomes the potential Vtp. The potential of the comparison input node CIN becomes the potential Vtn. The comparator CMP outputs the difference potential Vtp-Vtn between the potentials Vtp and Vtn as the output signal CPO, as shown in equation (5). Vtp-Vtn=-(VINP-VINN)+(Vrefp-Vrefn) / 2 ···(5)

[0064] That is, the comparator CMP outputs the magnitude relationship between (VINP-VINN) and (Vrefp-Vrefn) / 2 as the output signal CPO. The control circuit SAR determines the most significant bit of the digital code to be "1" if (VINP-VINN) is equal to or greater than (Vrefp-Vrefn) / 2 based on the output signal CPO. Also, the control circuit SAR determines the most significant bit of the digital code to be "0" if (VINP-VINN) is less than (Vrefp-Vrefn) / 2 based on the output signal CPO. The most significant bit of the digital code corresponds to the switch circuits SP3 and SN3.

[0065] Next, a method for determining the bits following the most significant bit will be described. A method for determining the bits (the second most significant bits) corresponding to the switch circuits SP2 and SN2 will be described.

[0066] Let us assume that the most significant bit of the digital code corresponding to the switch circuits SP3 and SN3 is determined to be 1 and (VINP-VINN) is equal to or greater than (Vrefp-Vrefn) / 2. In this case, the comparator CMP compares (VINP-VINN) with (Vrefp-Vrefn)×3 / 4, examines which is larger, and narrows the range of the (VINP-VINN) value.

[0067] Specifically, the switch circuit SP4 is connected to the reference voltage node Vrefp. The switch circuits SP0A, SP0, and SP1 are connected to the reference voltage node Vrefn. The switch circuits SP2 and SP3 are connected to the reference voltage node Vrefp. A first terminal of the capacitors CP0A, CP0, and CP1 having a total capacitance 4C is connected to the reference voltage node Vrefn. A first terminal of the capacitors CP2 to CP4 having a total capacitance 28C is connected to the reference voltage node Vrefp. The potential Vtp of the top node TOPP at this time is given by equation (6). -28C(Vrefp-Vtp)+4C(Vtp-Vrefn)=-32C(VINP-VINN) / 2 Vtp=-(VINP-VINN) / 2+(Vrefp+Vrefn) / 2+3×(Vrefp-Vrefn) / (2×4) ···(6)

[0068] The switch circuit SN4 is connected to the reference voltage node Vrefn. The switch circuits SN0A, SN0, and SN1 are connected to the reference voltage node Vrefp. The switch circuits SN2 and SN3 are connected to the reference voltage node Vrefn. A third terminal of the total capacitance 4C of the capacitors CN0A, CN0, and CN1 is connected to the reference voltage node Vrefp. A third terminal of the total capacitance 28C of the capacitors CN2 to CN4 is connected to the reference voltage node Vrefn. The potential Vtn of the top node TOPN at this time is given by equation (7). -4C(Vrefp-Vtp)+28C(Vtp-Vrefn)=32C(VINP-VINN) / 2 Vtn=(VINP-VINN) / 2+(Vrefp+Vrefn) / 2-3×(Vrefp-Vrefn) / (2×4) ···(7)

[0069] The potential of the comparison input node CIP becomes the potential Vtp. The potential of the comparison input node CIN becomes the potential Vtn. The comparator CMP outputs the difference potential Vtp-Vtn between the potentials Vtp and Vtn as the output signal CPO, as shown in equation (8). Vtp-Vtn=-(VINP-VINN)+3×(Vrefp-Vrefn) / 4 ···(8)

[0070] That is, the comparator CMP outputs the magnitude relationship between (VINP-VINN) and (Vrefp-Vrefn)×3 / 4 as the output signal CPO. If (VINP-VINN) is equal to or greater than (Vrefp-Vrefn)×3 / 4 based on the output signal CPO, the control circuit SAR determines the second most significant bit of the digital code to be "1". Also, if (VINP-VINN) is smaller than (Vrefp-Vrefn)×3 / 4 based on the output signal CPO, the control circuit SAR determines the second most significant bit of the digital code to be "0". The second most significant bit of the digital code corresponds to the switch circuits SP2 and SN2.

[0071] Similarly, the control circuit SAR controls the switch circuits SP0A and SP0 to SP4 and the switch circuits SN0A and SN0 to SN4 to obtain (VINP-VINN) and (Vrefp-Vref n ) can be divided. This allows the control circuit SAR to narrow the range of (VINP-VINN) in sequence and determine the final digital code.

[0072] As described above, the comparison by the comparator CMP is as follows: if (VINP-VINN) is greater than the reference voltage / 2, then it compares (VINP-VINN) with 3 / 4 of the reference voltage. If (VINP-VINN) is less than the reference voltage / 2, then it compares (VINP-VINN) with 1 / 4 of the reference voltage. Furthermore, if (VINP-VINN) is greater than 1 / 4 of the reference voltage, then it compares (VINP-VINN) with 3 / 8 of the reference voltage. Alternatively, if (VINP-VINN) is less than 1 / 4 of the reference voltage, then it compares (VINP-VINN) with 1 / 8 of the reference voltage. In other words, it judges the magnitude relationship between the potential difference of (VINP-VINN) and the potential obtained by dividing the reference voltage (Vrefp-Vrefn), and gradually narrows the range of the potential difference value of the sampled (VINP-VINN) to determine the final digital code.

[0073] After step S203 in FIG. 2, the analog-to-digital converter circuit 100 returns to step S201 and repeats steps S201 to S203.

[0074] As described above, according to this embodiment, in the reset operation in step S201, the capacitors CP and CN do not reset the charge amount to 0, but distribute the initial charge.

[0075] In the sampling operation of step S202, the amount of charge that the capacitors CP and CN are charged with from the input nodes VINP and VINN is the difference between the amount of charge of the capacitors CP and CN based on the input voltages of the input nodes VINP and VINN in the previous sampling operation and the amount of charge of the capacitors CP and CN based on the input voltages of the input nodes VINP and VINN in the current sampling operation. Therefore, the amount of charge that the capacitors CP and CN are charged with from the input nodes VINP and VINN is small, so that the equivalent input resistance RIN of the analog-digital conversion circuit 100 can be made sufficiently high, and the sampling operation time can be shortened. This makes it possible to suppress deterioration in the accuracy of the conversion result of the analog-digital conversion circuit 100.

[0076] Second embodiment Fig. 5 is a diagram showing a configuration example of an analog-digital conversion circuit 100 according to the second embodiment. The analog-digital conversion circuit 100 in Fig. 5 is obtained by adding resistive sub-digital-analog conversion circuits SUBDACP, SUBDACN, resistive correction digital-analog conversion circuits CALDACP, CALDACN, capacitors CPA-CPD, CNA-CND, a switch circuit SW4, and a register file (memory) RF to the analog-digital conversion circuit 100 in Fig. 1.

[0077] Also, the switch circuit SP0' and the capacitor CP0' in Fig. 5 are provided in place of the switch circuit SP0A and the capacitor CP0A in Fig. 1. The relative capacitance value of the capacitor CP0' is 1 C. The switch circuit SP0' connects a first terminal of the capacitor CP0' to the resistive sub digital-to-analog conversion circuit SUBDACP, the bottom node BTP, the reference voltage node Vrefp, or Vrefn.

[0078] The switch circuit SN0' and the capacitor CN0' in Fig. 5 are provided in place of the switch circuit SN0A and the capacitor CN0A in Fig. 1. The relative capacitance value of the capacitor CN0' is 1C. The switch circuit SN0' connects the third terminal of the capacitor CN0' to the resistive sub digital-to-analog conversion circuit SUBDACN, the bottom node BTN, the reference voltage node Vrefp, or Vrefn.

[0079] Switch circuits SP0 to SP7 and capacitors CP0 to CP7 in Fig. 5 are provided in place of switch circuits SP0 to SP4 and capacitors CP0 to CP4 in Fig. 1. Switch circuits SN0 to SN7 and capacitors CN0 to CN7 in Fig. 5 are provided in place of switch circuits SN0 to SN4 and capacitors CN0 to CN4 in Fig. 1. These are signed 7-bit capacitive main digital-to-analog conversion circuits MAINDAC, and are similar to those in the first embodiment.

[0080] The analog-to-digital conversion circuit 100 is a 14-bit analog-to-digital conversion circuit that converts an analog input voltage into a 14-bit digital code. The 14-bit analog-to-digital conversion circuit 100 has a 7-bit capacitive main digital-to-analog conversion circuit MAINDAC and 7-bit resistive sub digital-to-analog conversion circuits SUBDACP and SUBDACN. The 7-bit capacitive main digital-to-analog conversion circuit MAINDAC converts the upper 7 bits of the 14-bit digital code into an analog voltage. The 7-bit resistive sub digital-to-analog conversion circuits SUBDACP and SUBDACN convert the lower 7 bits of the 14-bit digital code into an analog voltage. This makes it possible to reduce the circuit scale of the high-resolution analog-to-digital conversion circuit 100.

[0081] The analog-to-digital conversion circuit 100 further includes resistance correction digital-to-analog conversion circuits CALDACP and CALDACN. In the 14-bit or higher analog-to-digital conversion circuit 100, the resistance correction digital-to-analog conversion circuits CALDACP and CALDACN correct the manufacturing error of the capacitive main digital-to-analog conversion circuit MAINDAC. This enables the analog-to-digital conversion circuit 100 to perform high-resolution analog-to-digital conversion.

[0082] The resistive sub digital-to-analog conversion circuit SUBDACP outputs a first analog voltage based on the lower 7-bit digital code of the 14-bit digital code to the comparison input node CIP via the capacitors CPD and CP0'.

[0083] The resistive sub digital-to-analog conversion circuit SUBDACN outputs a second analog voltage based on the lower 7-bit digital code of the 14-bit digital code to the comparison input node CIN via the capacitors CND and CN0'.

[0084] The resistance correction digital-to-analog conversion circuit CALDACP is connected to the comparison input node CIP via the capacitors CPA to CPC, and corrects the voltages of the capacitors CP0' and CP0 to CP7.

[0085] The resistance correction digital-to-analog conversion circuit CALDACN is connected to the comparison input node CIN via the capacitors CNA to CNC, and corrects the voltages of the capacitors CN0' and CN0 to CN7.

[0086] In the analog-to-digital conversion circuit 100, of the 14-bit conversion resolution and positive / negative sign bit, the capacitive main digital-to-analog conversion circuit MAINDAC is responsible for determining the most significant 7 bits and the positive / negative sign bit, and the resistive sub-digital-analog conversion circuits SUBDACP and SUBDACN are responsible for determining the least significant 7 bits. Note that the resistive sub-digital-analog conversion circuits SUBDACP and SUBDACN have two voltage outputs divided into higher and lower bits by resistor division in order to reduce the time constant of the output node and speed up operation.

[0087] The voltage output of the upper bit of the resistive sub-digital-analog conversion circuit SUBDACP is connected to the top node TOPP via a capacitor CP0', and the voltage output of the lower bit of the resistive sub-digital-analog conversion circuit SUBDACP is connected to the comparison input node CIP via a capacitor CPD.

[0088] Similarly, the voltage output of the upper bit of the resistive sub-digital-analog conversion circuit SUBDACN is connected to the top node TOPN via a capacitor CN0'. Also, the voltage output of the lower bit of the resistive sub-digital-analog conversion circuit SUBDACN is connected to the comparison input node CIN via a capacitor CND.

[0089] In addition to the capacitive main digital-analog conversion circuit MAINDAC and resistive sub digital-analog conversion circuits SUBDACP, SUBDACN for performing 14-bit conversion, the analog-digital conversion circuit 100 is provided with 9-bit resistive correction digital-analog conversion circuits CALDACP, CALDACN for canceling mismatches between capacitors. These resistive correction digital-analog conversion circuits CALDACP, CALDACN are used to realize a self-correction function.

[0090] The resistance correction digital-to-analog conversion circuit CALDACP is divided into three output voltages, each of which is connected to the comparison input node CIP via the capacitors CPA to CPC. The resistance correction digital-to-analog conversion circuit CALDACN is divided into three output voltages, each of which is connected to the comparison input node CIN via the capacitors CNA to CNC.

[0091] Here, the resistance correction digital-analog conversion circuits CALDACP and CALDACN have, for example, an extra 2-bit resolution compared to the resistance sub-digital-analog conversion circuits SUBDACP and SUBDACN, and can perform correction with a resolution of 1 / 4 that of 1 LSB (least significant bit) of the 14-bit analog-to-digital conversion.

[0092] 2, the bits are determined starting from the most significant bit of the capacitive main digital-analog conversion circuit MAINDAC, as in the first embodiment. After the most significant 7 bits of the capacitive main digital-analog conversion circuit MAINDAC are determined, the least significant 7 bits are determined using the resistive sub digital-analog conversion circuits SUBDACP and SUBDACN.

[0093] During the successive approximation in step S203, the resistance correction digital-to-analog conversion circuits CALDACP and CALDACN operate to correct the capacitive main digital-to-analog conversion circuit MAINDAC.

[0094] The capacitor mismatch of the capacitive main digital-to-analog conversion circuit MAINDAC is measured when the analog-to-digital conversion circuit 100 is powered on, etc. Data for correcting the measured capacitor mismatch is written to the register file RF.

[0095] The resistive sub-digital-analog conversion circuits SUBDACP and SUBDACN have voltage outputs for 4 upper bits and voltage outputs for 3 lower bits.

[0096] The resistance correction digital-to-analog conversion circuits CALDACP and CALDACN each have a 3-bit voltage output representing the upper order, a 3-bit voltage output representing the middle order, and a 3-bit voltage output representing the lower order.

[0097] The outputs of the resistive sub-digital-analog conversion circuits SUBDACP, SUBDACN and the resistive correction digital-analog conversion circuits CALDACP, CALDACN are divided and added by capacitors. This reduces the time constants of the resistive sub-digital-analog conversion circuits SUBDACP, SUBDACN and the resistive correction digital-analog conversion circuits CALDACP, CALDACN, resulting in an increase in speed.

[0098] The error of the capacitive main digital-to-analog conversion circuit MAINDAC measured by the mismatch measurement of the capacitors can be converted into the amount of correction (correction data) of the capacitors carrying each bit. The correction data is stored in the register file RF.

[0099] In the successive approximation operation stage in step S203, as described above, first, trial and judgment are performed on the most significant bit, then trial and judgment are performed on the second most significant bit, and further trial and judgment are performed on the third most significant bit. After that, trial and judgment are performed on each bit up to the least significant bit.

[0100] The resistance correction digital-analog conversion circuits CALDACP and CALDACN calculate a correction amount corresponding to the digital code input to the capacitive main digital-analog conversion circuit MAINDAC at each stage of the successive approximation operation, and perform the correction.

[0101] Next, the operation of the error correction control will be described. After the sampling operation, when the most significant bit is sampled, the register file RF outputs a correction value corresponding to the capacitor carrying the most significant bit. The resistance correction digital-to-analog CALDACP and CALDACN output a voltage based on the value of the register file RF. At the end of the most significant bit comparison period, the comparator CMP finishes the judgment and outputs "1" or "0".

[0102] As soon as the period for determining the second most significant bit begins, if the most significant bit is determined to be "1", the most significant bit correction value of the register file RF is stored in the register, and if the most significant bit is determined to be "0", the value 0 is stored.

[0103] After that, during the trial and judgment period for the second bit, the register file RF outputs the correction value of the capacitor that handles the second most significant bit. The resistance correction digital-to-analog CALDACP and CALDACN output a voltage based on the sum of the output value of the register file RF and the value of the register.

[0104] Thereafter, in the same manner, a correction amount according to the digital code of the capacitive main digital-analog conversion circuit MAINDAC is input to the resistive correction digital-analog conversion circuits CALDACP and CALDACN. After the higher bits are determined by the capacitive main digital-analog conversion circuit MAINDAC, the lower bits are searched for by the resistive sub digital-analog conversion circuits SUBDACP and SUBDACN. The resistive sub digital-analog conversion circuits SUBDACP and SUBDACN do not need to perform correction because their weighting is small relative to the dynamic range of the analog-to-digital conversion.

[0105] According to this embodiment, the 14-bit analog-to-digital conversion circuit 100 has a 7-bit capacitive main digital-to-analog conversion circuit MAINDAC, a 7-bit resistive sub digital-to-analog conversion circuit SUBDACP, SUBDACN, and a 9-bit resistive correction digital-to-analog conversion circuit CALDACP, CALDACN, and can convert an input analog voltage into a 14-bit digital code.

[0106] (Third embodiment) 6 is a diagram showing an example of the configuration of a semiconductor integrated circuit 600 according to the third embodiment. The semiconductor integrated circuit 600 has an internal circuit 610 and an analog-to-digital converter 100. The analog-to-digital converter 100 is the analog-to-digital converter 100 of the first or second embodiment.

[0107] The internal circuit 610 includes a p-channel field effect transistor 601, an n-channel field effect transistor 602, a resistor 603, and a capacitor 604. The p-channel field effect transistor 601 and the n-channel field effect transistor 602 configure an inverter. The resistor 603 and the capacitor 604 configure a first-order RC filter.

[0108] The internal circuit 610 is, for example, a duty ratio measurement circuit for a clock signal CLK. When the semiconductor integrated circuit 600 is a wireless communication circuit, a phase-locked loop circuit (PLL circuit) generates a clock signal CLK and supplies the clock signal CLK to a mixer circuit. The frequency of the clock signal CLK is high, for example, 12 GHz.

[0109] The clock signal CLK is transmitted from the PLL circuit to the destination circuit, relaying it through, for example, CMOS inverters and buffers. If the frequency of the clock signal CLK is high, the duty ratio of the clock signal CLK deteriorates as it is relayed. The duty ratio is the ratio between the period of one cycle of the clock signal and the period when the clock signal is at a high level. Typically, it is desirable for the duty ratio of the clock signal CLK to be 50%.

[0110] For example, in a wireless communication circuit that requires the transmission of a high-speed clock signal CLK, the deterioration of the duty ratio of the clock signal CLK must be adjusted after the wireless communication circuit is manufactured. In such a case, the current duty ratio of the clock signal CLK must be accurately measured for the adjustment.

[0111] A p-channel field effect transistor 601 and an n-channel field effect transistor 602 form an inverter, which shapes the waveform of the clock signal CLK. A resistor 603 and a capacitor 604 form a first-order RC filter, which smoothes the output signal of the inverter and outputs an analog DC voltage V1. When the duty ratio of the clock signal CLK is 50%, the DC voltage V1 becomes the average value of the high level and the low level of the clock signal CLK. The duty ratio of the clock signal CLK can be derived based on the DC voltage V1.

[0112] The internal circuit 610 outputs an analog differential input voltage based on the DC voltage V1 to the analog-to-digital converter 100. The analog-to-digital converter 100 converts the differential input voltage based on the input voltage V1 into a digital code D1, as in the first or second embodiment.

[0113] The resistor 603 is, for example, 20 kΩ, the capacitor 604 is, for example, 20 pF, and the signal source resistance Rs in Fig. 4 is high, for example, 100 kΩ. Therefore, if the equivalent input resistance RIN in Fig. 4 is low, the DC voltage V1 drops and the duty ratio cannot be measured accurately.

[0114] The analog-to-digital converter 100 of this embodiment has a sufficiently high equivalent input resistance RIN, so that it is possible to suppress a drop in the DC voltage V1 and measure an accurate duty ratio.

[0115] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Industrial Applicability]

[0116] It is possible to provide a sampling circuit and an analog-to-digital conversion circuit that can provide a sufficiently high equivalent input resistance.

Claims

1. A sampling circuit that repeats a series of operations including a reset operation and a sampling operation, and samples a differential input voltage in the sampling operation, a first capacitor having a first terminal and a second terminal; a second capacitor having a third terminal and a fourth terminal; a first input node to which a first input voltage, which is one of the differential input voltages, is input; a second input node to which a second input voltage, which is the other of the differential input voltages, is input; a first switch circuit provided between the first input node and the first terminal; a second switch circuit provided between the second input node and the third terminal; a third switch circuit provided between the first terminal and the third terminal; a fourth switch circuit provided between the second terminal and the fourth terminal; In the reset operation, the first switch circuit and the second switch circuit are turned off, and the third switch circuit and the fourth switch circuit are turned on; In the sampling operation, the third switch circuit is turned off, and the first, second and fourth switch circuits are turned on.

2. An analog-to-digital conversion circuit that converts an analog input voltage into a digital code with a first number of bits by repeating a series of operations including a reset operation, a sampling operation, and a successive approximation operation, a plurality of first capacitors each having a first terminal and a second terminal; a plurality of second capacitors each having a third terminal and a fourth terminal; a first top node coupled to the second terminals of the plurality of first capacitors; a second top node coupled to the fourth terminals of the plurality of second capacitors; a first input node to which a first input voltage, which is one of a differential input voltage, is input; a second input node to which a second input voltage, which is the other of the differential input voltages, is input; a first switch circuit provided between the first input node and a first bottom node; a second switch circuit provided between the second input node and a second bottom node; a third switch circuit provided between the first bottom node and the second bottom node; a fourth switch circuit provided between the first top node and the second top node; a plurality of fifth switch circuits respectively connecting the first terminals of the plurality of first capacitors to the first bottom node, a first reference voltage node, or a second reference voltage node; a plurality of sixth switch circuits respectively connecting the third terminals of the plurality of second capacitors to the second bottom node, the first reference voltage node, or the second reference voltage node; a comparator for comparing a voltage of the first top node with a voltage of the second top node; a control circuit that controls the fifth switch circuits and the sixth switch circuits based on an output signal of the comparator in the successive approximation operation, in the reset operation, the first switch circuit and the second switch circuit are turned off, the third switch circuit and the fourth switch circuit are turned on, the fifth switch circuits respectively connect the first terminals of the first capacitors to the first bottom node, and the sixth switch circuits respectively connect the third terminals of the second capacitors to the second bottom node; An analog-to-digital conversion circuit, in which, during the sampling operation, the third switch circuit is turned off, the first, second and fourth switch circuits are turned on, the plurality of fifth switch circuits respectively connect the first terminals of the plurality of first capacitors to the first bottom node, and the plurality of sixth switch circuits respectively connect the third terminals of the plurality of second capacitors to the second bottom node.

3. a first comparison input node connected to one input terminal of the comparator; a second comparison input node connected to the other input terminal of the comparator; a seventh switch circuit provided between the first top node and the first comparison input node; an eighth switch circuit provided between the second top node and the second comparison input node; The analog-to-digital conversion circuit according to claim 2 , further comprising:

4. a ninth switch circuit provided between a bias voltage node and the first comparison input node; a tenth switch circuit provided between the bias voltage node and the second comparison input node; 4. The analog-to-digital conversion circuit according to claim 3, further comprising:

5. a first resistive sub-digital-analog conversion circuit that outputs a first analog voltage to the first comparison input node based on a lower-bit digital code of the digital code having the first number of bits; a second resistive sub-digital-analog conversion circuit that outputs a second analog voltage to the second comparison input node based on the digital code of the lower bit; 5. The analog-to-digital conversion circuit according to claim 3, further comprising:

6. a first resistance correction digital-to-analog conversion circuit connected to the first comparison input node for correcting voltages of the first capacitors; a second resistance correction digital-to-analog conversion circuit connected to the second comparison input node for correcting voltages of the second capacitors; 6. The analog-to-digital converter circuit according to claim 3, further comprising:

7. An internal circuit that outputs an analog differential input voltage; an analog-to-digital conversion circuit that converts the differential input voltage into a digital code with a first number of bits; The analog-to-digital conversion circuit includes: An analog-to-digital conversion circuit that repeats a series of operations including a reset operation, a sampling operation, and a successive approximation operation, a plurality of first capacitors each having a first terminal and a second terminal; a plurality of second capacitors each having a third terminal and a fourth terminal; a first top node coupled to the second terminals of the plurality of first capacitors; a second top node coupled to the fourth terminals of the plurality of second capacitors; a first input node to which a first input voltage, which is one of the differential input voltages, is input; a second input node to which a second input voltage, which is the other of the differential input voltages, is input; a first switch circuit provided between the first input node and a first bottom node; a second switch circuit provided between the second input node and a second bottom node; a third switch circuit provided between the first bottom node and the second bottom node; a fourth switch circuit provided between the first top node and the second top node; a plurality of fifth switch circuits respectively connecting the first terminals of the plurality of first capacitors to the first bottom node, a first reference voltage node, or a second reference voltage node; a plurality of sixth switch circuits respectively connecting the third terminals of the plurality of second capacitors to the second bottom node, the first reference voltage node, or the second reference voltage node; a comparator for comparing a voltage of the first top node with a voltage of the second top node; a control circuit that controls the fifth switch circuits and the sixth switch circuits based on an output signal of the comparator in the successive approximation operation, in the reset operation, the first switch circuit and the second switch circuit are turned off, the third switch circuit and the fourth switch circuit are turned on, the fifth switch circuits respectively connect the first terminals of the first capacitors to the first bottom node, and the sixth switch circuits respectively connect the third terminals of the second capacitors to the second bottom node; a semiconductor integrated circuit in which, during the sampling operation, the third switch circuit is turned off, the first, second and fourth switch circuits are turned on, the plurality of fifth switch circuits respectively connect the first terminals of the plurality of first capacitors to the first bottom node, and the plurality of sixth switch circuits respectively connect the third terminals of the plurality of second capacitors to the second bottom node.

8. The analog-to-digital conversion circuit includes: a first comparison input node connected to one input terminal of the comparator; a second comparison input node connected to the other input terminal of the comparator; a seventh switch circuit provided between the first top node and the first comparison input node; an eighth switch circuit provided between the second top node and the second comparison input node; The semiconductor integrated circuit according to claim 7 , further comprising:

9. The analog-to-digital conversion circuit includes: a ninth switch circuit provided between a bias voltage node and the first comparison input node; a tenth switch circuit provided between the bias voltage node and the second comparison input node; The semiconductor integrated circuit according to claim 8 , further comprising:

10. The analog-to-digital conversion circuit includes: a first resistive sub-digital-analog conversion circuit that outputs a first analog voltage to the first comparison input node based on a lower-bit digital code of the digital code having the first number of bits; a second resistive sub-digital-analog conversion circuit that outputs a second analog voltage to the second comparison input node based on the digital code of the lower bit; 10. The semiconductor integrated circuit according to claim 8, further comprising:

11. The analog-to-digital conversion circuit includes: a first resistance correction digital-to-analog conversion circuit connected to the first comparison input node for correcting voltages of the first capacitors; a second resistance correction digital-to-analog conversion circuit connected to the second comparison input node for correcting voltages of the second capacitors; 11. The semiconductor integrated circuit according to claim 8, further comprising:

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