Semiconductor structures, methods (multiple threshold voltages for nanosheets)

Abstract

To fabricate field effect transistors.SOLUTION: A semiconductor structure comprises: nanosheet stacks, each comprising alternating layers of a sacrificial semiconductor material and a semiconductor channel material vertically aligned and stacked one on top of another; and a crystallized gate dielectric layer surrounding semiconductor channel layers of a first subset of the nanosheet stacks; a dipole layer on top of a crystallized gate dielectric and surrounding the semiconductor channel layers of the first subset of the nanosheet stacks; and a gate dielectric modified by a diffused dipole material surrounding semiconductor channel layers of a second subset of the nanosheet stacks. A method comprises: forming nanosheet stacks on a substrate, each nanosheet stack comprising alternating layers of a sacrificial semiconductor material and a semiconductor channel material vertically aligned and stacked one on top of another; removing the sacrificial semiconductor material layers of a set of nanosheet stacks; forming a gate dielectric surrounding the semiconductor channel layers of the nanosheet stacks; and crystalizing the gate dielectric of a subset of the nanosheet stacks.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present invention relates generally to the field of semiconductor manufacturing, and more specifically to the manufacture of field effect transistors.

[0002] Complementary metal oxide semiconductor (CMOS) technology is commonly used for field effect transistors (hereafter "FETs") as part of advanced integrated circuits (hereafter "ICs") such as central processing units (hereafter "CPUs"), memory, and storage devices. As the demand for reducing the dimensions of transistor devices continues, nanosheet FETs help achieve this while maintaining the performance of FET devices by reducing the footprint of the FET devices. Nanosheet FETs include multiple stacked nanosheets that extend between a pair of drain epitaxial regions. The device can be a gate around the entire perimeter of the device or transistor, where the gate surrounds a portion of the nanosheet channel. Nanosheet devices include one or more layers of semiconducting channel material portions having a vertical thickness substantially less than their width. Summary of the Invention [Problem to be solved by the invention]

[0003] The limited space between the channels of nanosheet devices makes it difficult to tune the threshold voltage using conventional techniques. To increase the flexibility of the design of semiconductor devices, it would be advantageous to have more than one threshold voltage in the semiconductor structure. [Means for solving the problem]

[0004] According to one embodiment, a semiconductor structure is provided, the semiconductor structure comprising: nanosheet stacks on a substrate, each nanosheet stack comprising alternating layers of a sacrificial semiconductor material and a semiconductor channel material stacked on top of one another in vertical alignment, a crystallized gate dielectric layer surrounding a semiconductor channel layer of a first subset of the nanosheet stacks, a dipole layer on top of the crystallized gate dielectric and surrounding a layer of semiconductor channel material of the first subset of the nanosheet stacks, and a gate dielectric modified with diffused dipole material surrounding a semiconductor channel layer of a second subset of the nanosheet stacks.

[0005] According to one embodiment, a semiconductor structure is provided that includes nanosheet stacks on a substrate, each nanosheet stack including alternating layers of a sacrificial semiconductor material and a semiconducting channel material stacked on top of one another in vertical alignment, and a crystallized gate dielectric surrounding the semiconducting channel layer of the nanosheet stack.

[0006] According to one embodiment, a method is provided, the method comprising forming nanosheet stacks on a substrate, each nanosheet stack comprising alternating layers of sacrificial semiconductor material and semiconducting channel material stacked on top of one another in vertical alignment, removing a layer of sacrificial semiconductor material of a set of the nanosheet stacks, forming a gate dielectric surrounding a semiconducting channel layer of the nanosheet stacks, and crystallizing the gate dielectric of a subset of the nanosheet stacks. [Brief description of the drawings]

[0007] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings, in which various features are not to scale since the illustrations are for clarity in facilitating understanding of the invention by those skilled in the art with respect to the detailed description.

[0008] [Figure 1] 1A-1D depict cross-sectional views of a semiconductor structure at intermediate stages of processing, in accordance with example embodiments.

[0009] [Diagram 2] 1 illustrates a cross-sectional view of a semiconductor structure illustrating selective removal of a sacrificial semiconductor material layer according to an illustrative embodiment.

[0010] [Diagram 3] 1 illustrates a cross-sectional view of a semiconductor structure illustrating the formation of a gate dielectric according to an illustrative embodiment.

[0011] [Figure 4] 1 illustrates a cross-sectional view of a semiconductor structure illustrating formation of a first gate conductor and a first blanket sacrificial layer according to an exemplary embodiment.

[0012] [Diagram 5] 1 illustrates a cross-sectional view of a semiconductor structure illustrating the formation of an organic polymer layer according to an exemplary embodiment.

[0013] [Figure 6] 1 illustrates a cross-sectional view of a semiconductor structure illustrating selective removal of a first blanket sacrificial layer and a first gate conductor according to an exemplary embodiment.

[0014] [Figure 7] 1 illustrates a cross-sectional view of a semiconductor structure illustrating selective crystallization of a gate dielectric according to an exemplary embodiment.

[0015] [Figure 8] 1 illustrates a cross-sectional view of a semiconductor structure illustrating removal of a residual first blanket sacrificial layer and a residual first gate conductor according to an example embodiment.

[0016] [Figure 9] 1 illustrates a cross-sectional view of a semiconductor structure illustrating the formation of a dipole layer according to an exemplary embodiment.

[0017] [Figure 10] 1 illustrates a cross-sectional view of a semiconductor structure illustrating the formation of a second gate semiconductor and a second blanket sacrificial layer in accordance with an illustrative embodiment.

[0018] [Figure 11] 1A-1C show cross-sectional views of a semiconductor structure illustrating an annealing step according to an exemplary embodiment.

[0019] [Figure 12] 1 illustrates a cross-sectional view of a semiconductor structure illustrating removal of a second blanket sacrificial layer and a second gate semiconductor according to an exemplary embodiment.

[0020] [Figure 13] 1 illustrates a cross-sectional view of a semiconductor structure illustrating the formation of a work function metal according to an example embodiment.

[0021] [Figure 14] 14 illustrates a cross-sectional view of FIG. 13 according to an exemplary embodiment.

[0022] It will be appreciated that for simplicity and clarity of the figures, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or similar features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Detailed embodiments of the claimed structures and methods are disclosed herein, however, it can be understood that the disclosed embodiments are merely examples of the claimed structures and methods that can be embodied in various forms. The present invention, however, may be embodied in many different forms and should not be considered limited to the exemplary embodiments described herein. In the specification, details of well-known features and techniques are omitted so as to avoid unnecessarily obscuring the presented embodiments.

[0024] References in the specification to "one embodiment," "one embodiment," "an example embodiment," and the like indicate that the embodiment being described includes a particular feature, structure, or characteristic, but not all embodiments may necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in the context of one embodiment, it is believed to be within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in the context of other embodiments, whether or not explicitly described.

[0025] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that it can be directly on the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will also be understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0026] For the benefit of not obscuring the presentation of the embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and illustration, and some examples may not be described in detail. In other examples, some process steps or operations known in the art may not be described at all. It should be understood that the following description focuses heavily on the distinctive features or elements of various embodiments of the present invention.

[0027] Nanosheet transistors can be formed from stacked nanosheets with alternating layers of silicon and silicon germanium that are then formed into a nanosheet stack. A gate around the entire perimeter of the structure can be formed from the nanosheet stack. As the dimensions of nanosheet transistors continue to decrease, the close spacing between the channels of nanosheet transistors makes it difficult to change or tune different threshold voltages.

[0028] The present invention relates generally to semiconductor manufacturing, and more specifically to tuning the threshold voltage of nanosheet transistors. Threshold voltage tuning can be a major obstacle in nanosheet manufacturing due to aggressive device scale.

[0029] The inventors have discovered that the threshold voltage of nanosheet transistors can be tuned by selective crystallization of the gate dielectric layer. The inventors have also discovered that the dipole layer used to further tune the threshold voltage is not dispersed into the crystallized gate dielectric. Thus, the inventors have discovered that selectively crystallizing the gate dielectric can be used to generate a variety of different threshold voltages.

[0030] In particular, embodiments of the present invention disclose selectively crystallizing a gate dielectric layer during fabrication of a nanosheet transistor to modify the threshold voltage of the transistor. Additional embodiments of the present invention disclose selectively crystallizing the gate dielectric to prevent the dipole layer from diffusing into the gate dielectric and further generate multiple different threshold voltages. Techniques involving selectively crystallizing the gate dielectric are described in detail below by referring to the accompanying drawings of Figures 1 to 14 according to exemplary embodiments.

[0031] Referring now to Figure 1, a semiconductor structure 100 (hereafter "structure") at an intermediate stage of processing is shown in accordance with an exemplary embodiment. Figure 1 is a cross-sectional view of structure 100. Structure 100 of Figure 1 may be formed or provided. Structure A and Structure B are the same at this point in processing and will remain identical unless otherwise noted.

[0032] The structure 100 may include nanosheet stacks 20 separated by a bottom isolation layer 12 on a base substrate 10. The structure 100 may include shallow trench isolation regions (hereinafter "STI regions") 22. It should be noted that although a limited number of nanosheet stacks 20 are depicted, any number of nanosheet stacks 20 may be formed.

[0033] Substrate 10 may be, for example, a bulk substrate, which may be made of any of several known semiconductor materials, such as, for example, silicon, germanium, silicon germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide, or indium gallium arsenide. Typically, substrate 10 may be on the order of several hundred microns thick, but is not limited thereto. In other embodiments, substrate 10 may be a layered semiconductor, such as silicon-on-insulator or SiGe-on-insulator, where a buried insulator layer separates the base substrate from an overlying semiconductor layer.

[0034] A silicon germanium layer may be formed on the substrate, not shown. The silicon germanium layer may have, for example, a germanium concentration of about 60 atomic percent, although percentages greater than and less than 60% may also be used. The silicon germanium layer may be formed using deposition or epitaxial growth techniques. The silicon germanium layer may then be selectively removed from the remaining layers of the nanosheet stack 20, as described below. Thus, the silicon germanium layer may be made of other materials that allow selective removal.

[0035] The terms "epitaxially growing or depositing, or a combination thereof" and "epitaxially grown or deposited, or a combination thereof" refer to the growth of a semiconductor material on a deposition surface of the semiconductor material, where the growing semiconductor material has the same crystalline properties as the semiconductor material of the deposition surface. In epitaxial deposition techniques, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the atoms to be deposited arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and direct themselves into the crystalline arrangement of the atoms of the deposition surface. Thus, the epitaxial semiconductor material has the same crystalline properties as the deposition surface on which it is formed.

[0036] Examples of various epitaxial growth techniques include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), ambient pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature of epitaxial deposition typically ranges from about 550°C to about 900°C. Higher temperatures typically result in faster deposition, but faster deposition may result in crystal defects and film cracking. The epitaxial growth of the first and second semiconductor materials, which provide the sacrificial semiconductor material layer and the semiconductor channel material layer, respectively, may be carried out using any well-known precursor gas or gas mixture. Carrier gases such as hydrogen, nitrogen, helium, and argon may be used.

[0037] The nanosheet stack 20 includes alternating layers of vertically aligned sacrificial semiconductor material layers 16 and semiconducting channel material layers 18. The nanosheet stack 20 is formed on a silicon germanium layer. In FIG. 1, and by way of example only, the nanosheet stack 20 includes three sacrificial semiconductor material layers 16 and three semiconducting channel material layers 18. The material stacks that may be used in embodiments of the present invention are not limited to the specific embodiment shown in FIG. 1. The nanosheet stack 20 may include any number of sacrificial semiconductor material layers 16 and semiconducting channel material layers 18. The nanosheet stack 20 is used to create a gate-all-around device including vertically stacked semiconducting channel material nanosheets for a p-channel field effect transistor (PFET) or n-channel field effect transistor (NFET) device.

[0038] The sacrificial semiconductor material layers 16 are constructed of a first semiconductor material that is compositionally different from at least the top portion of the substrate 10 and compositionally different from the silicon germanium layer having 60% germanium. In one embodiment, each sacrificial semiconductor material layer 16 may have a germanium concentration less than 50 atomic percent. In another example, each sacrificial semiconductor material layer 16 may have a germanium concentration ranging from about 20 atomic percent to about 40 atomic percent. Each sacrificial semiconductor material layer 16 may be formed using known deposition techniques or epitaxial growth techniques as described above.

[0039] Each semiconductor channel material layer 18 is constructed of a second semiconductor material that is compositionally different from at least the top of substrate 10, compositionally different from the silicon germanium layer, and compositionally different from the sacrificial material layer 16. Each semiconductor channel material layer 18 has a different etch rate than the first semiconductor material of sacrificial semiconductor material layer 16, and has a different etch rate than the silicon germanium layer. The second semiconductor material may be, for example, silicon. The second semiconductor material may be formed for each semiconductor channel material layer 18 using known deposition techniques or the epitaxial growth techniques described above.

[0040] The nanosheet stack 20 (16, 18) may be formed by sequential epitaxial growth of alternating layers of a first semiconductor material and a second semiconductor material.

[0041] The sacrificial semiconductor material layers 16 of the nanosheet stack 20 may have a thickness in the range of about 5 nm to about 12 nm, while the semiconductor channel material layers 18 of the semiconductor stack 20 may have a thickness in the range of about 3 nm to about 12 nm. Each sacrificial semiconductor material layer 16 may have a thickness that is the same as or different from the thickness of each semiconductor channel material layer 18. In one embodiment, each sacrificial semiconductor material layer 16 has the same thickness. In one embodiment, each semiconductor channel material layer 18 has the same thickness.

[0042] The nanosheet stack 20 is formed by patterning the sacrificial semiconductor material layer 16 and the semiconductor channel material layer 18. The silicon germanium layer may be patterned simultaneously with the nanosheet stack 20. More specifically, the sacrificial semiconductor material layer 16, the semiconductor channel material layer 18, and portions of the silicon germanium layer are etched using an anisotropic etching technique, such as reactive ion etching (RIE), to stop on the substrate 10 and the STI regions 22. The nanosheet stack 20 includes alternating nanosheets of the remaining portions of each sacrificial semiconductor material layer 16 and each semiconductor channel material layer 18 over all remaining portions of the silicon germanium layer. After etching, the sidewalls of each sacrificial semiconductor material layer 16 are vertically aligned to the sidewalls of each semiconductor channel material layer 18 and to the sidewalls of the silicon germanium layer.

[0043] Adjacent nanosheet stacks 20 may be isolated from one another by regions of dielectric material, such as, for example, STI regions 22. STI regions 22 may be formed using known patterning and deposition techniques.

[0044] As previously mentioned, the silicon germanium layer is then selectively removed using one or more known techniques. In doing so, the silicon germanium layer is selectively removed from the semiconductor channel material layer 18, the semiconductor channel material layer 18, and the STI region 22. For example, a wet etching technique may be used to selectively remove the silicon germanium layer. The wet etching technique may use special chemical solutions, including, for example, tetramethylammonium hydroxide (TMAH) solution, potassium hydroxide (KOH) solution, ethylenediamine and pyrocatechol (EDP) solution. Alternatively, a wet etching technique relying on, for example, a mixture solution of HF-HNO3-H2SO4 may be used.

[0045] A bottom isolation layer 12 may be formed on the substrate 10 below the nanosheet stack 20 in the gap created by the removal of the silicon germanium layer. The bottom isolation layer 12 may be formed by conformally depositing a dielectric material followed by one or more etching or recess steps.

[0046] The bottom isolation layer 12 may be constructed from silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" as used throughout this application refers to a dielectric material having a dielectric constant less than silicon dioxide. In another embodiment, a self-planarizing material such as spin-on glass (SOG) or a spin-on low-k dielectric material such as SiLK may be used as the bottom isolation layer 12. The use of a self-planarizing dielectric material as the bottom isolation layer 12 may avoid the need to perform a subsequent etch or recess. SiLK is a trademark of Dow Chemical Company.

[0047] In some embodiments, as shown, the bottom isolation layer 12 may be selectively etched such that the vertical surfaces of the bottom isolation layer 12 are aligned with the nanosheet stack 20 and such that the top surfaces of the STI regions 22 are exposed. For example, an anisotropic etching technique such as reactive ion etching (RIE) may be used to etch the bottom isolation layer 12. After etching, the sidewalls of each sacrificial semiconductor material layer 16 are vertically aligned with the sidewalls of each semiconductor channel material layer 18 and with the sidewalls of the bottom isolation layer 12. Although not shown, in other embodiments, the bottom isolation layer 12 may extend from one nanosheet stack 20 to the next, leaving a continuous layer covering the STI regions 22.

[0048] Referring now to Figure 2, a structure 100 is shown according to an exemplary embodiment. As shown in Figure 2, the sacrificial semiconductor material layer 16 is selectively removed using one or more etching techniques. In doing so, the sacrificial semiconductor material layer 16 is selectively removed from the semiconductor channel material layer 18, the bottom isolation layer 12, and the STI regions 22. As shown in Figure 2, the remaining semiconductor channel material layer 18 is shown suspended and supported on both ends by additional portions of the structure 100, not shown.

[0049] For example, wet etching techniques can be used to selectively remove the sacrificial semiconductor material layer 16. Wet etching techniques can use special chemical solutions, including, for example, tetramethylammonium hydroxide (TMAH) solution, potassium hydroxide (KOH) solution, ethylenediamine and pyrocatechol (EDP) solution. Alternatively, wet etching techniques relying on, for example, a mixture solution of HF-HNO3-H2SO4 can be used.

[0050] Referring now to Figure 3, a structure 100 is shown according to an exemplary embodiment. As shown in Figure 3, a gate dielectric 24 is formed in each cavity and surrounds the suspended portion of the semiconductor channel material layer 18. The gate dielectric 24 further covers the STI regions 22 and the bottom isolation layer 12 as shown. In practice, the gate oxide 24 is deposited directly on an interface layer (not shown). The interface layer may be, for example, a native oxide such as silicon oxide.

[0051] The gate dielectric 24 may be an oxide, nitride, or oxynitride, or a combination thereof. In one example, the gate dielectric 24 may be a high-k material. Exemplary high-k dielectrics include HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfO x N y , ZrO x N y , LaO x N y , AlO x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y2O x N y , SiON, SiN x , their silicides, and alloys thereof. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2. In some embodiments, a multi-layered gate dielectric structure may be formed that includes different gate dielectric materials, such as silicon dioxide and a high-k gate dielectric, and may be used as the gate dielectric 24.

[0052] The gate dielectric 24 may be formed by a deposition technique including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or other similar deposition techniques. In one embodiment, the gate dielectric 24 may have a thickness in the range of about 1 nm to about 10 nm. Other thicknesses less than or greater than the above thickness range may also be used for the gate dielectric 24.

[0053] Referring now to Figure 4, a structure 100 is shown according to an exemplary embodiment. As shown in Figure 4, a first sacrificial gate 26 is formed on and over the gate dielectric 24. For example, a first sacrificial gate 26 is formed in each cavity and surrounds the suspended portion of the semiconducting channel material layer 18. As also shown in Figure 4, a first blanket sacrificial layer 28 may be formed over the first sacrificial gate 26 and may fill the areas between adjacent nanosheet stacks 20.

[0054] The first sacrificial gate 26 may comprise any material, such as, for example, polysilicon, amorphous silicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least two elemental metals, or a multilayered combination thereof.

[0055] The first sacrificial gate 26 may be formed by a deposition technique including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or other similar deposition techniques. When a metal silicide is formed, conventional silicide techniques may be used. In one embodiment, the first sacrificial gate 26 may have a thickness in the range of about 1 nm to about 50 nm, more preferably in the range of about 3 nm to about 10 nm. Other thicknesses less than or greater than the above thickness range may also be used for the first sacrificial gate 26. In one embodiment, the thickness of the first sacrificial gate 26 is deposited to a thickness sufficient to completely surround each of the semiconductor channel material layers 18, filling or substantially filling the space between adjacent semiconductor channel material layers 18.

[0056] First blanket sacrificial layer 28 may include any oxygen blocking material including, for example, amorphous silicon, polycrystalline silicon, amorphous carbon, amorphous germanium, polycrystalline germanium, or fabricated polycrystalline silicon germanium. First blanket sacrificial layer 28 may be formed using a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or other similar deposition techniques.

[0057] Now referring to Fig. 5, a structure 100 is shown according to an exemplary embodiment. As shown in Fig. 5, an organic polymer layer 30 can be selectively formed. The organic polymer layer 30 may cover selected nanosheet stacks 20 and may not cover other nanosheet stacks 20. As shown in Fig. 5, the organic polymer layer 30 is used to cover two nanosheet stacks 20 in structure B and does not cover two nanosheet stacks in structure A.

[0058] The organic polymer layer 30 may be formed by blanket deposition using typical deposition techniques including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or other similar deposition techniques. The material of the organic polymer layer 30 may include a photosensitive organic polymer including a photosensitive material. The organic polymer may include an epoxy resin, a phenolic resin, a polyacrylate resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene sulfide resin, a polyphenylene ether resin, or a benzocyclobutene (BCB). The material of the organic polymer layer 30 may be selected to be compatible with the first sacrificial gate 26 and the first blanket sacrificial layer 28. Specifically, the material is selected such that one or more of the first sacrificial gate 26, the first blanket sacrificial layer 28, or the organic polymer layer 30 are etched or recessed selectively or with each other.

[0059] At this processing point, structures A and B are different. Specifically, organic polymer layer 30 only covers structure B, and not structure A.

[0060] 6, a structure 100 is shown in accordance with an exemplary embodiment. As shown in FIG. 6, the first blanket sacrificial layer 28 and the first sacrificial gate 26 may be selectively removed from structure A. Subsequently, the organic polymer layer 30 may be removed from structure B.

[0061] As explained above, wet etching techniques are used to selectively remove the first blanket sacrificial layer 28 and the first gate 26, selectively from the organic polymer layer 30. The wet etching techniques may use special chemical solutions, including, for example, tetramethylammonium hydroxide (TMAH) solution, potassium hydroxide (KOH) solution, ethylenediamine and pyrocatechol (EDP) solution. Alternatively, wet etching techniques relying on, for example, a mixture solution of HF-HNO3-H2SO4 may be used. The etching may be performed in one or multiple steps.

[0062] Following removal of the first blanket sacrificial layer 28 and first sacrificial gate 26 in structure A, the organic polymer layer 30 may be removed from structure B. Wet etching techniques may be used to selectively remove the organic polymer layer 30, selective to the first blanket sacrificial layer 28, first sacrificial gate 26 and gate dielectric 24 of structure B.

[0063] At this processing point, structures A and B differ. Specifically, first blanket sacrificial layer 28 and first sacrificial gate 26 remain in structure B, but neither first blanket sacrificial layer 28 nor first sacrificial gate 26 remain in structure A.

[0064] 7, a structure 100 is shown according to an exemplary embodiment. As shown in FIG. 7, the structure 100 may be exposed to a spike anneal, a high temperature anneal, a laser spike anneal, or another type of anneal to crystallize the exposed portion of the gate dielectric 24. In structure A, the gate dielectric 24 becomes a crystallized gate dielectric 32 having a different characteristic than the gate dielectric 24. The gate dielectric 24 in structure B is protected by the first sacrificial gate 26 and the first blanket sacrificial layer 28 and therefore will not be exposed and will not be crystallized by the spike anneal.

[0065] In one embodiment, the annealing technique may include exposing the structure 100 to a high temperature in the range of about 800° C. to about 1250° C. for a time period of about 1 ms to about 500 ms. In another embodiment, a high temperature rapid thermal annealing (RTA) technique may be used. Normally, high temperatures cannot be used during processing due to the risk of damaging the gate metal or work function metal, however, in this case, neither the gate metal nor the work function metal have yet been formed.

[0066] The threshold voltage of the nanosheet transistor depends on the material and structure of the nanosheet stack 20, and also on the thickness and composition of the gate dielectric surrounding each of the semiconducting channel material layer 18 and the nanosheet stack 20. Before the laser spike anneal, structure A and structure B each had the same gate dielectric layer (i.e., gate dielectric 24) formed at the same time and having the same original thickness and composition, and therefore may have the same, or substantially the same, threshold voltage. However, after the laser spike anneal step, structure A has a crystallized gate dielectric 32, which has a different composition compared to the gate dielectric 24 of structure B. Thus, the threshold voltage of structure A will be different from the threshold voltage of structure B.

[0067] The use of spike laser annealing allows for selective crystallization without additional processing steps that would previously be required to form structure A and structure B with different gate dielectrics and different threshold voltages.

[0068] 8, a structure 100 is shown in accordance with an exemplary embodiment. As shown in FIG 8, the first blanket sacrificial layer 28 and the portion of the first sacrificial gate 26 remaining on structure B are removed.

[0069] As explained above, wet etching techniques may be used to selectively remove the remaining portions of the first blanket sacrificial layer 28 and the first sacrificial gate 26, selectively to the gate dielectric 24 and the crystallized gate dielectric 32.

[0070] 9, an exemplary embodiment of a structure 100 is shown. As shown in FIG. 9, a dipole layer 34 may be formed.

[0071] In structure A, a dipole layer 34 is formed on the crystallized gate dielectric 32 surrounding the semiconductor channel material layer 18 of the nanosheet stack 20. The dipole layer 34 is further formed on the crystallized gate dielectric 32 covering the bottom isolation layer 12 and the STI region 22.

[0072] In structure B, a dipole layer 34 is formed on the gate dielectric 24 surrounding the semiconductor channel material layer 18 of the nanosheet stack 20. The dipole layer 34 is further formed on the gate dielectric 24 covering the bottom isolation layer 12 and the STI region 22.

[0073] The dipole layer 34 may be formed by blanket deposition using typical deposition techniques including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or other similar deposition techniques. The material of the dipole layer 34 may include any suitable dipole layer known to those skilled in the art. For example, in some embodiments, the dipole layer 34 may include lanthanum oxide (La2O3) or aluminum oxide (Al2O3). In some embodiments, lanthanum oxide (La2O3) is commonly used for NFET devices and aluminum oxide (Al2O3) is commonly used for PFET devices. In other embodiments, lanthanum oxide (La2O3) and aluminum oxide (Al2O3) may be used for either NFET or PFET devices to achieve desired device characteristics.

[0074] Tuning the material of the dipole layer 34 can be another way to change the threshold voltage for nanosheet transistors. In one embodiment, for example, a lanthanum oxide (La2O3) dipole layer 34 can generally lower the threshold voltage of an NFET device and generally raise the threshold voltage of a PFET device. In an alternative embodiment, for example, an aluminum oxide (Al2O3) dipole layer 34 can generally increase the threshold voltage of an NFET device and generally lower the threshold voltage of a PFET device.

[0075] In some embodiments, it may be desirable to selectively deposit dipole layers 34 above selected nanosheet stacks 20 and not elsewhere.

[0076] 10, a structure 100 according to an exemplary embodiment is shown. As shown in FIG. 10, a second sacrificial gate 36 is formed.

[0077] In structure A, a second sacrificial gate 36 is formed in each cavity and surrounds the suspended portions of the semiconductor channel material layer 18, the crystallized gate dielectric 32 and the dipole layer 34. Meanwhile, in structure B, a second sacrificial gate 36 is formed in each cavity and surrounds the suspended portions of the semiconductor channel material layer 18, the gate dielectric 24 and the dipole layer 34. In some cases, the second sacrificial gate 36 also covers the surfaces of the STI regions 22 and the bottom isolation layer 12.

[0078] Also, as shown in FIG. 10, a second blanket sacrificial layer 38 may be formed overlying the second sacrificial gate semiconductor 36 and filling the areas between adjacent nanosheet stacks 20 .

[0079] A second sacrificial gate semiconductor 36 may be formed and may include materials such as those described above with respect to the first sacrificial gate 26. A second blanket sacrificial layer 38 may be formed and may include materials such as those described above with respect to the first blanket sacrificial layer 28.

[0080] 11, a structure 100 is shown according to an exemplary embodiment. As shown in FIG. 11, an annealing process is performed to diffuse the dipole layer 34 into the gate dielectric 24 only in structure B. In contrast, the dipole layer 34 is not diffused into the crystallized gate dielectric 32 of structure A, but instead remains on the gate dielectric layer 24.

[0081] More specifically, structure A remains substantially the same before and after annealing because the crystallized gate dielectric 32 prevents the dispersion of the dipole layer 34. Thus, only in structure A, the crystallized gate dielectric 32 separates the dipole layer 34 from the semiconductor channel material layer 18. In contrast, annealing causes the dipole layer 34 to diffuse into the (amorphous) gate dielectric layer 24 of structure B. After annealing, dipole material from the dipole layer 34, such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), or both, can be detected in the gate layer 24 and at the interface between the gate layer 24 and the interface layer. As described herein above, annealing can include a spike anneal, a high temperature anneal, or a laser spike anneal, or another type of anneal.

[0082] Diffusing the dipole material 34 into the gate dielectric layer 24 of structure B is another example of how selective crystallization, or the lack thereof in this example, can be used to adjust or change the threshold voltage of such nanosheet devices according to the disclosed embodiments. For example, structure B with diffused dipole material can be designed and manufactured to have a different threshold than structure A. Even more uniquely, the disclosed embodiments teach how to fabricate nanosheet devices with different threshold voltages using selective crystallization of the gate dielectric layer 24.

[0083] 12, a structure 100 is shown in accordance with an exemplary embodiment. As shown in FIG. 12, the second blanket sacrificial layer 38 and the second sacrificial gate 36 may be removed from the structure 100. Also, the dipole layer 34 may be removed from the structure A.

[0084] As explained above, one or more etching techniques, e.g., wet etching techniques, may be used to selectively remove the second blanket sacrificial layer 38, the second gate semiconductor 36 from the substrates of Structure A and Structure B. In Structure A, the wet etch will remove the dipole layer 34 selectively from the crystallized gate dielectric 32. In Structure B, the wet etch will remove a portion of the gate dielectric 24, however, diffused dipole material remains along the remaining portion of the gate dielectric 24 and the interface between the gate dielectric 24 and the interface layer.

[0085] 13 and 14, a structure 100 is shown in accordance with an exemplary embodiment. Structure A in Fig. 14 is a cross-sectional view perpendicular to the cross-sectional view of structure A shown in Fig. 13, taken along section line AA. Structure B in Fig. 14 is a cross-sectional view perpendicular to the cross-sectional view of structure B shown in Fig. 13, taken along section line BB. As shown in Figs. 13 and 14, a work function metal 40 can be formed.

[0086] The work function metal 40 can be formed as part of conventional gate processing for a nanosheet FET formed from the gate stack 20. Due to the differences between Structure A and Structure B, the same work function metal 40 can be used for both. The differences between the two structures, including the crystallized gate dielectric 32 of Structure A compared to the gate dielectric 24 of Structure A, and the diffused dipole material of Structure B, can be used to create two or more transistors with different threshold voltages even with the same work function metal 40.

[0087] In one embodiment, either structure A or B can be used as either an NFET or a PFET device.

[0088] The work function metal 40 may be conformally formed on the structure 100 according to an exemplary embodiment. The work function metal 40 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), and chemical vapor deposition (CVD).

[0089] The material selected for the work function metal 40 may be selected based on whether an NFET or PFET device is desired. In one embodiment, the work function metal 40 of a PFET device may include a metal nitride, such as titanium nitride or tantalum nitride, titanium carbide, titanium aluminum carbide, or other suitable material known in the art. In one embodiment, the work function metal 40 of an NFET device may include, for example, titanium aluminum carbide, or other suitable material known in the art. In one embodiment, the work function metal 40 may include one or more layers to achieve the desired device characteristics.

[0090] 14, inner spacers 42 may be formed, and source drain regions 44 and gate spacers 46 may all be formed by known techniques. The formation of source drain regions 44 and gate spacers 46 is typically completed prior to the start of processing shown in FIG.

[0091] Within the structure 100, there can be different combinations of gate dielectric layers and dipole layers to produce devices with different threshold voltages.

[0092] According to the embodiments described herein, selective crystallization of the gate dielectric provides at least four different techniques for controlling or tuning the threshold voltage of the disclosed nanosheet devices. For example, a first nanosheet transistor with a first threshold voltage would include only the gate dielectric 24 alone, without any crystallization or dipole layer, a second nanosheet transistor with a second threshold voltage would include only the crystallized gate dielectric 32 alone, without any dipole layer 34, a third nanosheet transistor with a third threshold voltage would include a dipole layer 34 diffused in the gate dielectric 24, as shown in structure B, and a fourth nanosheet transistor with a fourth threshold voltage would include only the dipole layer 34 on top of the crystallized gate dielectric 32, as shown in structure A.

[0093] As briefly discussed above, embodiments of the present invention disclose more efficient and less invasive techniques for fabricating nanosheet transistors with different threshold voltages. For example, to achieve different threshold voltages, conventional fabrication techniques require depositing different materials, e.g., different gate dielectrics. Doing so inherently requires deposition, masking, and etching techniques that can be invasive and harmful to the surrounding structures. Instead, embodiments of the present invention provide techniques for achieving different threshold voltages while minimizing additional processing steps, thereby minimizing collateral damage to the surrounding structures. For example, embodiments of the present invention start with a single gate dielectric material (24) and by modifying the gate dielectric by crystallization, devices with different threshold voltages are achievable.

[0094] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over the technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. nanosheet stacks on a substrate, each nanosheet stack comprising alternating layers of a sacrificial semiconductor material and a semiconducting channel material stacked on top of one another in vertical alignment; a crystallized gate dielectric layer surrounding the semiconductor channel material layer of the first subset of the nanosheet stack; a dipole layer overlying the crystallized gate dielectric and surrounding the layer of semiconducting channel material of the first subset of the nanosheet stack; a gate dielectric modified by diffused dipole material surrounding the semiconducting channel material layer of a second subset of the nanosheet stacks; 1. A semiconductor structure comprising:

2. a layer of a first gate conductor perpendicular to the nanosheet stack, the first gate conductor wrapping around the layer of semiconducting channel material of the nanosheet stack; The semiconductor structure of claim 1 .

3. 3. The semiconductor structure of claim 1, wherein crystallizing the gate dielectric comprises annealing the gate dielectric to form the crystallized gate dielectric.

4. 4. The semiconductor structure of claim 1, wherein the layer of sacrificial semiconductor material comprises silicon germanium.

5. 5. The semiconductor structure of claim 1, further comprising source drain regions extending laterally from either end of the semiconductor channel material layer of the nanosheet stack.

6. 6. The semiconductor structure of claim 1, wherein the crystallized gate dielectric layer is in direct contact with and covers shallow trench isolation regions between adjacent nanosheet stacks.

7. nanosheet stacks on a substrate, each nanosheet stack comprising alternating layers of a sacrificial semiconductor material and a semiconducting channel material stacked on top of one another in vertical alignment; a crystallized gate dielectric surrounding the semiconductor channel material layer of the nanosheet stack; 1. A semiconductor structure comprising:

8. a dipole layer overlying the crystallized gate dielectric and surrounding the layer of semiconducting channel material of the subset of nanosheet stacks; 8. The semiconductor structure of claim 7, further comprising:

9. a layer of a first gate conductor perpendicular to the nanosheet stack, the first gate conductor wrapping around the layer of semiconducting channel material of the nanosheet stack; 9. The semiconductor structure of claim 7 or 8.

10. 10. The semiconductor structure of claim 7, wherein crystallizing the gate dielectric comprises annealing the gate dielectric to form the crystallized gate dielectric.

11. 11. The semiconductor structure of claim 7, wherein the layer of sacrificial semiconductor material comprises silicon germanium.

12. 12. The semiconductor structure of claim 7, further comprising source drain regions extending laterally from either end of the semiconductor channel material layer of the nanosheet stack.

13. 13. The semiconductor structure of claim 7, wherein the layer of crystallized gate dielectric is in direct contact with and covers shallow trench isolation regions between adjacent nanosheet stacks.

14. forming nanosheet stacks on a substrate, each nanosheet stack comprising alternating layers of a sacrificial semiconductor material and a semiconducting channel material stacked on top of one another in vertical alignment; removing a sacrificial semiconductor material layer of the set of nanosheet stacks; forming a gate dielectric surrounding a semiconductor channel material layer of the nanosheet stack; crystallizing the gate dielectric of a subset of the nanosheet stacks; A method comprising:

15. 15. The method of claim 14, further comprising forming a dipole layer surrounding the gate dielectric surrounding the semiconducting channel material layer of a subset of the nanosheet stacks.

16. diffusing the dipole layer into the gate dielectric surrounding the semiconductor channel material layer of the subset of the nanosheet stacks. The method of claim 15 further comprising:

17. forming a layer of a first gate conductor perpendicular to the nanosheet stack, the first gate conductor wrapping around the layer of semiconducting channel material of the nanosheet stack; 17. The method according to any one of claims 14 to 16.

18. 18. The method of any one of claims 14 to 17, wherein crystallizing the gate dielectric comprises annealing the gate dielectric to form a crystallized gate dielectric.

19. 19. The method of any one of claims 14 to 18, wherein the sacrificial semiconductor material layer comprises silicon germanium.

20. 20. The method of any one of claims 14 to 19, further comprising forming source drain regions extending laterally from either end of the semiconducting channel material layer of the nanosheet stack.

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