Switched Capacitor Circuit

Abstract

To suppress leakage of electric charges from capacitances even when fluctuation in voltage at capacitance terminals is large at phase transitions of an operation.SOLUTION: A switched capacitor circuit is configured by a fully-differential operational amplifier circuit A1, input capacitances C1_P and C1_N, and switches S1_P, S1_N, S2_P, S2_N, S3_P, S3_N, S4_P, S4_N, S5_P, and S5_N. The switches S1_P, S5_P, and S3_P periodically switch a connection destination of an input side terminal of the input capacitance C1_P in an order of an input voltage VI_P, a voltage VCM2, and an input voltage VI_N. The switches S1_N, S5_N, and S3_N periodically switch a connection destination of an input side terminal of the input capacitance C1_N in an order of the input voltage VI_N, the voltage VCM2, and the input voltage VI_P, in synchronization with the switches S1_P, S5_P, and S3_P.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a switched capacitor circuit that realizes an equivalent resistance by a combination of capacitance and a switch, and in particular to a technique for suppressing charge leakage from a capacitance during a phase transition. [Background technology]

[0002] A switched capacitor circuit is a circuit that allows current to flow like a resistor by combining a switching element and a capacitance element (see Patent Document 1 and Patent Document 2). When forming a circuit inside an IC, by replacing the resistor with a switched capacitor circuit, it is possible to realize circuit characteristics according to the relative accuracy of the capacitance elements.

[0003] Fig. 4 is a block diagram of a fully differential switched capacitor integrator circuit that integrates the differential voltage of input terminals VI_P and VI_N, and Fig. 5 is a timing chart of the fully differential switched capacitor integrator circuit of Fig. 4. The fully differential switched capacitor integrator circuit is composed of a fully differential operational amplifier circuit A1, input capacitances C1_P and C1_N, integral capacitances C2_P and C2_N, and switches S1_P, S1_N, S2_P, S2_N, S3_P, S3_N, S4_P, and S4_N.

[0004] 5, the connection state of the switches S1_P, S1_N, S2_P, S2_N, S3_P, S3_N, S4_P, and S4_N is divided into two phases (φ1, φ2). In the phase when the clock signal φ1 is high and the clock signal φ2 is low, the switches S1_P and S1_N are on and the switches S2_P and S2_N are off, so that the input side terminal of the input capacitance C1_P is connected to the input terminal VI_P, and the input side terminal of the input capacitance C1_N is connected to the input terminal VI_N.

[0005] In the phase when the clock signal φ1 is low and the clock signal φ2 is high, the switches S1_P and S1_N are off and the switches S2_P and S2_N are on, so that the input side terminal of the input capacitance C1_P is connected to the input terminal VI_N, and the input side terminal of the input capacitance C1_N is connected to the input terminal VI_P.

[0006] On the other hand, in a phase in which the clock signal φ1 is high and the clock signal φ2 is low, the switches S3_P and S3_N are on and the switches S4_P and S4_N are off, and the terminals of the input capacitances C1_P and C1_N on the operational amplifier side are connected to the voltage VCM1. As a result, the input capacitances C1_P and C1_N are charged with electric charges according to the voltages input to the input terminals VI_P and VI_N.

[0007] In the phase when the clock signal φ1 is low and the clock signal φ2 is high, the switches S3_P and S3_N are off and the switches S4_P and S4_N are on, and the terminals of the input capacitances C1_P and C1_N on the op-amp side are connected to the input terminals of the fully differential op-amp circuit A1. As a result, at the moment when the clock signal φ2 becomes high, feedback is applied so that the voltages of the terminals of the input capacitances C1_P and C1_N on the op-amp side become equal.

[0008] The difference Q1(φ1) between the amount of charge Q1_P(φ1) stored in the input capacitance C1_P and the amount of charge Q1_N(φ1) stored in the input capacitance C1_N by the time the clock signal φ1 switches from high to low is given by the following equation. Q1(φ1) = Q1_P(φ1) - Q1_N(φ1) =C1_P(VI_P-VCM1)-C1_N(VI_N-VCM1)·(1)

[0009] The difference Q1(φ2) between the amount of charge Q1_P(φ2) stored in the input capacitance C1_P and the amount of charge Q1_N(φ2) stored in the input capacitance C1_N by the time the clock signal φ2 switches from high to low is given by the following equation. Q1(φ2) = Q1_P(φ2) - Q1_N(φ2) =C1_P(VI_N-VCM')-C1_N(VI_P-VCM')·(2)

[0010] Here, VCM' is the input terminal voltage of the fully differential operational amplifier circuit A1, and is determined by the differential output voltage of the fully differential operational amplifier circuit A1 and the amount of charge charged in the integral capacitances C2_P and C2_N. The fully differential operational amplifier circuit A1 normally applies feedback to the output voltage so that the center voltage of the differential output is constant. If the center voltage of the differential output is designed to be VCM1 and the input capacitance CI_P=CI_N, the amount of charge integrated in the integral capacitances C2_P and C2_N becomes an antisymmetric value, so VCM'=VCM1.

[0011] If CI_P=CI_N=CI, the amount of charge ΔQ1 transferred in one operation period of the clock signal φ1 of the switched capacitor integrator circuit of FIG. 4 is given by the following equation. ΔQ1=Q1(φ1)-Q1(φ2)=2×CI×(VI_P-VI_N) (3)

[0012] In the switched capacitor integration circuit of FIG. 4, a charge proportional to the differential voltage (VI_P-VI_N) is integrated for each cycle of the clock signal φ1. For example, in the typical circuit disclosed in Patent Document 2, the input capacitance is connected to the center voltage VCM1 of the differential output when the clock signal φ2 is in the High phase. In this case, the amount of charge transfer ΔQ1 is expressed by the following equation: ΔQ1=CI×(VI_P-VI_N) ···(4)

[0013] That is, the switched capacitor integrator circuit of FIG. 4 transfers twice the amount of charge for the same input capacitance compared to the circuit disclosed in Patent Document 2, and is therefore expected to improve the S / N ratio.

[0014] On the other hand, in the switched capacitor integrator circuit of FIG. 4, a problem may occur depending on the potential difference (VI_P-VI_N). In a typical CMOS process IC, as shown in Fig. 6, the switch S1_P is realized by a configuration called a transmission gate, which is a combination of an N-channel MOSFET (NMOS) 100 and a P-channel MOSFET (PMOS) 200. The same is true for the other switches S1_N, S2_P, S2_N, S3_P, S3_N, S4_P, and S4_N.

[0015] 7 shows cross-sectional views of the NMOS 100 and PMOS 200. In FIG. 7, 101 and 201 are P-type substrates, 102 is an N-type diffusion layer, 202 is a P-type diffusion layer, 103 and 203 are gate oxide films, 104 and 204 are gates made of polysilicon, and 205 is an N-type well.

[0016] In the NMOS 100, the N-type diffusion layer 102 is formed on the P-type substrate 101, and in the PMOS 200, the P-type diffusion layer 202 is formed on the N-type well 205. Usually, the P-type substrate 101 of the NMOS 100 is connected to the ground potential so that the potentials of the P-type substrate 101 and the N-type diffusion layer 102 are not forward biased. Similarly, the N-type well 205 of the PMOS 200 is connected to the power supply voltage VDD so that the potentials of the N-type well 205 and the P-type diffusion layer 202 are not forward biased.

[0017] However, when the potential of the diffusion layer of the MOS becomes lower than the ground potential or higher than the power supply voltage VDD, a forward bias current flows from the bulk (P-type substrate 101, N-type well 205) to the diffusion layer or from the diffusion layer to the bulk. For example, when the N-type diffusion layer 102 becomes lower than the ground potential, a forward bias current flows from the P-type substrate 101 of the NMOS to the N-type diffusion layer 102. Also, when the P-type diffusion layer 202 becomes higher than the power supply voltage VDD, a forward bias current flows from the P-type diffusion layer 202 of the PMOS to the N-type well 205.

[0018] In the circuit of FIG. 4, depending on the relationship between the input voltages VI_P and VI_N, a forward bias current may flow into the bulk or diffusion layer of the CMOS switch. In the circuit of FIG. 4, the amount of charge Q1_P(φ1) stored in the input capacitance C1_P by the time the clock signal φ1 switches from High to Low is expressed by the following equation. Q1_P=C1_P(VI_P-VCM1) ···(5)

[0019] At the moment when the clock signal φ2 becomes high, the charge shown in equation (5) is stored in the input capacitance C1_P, so that the voltage VCO_P(φ1_2) at the connection point between the input capacitance C1_P and the switches S3_P and S4_P is expressed by the following equation. VCO_P(φ1_2)=VI_N-(VI_P-VCM1) ···(6)

[0020] Here, depending on the values ​​of the input voltages VI_P and VI_N, the value of the voltage VCO_P (φ2) at the connection point between the input capacitance C1_P and the switches S3_P and S4_P in the phase in which the clock signal φ2 becomes high can be greater than or equal to the power supply voltage of the IC or less than the ground potential.

[0021] For example, if the power supply voltage is VDD and the voltage VCM1 is designed to be VCM1 ≥ VDD / 2, then under the condition that (VI_P-VI_N) < -VDD / 2, the voltage VCO_P(φ1_2) at the connection point between the input capacitance C1_P and the switches S3_P and S4_P at the moment the clock signal φ2 goes high will be expressed by the following equation. VCO_P(φ1_2)=-(VI_P-VI_N)+VCM1>VDD (7)

[0022] Therefore, since the voltage VCO_P (φ1_2) becomes higher than the power supply voltage VDD, a voltage higher than the power supply voltage VDD is applied to the diffusion layers of the NMOS and PMOS of the switches S3_P and S4_P.

[0023] Conversely, if the voltage of VCM1 is designed to be VCM1≦VDD / 2, then under the condition that (VI_P-VI_N)>VDD / 2, the voltage VCO_P(φ1_2) at the connection point between the input capacitance C1_P and the switches S3_P and S4_P at the moment the clock signal φ2 goes high will be expressed by the following equation. VCO_P(φ1_2)=-(VI_P-VI_N)+VCM1<0 ···(8)

[0024] Therefore, since the voltage VCO_P (φ1_2) becomes lower than the ground potential, a voltage lower than the ground potential is applied to the diffusion layers of the NMOS and PMOS of the switches S3_P and S4_P. In other words, when the possible value of the potential difference (VI_P-VI_N) is greater than the absolute value of VDD / 2, there is no unique solution for the voltage that keeps VCO_P (φ2) within the range of the power supply voltage VDD.

[0025] During operation of the switched-capacitor integrator circuit of Figure 4, if the voltage VCO_P at the connection point between the input capacitance C1_P and the switches S3_P, S4_P and the voltage VCO_N at the connection point between the input capacitance C1_N and the switches S3_N, S4_N become higher than the power supply voltage VDD or lower than ground potential, a current will flow from the bulk of the NMOS of the switches S3_P, S3_N, S4_P, S4_N to the diffusion layer, or from the diffusion layer of the PMOS to the bulk.

[0026] As a result, the charge of the input capacitances C1_P and C1_N that were charged during the high phase of the clock signal φ1 leaks, causing an error in the integral value. When designing a switched-capacitor integrator circuit, it is necessary to take measures to avoid this charge leakage.

[0027] In Figure 4, a fully differential switched-capacitor integrator circuit is given as an example, but the same problem occurs in a single-ended switched-capacitor integrator circuit. If there is a large difference in the input capacitance terminal voltage between the phase in which clock signal φ1 is high and the phase in which clock signal φ2 is high, measures must be taken to avoid leakage of charge from the input capacitance. [Prior art documents] [Patent documents]

[0028] [Patent Document 1] Patent No. 3795338 [Patent Document 2] JP 2016-042627 A Summary of the Invention [Problem to be solved by the invention]

[0029] The present invention has been made to solve the above-mentioned problems, and aims to provide a switched capacitor circuit that can suppress leakage of charge from the capacitance even when there is a large fluctuation in the capacitance terminal voltage during a phase transition of operation. [Means for solving the problem]

[0030] The switched capacitor circuit of the present invention includes a sampling capacitor, an operational amplifier circuit, an input side switch configured to selectively connect an input side terminal of the sampling capacitor to any one of a first input voltage, a second input voltage, and a first reference voltage for charge transfer, and an output side switch configured to selectively connect a terminal of the sampling capacitor on the operational amplifier circuit side to any one of a second reference voltage for charge charging and an input terminal of the operational amplifier circuit, and periodically switches the connection destination of the input side terminal of the sampling capacitor between the first input voltage, the first reference voltage, and the second input voltage, in that order, to calculate a differential voltage between the first input voltage and the second input voltage. the output-side switch connects a terminal of the sampling capacitor on the operational amplifier circuit side to the second reference voltage in a phase in which the input-side switch connects the input-side terminal of the sampling capacitor to the first input voltage, and connects a terminal of the sampling capacitor on the operational amplifier circuit side to an inverting input terminal of the operational amplifier circuit in a phase in which the input-side switch connects the input-side terminal of the sampling capacitor to the first reference voltage or the second input voltage. It is characterized by the above. Moreover, one configuration example (first and second embodiments) of the switched capacitor circuit of the present invention further includes an integral capacitance having one end connected to the input terminal of the operational amplifier circuit and the other end connected to the output terminal of the operational amplifier circuit, and is characterized in that the input side terminal of the sampling capacitance is periodically switched between the first input voltage, the first reference voltage, and the second input voltage, in that order, thereby integrating the differential voltage between the first input voltage and the second input voltage.

[0031] Moreover, in one configuration example (second embodiment) of the switched capacitor circuit of the present invention, the input side switch includes a first switch having a first terminal connected to the first input voltage and a second terminal connected to the input side terminal of the sampling capacitance, a second switch having a first terminal connected to the input side terminal of the sampling capacitance and a second terminal connected to the first reference voltage, and a third switch having a first terminal connected to the second input voltage and a second terminal connected to the input side terminal of the sampling capacitance, and the output side switch includes a fourth switch having a first terminal connected to the terminal of the sampling capacitance on the operational amplifier circuit side and a second terminal connected to the second reference voltage, and a fifth switch having a first terminal connected to the terminal of the sampling capacitance on the operational amplifier circuit side and a second terminal connected to the inverting input terminal of the operational amplifier circuit, and the first, second and third switches periodically switch the connection destination of the input side terminal of the sampling capacitance in the order of the first input voltage, the first reference voltage and the second input voltage.

[0032] Also In one configuration example (second embodiment) of the switched capacitor circuit of the present invention, the first and second reference voltages are set so that the voltage at the connection point between the operational amplifier circuit side terminal of the sampling capacitor and the output side switch in the phase in which the input side switch connects the input side terminal of the sampling capacitor to the first reference voltage or the second input voltage falls within the range of ground potential and power supply voltage.

[0033] The switched capacitor circuit of the present invention a first sampling capacitor, a second sampling capacitor, an operational amplifier circuit, an input-side switch configured to selectively connect input-side terminals of the first and second sampling capacitors to one of a first input voltage, a second input voltage, and a first reference voltage for charge transfer, and an output-side switch configured to selectively connect operational amplifier circuit-side terminals of the first and second sampling capacitors to one of a second reference voltage for charge charging and an input terminal of the operational amplifier circuit, The operational amplifier circuit is a fully differential operational amplifier circuit. ,beforeThe input side switch includes a first switch having a first terminal connected to the first input voltage and a second terminal connected to an input side terminal of the first sampling capacitor, a second switch having a first terminal connected to the second input voltage and a second terminal connected to an input side terminal of the second sampling capacitor, a third switch having a first terminal connected to the input side terminal of the first sampling capacitor and a second terminal connected to the first reference voltage, a fourth switch having a first terminal connected to the input side terminal of the second sampling capacitor and a second terminal connected to the first reference voltage, a fifth switch having a first terminal connected to the second input voltage and a second terminal connected to the input side terminal of the first sampling capacitor, and a sixth switch having a first terminal connected to the first input voltage and a second terminal connected to the input side terminal of the second sampling capacitor. The output side switch includes a first terminal connected to a terminal of the first sampling capacitor on the fully differential operational amplifier circuit side and a second terminal connected to the the seventh switch connected to a second reference voltage; an eighth switch having a first terminal connected to a terminal of the second sampling capacitor on the fully differential operational amplifier circuit side and a second terminal connected to the second reference voltage; a ninth switch having a first terminal connected to the terminal of the first sampling capacitor on the fully differential operational amplifier circuit side and a second terminal connected to an inverting input terminal of the fully differential operational amplifier circuit; and a tenth switch having a first terminal connected to a terminal of the second sampling capacitor on the fully differential operational amplifier circuit side and a second terminal connected to a non-inverting input terminal of the fully differential operational amplifier circuit, the first, third and fifth switches periodically switch the connection destination of the input side terminal of the first sampling capacitor between the first input voltage, the first reference voltage and the second input voltage in this order, and the second, fourth and sixth switches periodically switch the connection destination of the input side terminal of the second sampling capacitor between the second input voltage, the first reference voltage and the first input voltage in this order in synchronization with the first, third and fifth switches. the seventh and eighth switches connect terminals of the first and second sampling capacitors on the fully differential operational amplifier circuit side to the second reference voltage in a phase in which the input-side switch connects the input-side terminal of the first sampling capacitor to the first input voltage and the input-side terminal of the second sampling capacitor to the second input voltage, and the ninth and tenth switches connect the terminal of the first sampling capacitor on the fully differential operational amplifier circuit side to the inverting input terminal of the operational amplifier circuit and the terminal of the second sampling capacitor on the fully differential operational amplifier circuit side to the non-inverting input terminal of the operational amplifier circuit in a phase in which the input-side switch connects the input-side terminal of the first sampling capacitor to the first reference voltage or the second input voltage and the input-side terminal of the second sampling capacitor to the first reference voltage or the first input voltage. It is characterized by the above.

[0034] Moreover, one configuration example (first embodiment) of the switched capacitor circuit of the present invention further includes a first integral capacitance having one end connected to an inverting input terminal of the fully differential operational amplifier circuit and the other end connected to a non-inverting output of the fully differential operational amplifier circuit, and a second integral capacitance having one end connected to the non-inverting input terminal of the fully differential operational amplifier circuit and the other end connected to the inverting output of the fully differential operational amplifier circuit, wherein the first, third and fifth switches periodically switch the connection destination of the input side terminal of the first sampling capacitance to the first input voltage, the first reference voltage and the second input voltage, in that order, and the second, fourth and sixth switches periodically switch the connection destination of the input side terminal of the second sampling capacitance to the second input voltage, the first reference voltage and the first input voltage, in synchronization with the first, third and fifth switches, thereby integrating a differential voltage between the first input voltage and the second input voltage.

[0035] Also In one configuration example (first embodiment) of the switched capacitor circuit of the present invention, the first and second reference voltages are set so that, in a phase in which the input side switch connects the input side terminal of the first sampling capacitor to the first reference voltage or the second input voltage, and connects the input side terminal of the second sampling capacitor to the first reference voltage or the first input voltage, the voltage at the connection point between the first sampling capacitor and the seventh and ninth switches and the voltage at the connection point between the second sampling capacitor and the eighth and tenth switches are within the range of ground potential and power supply voltage. Effect of the Invention

[0036] According to the present invention, by periodically switching the connection destination of the input terminal of the sampling capacitor between the first input voltage, the first reference voltage, and the second input voltage in that order, it is possible to suppress leakage of charge from the sampling capacitor even when the amplitude of the differential voltage between the first input voltage and the second input voltage is large. As a result, the present invention makes it possible to reduce errors in signal processing. [Brief description of the drawings]

[0037] [Figure 1] FIG. 1 is a circuit diagram of a fully differential switched-capacitor integrator circuit according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a timing chart of the fully differential switched-capacitor integrator circuit according to the first embodiment of the present invention. [Diagram 3] FIG. 3 is a circuit diagram of a single-ended switched capacitor integrator circuit according to a second embodiment of the present invention. [Figure 4] FIG. 4 is a circuit diagram of a conventional fully differential switched-capacitor integrator circuit. [Diagram 5] FIG. 5 is a timing chart of a conventional fully differential switched-capacitor integrator circuit. [Figure 6] FIG. 6 is a circuit diagram of a transmission gate. [Figure 7] FIG. 7 is a cross-sectional view of an N-channel MOSFET and a P-channel MOSFET. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] [First Example] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram of a fully differential switched capacitor integrator circuit according to a first embodiment of the present invention, and Fig. 2 is a timing chart of the switched capacitor integrator circuit of Fig. 1.

[0039] The switched capacitor integrator circuit of this embodiment includes a fully differential operational amplifier circuit A1 (operational amplifier circuit), input capacitances C1_P,C1_N (sampling capacitance), one end of an integral capacitance C2_P connected to the inverting input terminal of the fully differential operational amplifier circuit A1 and the other end connected to the non-inverting output terminal of the fully differential operational amplifier circuit A1, one end of an integral capacitance C2_N connected to the non-inverting input terminal of the fully differential operational amplifier circuit A1 and the other end connected to the inverting output terminal of the fully differential operational amplifier circuit A1, a switch S1_P having a first terminal connected to an input terminal VI_P (first input voltage) and a second terminal connected to an input side terminal of the input capacitance C1_P and a control terminal to which a clock signal φ1 is input, and a first terminal connected to an input terminal V a switch S1_N having a first terminal connected to the input terminal VI_N and a second terminal connected to the input terminal of the input capacitance C1_N and a control terminal to which the clock signal φ1 is input; a switch S2_P having a first terminal connected to the input terminal VI_N and a second terminal connected to the input terminal of the input capacitance C1_P and a control terminal to which the clock signal φ2b is input; a switch S2_N having a first terminal connected to the input terminal VI_P and a second terminal connected to the input terminal of the input capacitance C1_N and a control terminal to which the clock signal φ2b is input; a switch S3_P having a first terminal connected to a terminal on the operational amplifier side of the input capacitor C1_N, a second terminal connected to a voltage VCM1 (second reference voltage), and a control terminal to which a clock signal φ1 is input; a switch S3_N having a first terminal connected to a terminal on the operational amplifier side of the input capacitor C1_N, a second terminal connected to the voltage VCM1, and a control terminal to which a clock signal φ1 is input; a switch S4_P having a first terminal connected to a terminal on the operational amplifier side of the input capacitor C1_P, a second terminal connected to an inverting input terminal of the fully differential operational amplifier circuit A1, and a control terminal to which a clock signal φ2 is input; The switch S4_N is connected to the op-amp side terminal of the input capacitance C1_N, the second terminal is connected to the non-inverting input terminal of the fully differential op-amp circuit A1, and the control terminal is input with the clock signal φ2; the switch S5_P is connected to the input side terminal of the input capacitance C1_P, the second terminal is connected to the voltage VCM2 (first reference voltage), and the control terminal is input with the clock signal φ2a; and the switch S5_N is connected to the input side terminal of the input capacitance C1_N, the second terminal is connected to the voltage VCM2, and the control terminal is input with the clock signal φ2a.

[0040] The switches S1_P, S1_N, S2_P, S2_N, S5_P and S5_N configure input side switches, and the switches S3_P, S3_N, S4_P and S4_N configure output side switches. The clock signals φ1, φ2, φ2a, and φ2b are output from a clock signal source (not shown).

[0041] In this embodiment, switches S5_P and S5_N are added to the switched capacitor integration circuit shown in Figure 4, the charge hold phase φ2 of the switched capacitor integration circuit is divided into two phases, φ2a and φ2b, and the connection state of switches S1_P, S1_N, S2_P, S2_N, S5_P, and S5_N is divided into three phases (φ1, φ2a, φ2b).

[0042] In the phase when the clock signal φ1 is high and the clock signals φ2, φ2a, and φ2b are low, switches S1_P and S1_N are on and switches S2_P, S2_N, S5_P, and S5_N are off, so that the input side terminal of input capacitance C1_P is connected to input terminal VI_P, and the input side terminal of input capacitance C1_N is connected to input terminal VI_N.

[0043] In a phase in which the clock signals φ1 and φ2b are low and the clock signals φ2 and φ2a are high, the switches S1_P, S1_N, S2_P, and S2_N are off and the switches S5_P and S5_N are on, and the input side terminals of the input capacitances C1_P and C1_N are connected to the voltage VCM2.

[0044] In a phase in which the clock signals φ1 and φ2a are low and the clock signals φ2 and φ2b are high, switches S1_P, S1_N, S5_P, and S5_N are off and switches S2_P and S2_N are on, so that the input side terminal of input capacitance C1_P is connected to input terminal VI_N, and the input side terminal of input capacitance C1_N is connected to input terminal VI_P.

[0045] As in the conventional case, when the clock signal φ1 is high and the clock signal φ2 is low, the switches S3_P and S3_N are on and the switches S4_P and S4_N are off, and the terminals of the input capacitances C1_P and C1_N on the op-amp side are connected to the voltage VCM1. Also, when the clock signal φ1 is low and the clock signal φ2 is high, the switches S3_P and S3_N are off and the switches S4_P and S4_N are on, and the terminals of the input capacitances C1_P and C1_N on the op-amp side are connected to the input terminals of the fully differential op-amp circuit A1.

[0046] In the phase in which the clock signal φ2a becomes High, the value of the voltage VCO_P(φ2a) at the connection point between the input capacitance C1_P and the switches S3_P, S4_P is expressed by the following equation. VCO_P(φ2a)=VCM2-(VI_P-VCM1) ···(9)

[0047] Furthermore, the value of the voltage VCO_P(φ2b) at the connection point between the input capacitance C1_P and the switches S3_P, S4_P in the phase in which the clock signal φ2b becomes High is expressed by the following equation. VCO_P(φ2b)=VI_N-(VCM2-VCM') ···(10)

[0048] In equation (10), VCM'=VCM1 (when the common-mode feedback voltage=VCM1). In order to avoid leakage of the charge of the input capacitances C1_P and C1_N that are charged when the clock signal φ1 is in the high phase, the values ​​of the voltages VCM1 and VCM2 should be designed so that the values ​​of the voltages VCO_P(φ2a) and VCO_P(φ2b) in equations (9) and (10) do not exceed the range from ground potential to the power supply voltage VDD.

[0049] For example, if VCM1=VCM2=VDD / 2 for the power supply voltage VDD, the voltages VCO_P(φ2a) and VCO_P(φ2b) will be as follows. VCO_P(φ2a)=VDD-VI_P ···(11) VCO_P(φ2b)=VI_N (12)

[0050] However, 0 V≦VI_P≦VDD and 0 V≦VI_N≦VDD. According to equations (11) and (12), as long as the input voltages VI_P and VI_N are within the range between the ground potential and the power supply voltage VDD, the voltages VCO_P(φ2a) and VCO_P(φ2b) at the connection points between the input capacitance C1_P and the switches S3_P and S4_P will also be within the range between the ground potential and the power supply voltage VDD.

[0051] Equations (11) and (12) only show the voltage at the connection point between the input capacitance C1_P and the switches S3_P and S4_P. However, by setting, for example, VCM1=VCM2=VDD / 2, the voltage VCO_N at the connection point between the input capacitance C1_N and the switches S3_N and S4_N will also be within the range between the ground potential and the power supply voltage VDD.

[0052] In this embodiment, the voltage on the input terminal side of the input capacitance C1_P is not changed from VI_P to VI_N at once, but is passed through VCM2. When the potential difference between the input voltage VI_P and the input voltage VI_N is large, the instantaneous voltage change amount can be suppressed within a specified value by passing through a known voltage VCM2, and the charge leakage of the input capacitance C1_P can be suppressed. The same is true for the input capacitance C1_N. Therefore, in this embodiment, in applications such as differential input, it becomes possible to obtain a voltage signal with a large amplitude, and compared to the configuration disclosed in Patent Document 2, an improvement in the S / N ratio of the integrating circuit can be expected.

[0053] [Second Example] In the first embodiment, a fully differential switched capacitor integrator circuit has been described as an example, but the present invention can also be applied to a single-ended switched capacitor integrator circuit. Fig. 3 is a circuit diagram of a single-ended switched capacitor integrator circuit according to a second embodiment of the present invention.

[0054] The switched capacitor integrator circuit of this embodiment includes an operational amplifier circuit A2 (operational amplifier circuit) having a non-inverting input terminal connected to a voltage VCM1 (second reference voltage), an input capacitance C1 (sampling capacitance), an integrating capacitance C2 having one end connected to the inverting input terminal of the operational amplifier circuit A2 and the other end connected to the output terminal of the operational amplifier circuit A2, a switch S1 having a first terminal connected to an input terminal V1 (first input voltage) and a second terminal connected to an input side terminal of the input capacitance C1 and having a control terminal to which a clock signal φ1 is input, and a first terminal connected to an input terminal V2 (second input voltage) and a second terminal connected to the input side terminal of the input capacitance C1. a switch S2 having a first terminal connected to a terminal on the operational amplifier side of the input capacitance C1, a second terminal connected to a voltage VCM1, and a control terminal to which the clock signal φ1 is input; a switch S4 having a first terminal connected to a terminal on the operational amplifier side of the input capacitance C1, a second terminal connected to an inverting input terminal of the operational amplifier circuit A2, and a control terminal to which the clock signal φ2 is input; and a switch S5 having a first terminal connected to a terminal on the input side of the input capacitance C1, a second terminal connected to a voltage VCM2 (first reference voltage), and a control terminal to which the clock signal φ2a is input.

[0055] The switches S1, S2, and S5 constitute an input side switch, and the switches S3 and S4 constitute an output side switch. In this embodiment, the timing chart of the switched capacitor integrator is the same as that shown in FIG.

[0056] In a phase in which the clock signal φ1 is high and the clock signals φ2, φ2a, and φ2b are low, the switch S1 is on and the switches S2 and S5 are off, and the input side terminal of the input capacitance C1 is connected to the input terminal V1. In a phase in which the clock signals φ1 and φ2b are low and the clock signals φ2 and φ2a are high, the switches S1 and S2 are off and the switch S5 is on, and the input side terminal of the input capacitance C1 is connected to the voltage VCM2. In a phase in which the clock signals φ1 and φ2a are low and the clock signals φ2 and φ2b are high, the switches S1 and S5 are off and the switch S2 is on, and the input side terminal of the input capacitance C1 is connected to the input terminal V2.

[0057] In the phase where the clock signal φ1 is high and the clock signal φ2 is low, the switch S3 is on and the switch S4 is off, and the terminal of the input capacitance C1 on the op-amp side is connected to the voltage VCM1. In the phase where the clock signal φ1 is low and the clock signal φ2 is high, the switch S3 is off and the switch S4 is on, and the terminal of the input capacitance C1 on the op-amp side is connected to the inverting input terminal of the op-amp circuit A2.

[0058] In this embodiment, the differential voltage between input terminals V1 and V2 is integrated for each cycle of the clock signal φ1. As in the first embodiment, the connection destination of the input capacitance C1 is switched between two stages, φ2a and φ2b, to transfer the charge to the integral capacitance C2 in stages, thereby preventing the charge from leaking from the input capacitance C1 even when the amplitude of V1-V2 is large.

[0059] In the first and second embodiments, a switched capacitor integrator circuit has been used as an example, but the present invention is considered to be broadly applicable to switched capacitor circuits in general, and can be used as a method for suppressing charge leakage when there is large fluctuation in capacitance terminal voltage during phase transitions in operation. [Industrial Applicability]

[0060] The present invention can be applied to a switched capacitor circuit. [Explanation of symbols]

[0061] A1…Fully differential operational amplifier circuit, A2…Operational amplifier circuit, C1, C1_P, C1_N…Input capacitance, C2, C2_P, C2_N…Integral capacitance, S1, S1_P, S1_N, S2, S2_P, S2_N, S3, S3_P, S3_N, S4, S4_P, S4_N, S5, S5_P, S5_N…Switch.

Claims

1. Sampling capacity, An operational amplifier circuit; an input-side switch configured to selectively connect an input-side terminal of the sampling capacitor to any one of a first input voltage, a second input voltage, and a first reference voltage for charge transfer; an output-side switch configured to selectively connect a terminal of the sampling capacitor on the operational amplifier circuit side to either a second reference voltage for charging or an input terminal of the operational amplifier circuit; a connection destination of an input side terminal of the sampling capacitor is periodically switched between the first input voltage, the first reference voltage, and the second input voltage in this order, thereby calculating a differential voltage between the first input voltage and the second input voltage; the output-side switch connects a terminal of the sampling capacitor on the operational amplifier circuit side to the second reference voltage in a phase in which the input-side switch connects the input-side terminal of the sampling capacitor to the first input voltage, and connects a terminal of the sampling capacitor on the operational amplifier circuit side to an inverting input terminal of the operational amplifier circuit in a phase in which the input-side switch connects the input-side terminal of the sampling capacitor to the first reference voltage or the second input voltage.

2. 2. The switched capacitor circuit according to claim 1, an integral capacitance having one end connected to the input terminal of the operational amplifier circuit and the other end connected to the output terminal of the operational amplifier circuit; A switched capacitor circuit characterized in that a connection of an input side terminal of the sampling capacitor is periodically switched between the first input voltage, the first reference voltage, and the second input voltage, in that order, thereby integrating a differential voltage between the first input voltage and the second input voltage.

3. 3. The switched capacitor circuit according to claim 1, The input side switch is a first switch having a first terminal connected to the first input voltage and a second terminal connected to an input side terminal of the sampling capacitor; a second switch having a first terminal connected to the input terminal of the sampling capacitor and a second terminal connected to the first reference voltage; a third switch having a first terminal connected to the second input voltage and a second terminal connected to the input side terminal of the sampling capacitor; The output side switch is a fourth switch having a first terminal connected to a terminal of the sampling capacitor on the operational amplifier circuit side and a second terminal connected to the second reference voltage; a fifth switch having a first terminal connected to a terminal of the sampling capacitor on the operational amplifier circuit side and a second terminal connected to an inverting input terminal of the operational amplifier circuit; a first switch for switching a connection of an input terminal of the sampling capacitor to a first input voltage, a second switch for switching a connection of an input terminal of the sampling capacitor to a first reference voltage, and a second input voltage in that order;

4. 4. The switched-capacitor circuit according to claim 1, a first reference voltage and a second reference voltage are set so that a voltage at a connection point between the operational amplifier circuit side terminal of the sampling capacitor and the output side switch during a phase in which the input side switch connects the input side terminal of the sampling capacitor to the first reference voltage or the second input voltage falls within a range between ground potential and power supply voltage.

5. A first sampling capacitance; a second sampling capacitance; and An operational amplifier circuit; an input-side switch configured to selectively connect input-side terminals of the first and second sampling capacitors to one of a first input voltage, a second input voltage, and a first reference voltage for charge transfer; an output-side switch configured to selectively connect terminals of the first and second sampling capacitors on the operational amplifier circuit side to either a second reference voltage for charging or an input terminal of the operational amplifier circuit; the operational amplifier circuit is a fully differential operational amplifier circuit, The input side switch is a first switch having a first terminal connected to the first input voltage and a second terminal connected to an input side terminal of the first sampling capacitor; a second switch having a first terminal connected to the second input voltage and a second terminal connected to an input side terminal of the second sampling capacitor; a third switch having a first terminal connected to the input terminal of the first sampling capacitor and a second terminal connected to the first reference voltage; a fourth switch having a first terminal connected to the input terminal of the second sampling capacitor and a second terminal connected to the first reference voltage; a fifth switch having a first terminal connected to the second input voltage and a second terminal connected to an input side terminal of the first sampling capacitor; a sixth switch having a first terminal connected to the first input voltage and a second terminal connected to an input side terminal of the second sampling capacitor; The output side switch is a seventh switch having a first terminal connected to a terminal of the first sampling capacitor on the fully differential operational amplifier circuit side and a second terminal connected to the second reference voltage; an eighth switch having a first terminal connected to a terminal of the second sampling capacitor on the fully differential operational amplifier circuit side and a second terminal connected to the second reference voltage; a ninth switch having a first terminal connected to a terminal of the first sampling capacitor on the fully differential operational amplifier circuit side and a second terminal connected to an inverting input terminal of the fully differential operational amplifier circuit; a tenth switch having a first terminal connected to a terminal of the second sampling capacitor on the fully differential operational amplifier circuit side and a second terminal connected to a non-inverting input terminal of the fully differential operational amplifier circuit; the first, third, and fifth switches periodically switch a connection destination of an input side terminal of the first sampling capacitor in the order of the first input voltage, the first reference voltage, and the second input voltage, and the second, fourth, and sixth switches periodically switch a connection destination of an input side terminal of the second sampling capacitor in the order of the second input voltage, the first reference voltage, and the first input voltage, in synchronization with the first, third, and fifth switches; the seventh and eighth switches connect terminals of the first and second sampling capacitors on the fully differential operational amplifier circuit side to the second reference voltage in a phase in which the input-side switch connects the input-side terminal of the first sampling capacitor to the first input voltage and connects the input-side terminal of the second sampling capacitor to the second input voltage; the ninth and tenth switches connect a terminal of the first sampling capacitance on the fully differential operational amplifier circuit side to an inverting input terminal of the operational amplifier circuit and connect a terminal of the second sampling capacitance on the fully differential operational amplifier circuit side to a non-inverting input terminal of the operational amplifier circuit in a phase in which the input-side switch connects an input terminal of the first sampling capacitance to the first reference voltage or the second input voltage and connects an input terminal of the second sampling capacitance to the first reference voltage or the first input voltage.

6. 6. The switched capacitor circuit according to claim 5, a first integral capacitance having one end connected to the inverting input terminal of the fully differential operational amplifier circuit and the other end connected to the non-inverting output of the fully differential operational amplifier circuit; a second integral capacitance having one end connected to the non-inverting input terminal of the fully differential operational amplifier circuit and the other end connected to the inverting output of the fully differential operational amplifier circuit; the first, third and fifth switches periodically switch a connection of an input side terminal of the first sampling capacitor to the first input voltage, the first reference voltage and the second input voltage, in that order, and the second, fourth and sixth switches periodically switch a connection of an input side terminal of the second sampling capacitor to the second input voltage, the first reference voltage and the first input voltage, in synchronization with the first, third and fifth switches, thereby integrating a differential voltage between the first input voltage and the second input voltage.

7. 7. The switched capacitor circuit according to claim 5, the first and second reference voltages are set so that, in a phase in which the input side switch connects the input side terminal of the first sampling capacitor to the first reference voltage or the second input voltage, and connects the input side terminal of the second sampling capacitor to the first reference voltage or the first input voltage, a voltage at a connection point between the first sampling capacitor and the seventh and ninth switches and a voltage at a connection point between the second sampling capacitor and the eighth and tenth switches are within a range between ground potential and power supply voltage.

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