STAIR-LIKE STRUCTURE FOR ELECTRICALLY CONNECTING MULTIPLE HORIZONTAL CONDUCTIVE LAYERS IN A THREE-DIMENSIONAL MEMORY DEVICE - Patent application

Abstract

Efficient electrical connection of the active strips to the semiconductor layer is achieved by various methods and various stair-like structures formed from the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) on a semiconductor substrate. [Selected Figure] Figure 1a

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The present invention relates to non-volatile NOR memory strings, and more particularly to providing electrical connections to multiple conductor layers in a three-dimensional structure of a non-volatile NOR memory string. [Background technology]

[0002] Description of Related Art Provisional Patent Applications I and II and Nonprovisional Patent Applications I, II, and III disclose numerous examples of thin-film storage transistors configured in an array of NOR-type memory strings ("NOR memory strings") in a three-dimensional memory structure. The NOR memory strings and thin-film storage transistors are each formed along horizontal strips with multiple semiconductor or conductor layers that function as the source, drain, and channel regions of the thin-film storage transistors. During read, programming, and erase operations, one or more of these semiconductor or conductor layers are connected to a voltage source to achieve appropriate bias conditions or to other circuitry (e.g., a sense amplifier) ​​required for the respective operations. Summary of the Invention

[0003] According to embodiments of the present invention, various stair-like structures and methods are used to form active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) on a semiconductor substrate, providing efficient electrical connection of the active strips to a semiconductor layer.

[0004] The present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0005] [Figure 1a]FIG. 1a is a schematic diagram of a memory structure 100 including a NOR memory string to which the present invention can be applied. [Figure 1b] FIG. 1b is a schematic diagram showing the semiconductor and conductor layers of an active strip 101 of the memory structure 100 of FIG. 1a. [Figure 2i] FIG. 2i illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2ii] FIG. 2ii illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2iii] FIG. 2iii illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2iv] FIG. 2iv illustrates one method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2v] FIG. 2v illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2vi] FIG. 2vi illustrates one method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2vii] FIG. 2vii illustrates one method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2viii] FIG. 2viii illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2ix] FIG. 2ix illustrates one method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2x]FIG. 2x illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2xi] FIG. 2xi illustrates one method for forming a stair structure in the stepped portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 2xii] FIG. 2xii illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xiii] FIG. 2xiii illustrates one method for forming a stepped structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xiv] FIG. 2xiv illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xv] FIG. 2xv illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xvi] FIG. 2xvi illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xvii] FIG. 2xvii illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xviii]FIG. 2xviii illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xix] FIG. 2xix illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xx] FIG. 2xx illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xxi] FIG. 2xxi illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xxii] Figure 2xxii illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 2xxiii] Figure 2xxiii illustrates one method for forming a staircase structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers in the active layer, in accordance with one embodiment of the present invention. [Figure 3i] FIG. 3i illustrates a method for forming a stepped structure in the stepped portion 108 of the memory structure 400, with the phosphorous doped polysilicon body layer 403 shorted to the source region 523, according to one embodiment of the present invention. [Figure 3ii]FIG. 3ii illustrates a method for forming a stepped structure in the stepped portion 108 of the memory structure 400, with the phosphorous doped polysilicon body layer 403 shorted to the source region 523, according to one embodiment of the present invention. [Figure 3iii] FIG. 3iii illustrates a method for forming a stepped structure in the stepped portion 108 of the memory structure 400, with the phosphorous doped polysilicon body layer 403 shorted to the source region 523, according to one embodiment of the present invention. [Figure 3iv] FIG. 3iv illustrates a method for forming a stepped structure in stepped portion 108 of memory structure 400 with phosphorous doped polysilicon body layer 403 shorted to source region 523, according to one embodiment of the present invention. [Figure 3v] FIG. 3v illustrates a method for forming a stepped structure in stepped portion 108 of memory structure 400 with phosphorous doped polysilicon body layer 403 shorted to source region 523, according to one embodiment of the present invention. [Figure 3vi] FIG. 3vi illustrates a method for forming a stepped structure in stepped portion 108 of memory structure 400 with phosphorous doped polysilicon body layer 403 shorted to source region 523, according to one embodiment of the present invention. [Figure 3vii] FIG. 3vii illustrates a method for forming a stepped structure in the stepped portion 108 of the memory structure 400, with the phosphorous doped polysilicon body layer 403 shorted to the source region 523, according to one embodiment of the present invention. [Figure 3viii] FIG. 3viii illustrates a method for forming a stepped structure in the stepped portion 108 of the memory structure 400, with the phosphorous doped polysilicon body layer 403 shorted to the source region 523, according to one embodiment of the present invention. [Figure 3ix] FIG. 3ix illustrates a method for forming a stepped structure in stepped portion 108 of memory structure 400 with phosphorous doped polysilicon body layer 403 shorted to source region 523, according to one embodiment of the present invention. [Figure 4i]FIG. 4i shows the stepped portion 108 of the memory structure 600 after conductive polysilicon spacers 602 have been provided on the shoulders of each active layer step and substantially all of the conformally deposited conductive polysilicon layer 601 has been removed, in accordance with one embodiment of the present invention. [Figure 4ii] FIG. 4ii shows a perspective view of the staircase structure of FIG. 4i according to one embodiment of the present invention. [Figure 5-1] FIG. 5 a shows a cross-sectional view of memory structure 700 , and FIG. 5 b shows a top view of semiconductor substrate 150 underlying memory structure 700 . [Figure 5-2] FIG. 5c shows a perspective view of memory structure 700. [Figure 6i] FIG. 6i illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 6ii] FIG. 6ii illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 6iii] FIG. 6iii illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 6iv] FIG. 6iv illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 6v] FIG. 6v illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 6vi] FIG. 6vi illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 6vii] FIG. 6vii illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 6viii]FIG. 6viii illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 6ix] FIG. 6ix illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 6x] FIG. 6x illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 6xi] FIG. 6xi illustrates a manufacturing process for forming the stepped portion 108 of the memory structure 700 of FIGS. 5-1 and 5-2 described above. [Figure 7i] FIG. 7i illustrates yet another method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 7ii] FIG. 7ii illustrates yet another method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 7iii] FIG. 7iii illustrates yet another method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 7iv] FIG. 7iv illustrates yet another method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 7v] FIG. 7v illustrates yet another method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 7vi] FIG. 7vi illustrates yet another method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 7vii] FIG. 7vii illustrates yet another method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 7viii]FIG. 7viii illustrates yet another method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. [Figure 7ix] Figure 7ix illustrates yet another method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention.

[0006] To facilitate the following detailed description, like elements in the figures are designated by like reference numerals. The figures are drawn for purposes of clarity and are not drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0007] Non-provisional Patent Applications I, II, and III disclose high-density structures typified by arrays of substantially non-volatile memory cells. The memory arrays described in Non-provisional Patent Applications I, II, and III are configured as stacks of interconnected storage transistors ("active stacks") formed on a semiconductor substrate. Specifically, Non-provisional Patent Applications I, II, and III disclose multiple strips of semiconductor layer ("active strips") in each active stack, each active strip including storage transistors configured as one or more NOR-type memory strings ("NOR memory strings"). The semiconductor substrate on which the memory array is constructed may also include various types of supporting circuitry (e.g., power supply circuitry, address decoders, sense amplifiers, input / output circuitry, comparators, and control and other logic circuitry).

[0008] FIG. 1a is a schematic diagram of a memory structure 100 including a NOR memory string fabricated using a method according to the present invention. According to this, the NOR memory string consists of individually and independently addressable storage transistors sharing a common source region and a common drain region. As described in Nonprovisional Patent Applications I, II, and III, each memory string is formed along one side of an active strip having multiple layers of dielectric, semiconductor, and conductive materials. As shown in FIG. 1a, the memory structure 100 is configured as m active stacks, each having n active strips, where m and n are both any integer. For example, the value of m can be 1, 2, 4, 8, 16, 32, 64, ..., 8192, or greater. Similarly, the value of n can be 1, 2, 4, 8, 16, 32, 64, or greater than 64.

[0009] FIG. 1a shows a memory structure 100 represented as having active stacks 130-(p-1), 130-p, and 130-(p+1) as representative active stacks. Within each active stack, n active strips, labeled 101-1, 101-2, ..., 101-n, are separated from one another by insulating layers 106, electrically insulating them from one another. The insulating layers 106 are, for example, silicon nitride. The outer surfaces of each active stack are covered by a charge storage material layer 121 (e.g., an oxide-nitride-oxide ("ONO") triple layer, known to those skilled in the art). The spaces between the active stacks are filled with a number of conductor columns (not shown), separated from the active strips by the charge storage material layers 121. These conductor columns function as gate electrodes for storage transistors. In effect, during read, write, and erase operations, each conductor column functions as a "word line" for selecting and activating one of the storage transistors formed in the active strips of two adjacent active stacks. In the detailed description that follows, for brevity and ease of reference, the direction generally perpendicular to the surface of the semiconductor substrate ("vertical") will be designated z, the direction along the length of each active strip will be designated y, and the direction along the width of each active strip will be designated x. The x and y directions may also be referred to as "horizontal directions." One or more wiring layers ("global wiring layers") may be formed above and / or below memory structure 100 to interconnect terminals of storage transistors in the NOR strings of memory structure 100 with circuitry within the semiconductor substrate.

[0010] One or more portions 108 of each active stack include at least one "staircase" structure or at least one "inverted staircase" structure. The staircase and inverted staircase structures allow electrical access to the semiconductor or conductor layers (e.g., common drain regions or "bit lines") of the active strips from one of the global interconnect layers via conductor-filled vias in the case of the staircase structures or buried contacts in the case of the inverted staircase structures. In FIG. 1a, portions 108 ("staircase portions 108") are provided on the front and back sides of each active stack. Storage transistors are formed in the portions of the active stack other than the stepped portions. In FIG. 1a, array portions 109 are provided between the stepped portions 108. Thus, an inverted staircase structure is formed by successively extending the active strip in the y-direction beyond the active strip immediately below it in each stepped portion. This allows the semiconductor or conductor layers of the active strips to be connected to the circuitry of the semiconductor substrate and any global wiring layers disposed below the memory structure 100 without the risk of the buried contacts being electrically shorted to other active strips. Similarly, a staircase structure is formed by successively extending the active strip in the y-direction beyond the active strip immediately above it, at each staircase. This allows conductor-filled vias to connect the semiconductor or conductor layers of the active strips to the circuitry of the semiconductor substrate through one or more global wiring layers disposed above the memory structure 100 without the risk of the vertical conductors being electrically shorted to other active strips.

[0011] 1b is a schematic diagram showing the dielectric, semiconductor, and conductor layers of an active strip 101. As shown in FIG. 1b, the active strip 101 includes: (i) a P +(ii) semiconductor layers 103, 104 (e.g., phosphorus-doped polysilicon or arsenic-doped polysilicon) and (iii) intrinsically doped or lightly doped P-type (P - 1b includes a P-type semiconductor layer 102 (typically boron-doped). Between the dashed lines are conductors (not shown) that function as gate electrodes of the storage transistors of the NOR strings, separated from each active strip by a charge storage material layer 121. The dashed lines in FIG. 1b indicate the locations of conductors 122-(k-1), 122-k, and 122-(k+1), which are representative of such conductors. Furthermore, as shown in FIG. 1b, a conductor layer 105 (e.g., any refractory metal, such as tungsten, customarily having adhesion and barrier films) is formed on the P + The semiconductor layers 103 and 104 are adjacent to and in contact with the conductive layer 105. The conductive layer 105 reduces the resistance of the common source and drain regions of the NOR memory string. The insulating layer 106 (e.g., silicon nitride or silicon oxide) electrically isolates the active strips in the active stack from adjacent active strips.

[0012] Various fabrication methods can be used. For example, Provisional Patent Applications I, II, and III disclose various exemplary methods for forming NOR memory strings of memory structures. For example, Figures 3 to 11 and 12A to 12D of Nonprovisional Patent Application II, in conjunction with the description in the specification of those applications, illustrate a method for forming a NOR memory string extending along a direction parallel to the surface of a semiconductor substrate (e.g., the y-direction).

[0013] According to one embodiment of the present invention, a process is provided for forming a staircase structure for a memory structure including NOR memory strings on a planar surface of a semiconductor substrate that may initially have various types of support circuitry (e.g., power supply circuitry, address decoders, sense amplifiers, input / output circuitry, comparators, and control and other logic circuitry) formed in (or on) the semiconductor substrate.

[0014] An insulating layer (e.g., silicon dioxide) is formed on the planar surface. Buried contacts are formed in the insulating layer to connect to underlying circuitry. One or more global interconnect layers are then formed on the insulating layer (collectively referred to as substrate 150 in the detailed description below). A base oxide layer 107 (e.g., a 50 nm silicon dioxide layer) is then provided (see, e.g., FIG. 2i, described in the detailed description below). Active strip semiconductor and conductor layers (collectively referred to as "active layers") are then provided. Multiple active layers are then formed by stacking active layers one on top of the other, with each active layer separated by an insulating layer 106 (e.g., a 30 nm nitride layer). In one embodiment, each active layer comprises, in deposition order: (a) a sacrificial layer 105s-b ("SAC4 layer 105s-b"; e.g., a 40 nm silicon germanium layer); and (b) a P + (c) a doped polysilicon layer 104 ("drain polysilicon 104"; e.g., a 30 nm in-situ arsenic-doped polysilicon film); (d) a silicon oxide layer 102o ("sacrificial channel oxide or SAC2 layer 102o"; e.g., an 80 nm silicon oxide film) that will later be recessed to accommodate a suitable channel material; and (e.g., a P + The polysilicon layer 103 ("source polysilicon 103"; e.g., a 30 nm in-situ arsenic-doped polysilicon film) and (e) sacrificial layers 105s-t ("SAC4 layers 105s-t"; e.g., 40 nm silicon germanium layers). The SAC4 layers 105s-b and 105s-t are sacrificial layers that will be replaced with metal conductor layers later, as described below.

[0015] During active layer deposition, stair structures are formed in the stepped portions to electrically access the drain polysilicon 104 of each active strip. This detailed description will focus on the stair structures for electrically contacting the drain polysilicon 104 and the source polysilicon 103. It will be understood that these stair structures are provided in the stepped portions of the memory structure (e.g., stair portion 108 in FIG. 1a). Unless otherwise noted, it will be understood that FIGS. 2i-2xxiii, 3i-3ix, 4i-4ii, 5-1 and 5-2, and 6i-6xi herein each illustrate a portion of the stair portion 108. Storage transistors are formed in the memory array in the array portion 109 of the memory structure. For clarity, the array portion 109 (the structure and fabrication of which are described in detail, for example, in Nonprovisional Patent Application No. III) is not shown in the figures. The array region 109 is protected from the stair-forming step by applying appropriate masking to the array region 109. According to one embodiment of the present invention, the stair-like structure is formed using one photolithography step for every two active layers. Figures 2i-2xi illustrate the formation of the stair-like structure in the stair-like portion 108 of the memory structure 100 according to the above embodiment of the present invention.

[0016] FIG. 2i shows memory structure 100 after active layers 101-1 and 101-2 have been deposited. A photoresist layer 201 is then deposited and patterned over memory structure 100. A first etching step removes (a) insulating layer 106 and (b) active layer 101-2 (i.e., SAC4 layer 105s-t, source polysilicon 103, SAC2 layer 102o, drain polysilicon 104, and SAC4 layer 105s-b of active layer 101-2) from exposed areas not protected by photoresist layer 201. This first etching step stops on insulating layer 106 directly above active layer 101-1. The resulting structure is shown in FIG. 2ii.

[0017] The photoresist layer 201 is then recessed by slimming it by a predetermined amount (indicated by the arrows) as known to those skilled in the art, further exposing the active strip 101-2. The resulting structure is shown in FIG. 2iii. A second etching step then removes the exposed portions of the insulating layer 106 directly above the active layer 101-1 and the insulating layer 106 directly above the active layer 101-2, followed by further etching (a) the SAC4 layers 105s-t of each of the active layers 101-1 and 101-2, and (b) the source polysilicon 103 of each of the active layers 101-1 and 101-2. This second etching step stops at the SAC2 layer 102o of each of the active layers 101-1 and 101-2. The resulting structure (a two-step staircase structure) is shown in FIG. 2iv. The photoresist layer 201 is then removed.

[0018] Next, silicon oxide 202 is applied to fill the cavities formed by the first and second etching steps, and the resulting surface is then planarized by a planarization step (e.g., chemical mechanical polishing (CMP)). The resulting structure is shown in FIG. 2v. Vias are then formed in the silicon oxide 202 and the underlying sacrificial SAC2 layer 102o of each of the active layers 101-1, 101-2 (not shown in FIG. 2v) to provide access to the drain polysilicon 104 of each of the active layers 101-1, 101-2. These vias may be created by a subsequent oxide etch after all the active layers have been formed, as described below.

[0019] Figures 2vi-2x show how the stepped portion 108 of memory structure 100 extends into two more active layers. Figure 2vi shows the stepped portion 108 of memory structure 100 after active layers 101-3 and 101-4 have been deposited. A photoresist layer 201 is then deposited, and active layer 101-4 is etched in the same manner as active layer 101-2, as shown in Figure 2ii. The resulting structure of active layer 101-4 is shown in Figure 2vii.

[0020] Next, the photoresist layer 201 is recessed, and the exposed areas of the active layers 101-3 and 101-4 below the recessed photomask are subjected to a second etch. Unlike the etch of the active layer 101-1 shown in FIG. 2iv, the etch of the active layer 101-3 does not stop at the SAC2 layer 102o of each of the active layers 101-3 and 101-4. This also removes the exposed portions of the drain polysilicon 104 and SAC4 layer 105s-b of the active layers 101-3 and 101-4. The resulting structure is shown in FIG. 2vii. The exposed portions of the drain polysilicon 104 and SAC4 layer 105s-b of each of the active layers 101-3 and 101-4 are removed, allowing the via to extend from above the active layers 101-3 and 101-4 to the drain polysilicon layer 103 of the active layers 101-1 and 101-2 (it is not necessary to remove portions of these layers, as the via is not expected to pass through the space occupied by the drain polysilicon layer 103 and SAC4 layer 105s-b of the active layer 101-1).

[0021] The photoresist layer 201 is then recessed again to remove the exposed portions of the insulating layer 106 located directly above each of the active layers 101-4, 101-3, and 101-2, i.e., (a) the SAC4 layers 105s-t of each of the active layers 101-4, 101-3, and 101-2, and (b) the source polysilicon 103 of each of the active layers 101-4, 101-3, and 101-2, to expose the drain polysilicon 104 of each of the active layers 101-4, 101-3, and 101-2. The resulting structure is shown in Figure 2ix.

[0022] The photoresist layer 201 is then removed. Silicon oxide 202 is then applied to fill the cavities formed by the etching steps of Figures 2vii-2ix, after which the resulting surface is planarized by a planarization step (e.g., CMP). The resulting structure is shown in Figure 2x.

[0023] The steps described above with reference to Figures 2vi to 2x can be repeated for each deposition of two active layers. Note that the staircase formation step described with reference to Figures 2i to 2x requires one photolithography ("photomasking") step for each deposition of two active layers, whereas conventional staircase formation steps require one or more photolithography steps for each deposition of each active layer. Therefore, in this respect, the staircase formation step of the present invention is advantageous over conventional staircase formation steps.

[0024] After all active layers of memory structure 100 have been deposited and the cavities in the last two active layers formed by the final first and second etching steps have been filled, an oxide etch is performed for a time appropriate to form vias down to the drain polysilicon layer 104 of each active layer. The resulting structure is shown in Figure 2xi, which shows four active layers 101-1, 101-2, 101-3, and 101-4 for illustrative purposes only. In Figure 2xi, vias 203-1, 203-2, 203-3, and 203-4 may be formed to provide access to any semiconductor or conductive material layer of each active layer present.

[0025] In some embodiments, after the planarization step that creates the memory structure 100 of FIG. 2xi, the stepped portion 108 is protected by a mask during a substantial portion of the remaining processing in the array portion 109, except for the trench etch step to form the active stack, the oxide etch step that creates the memory structure 100 of FIG. 2xi, and the replacement of the SAC4 layers 105s-b, 105s-t with metal or other conductors. An example of a fabrication process, including the remaining processing steps, is disclosed, for example, in Provisional Patent Application No. 10-144444. Those skilled in the art will appreciate that the present invention is applicable to any structure having any desired number of active layers and vias. These vias, when filled with a conductive material (e.g., a barrier material and any refractory metal, such as tungsten or other conductive material), electrically connect the drain polysilicon 104 to circuitry within the semiconductor substrate 150 via conductors in one or more global wiring layers formed over the memory structure 100.

[0026] According to various embodiments, each active layer comprises one or more P-type semiconductor layers (e.g., 5.0×10 ohms) including a P-type body layer for supplying charge carriers to a charge carrier-depleted channel region during an erase operation. 18 ~5.0×10 21 cm -3 P with a dopant concentration of + Polysilicon layer or P++ In such embodiments, the P-type body layer preferably is electrically connected to a bias voltage source. In some embodiments, the P-type body layer is shorted to the source polysilicon layer 103. Figures 2xii-2xxiii illustrate one method for forming a stepped structure in the stepped portion 108 of the memory structure 160 that allows connection to both the source and drain polysilicon layers of the active layer, in accordance with one embodiment of the present invention.

[0027] 2xii shows the memory structure 160 after the active layers 101-1 and 101-2 have been deposited. In FIG. 2xii, the active layers 101-1 and 101-2 each include (a) a sacrificial layer 105s-b (“SAC4 layer 105s-b”; e.g., a silicon germanium layer) and (b) a P + (c) a doped polysilicon layer 104 (drain layer); (d) a silicon oxide layer 102a ("sacrificial channel oxide or SAC2 layer 102a"; e.g., a 30 nm silicon oxide film); and (e) a P-type body region 403 (e.g., a 20 nm P + doped polysilicon layer), (e) silicon oxide layer 102b (“sacrificial channel oxide or SAC2 layer 102b”; e.g., a 30 nm silicon oxide film), and (f) P + The SAC4 layers 105s-b and 105s-t are sacrificial layers that will later be replaced with metal conductor layers, as described below. The SAC2 layers 102a and 102b are each later recessed to receive the channel material (e.g., lightly doped P-type polysilicon) that will be deposited. - The channel region is P + Body region 403 (this region is generally - more doped than the channel region) and P + It is shared by the body region 403. + The body region 403 transports charge carriers (“holes”) to the P -By supplying the Pt to the channel region, the erase operation becomes more efficient. + Body region 403 and P - Between the channel region and the gate electrode, an ultra-thin dielectric layer (as thin as a monolayer of several dielectric materials, but typically less than 2-3 nm thick) is deposited or thermally grown. This optional ultra-thin dielectric layer is used to prevent the P + Body area 403 to P - While suppressing boron autodoping into the channel, when an appropriate high voltage is applied during the erase operation, + The abundant holes in the body region 403 are transferred to the relatively depleted P - The channel can be supplied (eg, by tunneling).

[0028] Next, a photoresist layer is deposited and patterned on the memory structure 160, followed by the steps described above with reference to Figures 2i-2iv (where, of course, SAC2 layer 102a, P-type body layer 403, and SAC2 layer 102b are removed during the steps described above with reference to Figures 2i-2iv in which SAC2 layer 102o is removed). The resulting structure is shown in Figure 2xiii after the photoresist layer has been removed. A photoresist layer 210 is then applied to cover the surface of memory structure 160 and fill the cavities formed by the etching steps of Figures 2i-2iv. The photoresist layer 210 is then patterned to expose areas of stepped portions 108 on the surface of memory structure 160. An anisotropic etch is then performed to remove the exposed areas of insulating layer 106 on active layer 101-2 and the layers of material of active layer 101-2. The resulting structure is shown in Figure 2xiv. Next, after the photoresist layer 210 is removed, silicon oxide 202 is deposited over the memory structure 160 to fill the cavities formed by the etching step described above, and then planarized, resulting in the structure shown in Figure 2xv.

[0029] The next two active layers, active layers 101-3 and 101-4, are then deposited on memory structure 160. The steps described above with reference to Figures 2vi-2ix are then performed to form stepped portions for electrically connecting the drain polysilicon 103 of active layers 101-3 and 101-4. (Obviously, SAC2 layer 102a, P-type body layer 403, and SAC2 layer 102b are removed during the steps described above with reference to Figures 2vi-2ix in which SAC2 layer 102o is removed.) The resulting structure is shown in Figure 2xvi.

[0030] Next, a photoresist layer 211 is applied over the memory structure 160, filling the cavities formed by the etching steps of Figures 2i-2iv and then patterning. The resulting structure is shown in Figure 2xvii. An isotropic etch is then performed to remove the exposed areas of the insulating layer 106 over the active layers 101-4 and the material layers of the active layers 101-4. The resulting structure is shown in Figure 2xix. Next, the photoresist layer 211 is recessed as shown in Figure 2xx. Then, an isotropic etch is performed to remove the exposed areas of the insulating layer 106 and the material layers of the active layers 101-3 and 101-4. This leaves a structure with two exposed steps as shown in Figure 2xx. Next, the photoresist layer 211 is removed. The resulting structure is shown in Figure 2xxi.

[0031] Silicon oxide 202 is then used to fill the cavities created by the etching step described above and then planarized, resulting in the structure shown in Figure 2xxii.

[0032] The steps described above with reference to Figures 2xvi to 2xxii may be repeated for each deposition of two active layers.

[0033] After all active layers of memory structure 160 have been formed and the cavities in the last two active layers formed by the final first and second etch steps have been filled, a first oxide etch is performed for a time appropriate to form vias down to the drain polysilicon layer 104 of each active layer. A second oxide etch is then performed to form vias down to the P-type body layer 403. The resulting structure is shown in Figure 2xxiii. The first and second oxide etches are each configured to stop at different layers (e.g., the first oxide etch may be configured to stop at the P-type body layer 403, as known to those skilled in the art). + The first oxide etch is set to stop on the doped drain polysilicon 104 and the second oxide etch is set to stop on the source metal strip layer 105t).

[0034] In Figure 2xxiii, for illustrative purposes only, four active layers 101-1, 101-2, 101-3, and 101-4 are shown. In Figure 2xxiii, vias 203-1, 203-2, 203-3, and 203-4 are formed to access the drain polysilicon 104 of each active layer, and vias 204-1, 204-2, 204-3, and 204-4 are formed to reach the P-type body layer 403. Vias 204-1, 204-2, 204-3, and 204-4 also extend through the source polysilicon 103, respectively, along the way to the P-type body layer 403. This allows the source polysilicon 103 and the P-type body layer 403 to be shorted together when the vias are filled with conductive cores.

[0035] Alternatively, in another embodiment, the process steps shown in Figures 3i-3ix are used to create a stepped structure that contacts the P-type body layer. For example, Figure 3i shows that in stepped portion 108, a phosphorus-doped polysilicon body layer 403 is included in each active layer.

[0036] 7i-7ix illustrate yet another method for forming a staircase structure in the staircase portion 108 of the memory structure 100, according to one embodiment of the present invention. FIG. 7i illustrates the memory structure 800 after the active layers 101-1, 101-2, 101-3, and 101-4 have been deposited. In FIG. 7i, the active layers 101-1, 101-2, 101-3, and 101-4 each include (a) a sacrificial layer 105s-b ("SAC4 layer 105s-b"; e.g., a silicon germanium layer) and (b) a P + (c) a doped polysilicon layer 104 (drain layer); (d) a silicon oxide layer 102 ("SAC2 layer 102", a 30 nm silicon oxide film); and (e) a P + The memory structure 800 includes a polysilicon layer 103 (source layer), and (e) sacrificial layers 105s-t ("SAC4 layers 105s-t", e.g., silicon germanium layers). The SAC4 layers 105s-b, 105s-t are each sacrificial layers that will later be replaced with metal conductor layers, as described below. The SAC2 layer 102 is later recessed to receive the channel material (e.g., lightly doped P-type polysilicon) that will be deposited. The active layers 101-1, 101-2, 101-3, and 101-4 are each separated from one another by an insulating layer 106. FIG. 7 shows a cross-sectional view of a memory structure 800 along the length of an active stack that will be formed to have four active strips. The ends of the active stack, designated by reference numerals 801 and 802, are connected to the conductor layers (e.g., P + Polysilicon layer 103 and P + 7i-7ix are not drawn to scale. The portion of memory structure 800 between portions 801 and 802 that is provided for the formation of memory cells is shown schematically as portion 803. In practice, portion 803 would accommodate a large number of memory cells (e.g., 8196 or more).

[0037] As shown in Figure 7i, a photoresist layer 806 is deposited and patterned on the memory structure 800. The exposed portions of the active layers 101-4 are removed using this patterned photoresist layer 806. That is, the insulating layer 106, the SAC4 layers 105s-t, and the P + Polysilicon layer 103, SAC2 layer 102, P + Selective etching is then performed on the polysilicon layer 104 and the SAC4 layers 105s-b in succession. The resulting structure is shown in Figure 7ii. The photoresist layer 806 is then recessed to further expose the underlying portions of the memory structure 800, as shown in Figure 7iii. The exposed portions of the active layers 101-3, 101-4 are then removed. That is, the insulating layer 106, the SAC4 layers 105s-t, and the P + Polysilicon layer 103, SAC2 layer 102, P + Selective etching is then performed sequentially on polysilicon layer 104 and SAC4 layer 105s-b. The resulting structure is shown in FIG. 7iv. The recessing and active layer etching steps shown in FIGS. 7iii-7iv are then repeated to remove exposed portions of active layers 101-2, 101-3, and 101-4. Photoresist layer 806 is then replaced with a new photoresist layer 807 that fills the cavity created by the removal of the active layers. Photoresist layer 807 is then patterned, as shown in FIG. 7v. Note that portion 801 of memory structure 800 is protected from the patterning of photoresist layer 807 (i.e., this portion is reserved for electrical connection to the source layer).

[0038] Then, selective etching is performed successively to remove the insulating layer 106, the SAC4 layer 105s-b, and the P +The exposed portions of polysilicon layer 103 are removed, thereby exposing SAC2 layer 102. The resulting structure is shown in Figure 7vi. Photoresist layer 807 is then removed, after which an oxide layer 808 (e.g., SiO2) is deposited over memory structure 800 and planarized by CMP, as shown in Figure 7vii.

[0039] At this time, active layers 101-1, 101-2, 101-3, and 101-4 are etched to form a stack of active strips. In addition, SAC2 layer 102 is recessed to accommodate a channel material (e.g., lightly doped polysilicon or single crystal silicon) that will be deposited into the resulting cavities extending along the opposite side of each active strip. See, for example, Nonprovisional Patent Application No. III for appropriate steps regarding etching the active layers to form active steps, recessing the SAC2 layer of each active strip, and providing a channel material that fills the resulting cavities from the recessed SAC2 layer.

[0040] Bit line contacts are then photolithographically defined and anisotropic oxide etching is performed to remove the P + Open vias to make electrical contact to polysilicon layer 104 (this anisotropic oxide etch removes the underlying P + (The remaining SAC2 layer 102 is also etched to expose the polysilicon layer 104.) As shown in FIG. 7viii, the via openings are filled with a conductive material (e.g., tungsten, tantalum, or other refractory metal with suitable barrier and adhesion films). Figure 7viii shows representative via openings 810a, 810b, 810c, and 810d filled with tungsten. Figure 7viii also shows that the cross section cuts through corresponding channel material 809a, 809b, 809c, and 809d in the recesses of the SAC2 layer 102 of active layers 101-4, 101-3, 101-2, and 101-1, respectively, at portion 801 (i.e., the source line contact portion).

[0041] Thereafter, the source line contacts are photolithographically defined and anisotropic etching is performed sequentially to remove the oxide layer 808, the insulating layer 106, the SAC4 layers 105s-t, and the P + Via openings for the source lines are cut through the polysilicon layer 103, thereby exposing the channel materials 809a, 809b, 809c, and 809d. To ensure that good contacts are made to the channel materials 809a, 809b, 809c, and 809d, an ion implantation step may be performed to introduce dopant species (e.g., P-type dopant species such as boron) at the contact points of the channel materials 809a, 809b, 809c, and 809d. The via openings are then filled with a conductive material (e.g., tungsten with suitable barrier and adhesion films), as shown in FIG. 7ix. Representative via openings 811a, 811b, 811c, and 811d are shown filled with tungsten. In this way, the P-type dopant species of each active layer are formed. + The polysilicon layer 103 and the channel material are electrically shorted together, thereby providing a bias voltage to the substrate that, if desired, will be provided to the channel materials 809a, 809b, 809c, and 809d, while the stepped structure of portions 801 and 802 provides electrical connection to the common source and drain electrodes of each active strip formed from active layers 101-1, 101-2, 101-3, and 101-4.

[0042] As mentioned above, in another embodiment, a stepped structure contacting a P-type body layer is formed using the process steps illustrated in Figures 3i-3ix. Figure 3i illustrates the stepped portion 108 of a memory structure 400 having multiple active layers separated from one another by an interlevel dielectric layer 503. In Figure 3i, to simplify the detailed description, only the active layer 300 formed on the memory structure 400 is illustrated. It is understood that each active layer of the memory structure 400 is processed as described below in conjunction with Figures 3i-3ix. As illustrated in Figure 3i, the active layer 300 includes (a) a first sacrificial layer (SAC4 layer) 524b, which will later be replaced with a metal or conductor layer; (b) a P + Common drain region 521 and P + (c) oxide layers 522a, 522b; (d) phosphorus-doped polysilicon body layer 403; and (e) a thin sacrificial oxide layer 571. In this embodiment, P + The common drain region 521 is connected to the semiconductor substrate 150 (not shown) using a buried contact through a metal plug in a via etched in the interlayer dielectric layer 503 (see below in conjunction with Figures 3viii-3ix).

[0043] As shown in Figure 3ii, a thin sacrificial oxide layer 571 is deposited, and then patterned and etched to form a step. +After the common source region 523, the oxide layer 522a, and the phosphorus-doped polysilicon body layer 403 are removed, the process stops on the surface of the oxide layer 522b. Next, a thin conductive polysilicon layer 551 is conformally deposited on the exposed surface of the memory structure 400 (FIG. 3iii). Then, as shown in FIG. 3iv, the conductive polysilicon layer 551 is anisotropically etched so that the conductive polysilicon layer 551 remains only on the sidewalls of the step of FIG. 3iii. Next, a nickel or nickel alloy metal layer 552 is deposited on the step (FIG. 3v). Then, a salicidation step is performed at a temperature of 600° C. or less to salicide the conductive polysilicon layer 551 (i.e., nickel silicide shunt 553) remaining on the sidewalls of the step (FIG. 3vi). This causes the phosphorus-doped polysilicon body layer 403 and N + The common source region 523 is electrically shorted to each other. Next, the remainder of the nickel or nickel alloy metal layer 552 is removed by isotropic etching. Good (FIG. 3vii). An interlevel dielectric layer 503 is then deposited in preparation for the deposition of the next active layer (FIG. 3viii). Next, as shown in FIG. 3ix, a dielectric layer 513 (e.g., oxide) is deposited and then planarized. Vias are then formed by etching through the interlevel dielectric layer 503 and the dielectric layer 513 to reach the reserved buried contacts below the interlevel dielectric layer 503. Next, a sacrificial layer 524a of the next active layer (which will later be replaced by a metal conductor) is deposited using conventional methods. The vias through the interlevel dielectric layer 503 and the dielectric layer 513 are then filled with a metal or conductor, thereby forming sacrificial layers 524b and P of the next active layer. + The metal (eg, any refractory metal such as tungsten) or conductor that replaces the common drain region 521 will be connected.

[0044] In some embodiments, after planarizing the dielectric layer 513 filling the step-down of the last active layer, the stepped portion 108 is protected by a mask during a substantial portion of the remaining processing in the array portion 109, except for the "NIN" trench etch step that forms the active stack and replaces the sacrificial layers 524a, 524b with metal or other conductors. An example of a fabrication process, including the remaining processing steps, is disclosed, for example, in Provisional Patent Application No. 10-144444. Those skilled in the art will appreciate that the present invention is applicable to any structure having any desired number of active layers and vias.

[0045] According to another embodiment of the present invention, P + An alternative method for connecting the common source region to the phosphorus-doped polysilicon body region is provided. Figure 4i shows the stepped portion 108 of the memory structure 600, in which each active layer in the memory structure 600 includes (a) a sacrificial layer (SAC4 layer) 524a, 524b that will later be replaced with a metal or conductor layer; (b) a P + Common source layer 523 and P + 4i shows adjacent active layers separated from one another by an interlayer dielectric layer (ILD) 503. For purposes of illustration, only two steps formed by two active layers are shown in FIG. 4i. Those skilled in the art will appreciate that any suitable number of active layers may be processed using the fabrication process described herein. Similar to the fabrication process described above with reference to FIGS. 3i-3ix, the stepped structure of memory structure 600 in FIG. 4i is achieved by eliminating a step in the processing of each deposited active layer. Each active layer is patterned in a photomask step, followed by the SAC4 layer 524a, P + The common source region 523, the phosphorus-doped body region 522, and the P +An etching step is performed to selectively remove the exposed portion of the common drain region 521, thereby eliminating the step of exposing the sacrificial layer 524b. Then, a conductive conformal polysilicon film 601 (e.g., having a thickness of 40 nm) is deposited on the step. The polysilicon film 601 has a boron dopant concentration of 1.0×10 19 ~5.0×10 19 cm -3 Thereafter, an anisotropic spacer etch is performed to remove substantially all of the conductive polysilicon film 601 except for the spacers remaining on the sidewalls of each step. The remaining spacers in the conductive polysilicon film 601 are further etched (e.g., a timed etch) to remove the P + A conductive polysilicon spacer 602 is provided, which functions as an ohmic contact to short-circuit the common drain region 521 to the phosphorus-doped body region 522. The thickness of the conductive polysilicon spacer 602 is, for example, 40 to 50 nm. In this way, the phosphorus-doped body region 522 is electrically connected to the P + A body bias voltage is provided by the bit line represented by the common drain region 521. An oxide 630 is then applied to fill the step formed in the active layer.

[0046] In a subsequent step, after all the active layers have been processed, vias (represented by the numeral 631 in FIG. 4i) may be created and then filled to form conductive plugs connecting the metallic or conductive material that replaces SAC4 layer 524b. The conductive plugs in these vias 631 allow circuitry in semiconductor substrate 150 to be connected to the semiconductor or conductive layers of the active strips through a global wiring layer formed over memory structure 600.

[0047] FIG. 4i shows the conductive polysilicon spacers 602 after substantially all of the conductive polysilicon 601 has been removed.

[0048] FIG. 4ii shows a perspective view of the stepped portion 108 of the memory structure 600 of FIG. 4i, according to one embodiment of the present invention.

[0049] As discussed above, the method for forming the staircase structure associated with Figures 2i-2vi requires at least one photomasking step for every two active layers, and the method for forming the staircase structure associated with Figures 3i-3ix requires at least one photomasking step for every active layer. In contrast, forming an inverted staircase structure using any of the methods disclosed in Nonprovisional Patent Application No. III requires at least two photomasking steps for every active layer. According to the following embodiment of the present invention, conductor columns used as word lines for array portion 109 are formed in staircase portion 108 in a manner similar to that described above, and these conductor columns are used as conductors to connect conductive layers in the active strips to circuitry in semiconductor substrate 150.

[0050] According to one embodiment of the present invention, FIG. 5a (FIG. 5-1) is a simplified cross-sectional view of a memory structure 700, FIG. 5b (FIG. 5-1) is a top view of a semiconductor substrate 150 provided under the memory structure 700, and FIG. 5c (FIG. 5-2) is a perspective view of the memory structure 700 (showing a portion of the stepped portion 108 and the array portion 109). In FIG. 5a (FIG. 5-1), the memory structure 700 is shown with P + The active strips are represented by common drain regions 724-1, 724-2, 724-3, and 724-4. To simplify the detailed description herein, other conductive and non-conductive layers are not shown. Although only four active strips are shown in FIG. 5a (FIG. 5-1), it is understood that any suitable number of active strips may be provided. The guidance and teachings herein may also apply to other conductive layers in each active strip.

[0051] As shown schematically in FIG. 5a (FIG. 5-1), the memory structure 700 includes an array region 109 located between a stepped region 108L at one end of the memory structure 700 and a stepped region 108R at the other end of the memory structure 700. In the array region 109, conductor columns 711 function as gate electrodes or word lines for thin-film storage transistors formed along the active strips, with each conductor column connected to conductors in either a global wiring layer 712A above the memory structure 700 or a global wiring layer 712B below the memory structure 150. FIG. 5b (FIG. 5-1) also shows how signals from the conductor columns in the array region 109 are routed to various circuits in the semiconductor substrate 150 by conductors in the global wiring layer 712A and the global wiring layer 712B. Furthermore, FIG. 5a (FIG. 5-1) shows that in each of the stepped regions 108L and 108R, P + The conductor column 711 is used to connect the common drain regions 724-1, 724-2, 724-3, and 724-4 to the circuitry within the semiconductor substrate 150. Specifically, the stepped structure of the stepped portions 108L and 108R allows the P + A conductive plug (e.g., any of the conductive plugs 725 shown in FIG. 5c (FIG. 5-2)) in a via above each of the common drain regions 724-1, 724-2, 724-3, 724-4 can be connected to one of the conductive columns 711 through a section of conductor in the global wiring layer 712A. Each conductor column is connected to a corresponding one of the bit line segments 743L, 743R, which are selectively connected to sense amplifiers and voltage sources in the semiconductor substrate 150. In this manner, the conductive layer in the active strip is connected to the circuitry in the semiconductor substrate 150, thereby enabling the use of a similar photomasking step corresponding to the step of connecting the conductor columns 711 to the global wiring layer 712A. In FIGS. 5a (FIG. 5-1) and 5b (FIG. 5-1), P + The common drain regions 724-1, 724-3 are connected to a bit line segment 743L in a stepped portion 108L located at one end of the memory structure 700, while P +Common drain regions 724-2, 724-4 are connected to bit line segment 743R in stepped portion 108R at the other end of memory structure 700.

[0052] 6i-6xi are schematic diagrams illustrating a manufacturing process for forming the memory structure 700 described above with reference to FIGS. 5-1 and 5-2.

[0053] First, as shown in FIG. 6i, active layers 101-1, 101-2, 101-3 of memory structure 700 are provided on conductors 712B of the global interconnect layer on semiconductor substrate 150 using any suitable deposition steps. As shown in FIG. 6i, for each active layer, only sacrificial (SAC4) layers 524a, 524b and semiconductor layer 528 are shown (SAC4 layers 524a, 524b may each be a sacrificial nitride layer, a sacrificial oxide layer, or a sacrificial layer having other materials that will be replaced with a metal layer or a conductor layer in a subsequent step). Those skilled in the art will recognize that semiconductor layer 528 (e.g., a polysilicon layer) is a P + A common drain region 521, a channel region 522, and a P + It will be appreciated that the active layer 109 includes a common source region 523 (which is not shown separately in Figures 6i-6xi to simplify the detailed description herein). Also, although only three active layers are shown in Figures 6i-6xi, those skilled in the art will appreciate that any suitable number of active layers may be provided. In Figure 6i, adjacent active layers are separated from each other by an insulating layer 503. Also, Figure 6i shows only a portion of the array portion 109 and the stepped portion 108R.

[0054] The active layers 101-1, 101-2, and 101-3 are then patterned and etched to form a staircase structure, as shown in FIG. 6ii. Next, an oxide 731 (e.g., silicon oxide) is deposited on the staircase structure and then planarized. The resulting memory structure 700 is shown in FIG. 6iii. A hard mask 751 may then be applied. The hard mask 751 provides structural integrity to the memory structure 700 during the subsequent high-aspect-ratio etch (trench etch or "NIN" etch) to create the active stacks. The resulting memory structure 700, showing active stacks 732a, 732b, 732c, and 732d, is shown in FIG. 6iv. In FIG. 6iv, the lengths of the active stacks 732b and 732d in the x-direction may be longer. This results in narrower active strips in the array section 109, but larger, lower-resistance conductive plugs for the vias in the staircase section 108R. Similarly, it will be understood that the lengths of the active stacks 732a and 732c in the x direction may be increased on the stepped portion 108L side.

[0055] The hard mask 731 is then removed. A NIN etch is performed to expose the SAC4 layers 524a and 524b at the sidewalls of the active stacks 732a, 732b, 732c, and 732d. The SAC4 layers 524a and 524b are then etched away and replaced with metal or other conductors. Details of this metal or other conductor replacement are disclosed, for example, in Non-Provisional Patent Application I, which further discloses means for providing support structures to ensure structural integrity within the active stacks when the SAC4 layers 524a and 524b are completely removed. The resulting memory structure 700 is shown in FIG. 6v.

[0056] Next, a charge trapping or storage material 733 (e.g., an oxide-nitride-oxide trilayer) is conformally deposited over the memory structure 700 and then planarized. The resulting memory structure 700 is shown in Figure 6vi. Next, P + Polysilicon 735 (e.g., 5.0 × 10 19 ~1.0×10 21 cm -3 A silicon dioxide (having a dopant concentration in the range of 0.1 to 1.5) or other conductive or metallic material is deposited to fill the trenches between the active strips and then planarized. The resulting memory structure 700 is shown in Figure 6vii.

[0057] Then, as shown in Figure 6viii, P + Polysilicon or other conductive material 735 is patterned and etched to form conductor columns 735W, which function as local word lines in array portion 109, and conductor columns 735C in stepped portion 108. This etching step forms trenches between adjacent conductor columns 735W or 735C. These trenches are then filled with oxide 736 to electrically isolate the conductor columns from each other. The resulting memory structure 700 is shown in FIG. 6ix. Vias are then formed using an oxide etch that stops on metal layer 524a, which is then filled with conductors.

[0058] Figure 6x shows filled vias 737a, 737b, 737c, 737d, 737e, and 737f in the stepped structure of active stacks 732b and 732d in stepped portion 108R. As shown in Figure 6xi, each filled via 737a is connected to one of the adjacent conductor columns 735C via conductors in global wiring layer 712A, which in turn are connected to conductors in global wiring layer 712B, for routing signals to circuitry in semiconductor substrate 150 or to corresponding bit line segments (not shown).

[0059] Alternatively, as described above with reference to Figures 6vi to 6viii, P + Rather than depositing, patterning, and etching polysilicon 735 to provide local word lines 735W in the array portion 109, a damascene-type process, as described in detail in Provisional Patent Application IV, may instead be used to form local word lines 735W in the array portion 109 by depositing a conductive material into via-like cavities formed in a dielectric material (e.g., charge trapping or charge storage material 733). This configuration provides via-like cavities that are subsequently filled with a conductive material to form conductor columns 735C in the stepped portion 108 of the memory structure 700. The via-like cavities remain unfilled when the local word lines 735W are formed in the array portion 109 of the memory structure 700. These unfilled via-like cavities are then filled with the same material (e.g., tungsten) as used to fill the vias 737a, 737b, 737c, 737d, 737e, and 737f at the same time. + If the local word line 735W is formed using a polysilicon material, the conductor column 735C may be formed using a material with a lower resistivity. Even in the damascene process described above, it is possible to choose to form both the local word line 735W and the conductor column 735C using a conductor with a low resistivity (e.g., tungsten). In this case, the local word line 735W and the conductor column 735C are formed simultaneously.

[0060] The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to limit the present invention. Various modifications and variations are possible within the scope of the present invention. The gist of the present invention is set forth in the appended claims.

Claims

1. 1. A memory structure formed on a planar surface of a semiconductor substrate having a plurality of circuit elements formed thereon, comprising: (i) a stepped structure formed on the flat surface, the stepped structure including a plurality of active strips arranged overlapping each other along a first direction generally perpendicular to the flat surface, each of the active strips extends in a second direction substantially parallel to the flat surface and constitutes one step in the staircase structure; and (1) a first semiconductor layer having a first conductivity type; (2) a second semiconductor layer having the first conductivity type provided under the first semiconductor layer; and (3) A stepped structure including a first dielectric layer having an insulating material between the first semiconductor layer and the second semiconductor layer, the first dielectric layer having a third semiconductor layer having a second conductivity type embedded therein, the third semiconductor layer being adjacent to both the first semiconductor layer and the second semiconductor layer; (ii) a second dielectric layer disposed adjacent to the stepped structure; and (iii) a first plurality of wiring conductors each extending along a third direction that is generally parallel to the planar surface and generally perpendicular to the second direction; (iv) a plurality of conductor columns, each extending along the first direction, electrically connected to a corresponding circuit element in the semiconductor substrate via one of the first plurality of wiring conductors, adjacent to the plurality of active strips but electrically isolated from each active strip by the second dielectric layer; (v) a third dielectric layer disposed on the stepped structure and having embedded therein a plurality of vias including a conductive material electrically connecting one of the first plurality of wiring conductors to one of the first and second semiconductor layers of one active strip at a step corresponding to an active step.

2. 2. The memory structure of claim 1, a second plurality of wiring conductors formed between the semiconductor substrate and the stepped structure and extending along the third direction; The memory structure, wherein said second plurality of wiring conductors each electrically connect one of said conductor columns to a corresponding one of said circuit elements.

3. 2. The memory structure of claim 1, further comprising a plurality of conductive segments formed between the stepped structure and the semiconductor substrate; A memory structure in which each of said conductor columns electrically connects to a corresponding one of said circuit elements via one of said conductive segments.

4. 4. A memory structure as claimed in claim 3, comprising: A memory structure in which each of the conductive segments electrically connects to the second semiconductor layer of the active strip.

5. 2. The memory structure of claim 1, A memory structure wherein each of said conductor columns comprises polysilicon.

6. 2. The memory structure of claim 1, A memory structure in which each of the active strips includes one or more NOR type memory strings.

7. 7. A memory structure as claimed in claim 6, comprising: The stepped structure is provided at one end of the active strip, A memory structure in which the NOR memory strings form a memory array of storage transistors in portions of the active strips remote from the staircase structure.

8. 2. The memory structure of claim 1, A memory structure wherein the conductive material comprises a refractory metal.

9. 9. A memory structure as claimed in claim 8, comprising: A memory structure wherein said refractory metal comprises tungsten.

10. 2. The memory structure of claim 1, Each of the active strips is a first conductor layer adjacent to the first semiconductor layer and having a lower electrical resistivity than the first semiconductor layer; a second conductor layer adjacent to the second semiconductor layer and having a lower electrical resistivity than the second semiconductor layer.

11. 2. The memory structure of claim 1, A memory structure in which the third semiconductor layer forms one or more channel regions of one or more thin film transistors.

12. A structure provided on a semiconductor substrate, a memory array region and a plurality of active layers forming stepped regions on both sides of the memory array region; Each of the stepped regions has a stepped structure, Each of the active layers comprises: (1) a first semiconductor layer having a first conductivity type; (2) a second semiconductor layer having the first conductivity type provided under the first semiconductor layer; (3) a dielectric layer having an insulating material between the first semiconductor layer and the second semiconductor layer, isolating the first semiconductor layer and the second semiconductor layer from each other, and having a recess; (4) A third semiconductor layer having a second conductivity type filling the recess of the dielectric layer, the third semiconductor layer being adjacent to both the first semiconductor layer and the second semiconductor layer; each of the active layers constitutes one step of the stepped structure; the structure further comprises an insulator disposed on the stepped structure; A structure having a via opening embedded within the insulator for holding a conductive material in electrical contact with the first and second semiconductor layers of the active layer.

13. 13. The structure of claim 12, A structure in which the via openings reaching the first semiconductor layer of the active layer separately reach the third semiconductor layer of the active layer.

14. 13. The structure of claim 12, The structure further comprising a conductor layer adjacent each of the first and second semiconductor layers of the active layer.

15. A stepped structure including a plurality of active layers formed on a semiconductor substrate, comprising: Each of the active layers comprises: (1) a first semiconductor layer having a first conductivity type; (2) a second semiconductor layer having the first conductivity type provided under the first semiconductor layer; (3) a dielectric layer having a third semiconductor layer having a second conductivity type embedded therein, the third semiconductor layer being adjacent to both the first semiconductor layer and the second semiconductor layer and forming one or more channel regions; (4) a body layer having a third semiconductor material having the second conductivity type; A staircase structure, each of the steps of the staircase structure including a sidewall provided with a conductive semiconductor spacer that connects the second semiconductor layer and the body layer to each other without connecting the body layer to the first semiconductor layer.

16. 16. The staircase structure according to claim 15, The channel region is in contact with the body layer or is separated from the body layer by a thin dielectric layer, which has a stepped structure that suppresses autodoping of the channel region from the body layer but allows the movement of charge carriers between the channel region and the body layer.

17. 17. The staircase structure according to claim 16, A stepped structure in which the thickness of said thin dielectric layer is between 3 nm and 3 monolayers of the dielectric material forming said thin dielectric layer.

18. 16. The staircase structure according to claim 15, Further comprising a dielectric layer covering the step of the staircase structure, a via is embedded within the dielectric layer; A stepped structure, each of the vias including a conductive material for electrically connecting the second semiconductor layer of one of the active layers.

19. (i) providing a first active layer; (ii) providing a first insulating layer over the first active layer; (iii) providing a second active layer on the first insulating layer, The first active layer and the second active layer each have (1) a first semiconductor layer having a first conductivity type; (2) a second semiconductor layer having the first conductivity type provided under the first semiconductor layer; and (3) a dielectric layer having an insulating material between the first semiconductor layer and the second semiconductor layer, isolating the first semiconductor layer and the second semiconductor layer from each other, the dielectric layer having a third semiconductor layer having a second conductivity type embedded therein, the third semiconductor layer being adjacent to both the first semiconductor layer and the second semiconductor layer; (iv) providing a second insulating layer over the second active layer; (iv2) providing a photoresist layer on the second insulating layer; (v) processing the photoresist layer to expose a first region of the second insulating layer; (vi) exposing the first region of the first insulating layer by performing anisotropic removal of the first region of the second insulating layer and the second active layer exposed by removing the first region of the second insulating layer; (vii) recessing the photoresist layer to expose another area of ​​the second insulating layer; (viii) (a) performing anisotropic removal of the first region of the first insulating layer and the other region of the second insulating layer, and (b) the first semiconductor layer exposed by removing the first region of the first insulating layer and the first semiconductor layer exposed by removing the other region of the second insulating layer; (ix) filling the cavity formed by the anisotropic removal of steps (vi) and (viii) with the insulating material; (x) repeating steps (i) to (ix) a predetermined number of times; (xi) anisotropically removing the insulating material at predetermined locations to form a via opening reaching the second semiconductor layer of two or more active layers.

20. 20. The process of claim 19, Before step (v) exposes the first region of the second insulating layer by processing the photoresist layer, patterning the photoresist layer to expose a preliminary region of the second insulating layer; performing anisotropic removal on the preliminary region of the second insulating layer and on the second active layer exposed by removing the preliminary region of the second insulating layer; A process wherein treating the photoresist layer comprises recessing the photoresist layer.

21. 20. The process of claim 19, The process, wherein step (ix) further comprises the sub-step of planarizing after filling the cavity with the insulating material.

22. 20. The process of claim 19, Prior to step (ix) of filling the cavity with the insulating material, (a) providing a second photoresist layer on the second insulating layer; (b) treating the second photoresist layer to expose a second region of the second insulating layer; (c) anisotropically removing the second region of the second insulating layer and the second active layer exposed by removing the second region of the second insulating layer; (d) removing the second photoresist layer.

23. 23. The process of claim 22, A process in which the cavity formed by the anisotropic removal of sub-step (a) is filled with the insulating material used to fill the cavity formed by the anisotropic removal of steps (vi) and (viii).

24. 24. The process of claim 23, (xii) a process further comprising the step of forming a via opening through said first semiconductor layer of two or more active layers by anisotropic removal of said insulating material at predetermined locations.

25. 25. The process of claim 24, A process in which the via opening reaching the first semiconductor layer of the active layer reaches the third semiconductor layer of the active layer.

26. 23. The process of claim 22, Before the sub-step (b) processes the second photoresist layer to expose the second region of the second insulating layer, patterning the photoresist layer to expose a preliminary region of the second insulating layer; performing anisotropic removal on the preliminary region of the second insulating layer and on the second active layer exposed by removing the preliminary region of the second insulating layer; A process wherein said treating said second photoresist layer comprises recessing said second photoresist layer.

27. 20. The process of claim 19, The process wherein the first insulating layer and the second insulating layer each comprise silicon oxide.

28. 20. The process of claim 19, The process further comprising providing a sacrificial layer adjacent each of the first and second semiconductor layers, the sacrificial layer comprising a material having different etching characteristics than the first and second semiconductor layers of the active layer.

29. 29. The process of claim 28, The process further comprising replacing the sacrificial layer with a conductive layer having a resistivity lower than a resistivity of the first semiconductor layer and / or the second semiconductor layer adjacent to the sacrificial layer.

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