Quantum cascade laser element and quantum cascade laser device

Abstract

To provide a quantum cascade layer element and a quantum cascade layer device, capable of achieving an improvement in heat dissipation, a suppression of the oscillation of a higher-mode, and an improvement in stability.SOLUTION: A quantum cascade laser element 1 includes: a semiconductor substrate 2; a semiconductor laminate 3 that has a ridge portion 30 configured to include an active layer 31; an embedding layer 4 including a first portion 41 formed on a side surface 30b of the ridge portion 30 and a second portion 42 extending from the first portion 41 along a width direction of the semiconductor substrate 2; a metal layer 61 formed on a top surface 30a of the ridge portion 30, on the first portion 41, and on the second portion 42; and a dielectric layer 5 disposed between the second portion 42 and the metal layer 61. The dielectric layer 5 is formed such that a part of the second portion 42 is exposed from the dielectric layer 5. The metal layer 61 is in contact with the second portion 42 at the part. The thickness of the second portion 42 is thicker than the thickness of the first portion 41.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a quantum cascade laser element and a quantum cascade laser device. [Background technology]

[0002] A known quantum cascade laser element includes a semiconductor substrate, a semiconductor stack formed on the semiconductor substrate so as to have a ridge portion, a current blocking layer formed over the ridge portion and the semiconductor substrate, an insulating layer formed on the current blocking layer, and a metal layer formed over the top surface of the ridge portion and the insulating layer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-98262 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the quantum cascade laser element described above, in order to stably output fundamental mode light having an intensity peak at the center of the ridge in the width direction, it is required to suppress oscillation of higher mode light having intensity peaks on both sides of the center. In addition, improvement of heat dissipation and improvement of stability as a laser element are also required.

[0005] An object of the present invention is to provide a quantum cascade laser element and a quantum cascade laser device that can improve heat dissipation, suppress high-order mode oscillation, and improve stability. [Means for solving the problem]

[0006] The quantum cascade laser element of the present invention comprises a semiconductor substrate, a semiconductor stack formed on the semiconductor substrate to have a ridge portion comprising an active layer having a quantum cascade structure, a buried layer having a first portion formed on a side of the ridge portion and a second portion extending from an edge of the first portion on the semiconductor substrate side along the width direction of the semiconductor substrate, a metal layer formed on the top surface, the first portion, and the second portion of the ridge portion, and a dielectric layer disposed between the second portion and the metal layer, wherein the dielectric layer is formed such that a portion of the second portion is exposed from the dielectric layer, and a portion of the metal layer is in contact with the second portion.

[0007] In this quantum cascade laser element, a buried layer is provided having a first portion formed on the side surface of the ridge portion, and a second portion extending from an edge of the first portion on the semiconductor substrate side along the width direction of the semiconductor substrate. This allows heat generated in the active layer to be effectively dissipated. In addition, a metal layer is formed on the first portion formed on the side surface of the ridge portion. This allows oscillation in a higher mode to be suppressed while suppressing loss in the fundamental mode. In addition, a dielectric layer is disposed between the second portion and the metal layer. This allows the bonding strength between the metal layer and the buried layer to be improved. As a result, peeling or deterioration of the metal layer can be suppressed, and the stability of the laser element can be improved. In addition, a part of the second portion is exposed from the dielectric layer, and the metal layer is in contact with the second portion at this part. This allows the heat dissipation to be further improved. Therefore, this quantum cascade laser element allows improvement of heat dissipation, suppression of oscillation in a higher mode, and improvement of stability.

[0008] The dielectric layer may have an opening that exposes an inner portion of the second portion that is continuous with the first portion from the dielectric layer, and the metal layer may be in contact with the inner portion through the opening. In this case, the metal layer contacts the second portion in an inner region close to the ridge portion, so that the heat dissipation can be further improved. On the other hand, in an outer region far from the ridge portion, the metal layer is firmly bonded to the second portion through the dielectric layer. Since the metal layer is firmly bonded to the second portion in the outer region where peeling of the metal layer is likely to occur, peeling of the metal layer can be effectively suppressed. In addition, cleavage streaks may be formed near the inner edge of the dielectric layer (the inner edge of the opening) due to the cleavage process during manufacturing, but since the inner edge of the opening is away from the ridge portion, the influence of the cleavage streaks on the light output characteristics can be suppressed.

[0009] The width of the opening in the width direction of the semiconductor substrate may be at least twice the width of the active layer. In this case, the area where the metal layer contacts the second portion can be widened, and the heat dissipation can be further improved. In addition, the influence of the cleavage ridges on the optical output characteristics can be further suppressed.

[0010] The width of the opening in the width direction of the semiconductor substrate may be 10 times or more the thickness of the second portion. In this case, the area where the metal layer contacts the second portion can be further increased, and the heat dissipation can be further improved. Also, the influence of the cleavage streaks on the light output characteristics can be further suppressed.

[0011] The quantum cascade laser element of the present invention may further include a metal wire electrically connected to the metal layer, and the connection position between the metal layer and the wire may overlap with the dielectric layer when viewed from the thickness direction of the semiconductor substrate. In this case, peeling or the like of the metal layer caused by tensile stress acting on the metal layer from the wire can be suppressed.

[0012] In the thickness direction of the semiconductor substrate, the surface of the second portion opposite the semiconductor substrate is located between the surface of the active layer opposite the semiconductor substrate and the surface on the semiconductor substrate side, and when viewed in the width direction of the semiconductor substrate, a part of the metal layer on the first portion may overlap with the active layer. In this case, the second portion is located beside the active layer to effectively improve heat dissipation, while the metal layer on the first portion is located beside the active layer to effectively suppress oscillation in a higher mode. As a result, both improvement in heat dissipation and suppression of oscillation in a higher mode can be achieved in a well-balanced manner.

[0013] The first portion may be thinner than the second portion, which can achieve a better balance between improved heat dissipation and suppression of higher mode oscillations.

[0014] The metal layer may be formed directly on the first portion. In this case, the metal layer can be brought close to the active layer, and the oscillation of the higher mode can be effectively suppressed by the light absorption by the metal layer. In addition, for example, when another layer is formed between the metal layer and the first portion, there is a risk that the oscillation suppression characteristic of the higher mode may vary due to a manufacturing error of the other layer. However, by forming the metal layer directly on the first portion, such a situation can be suppressed, and the yield can be improved.

[0015] A quantum cascade laser device according to the present invention includes the quantum cascade laser element and a drive unit for driving the quantum cascade laser element. With this quantum cascade laser device, it is possible to improve heat dissipation, suppress oscillation in higher modes, and improve stability. Effect of the Invention

[0016] According to the present invention, it is possible to provide a quantum cascade laser element and a quantum cascade laser device that can improve heat dissipation, suppress high-order mode oscillation, and improve stability. [Brief description of the drawings]

[0017] [Figure 1] 1 is a cross-sectional view of a quantum cascade laser device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] 5(a) and 5(b) are diagrams illustrating a method for manufacturing a quantum cascade laser device. [Figure 4] 5(a) and 5(b) are diagrams illustrating a method for manufacturing a quantum cascade laser device. [Diagram 5] 5(a) and 5(b) are diagrams illustrating a method for manufacturing a quantum cascade laser device. [Figure 6] 5(a) and 5(b) are diagrams illustrating a method for manufacturing a quantum cascade laser device. [Figure 7] 1 is a graph showing an example of an electric field intensity distribution in a quantum cascade laser element. [Figure 8] FIG. 1A is a diagram showing an example of the spread of a fundamental mode, and FIG. 1B is a diagram showing an example of the spread of a first-order mode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same or corresponding elements are designated by the same reference numerals, and duplicated description will be omitted. [Quantum cascade laser element configuration]

[0019] As shown in FIG. 1 and FIG. 2, the quantum cascade laser element 1 includes a semiconductor substrate 2, a semiconductor laminate 3, a buried layer 4, a dielectric layer 5, a first electrode 6, and a second electrode 7. The semiconductor substrate 2 is, for example, a rectangular plate-shaped S-doped InP single crystal substrate. As an example, the length of the semiconductor substrate 2 is about 3 mm, the width of the semiconductor substrate 2 is about 500 μm, and the thickness of the semiconductor substrate 2 is about 100 μm. In the following description, the width direction of the semiconductor substrate 2 is referred to as the X-axis direction, the length direction of the semiconductor substrate 2 is referred to as the Y-axis direction, and the thickness direction of the semiconductor substrate 2 is referred to as the Z-axis direction. The side where the semiconductor laminate 3 is located with respect to the semiconductor substrate 2 in the Z-axis direction is referred to as the first side S1, and the side where the semiconductor substrate 2 is located with respect to the semiconductor laminate 3 in the Z-axis direction is referred to as the second side S2.

[0020] The semiconductor laminate 3 is formed on the surface 2a of the first side S1 of the semiconductor substrate 2. The semiconductor laminate 3 includes an active layer 31 having a quantum cascade structure. The semiconductor laminate 3 is configured to oscillate laser light having a predetermined central wavelength (for example, a wavelength in the mid-infrared region, and a central wavelength of any value between 4 and 11 μm). In this embodiment, the semiconductor laminate 3 is configured by laminating a lower cladding layer 32, a lower guide layer (not shown), the active layer 31, an upper guide layer (not shown), an upper cladding layer 33, and a contact layer (not shown) in this order from the semiconductor substrate 2 side. The upper guide layer has a diffraction grating structure that functions as a distributed feedback (DFB) structure.

[0021] The active layer 31 has, for example, an InGaAs / InAlAs multiple quantum well structure. The lower cladding layer 32 and the upper cladding layer 33 are each, for example, a Si-doped InP layer. The lower guide layer and the upper guide layer are each, for example, a Si-doped InGaAs layer. The contact layer is, for example, a Si-doped InGaAs layer.

[0022] The semiconductor laminate 3 has a ridge portion 30 extending along the Y-axis direction. The ridge portion 30 is composed of a portion of the first side S1 of the lower cladding layer 32, the lower guide layer, the active layer 31, the upper guide layer, the upper cladding layer 33, and the contact layer. The width of the ridge portion 30 in the X-axis direction is narrower than the width of the semiconductor substrate 2 in the X-axis direction. The length of the ridge portion 30 in the Y-axis direction is equal to the length of the semiconductor substrate 2 in the Y-axis direction. As an example, the length of the ridge portion 30 is about 3 mm, the width of the ridge portion 30 is about 8 μm, and the thickness of the ridge portion 30 is about 8 μm. The ridge portion 30 is located at the center of the semiconductor substrate 2 in the X-axis direction. The layers constituting the semiconductor laminate 3 are not present on both sides of the ridge portion 30 in the X-axis direction.

[0023] The ridge portion 30 has a top surface 30a and a pair of side surfaces 30b. The top surface 30a is the surface of the first side S1 of the ridge portion 30. The pair of side surfaces 30b are the surfaces on both sides of the ridge portion 30 in the X-axis direction. In this example, each of the top surface 30a and the side surfaces 30b is a flat surface. When viewed from the Y-axis direction, each side surface 30b is inclined with respect to the center line CL so as to approach the center line CL of the ridge portion 30 as it moves away from the semiconductor substrate 2 (toward the first side S1). The center line CL is a straight line that passes through the center (geometric center) of the ridge portion 30 as viewed from the Y-axis direction and is parallel to the Z-axis direction. When viewed from the Y-axis direction, the quantum cascade laser element 1 is configured to be axisymmetric with respect to the center line CL.

[0024] The semiconductor laminate 3 has a first end face 3a and a second end face 3b which are both end faces of the ridge portion 30 in the optical waveguide direction A. The optical waveguide direction A is parallel to the Y-axis direction which is the extension direction of the ridge portion 30. The first end face 3a and the second end face 3b function as light emitting end faces. The first end face 3a and the second end face 3b are located on the same plane as both end faces of the semiconductor substrate 2 in the Y-axis direction.

[0025] The buried layer 4 is a semiconductor layer made of, for example, an Fe-doped InP layer. The buried layer 4 has a pair of first portions 41 and a pair of second portions 42. The pair of first portions 41 are formed on a pair of side surfaces 30b of the ridge portion 30, respectively. The pair of second portions 42 each extend along the X-axis direction from an edge portion 41a of the second side S2 of the pair of first portions 41. Each second portion 42 is formed on a surface 32a of the lower cladding layer 32. The surface 32a is the surface of the first side S1 of a portion of the lower cladding layer 32 that does not constitute the ridge portion 30.

[0026] In the Z-axis direction, the surface 42a of the first side S1 of each second portion 42 is located between the surface 31a of the first side S1 and the surface 31b of the second side S2 of the active layer 31. In other words, when viewed from the X-axis direction, a part of the first side S1 of the second portion 42 overlaps with a part of the second side S2 of the active layer 31.

[0027] Each first portion 41 is formed over the entire side surface 30b of the ridge portion 30, and protrudes from the top surface 30a of the ridge portion 30 to the first side S1 in the Z-axis direction. A surface 41b of each first portion 41 opposite the ridge portion 30 has a first inclined surface 43 and a second inclined surface 44. In this example, each of the first inclined surface 43 and the second inclined surface 44 is a flat surface.

[0028] When viewed from the optical waveguide direction A, the first inclined surface 43 is inclined with respect to the side surface 30b of the ridge portion 30 so as to move away from the side surface 30b of the ridge portion 30 with increasing distance from the semiconductor substrate 2. In this example, when viewed from the optical waveguide direction A, the first inclined surface 43 is also inclined with respect to the center line CL of the ridge portion 30 so as to move away from the center line CL of the ridge portion 30 with increasing distance from the semiconductor substrate 2. The first inclined surface 43 is continuous with the surface 42a of the first side S1 of the second portion 42. The edge portion of the first inclined surface 43 on the semiconductor substrate 2 side overlaps with the active layer 31 when viewed from the X-axis direction.

[0029] The second inclined surface 44 is located on the first side S1 with respect to the first inclined surface 43, and is continuous with the first inclined surface 43. When viewed from the optical waveguide direction A, the second inclined surface 44 is inclined with respect to the center line CL of the ridge portion 30 so as to approach the center line CL of the ridge portion 30 with increasing distance from the semiconductor substrate 2. In this example, when viewed from the optical waveguide direction A, the second inclined surface 44 is also inclined with respect to the side surface 30b of the ridge portion 30 so as to approach the side surface 30b of the ridge portion 30 with increasing distance from the semiconductor substrate 2. The second inclined surface 44 protrudes from the top surface 30a of the ridge portion 30 to the first side S1 in the Z-axis direction.

[0030] The thickness T1 of the first portion 41 is thinner than the thickness T2 of the second portion 42. The thickness T1 of the first portion 41 may be equal to or less than half the thickness T2 of the second portion 42. The thickness T1 of the first portion 41 is the maximum thickness of the first portion 41 in the X-axis direction. In this example, the thickness of the first portion 41 increases as it approaches the boundary between the first inclined surface 43 and the second inclined surface 44 from the second side S2, and decreases as it moves away from the boundary toward the first side S1. That is, the thickness of the first portion 41 is maximum at the position of the boundary. Therefore, the thickness T1 of the first portion 41 is the distance between the side surface 30b of the ridge portion 30 and the boundary. The thickness T2 of the second portion 42 is the maximum thickness of the second portion 42 in the Z-axis direction. In this example, the thickness of the second portion 42 is uniform throughout the second portion 42. As an example, the thickness T1 of the first portion 41 is about 1 to 2 μm, and the thickness T2 of the second portion 42 is about 3.0 μm.

[0031] The dielectric layer 5 is an insulating layer made of, for example, a SiN film or a SiO2 film. The dielectric layer 5 is formed on a surface 47a of an outer portion 47 of the second portion 42 such that the top surface 30a of the ridge portion 30, a surface 41b of the first portion 41, and a surface 46a of an inner portion 46 of the second portion 42 are exposed from the dielectric layer 5. The inner portion 46 is a portion of the second portion 42 that is continuous with the first portion 41, and the outer portion 47 is a portion of the second portion 42 that is located outside the inner portion 46 in the X-axis direction. The surface 46a is a surface of a first side S1 of the inner portion 46, and the surface 47a is a surface of a first side S1 of the outer portion 47.

[0032] The dielectric layer 5 is formed on the surface 47a of the outer portion 47, but is not formed on the surface 46a of the inner portion 46, exposing the surface 46a. In other words, an opening 5a is formed in the dielectric layer 5 to expose the inner portion 46 from the dielectric layer 5. The opening 5a exposes the top surface 30a of the ridge portion 30, the surface 41b of the first portion 41, and the surface 46a of the inner portion 46 of the second portion 42 from the dielectric layer 5. In both the X-axis direction and the Y-axis direction, the outer edge of the dielectric layer 5 reaches the outer edge of the buried layer 4. The dielectric layer 5 also functions as an adhesion layer that enhances adhesion between the buried layer 4 and a metal layer 61 described later.

[0033] The width W1 of the opening 5a in the X-axis direction is at least twice the width W2 of the active layer 31 in the X-axis direction. The width W1 may be at least five times the width W2. As an example, the width W1 is about 50 μm, and the width W2 is about 9 μm. In the case where the width of the active layer 31 narrows toward the first side S1 as in this embodiment, the width W2 of the active layer 31 is the width at the end of the first side S1.

[0034] The width W1 of the opening 5a in the X-axis direction may be 10 times or more the thickness T3 of the buried layer 4 in the Z-axis direction. The thickness T3 of the buried layer 4 is the thicker of the thickness T1 of the first portion 41 and the thickness T2 of the second portion 42, and is the thickness T2 in this example. In other words, the width W1 of the opening 5a may be 10 times or more the thickness T2 of the second portion 42. As described above, the thickness T2 of the second portion 42 is, for example, about 3 μm.

[0035] The first electrode 6 has a metal layer 61 and a plating layer 62. The metal layer 61 is, for example, a Ti / Au layer, and functions as a base layer for forming the plating layer 62. The plating layer 62 is formed on the metal layer 61. The plating layer 62 is, for example, an Au plating layer. The thickness of the first electrode 6 in the Z-axis direction is, for example, 6 μm or more.

[0036] The metal layer 61 is integrally formed so as to extend over the top surface 30a of the ridge portion 30 and over the first portion 41 and the second portion 42 of the buried layer 4. The metal layer 61 is in contact with the top surface 30a of the ridge portion 30. As a result, the first electrode 6 is electrically connected to the upper cladding layer 33 via the contact layer. In both the X-axis direction and the Y-axis direction, the outer edge of the metal layer 61 is located inside the outer edges of the buried layer 4 and the dielectric layer 5. The distance in the X-axis direction between the outer edge of the metal layer 61 and the outer edge of the dielectric layer 5 (the outer edges of the semiconductor substrate 2, the semiconductor stack 3, and the buried layer 4) is, for example, about 50 μm.

[0037] The metal layer 61 is formed directly on the first portion 41. That is, no other layer (e.g., a dielectric layer or an insulating layer) is formed between the metal layer 61 and the first portion 41. The metal layer 61 is formed over the entire surface 41b of the first portion 41, and extends over the first inclined surface 43 and the second inclined surface 44. When viewed from the X-axis direction, a part of the metal layer 61 on the first inclined surface 43 overlaps with the active layer 31. More specifically, an edge of the second side S2 of the metal layer 61 on the first inclined surface 43 overlaps with the active layer 31. The metal layer 61 is provided so as to cover a part of the first portion 41 protruding from the top surface 30a of the ridge portion 30.

[0038] In the inner portion 46 of the second portion 42, the metal layer 61 is in contact with the surface 46a of the inner portion 46 through the opening 5a formed in the dielectric layer 5. In the outer portion 47 of the second portion 42, the metal layer 61 is formed on the second portion 42 through the dielectric layer 5. That is, the dielectric layer 5 is disposed between the outer portion 47 of the second portion 42 and the first electrode 6. When viewed from the Z-axis direction, the outer edge of the first electrode 6 is located inside the outer edges of the semiconductor substrate 2, the semiconductor stack 3, the buried layer 4, and the dielectric layer 5.

[0039] A plurality of wires 8 are electrically connected to a surface 62a of the first side S1 of the plating layer 62. Each wire 8 is formed by, for example, wire bonding, and is electrically connected to the metal layer 61 via the plating layer 62. The connection position between the metal layer 61 (plating layer 62) and each wire 8 overlaps with the dielectric layer 5 when viewed from the Z-axis direction. The number of wires 8 is not limited, and only one wire 8 may be provided.

[0040] The second electrode 7 is formed on the surface 2b of the second side S2 of the semiconductor substrate 2. The second electrode 7 is, for example, an AuGe / Au film, an AuGe / Ni / Au film, or an Au film. The second electrode 7 is electrically connected to the lower cladding layer 32 via the semiconductor substrate 2.

[0041] In the quantum cascade laser device 1, when a bias voltage is applied to the active layer 31 via the first electrode 6 and the second electrode 7, light is emitted from the active layer 31, and light having a predetermined central wavelength among the light is resonated in the distributed feedback structure. As a result, laser light having a predetermined central wavelength is emitted from each of the first end face 3a and the second end face 3b. Note that a high-reflection film may be formed on one of the first end face 3a and the second end face 3b. In this case, laser light having a predetermined central wavelength is emitted from the other end face of the first end face 3a and the second end face 3b. Alternatively, a low-reflection film may be formed on one of the first end face 3a and the second end face 3b. Also, a high-reflection film may be formed on the other end face different from the end face on which the low-reflection film is formed. In either of these cases, laser light having a predetermined central wavelength is emitted from one of the first end face 3a and the second end face 3b. In the former case, laser light is emitted from both the first end face 3a and the second end face 3b.

[0042] The quantum cascade laser element 1 can constitute a quantum cascade laser device together with a driving unit that drives the quantum cascade laser element 1. The driving unit is electrically connected to the first electrode 6 and the second electrode 7. The driving unit is, for example, a pulse driving unit that drives the quantum cascade laser element 1 so that the quantum cascade laser element 1 oscillates a laser light in a pulsed manner. [Manufacturing method of quantum cascade laser element]

[0043] A method for manufacturing the quantum cascade laser device 1 will be described with reference to FIGS. 3 to 6. First, as shown in FIG. 3(a), a semiconductor wafer 200 having a first main surface 200a and a second main surface 200b is prepared, and a semiconductor layer 300 is formed on the first main surface 200a of the semiconductor wafer 200. The semiconductor wafer 200 is, for example, an S-doped InP single crystal (100) wafer. The semiconductor wafer 200 includes a plurality of portions each of which will become a semiconductor substrate 2, and is cleaved along a line L in a later process as described later. Similarly, the semiconductor layer 300 includes a plurality of portions each of which will become a semiconductor laminate 3. The semiconductor layer 300 is formed by epitaxially growing each layer (i.e., each of the layers that will become the lower cladding layer 32, the lower guide layer, the active layer 31, the upper guide layer, the upper cladding layer 33, and the contact layer) by, for example, MO-CVD.

[0044] 3(b), a dielectric film 100 is formed on a portion of the semiconductor layer 300 that will become the ridge portion 30, and the semiconductor layer 300 is dry etched using the dielectric film 100 as a mask down to the lower cladding layer 32. The dielectric film 100 is made of, for example, a SiN film or a SiO2 film. The dielectric film 100 is patterned into the shape shown in FIG. 3(b) by, for example, photolithography and etching. The width of the dielectric film 100 in the X-axis direction is, for example, about 10 μm.

[0045] 4(a), the semiconductor layer 300 is wet-etched using the dielectric film 100 as a mask. As a result, a ridge portion 30 is formed in the semiconductor layer 300.

[0046] 4(b), a buried layer 400 is formed on the semiconductor layer 300. The buried layer 400 includes a plurality of portions each of which becomes a buried layer 4. The buried layer 400 is formed by crystal growth using MO-CVD, for example. The dielectric film 100 functions as a mask, so that the buried layer 400 is not formed on the dielectric film 100.

[0047] 5(a), the dielectric film 100 is removed by etching to form a dielectric layer 500 on the buried layer 400. The dielectric layer 500 includes a plurality of portions each of which becomes a dielectric layer 5. The dielectric layer 500 is patterned into the shape shown in FIG. 5(a) by, for example, photolithography and etching. As a result, an opening 5a (contact hole) is formed in the dielectric layer 500.

[0048] Then, as shown in FIG. 5(b), a metal layer 610 is formed on the top surface 30a of the ridge portion 30 and on the first portion 41 and the second portion 42 of the buried layer 4. Then, as shown in FIG. 6(a), a plating layer 620 is formed on the metal layer 610 by plating. The metal layer 610 includes a plurality of portions each of which will become the metal layer 61, and the plating layer 620 includes a plurality of portions each of which will become the plating layer 62. The metal layer 610 is formed, for example, by sputtering or evaporating Ti having a thickness of about 50 nm and Au having a thickness of about 300 nm in this order. The metal layer 610 on the line L is removed, for example, by etching, after the formation of the plating layer 620. The line L is a cleavage line that separates the plurality of portions that will become the quantum cascade laser element 1.

[0049] Next, as shown in FIG. 6(b), the second main surface 200b of the semiconductor wafer 200 is polished to thin the semiconductor wafer 200. Next, an electrode layer 700 is formed on the second main surface 200b of the semiconductor wafer 200. The electrode layer 700 includes a plurality of portions each of which becomes the second electrode 7. The electrode layer 700 may be subjected to an alloy heat treatment. Next, the semiconductor wafer 200 and the semiconductor layer 300 are cleaved along the line L. As a result, a plurality of quantum cascade laser elements 1 are obtained. [Action and Effects]

[0050] In the quantum cascade laser element 1, a buried layer 4 is provided having a first portion 41 formed on the side surface 30b of the ridge portion 30, and a second portion 42 extending from an edge portion 41a of the second side S2 of the first portion 41 along the X-axis direction (width direction of the semiconductor substrate 2). This allows heat generated in the active layer 31 to be effectively dissipated. In addition, a metal layer 61 is formed on the first portion 41 formed on the side surface 30b of the ridge portion 30. This allows oscillation in a higher mode to be suppressed while suppressing loss in the fundamental mode. In addition, a dielectric layer 5 is disposed between the second portion 42 and the metal layer 61. This allows the bonding strength between the metal layer 61 and the buried layer 4 to be improved. As a result, peeling or deterioration of the metal layer 61 can be suppressed, and the stability as a laser element can be improved. In addition, a part of the second portion 42 is exposed from the dielectric layer 5, and the metal layer 61 is in contact with the second portion 42 at the part. This allows heat dissipation to be further improved. Therefore, it is possible to improve heat dissipation, suppress high-order mode oscillation, and improve stability according to the quantum cascade laser device 1. Generally, the thermal conductivity of a dielectric material such as SiN or SiO2 is lower than that of a semiconductor and a metal.

[0051] Here, the effect of suppressing oscillation of the high-order transverse mode will be further described with reference to Fig. 7 and Fig. 8. Fig. 7 shows the electric field intensity distribution in the width direction of the semiconductor substrate 2, with the center of the ridge 30 as the origin of the X-axis. The intensity distribution of the fundamental mode M0 is shown by a solid line, and the intensity distribution of the first mode M1 is shown by a two-dot chain line. As shown in Fig. 7, the light of the fundamental mode M0 has an intensity peak near the center of the ridge 30, and the light of the first mode M1 has intensity peaks on both sides of the center of the ridge 30.

[0052] 8(a) is a diagram showing the spread of the fundamental mode M0 when viewed from the optical waveguide direction A, and FIG. 8(b) is a diagram showing the spread of the first mode M1 when viewed from the optical waveguide direction A. As shown in FIG. 8(a) and FIG. 8(b), each of the fundamental mode M0 and the first mode M1 has a substantially elliptical spread with the major axis along the Z-axis direction. As described above, by forming the metal layer 61 that easily absorbs light on the first portion 41, it is possible to suppress the loss of the fundamental mode M0 light (confining the fundamental mode M0 light within the ridge portion 30) while suppressing the oscillation of the first mode M1 light.

[0053] The dielectric layer 5 has an opening 5a that exposes the inner portion 46 of the second portion 42, which is continuous with the first portion 41, from the dielectric layer 5, and the metal layer 61 contacts the inner portion 46 through the opening 5a. As a result, the metal layer 61 contacts the second portion 42 in an inner region close to the ridge portion 30, and heat dissipation can be further improved. On the other hand, in an outer region far from the ridge portion 30, the metal layer 61 is firmly bonded to the second portion 42 through the dielectric layer 5. Since the metal layer 61 is firmly bonded to the second portion 42 in the outer region where peeling of the metal layer 61 is likely to occur, peeling of the metal layer 61 can be effectively suppressed. In addition, cleavage lines may be formed near the inner edge of the dielectric layer 5 (the inner edge of the opening 5a) due to the cleavage process during manufacturing, but since the inner edge of the opening 5a is away from the ridge portion 30, the influence of the cleavage lines on the light output characteristics can be suppressed. The cleavage lines may, for example, be formed in the buried layer 4 and extend to the lower cladding layer 32 and the semiconductor substrate 2 .

[0054] The width W1 of the opening 5a in the X-axis direction is at least twice the width of the active layer 31. This makes it possible to widen the area where the metal layer 61 contacts the second portion 42, thereby further improving heat dissipation. In addition, the influence of the cleavage streaks on the optical output characteristics can be further suppressed.

[0055] The width W1 of the opening 5a in the X-axis direction is 10 times or more the thickness T3 of the second portion 42. This makes it possible to further increase the area where the metal layer 61 contacts the second portion 42, thereby further improving heat dissipation. Also, the influence of the cleavage lines on the light output characteristics can be further suppressed.

[0056] A metal wire 8 is electrically connected to the metal layer 61, and the connection position between the metal layer 61 and the wire 8 overlaps with the dielectric layer 5 when viewed from the Z-axis direction (thickness direction of the semiconductor substrate 2). This makes it possible to prevent the metal layer 61 from peeling off due to the tensile stress acting on the metal layer 61 from the wire 8.

[0057] In the Z-axis direction, the surface 42a of the first side S1 (opposite side to the semiconductor substrate 2) of the second portion 42 is located between the surface 31a of the first side S1 and the surface 31b of the second side S2 (semiconductor substrate 2 side) of the active layer 31, and when viewed from the X-axis direction, a part of the metal layer 61 on the first portion 41 overlaps with the active layer 31. This makes it possible to effectively improve heat dissipation by positioning the second portion 42 beside the active layer 31, while effectively suppressing oscillation in a higher mode by positioning the metal layer 61 on the first portion 41 beside the active layer 31. As a result, it is possible to achieve both improvement in heat dissipation and suppression of oscillation in a higher mode in a well-balanced manner.

[0058] The thickness T1 of the first portion 41 is smaller than the thickness T2 of the second portion 42. This makes it possible to achieve both improved heat dissipation and suppression of oscillation in higher modes in a more balanced manner.

[0059] The metal layer 61 is formed directly on the first portion 41. This allows the metal layer 61 to be close to the active layer 31, and the high-order mode oscillation can be effectively suppressed by the light absorption by the metal layer 61. In addition, for example, if another layer (e.g., a dielectric layer or an insulating layer) is formed between the metal layer 61 and the first portion 41, there is a risk that the oscillation suppression characteristics of the high-order mode will vary due to a manufacturing error of the other layer. For example, there is a risk that the thickness of the other layer will differ between one side and the other side of the ridge portion 30 in the X-axis direction due to an alignment error, resulting in a different refractive index structure. In this regard, in the quantum cascade laser element 1, the metal layer 61 is formed directly on the first portion 41, so that such a situation can be suppressed and the yield can be improved. [Variations]

[0060] The present invention is not limited to the above-described embodiment. The materials and shapes of each component are not limited to those described above, and various materials and shapes can be adopted. Other known quantum cascade structures can be applied to the active layer 31. Other known stacked structures can be applied to the semiconductor stack 3. As an example, in the semiconductor stack 3, the upper guide layer does not need to have a diffraction grating structure that functions as a distributed feedback structure.

[0061] The outer edge of the metal layer 61 in the Y-axis direction may reach the outer edges of the buried layer 4 and the dielectric layer 5. In this case, it is possible to improve the heat dissipation at the first end facet 3a and the second end facet 3b. Each side face 30b of the ridge portion 30 may extend parallel to the center line CL. The metal layer 61 may be configured to include a plurality of portions separated from each other. For example, the metal layer 61 on the first portion 41 may be provided separately from the metal layer 61 on the second portion 42.

[0062] The first electrode 6 may be formed only by the metal layer 61 without providing the plating layer 62. In this case, the wire 8 may be connected to the surface of the first side S1 of the metal layer 61. In the above embodiment, the inner part 46 of the second part 42 is exposed from the dielectric layer 5, and the metal layer 61 is in contact with the inner part 46. However, it is sufficient that a part of the second part 42 is exposed from the dielectric layer 5, and the metal layer 61 is in contact with the second part 42 at the part. In the above embodiment, the surface 62a of the plating layer 62 is located on the second side S2 of the top surface 30a of the ridge portion 30, but the surface 62a may be located on the first side S1 of the top surface 30a. After the plating layer 62 is formed by plating so that the surface 62a is located on the first side S1 of the top surface 30a, the surface 62a may be flattened by polishing. [Explanation of symbols]

[0063] 1...quantum cascade laser element, 2...semiconductor substrate, 3...semiconductor stack, 4...buried layer, 5...dielectric layer, 5a...opening, 8...wire, 30...ridge portion, 30a...top surface, 30b...side surface, 31...active layer, 31a, 31b...surface, 41...first portion, 41a...edge, 42...second portion, 42a...surface, 46...inner portion, 61...metal layer.

Claims

1. A semiconductor substrate; a semiconductor laminate formed on the semiconductor substrate so as to have a ridge portion including an active layer having a quantum cascade structure; a buried layer having a first portion formed on a side surface of the ridge portion and a second portion extending along a width direction of the semiconductor substrate from an edge of the first portion on the semiconductor substrate side; a metal layer formed on a top surface of the ridge portion, the first portion, and the second portion; a dielectric layer disposed between the second portion and the metal layer; a metal wire electrically connected to the metal layer; the dielectric layer is formed such that a part of the second portion is exposed from the dielectric layer; the metal layer is in contact with the second portion at the portion; The thickness of the second portion is greater than the thickness of the first portion, an opening is formed in the dielectric layer to expose an inner portion of the second portion that is continuous with the first portion from the dielectric layer; the metal layer contacts the inner portion through the opening; a width of the opening in a width direction of the semiconductor substrate is equal to or greater than twice the width of the active layer; A quantum cascade laser element, wherein a connection position between the metal layer and the wire overlaps with the dielectric layer when viewed in a thickness direction of the semiconductor substrate.

2. The quantum cascade laser device according to claim 1 , wherein a part of the metal layer on the first portion overlaps with the active layer when viewed in a width direction of the semiconductor substrate.

3. 3. The quantum cascade laser device according to claim 1, wherein a width of the opening in a width direction of the semiconductor substrate is ten times or more a thickness of the second portion.

4. The quantum cascade laser device according to claim 1 , wherein the metal layer is formed directly on the first portion.

5. A quantum cascade laser element according to any one of claims 1 to 4, A quantum cascade laser device comprising: a driving unit that drives the quantum cascade laser element.

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