Semiconductor optical element and its manufacturing method

Abstract

To prevent deterioration in crystal quality of an embedded layer 42.SOLUTION: A semiconductor optical element includes: a lower mesa structure 24 composed of multiple layers that extend in a stripe shape and contain an active layer 28; a buried layer 42 that fills both sides of the lower mesa structure 24 and being composed of indium phosphide; and an upper mesa structure 26 that is composed of multiple layers including a lowermost layer 36 that extend in a stripe shape and being composed of a material containing no phosphorous, whose lowermost layer 36 has a bottom surface that protrudes from an uppermost layer 34 of the lower mesa structure 24, the bottom surface being in contact with the lower mesa structure 24 and the buried layer 42.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor optical device and a method for manufacturing the same. [Background technology]

[0002] In semiconductor optical devices, a buried heterostructure (BH) structure is known in which buried layers made of semiconductor layers are provided on both sides of a mesa stripe structure to suppress lateral current diffusion and increase the relaxation oscillation frequency. Also known is a structure in which only the part containing a multi-quantum well (MQW) is buried, rather than burying the entire mesa stripe structure, thereby increasing the optical confinement factor of the MQW (Patent Documents 1, 2, and 3).

[0003] The semiconductor optical device disclosed in Patent Document 2 has a two-stage structure consisting of a lower mesa structure including an MQW and an upper mesa structure including a diffraction grating layer, etc. Since the upper mesa structure is wider than the lower mesa structure, the bottom surface of the upper mesa structure is exposed from the lower mesa structure. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-165133 [Patent Document 2] Japanese Patent Application Publication No. 2018-56212 [Patent Document 3] Patent Publication No. 2021-27310 Summary of the Invention [Problem to be solved by the invention]

[0005] When MOCVD (Metal Organic Chemical Vapor Deposition) is used to form the burying layer, crystals grow not only from the substrate but also from the exposed bottom surface of the upper mesa structure. Crystal defects and voids can occur at the interface between the crystals grown in different directions, which can result in a deterioration of the crystal quality of the burying layer and lead to a decrease in the reliability and performance of the semiconductor optical device.

[0006] The present disclosure aims to prevent degradation of the crystalline quality of the buried layer. [Means for solving the problem]

[0007] The semiconductor optical device has a lower mesa structure extending in a stripe shape and consisting of multiple layers including an active layer, buried layers made of indium phosphide that embed both sides of the lower mesa structure, and an upper mesa structure extending in a stripe shape and consisting of multiple layers including a bottom layer made of a material that does not contain phosphorus, the bottom layer having a bottom surface that protrudes from the top layer of the lower mesa structure and the bottom surface being in contact with the lower mesa structure and the buried layer.

[0008] A method for manufacturing a semiconductor optical device includes the steps of: forming a mesa stripe structure having a lower mesa structure consisting of multiple layers extending in a stripe shape and including an active layer; and an upper mesa structure having multiple layers extending in a stripe shape on the lower mesa structure and including a bottom layer, the bottom layer having a bottom surface protruding from the top layer of the lower mesa structure and made of a material that does not contain phosphorus; and, after forming the mesa stripe structure, forming buried layers made of indium phosphide by crystal growth on both sides of the lower mesa structure so as to be in contact with the bottom surfaces. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view of a semiconductor optical device according to a first embodiment. [Figure 2] 2 is a cross-sectional view taken along line II-II of the semiconductor optical device shown in FIG. [Figure 3A]1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. [Figure 3B] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. [Figure 3C] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. [Figure 3D] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. [Figure 3E] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. [Figure 3F] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. [Figure 3G] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor optical device according to a second embodiment. [Figure 5] FIG. 10 is a plan view of a semiconductor optical device according to a third embodiment. [Figure 6] 6 is a cross-sectional view taken along the line VI-VI of the semiconductor optical device shown in FIG. 5. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Elements with the same reference numerals in all the drawings have the same or equivalent functions, and their repeated explanation will be omitted. Note that the size of the figures does not necessarily correspond to the magnification.

[0011] [First embodiment] FIG. 1 is a plan view of a semiconductor optical device according to a first embodiment. FIG. 2 is a cross-sectional view of the semiconductor optical device shown in FIG. 1 taken along line II-II. The semiconductor optical device is a semiconductor laser. The semiconductor optical device has an upper electrode 10 and a lower electrode 12 on its upper and lower surfaces, respectively, and a voltage is applied (current is injected) between them. This allows laser light to be emitted from the end facet of the mesa stripe structure 14, for example, in the 1.3 μm or 1.55 μm band. A non-reflective coating film 16 made of a dielectric is formed on the end facet on the emission side. A highly reflective coating film 18 made of a dielectric is formed on the end facet on the opposite side.

[0012] The semiconductor optical device has a substrate 20 made of indium phosphide (InP). A buffer layer 22 (lower cladding layer) made of InP is laminated on the substrate 20. A portion of the upper electrode 10 is disposed above the buffer layer 22. Therefore, parasitic capacitance occurs between the upper electrode 10 and the buffer layer 22. Increasing the distance between the upper electrode 10 and the buffer layer 22 can be considered to reduce the parasitic capacitance. Note that the buffer layer 22 may be omitted.

[0013] [Mesa stripe structure] The semiconductor optical device has a mesa stripe structure 14. At least a portion of the upper electrode 10 is on the mesa stripe structure 14. A portion of the buffer layer 22 is included in the mesa stripe structure 14 as a protruding portion. In other words, the upper surface of the buffer layer 22 is lower in areas other than the protruding portions. The mesa stripe structure 14 has a stacked structure of at least two stages with different widths. The mesa stripe structure 14 includes, in order from the side closest to the buffer layer 22, a lower mesa structure 24 and an upper mesa structure 26 that is wider than the lower mesa structure 24.

[0014] [Lower mesa structure] The lower mesa structure 24 extends in a stripe shape. The lower mesa structure 24 is composed of multiple layers. The lower mesa structure 24 is configured by stacking, in order from the side closest to the buffer layer 22, a lower SCH (Separate Confinement Heterostructure) layer 30, an active layer 28, an upper SCH layer 32, and a top layer 34. The active layer 28 may be MQW or bulk. The top layer 34 of the lower mesa structure 24 is made of InP, the same as the buffer layer 22. Note that the lower SCH layer 30, the active layer 28, and the upper SCH 32 have thicknesses that ensure optical characteristics, so it is difficult to change their thicknesses for other purposes.

[0015] The 3 dB bandwidth of a directly modulated semiconductor laser is limited to 1.55 fr by the relaxation oscillation frequency fr of the laser, so increasing the relaxation oscillation frequency fr is necessary to increase the speed. In a semiconductor laser having an MQW as the active layer 28, the relaxation oscillation frequency fr and the optical confinement factor Γ per quantum well are QW , the width W of the active layer 28 a and the drive current I m The following relationship exists between the drive current I m is the injection current minus the threshold current.

[0016]

number

[0017] Therefore, the width W of the active layer 28 a Reducing the optical confinement factor Γ QW / W a Increasing the value of , increases the relaxation oscillation frequency fr, leading to an improvement in the band f3dB.

[0018] [Upper mesa structure] The upper mesa structure 26 extends in a stripe shape. The upper mesa structure 26 is made of multiple layers. A bottom layer 36 of the upper mesa structure 26 is made of a material that does not contain phosphorus (P) (e.g., InGaAlAs, InAlAs, InGaAs). The bottom layer 36 has a bottom surface that protrudes from the top layer 34 of the lower mesa structure 24. The bottom surface is in contact with the lower mesa structure 24. An upper cladding layer 38 made of InP and a contact layer 40 are provided above the bottom layer 36.

[0019] [Embedding Layer] Both sides of the lower mesa structure 24 are buried with a burying layer 42. From the viewpoints of crystallinity and stress, the burying layer 42 is preferably made of the same material as the substrate 20. The burying layer 42 is made of InP. The burying layer 42 may be p-type InP, n-type InP, or high-resistivity InP doped with Fe or Ru, or may be a stack of materials selected from the group consisting of p-type InP, n-type InP, and high-resistivity InP. The base of the burying layer 42 (the buffer layer 22 on the substrate 20) is also made of InP.

[0020] The burying layers 42 are disposed on both sides of the lower mesa structure 24, but are not adjacent to the upper mesa structure 26. In such a structure, if the width of the portion not buried by the burying layers 42 (the upper mesa structure 26) is made larger than the width of the active layer 28, the optical confinement factor Γ QW / W a This leads to an increase in the relaxation oscillation frequency fr and an improvement in the bandwidth f3dB.

[0021] As described above, the upper surface of the buffer layer 22 is lower in the region other than the protrusion (part of the mesa stripe structure 14), and the buried layer 42 is thicker above that region. If the buried layer 42 is semi-insulating, the distance between the upper electrode 10 and the buffer layer 22 located thereon increases, and the parasitic capacitance decreases.

[0022] The bottom surface (edge) of the bottom layer 36 of the upper mesa structure 26 contacts the buried layer 42. The buried layer 42 is thickest at the portion that contacts the bottom surface of the bottom layer 36 of the upper mesa structure 26. The portion of the buried layer 42 that contacts the bottom surface of the bottom layer 36 forms a convex portion.

[0023] For example, if the buried layer 42 is made of Fe—InP, Fe interdiffuses with the dopant contained in the lower SCH layer 30 or the upper SCH layer 32. As a result, the buried layer 42 effectively becomes a thin, high-resistance layer (semi-insulating layer) in the portion adjacent to the lower mesa structure 24, which can increase parasitic capacitance. Therefore, by making the buried layer 42 thicker on both sides of the lower mesa structure 24 than in other regions, the effect of increasing parasitic capacitance can be suppressed. This effect is obtained because the bottom layer 36 of the upper mesa structure 26 is wider than the top layer 34 of the lower mesa structure 24.

[0024] [Insulating layer] The side surfaces of the upper mesa structure 26 and the top surface of the buried layer 42 are covered with an insulating layer 44. The insulating layer 44 is made of, for example, SiO2. The upper electrode 10 is located on the surface of the insulating layer 44. The insulating layer 44 has an opening or slit above the upper mesa structure 26, and the upper electrode 10 is electrically and physically connected to the contact layer 40.

[0025] The insulating layer 44 has a contact surface with the buried layer 42. The contact surface is located lower than the bottom surface of the bottom layer 36 of the upper mesa structure 26. The insulating layer 44 does not contact the top layer 34 of the lower mesa structure 24. A portion of the buried layer 42 is interposed between the top layer 34 of the lower mesa structure 24 and the insulating layer 44.

[0026] [Method of manufacturing semiconductor optical devices] 3A to 3G are diagrams illustrating a method for manufacturing a semiconductor optical device. The method for manufacturing a semiconductor optical device includes forming a mesa stripe structure 14. Forming the mesa stripe structure 14 includes forming multiple layers (FIG. 3A). A buffer layer 22, which is the base of the multiple layers, is made of InP. In a structure in which the buffer layer 22 is omitted, a substrate 20 made of InP serves as the base. An upper mesa structure 26 and a lower mesa structure 24 shown in FIG. 2 are formed from the multiple layers.

[0027] [Multi-layer formation] The multilayer structure is formed in one continuous step or in multiple steps using metalorganic chemical vapor deposition (MOCVD). The multilayer structure includes a layer 30A that will become the lower SCH layer 30, a layer 28A that will become the active layer 28, a layer 32A that will become the upper SCH layer 32, a layer 34A that will become the top layer 34 of the lower mesa structure 24, a layer 36A that will become the bottom layer 36 of the upper mesa structure 26, a layer 38A that will become the upper cladding layer 38, and a layer 40A that will become the contact layer 40. The layer 30A that will become the lower SCH layer 30 and the layer 32A that will become the upper SCH layer 32 are formed from InGaAsP, InGaAlAs, or InAlAs. The layer 28A that will become the active layer 28 is formed from a quaternary system such as InGaAsP or InGaAlAs. The layer 34A that will become the top layer 34 of the lower mesa structure 24 is formed from InP. The layer 36A that will become the bottom layer 36 of the upper mesa structure 26 is formed from a material that does not contain phosphorus (P) (for example, InGaAlAs).

[0028] A first coating film 46 is formed on the multilayer along the mesa stripe structure 14 (optical axis direction). Here, the first coating film 46 is made of SiO2. The first coating film 46 is formed in a region corresponding to the upper mesa structure 26 (FIG. 2).

[0029] [Formation of upper mesa structure] 3B, etching is performed on the stacked layer that will become the upper mesa structure 26 and the layer 34A that will become the top layer 34 (FIG. 2) of the lower mesa structure 24. By etching using the first coating film 46 as a mask, the stacked layer that will become the upper mesa structure 26 and the layer 34A that will become the top layer 34 of the lower mesa structure 24 are removed, leaving behind a region that corresponds to the upper mesa structure 26. In this way, the upper mesa structure 26 is formed.

[0030] [Formation of etching mask] 3C, a second coating film 50 is overlaid on the first coating film 46 remaining after the previous etching. The second coating film 50 covers the top and side surfaces of the upper mesa structure 26, covers the side surfaces of the layer to be etched 34B that will become the top layer 34 of the lower mesa structure 24, and covers the top surface of layer 32A that will become the second layer (upper SCH 32) of the lower mesa structure 24. The top surface of the upper mesa structure 26 is thick because the first coating film 46 and the second coating film 50 overlap, but is thin in other regions because only the second coating film 50 is formed.

[0031] 3D, the first coating film 46 and the second coating film 50 are etched to form an etching mask 48. The etching mask 48 covers the region corresponding to the upper mesa structure 26. Here, the etching mask 48 is made of SiO2.

[0032] When the stacked first coating film 46 and second coating film 50 are anisotropically dry etched in the vertical direction, the etching proceeds on the horizontal surfaces, removing the second coating film 50 but leaving the first coating film 46. This forms an etching mask 48 that covers the top and side surfaces of the upper mesa structure 26 and the side surfaces of the layer to be etched 34B that will become the top layer 34 of the lower mesa structure 24, exposing the other regions.

[0033] The etching mask 48 has a flared shape (overhang shape) in the portion adjacent to the side surface of the layer to be etched 34B that will become the uppermost layer 34 of the lower mesa structure 24. This can be formed by patterning using a stepper or electron beam lithography device and then performing anisotropic dry etching. Alternatively, this may be formed by controlling the film thickness of the second coating film 50.

[0034] [First selective etching] 3E, first selective etching (e.g., wet etching) is performed through the etching mask 48. In the first selective etching, the etching reaction on the top layer 34 of the lower mesa structure 24 is suppressed, while etching proceeds on stacked layers that become layers other than the top layer 34 of the lower mesa structure 24. The first selective etching is performed so that a region corresponding to the lower mesa structure 24 remains.

[0035] Specifically, layer 30A, which will become lower SCH layer 30, layer 28A, which will become active layer 28, and layer 32A, which will become upper SCH layer 32, are selectively etched. This allows the layers below top layer 34 of lower mesa structure 24 to be formed with a width narrower than that of upper mesa structure 26. The width is determined by the etching time. The height of the etched portion is the distance between the layers of material that suppress the etching reaction (buffer layer 22 and layer to be etched 34B).

[0036] The buffer layer 22 is hardly etched. The layer to be etched 34B, which becomes the top layer 34 of the lower mesa structure 24, is also hardly etched, and therefore the bottom layer 36 of the upper mesa structure 26 is also not etched. The layer to be etched 34B has the function of not affecting the shape of the upper mesa structure 26. As a result, a semiconductor optical device with excellent reliability and characteristics can be realized.

[0037] [Second selective etching] As shown in FIG. 3F, second selective etching is performed through the etching mask 48. In the second selective etching, the etching reaction on the lowermost layer 36 of the upper mesa structure 26 is suppressed, while etching proceeds on the layer to be etched 34B, which will become the uppermost layer 34 of the lower mesa structure 24. The second selective etching is performed so that a region corresponding to the lower mesa structure 24 remains. In the second selective etching, the multi-layered underlying layer is etched.

[0038] For example, wet etching is performed using an aqueous solution (e.g., a mixture of hydrochloric acid, phosphoric acid, and water) that selectively etches InP. This etches the buffer layer 22 and the layer to be etched 34B that will become the top layer 34 of the lower mesa structure 24. Here, the bottom layer 36 of the upper mesa structure 26 is made of a material that does not contain phosphorus (P) as a constituent element. Therefore, the etching stops at the boundary between the top layer 34 of the lower mesa structure 24 and the bottom layer 36 of the upper mesa structure 26, and the upper mesa structure 26 is not etched. Through the above steps, a mesa stripe structure 14 including the upper mesa structure 26 and the lower mesa structure 24 is formed.

[0039] [Formation of buried layer] 3G, after the mesa stripe structure 14 is formed, the buried layer 42 is formed on both sides of the lower mesa structure 24 so as to contact the bottom surface of the bottom layer 36 of the upper mesa structure 26. The formation is performed by crystal growth (e.g., MOCVD).

[0040] Crystal growth is performed with the upper mesa structure 26 covered with a patterning mask 52, except for its bottom surface. Here, the etching mask 48 described above is left as is and used as the patterning mask 52. The patterning mask 52 protrudes beyond the bottom surface along the side surfaces of the upper mesa structure 26. The patterning mask 52 protrudes in a direction away from the top layer 34 of the lower mesa structure 24 at a position spaced from the top layer 34.

[0041] In this embodiment, InP grows from the surface of the buffer layer 22, but because the bottom layer 36 of the upper mesa structure 26 is made of a material that does not contain phosphorus (P), InP does not grow from its bottom surface. Therefore, no crystal defects or voids occur in the buried layer 42, resulting in excellent reliability and performance. Note that even if phosphorus is not included in the elements that make up the lower SCH layer 30, the active layer 28, and the upper SCH layer 32, InP grows on the side surfaces due to the crystal planes.

[0042] This embodiment is particularly effective when the buffer layer 22 (or the substrate 20 if there is no buffer layer 22), the top layer 34 of the lower mesa structure 24, and the buried layer 42 are made of the same material (InP). Here, the term "same material" does not include differences in guest materials (e.g., dopants), but means that the host material (basic material) is the same.

[0043] [Insulating layer formation and subsequent processes] The patterning mask 52 is removed, and then an insulating layer 44 is formed to cover the top and both side surfaces of the upper mesa structure 26 and the top surface of the burying layer 42 (FIG. 2). Then, a portion of the insulating layer 44 is removed from the top surface of the upper mesa structure 26 to expose the top surface of the contact layer 40, and an upper electrode 10 is formed by vapor deposition. The upper electrode 10 is electrically and physically connected to the contact layer 40. A lower electrode 12 is also formed by vapor deposition on the bottom side of the substrate 20. In this way, the semiconductor optical device is completed.

[0044] [Second embodiment] 4 is a cross-sectional view of a semiconductor optical device according to the second embodiment. The semiconductor optical device may be any of a DFB (Distributed Feedback) laser, a DBR (Distributed Bragg Reflector) laser, and a DR (Distributed Reflector) laser. A p-type InP buffer layer 222 is stacked on a substrate 220 made of p-type InP.

[0045] The lower mesa structure 224 is formed by stacking a p-type lower SCH layer 230, an active layer 228 which is an MQW made of undoped strained InGaAlAs, an n-type upper SCH layer 232, and an n-type InP top layer 234 of the lower mesa structure 224.

[0046] The upper mesa structure 226 is formed by stacking, in order from the side closest to the lower mesa structure 224, a bottom layer 236, a first interlayer semiconductor layer 254 made of an n-type InP layer, a diffraction grating layer 256 made of n-type InGaAsP, a second interlayer semiconductor layer 258 made of an n-type InP layer, an adjustment semiconductor layer 260 made of n-type InGaAsP, an upper cladding layer 238 made of n-type InP, and an n-type contact layer 240. Note that the p-type and n-type may be reversed. The upper electrode 210 has a three-layer structure of Ti / Pt / Au from the side in contact with the contact layer 240. The lower electrode 212 is made of an AuZn-based material.

[0047] As in the first embodiment, the bottom layer 236 of the upper mesa structure 226 is formed of a material that does not contain phosphorus (P) as a constituent element, and a buried layer 242 with excellent crystallinity can be formed by the process described in the first embodiment.

[0048] This embodiment differs from the first embodiment in that a diffraction grating is included in the upper mesa structure 226. The first interlayer semiconductor layer 254, the diffraction grating layer 256, and the second interlayer semiconductor layer 258 are provided to form a floating-type diffraction grating. The diffraction grating layer 256 has a periodic diffraction grating, and for example, a λ / 4 shift structure is introduced in the direction perpendicular to the paper surface.

[0049] The semiconductor optical device is configured such that the width of the lower mesa structure 224 is narrowed to reduce the Γ QW / W a This has the effect of improving the relaxation oscillation frequency fr by increasing . However, semiconductor optical devices are also laser devices, and the value of the coupling coefficient κ of the diffraction grating is an important parameter in terms of other laser characteristics. For example, the coupling coefficient κ affects the resistance to optical feedback and the side mode suppression ratio.

[0050] The adjustment semiconductor layer 260 is a layer provided to increase the coupling coefficient κ of the diffraction grating. The adjustment semiconductor layer 260 is made of a material with a higher refractive index than the upper cladding layer 238, and the provision of the adjustment semiconductor layer 260 makes it possible to adjust κ. The other configurations are the same as those of the semiconductor optical device of the first embodiment.

[0051] [Third embodiment] Fig. 5 is a plan view of a semiconductor optical device according to a third embodiment. Fig. 6 is a cross-sectional view of the semiconductor optical device taken along line VI-VI of Fig. 5. The semiconductor optical device is an EA-DFB laser (Distributed Feedback Laser Integrated with Electro-absorption Modulator) that integrates a semiconductor laser 362 and an electro-absorption modulator 364.

[0052] An n-type InP buffer layer 322 is stacked on a substrate 320 made of n-type InP. The lower mesa structure 324 is formed by stacking an n-type lower SCH layer 330, an absorption layer 328 which is an MQW made of undoped strained InGaAlAs, a p-type upper SCH layer 332, and a top layer 334 of the lower mesa structure 324 made of p-type InP. The upper mesa structure 326 is formed by stacking, in order from the side closest to the lower mesa structure 324, a bottom layer 336, an upper cladding layer 338 made of p-type InP, and a p-type contact layer 340. Note that the p-type and n-type may be reversed.

[0053] In addition to the upper electrode 310 of the semiconductor laser 362, there is an upper electrode 366 of the electro-absorption modulator 364. The lower electrode 312 may be a common electrode for the semiconductor laser 362 and the electro-absorption modulator 364, or may be a separate electrode. The lower electrode 312 is formed on the lower surface of the substrate 320.

[0054] The semiconductor optical device has a mesa stripe structure 314 that spans both the semiconductor laser 362 and the electro-absorption optical modulator 364. A bulk waveguide structure is present between the semiconductor laser 362 and the electro-absorption optical modulator 364. Alternatively, the semiconductor laser 362 and the electro-absorption optical modulator 364 may be directly connected without including a bulk waveguide structure. The mesa stripe structure 314 is configured in two stages. The mesa stripe structure 314 of the semiconductor laser 362 has the same structure as that of the semiconductor optical device described in the second embodiment, for example.

[0055] In the electro-absorption optical modulator 364, the lower mesa structure 324 is sandwiched between buried layers 342. By narrowing the width of the absorption layer 328, the electric field strength per unit volume of the absorption layer 328 can be increased, which is advantageous in terms of low-voltage operation. However, narrowing the width of the upper mesa structure 326 increases the resistance. Therefore, by making the upper mesa structure 326 wider than the lower mesa structure 324, the electric field strength of the absorption layer 328 can be increased while suppressing the increase in resistance.

[0056] In this embodiment, the bottom layer 336 of the upper mesa structure 326 is also made of a material (e.g., InGaAlAs) that does not contain phosphorus (P) as a constituent element, and a buried layer 342 with excellent crystallinity can be formed by the process described in the first embodiment.

[0057] [Outline of the embodiment] (1) A semiconductor optical device comprising: a lower mesa structure (24) extending in a stripe shape and consisting of multiple layers including an active layer (28) or an absorption layer (328); a buried layer (42) made of indium phosphide burying both sides of the lower mesa structure (24); and an upper mesa structure (26) extending in a stripe shape and consisting of multiple layers including a bottom layer (36) made of a material not containing phosphorus, the bottom layer (36) having a bottom surface protruding from a top layer (34) of the lower mesa structure (24), the bottom surface being in contact with the lower mesa structure (24) and the buried layer (42).

[0058] Since the bottom layer 36 of the upper mesa structure 26 is made of a material that does not contain phosphorus, it is difficult for indium phosphide crystals to grow from the bottom surface, which prevents degradation of the crystal quality of the buried layer 42 made of indium phosphide.

[0059] (2) The semiconductor optical device according to (1), wherein the buried layer 42 has the greatest thickness at a portion that contacts the bottom surface of the lowermost layer 36 .

[0060] (3) The semiconductor optical element according to (2), wherein the portion of the buried layer 42 that contacts the bottom surface of the lowermost layer 36 is a convex portion.

[0061] (4) A semiconductor optical element according to any one of (1) to (3), further comprising an insulating layer 44 covering the side surface of the upper mesa structure 26 and the top surface of the burying layer 42.

[0062] (5) A semiconductor optical element according to (4), wherein a portion of the burying layer 42 is interposed between the top layer 34 of the lower mesa structure 24 and the insulating layer 44, and the insulating layer 44 does not contact the top layer 34.

[0063] (6) A semiconductor optical element according to (4) or (5), wherein the insulating layer 44 has a contact surface with the buried layer 42, and the contact surface is located lower than the bottom surface of the bottom layer 36.

[0064] (7) The semiconductor optical device according to any one of (1) to (6), wherein the base of the burying layer 42 is made of indium phosphide.

[0065] (8) The semiconductor optical device according to (7), wherein the base of the burying layer 42 is a buffer layer 22 on the substrate 20.

[0066] (9) The semiconductor optical device according to any one of (1) to (8), wherein the material of the bottom layer 36 is any one of InGaAlAs, InAlAs, and InGaAs.

[0067] (10) A method for manufacturing a semiconductor optical device, comprising: a step of forming a mesa stripe structure (14) having a lower mesa structure (24) consisting of multiple layers extending in a stripe shape and including an active layer (28) or an absorption layer (328); and an upper mesa structure (26) consisting of multiple layers extending in a stripe shape on the lower mesa structure (24) and including a bottom layer (36), the bottom layer (36) having a bottom surface protruding from the top layer (34) of the lower mesa structure (24), the bottom layer (36) being made of a material that does not contain phosphorus; and a step of forming, after forming the mesa stripe structure (14), burying layers (42) made of indium phosphide by crystal growth on both sides of the lower mesa structure (24) so ​​as to be in contact with the bottom surfaces.

[0068] Since the bottom layer 36 of the upper mesa structure 26 is made of a material that does not contain phosphorus, it is difficult for indium phosphide crystals to grow from the bottom surface, which prevents degradation of the crystal quality of the buried layer 42 made of indium phosphide.

[0069] (11) A method for manufacturing a semiconductor optical element according to (10), wherein the crystal growth is performed in a state where the upper mesa structure 26 is covered with a patterning mask 52 except for the bottom surface.

[0070] (12) A method for manufacturing a semiconductor optical element according to (11), wherein the patterning mask 52 protrudes beyond the bottom surface along the side of the upper mesa structure 26.

[0071] (13) A method for manufacturing a semiconductor optical element according to (12), wherein the patterning mask 52 protrudes in a direction away from the top layer 34 at a position spaced apart from the top layer 34 of the lower mesa structure 24.

[0072] (14) A method for manufacturing a semiconductor optical device according to any one of (10) to (13), wherein the step of forming the mesa stripe structure 14 includes the steps of: depositing a multilayer film that will become the upper mesa structure 26 and the lower mesa structure 24; etching the layer 34A that will become the upper mesa structure 26 and the top layer 34 of the lower mesa structure 24 so as to leave a region corresponding to the upper mesa structure 26; and etching the layer 34A that will become the upper mesa structure 26 and the top layer 34 of the lower mesa structure 24 while suppressing an etching reaction to the top layer 34 of the lower mesa structure 24. A method for manufacturing a semiconductor optical element includes a step of performing a first selective etching process in which etching proceeds on a stack of layers other than the top layer 34 of the lower mesa structure 24, and a step of performing a second selective etching process in which etching proceeds on the layer to be etched 34B that will become the top layer 34 of the lower mesa structure 24 while suppressing an etching reaction on the bottom layer 36 of the upper mesa structure 26, wherein the first selective etching and the second selective etching are performed in such a way that a region corresponding to the lower mesa structure 24 remains.

[0073] (15) A method for manufacturing a semiconductor optical element according to (14), further comprising the step of forming an etching mask 48 covering the region corresponding to the upper mesa structure 26 before the step of performing the first selective etching.

[0074] (16) A method for manufacturing a semiconductor optical element according to (14) or (15), wherein the base on which the multilayer is formed and the layer 34A that will become the top layer 34 are made of indium phosphide, and the second selective etching etches the base of the multilayer.

[0075] The present invention is not limited to the above-described embodiments and various modifications are possible. For example, the configurations described in the embodiments can be replaced with substantially the same configurations, configurations that achieve the same effects, or configurations that can achieve the same objectives. [Explanation of symbols]

[0076] 10 upper electrode, 12 lower electrode, 14 mesa stripe structure, 16 coating film, 18 coating film, 20 substrate, 22 buffer layer, 24 lower mesa structure, 26 upper mesa structure, 28 active layer, 30 lower SCH layer, 32 upper SCH layer, 34 top layer, 34B layer to be etched, 36 bottom layer, 38 upper cladding layer, 40 contact layer, 42 buried layer, 44 insulating layer, 46 first coating film, 48 etching mask, 50 second coating film, 52 patterning mask, 210 upper electrode, 212 lower electrode, 220 substrate, 222 buffer layer, 224 lower mesa structure, 226 upper mesa structure, 228 active layer, 230 lower SCH layer, 232 upper SCH layer, 234 Top layer, 236, bottom layer, 238, upper cladding layer, 240, contact layer, 242, burying layer, 254, first interlayer semiconductor layer, 256, diffraction grating layer, 258, second interlayer semiconductor layer, 260, adjusting semiconductor layer, 310, upper electrode, 312, lower electrode, 314, mesa stripe structure, 320, substrate, 322, buffer layer, 324, lower mesa structure, 326, upper mesa structure, 328, absorption layer, 330, lower SCH layer, 332, upper SCH layer, 334, top layer, 336, bottom layer, 338, upper cladding layer, 340, contact layer, 342, burying layer, 362, semiconductor laser, 364, electroabsorption optical modulator, 366, upper electrode.

Claims

1. a lower mesa structure extending in a stripe shape and consisting of multiple layers including an active layer; a buried layer made of indium phosphide burying both sides of the lower mesa structure; an upper mesa structure including a plurality of layers extending in a stripe shape and including a bottom layer made of a material that does not contain phosphorus, the bottom layer having a bottom surface that protrudes from an uppermost layer of the lower mesa structure, the bottom surface being in contact with the lower mesa structure and the buried layer; and the buried layer has a maximum thickness in the vertical direction at a portion in contact with the bottom surface of the lowermost layer, The semiconductor optical device has a convex portion in the buried layer that contacts the bottom surface of the lowermost layer.

2. 2. The semiconductor optical device according to claim 1, The semiconductor optical device further comprises an insulating layer covering the side surface of the upper mesa structure and the top surface of the burying layer.

3. 3. The semiconductor optical device according to claim 2, a portion of the buried layer is interposed between the uppermost layer of the lower mesa structure and the insulating layer; The insulating layer is not in contact with the top layer.

4. 4. The semiconductor optical device according to claim 2, the insulating layer has a contact surface with the buried layer; The contact surface is located lower than the bottom surface of the lowermost layer.

5. 5. The semiconductor optical device according to claim 1, The underlying layer of the buried layer is made of indium phosphide.

6. 6. The semiconductor optical device according to claim 5, The underlying layer of the buried layer is a buffer layer on a substrate.

7. 7. The semiconductor optical device according to claim 1, The semiconductor optical device wherein the material of the bottom layer is any one of InGaAlAs, InAlAs, and InGaAs.

8. forming a mesa stripe structure having a lower mesa structure made of a plurality of layers including an active layer extending in a stripe shape, and an upper mesa structure made of a plurality of layers including a bottom layer extending in a stripe shape on the lower mesa structure, the bottom layer having a bottom surface protruding from the top layer of the lower mesa structure and made of a material not containing phosphorus; After forming the mesa stripe structure, forming a buried layer made of indium phosphide by crystal growth on both sides of the lower mesa structure so as to be in contact with the bottom surface; Including, the buried layer is formed so as to have a maximum thickness in the vertical direction at a portion in contact with the bottom surface of the lowermost layer, A method for manufacturing a semiconductor optical device, wherein the portion of the buried layer that contacts the bottom surface of the lowermost layer is made into a convex portion.

9. 9. A method for manufacturing a semiconductor optical device according to claim 8, comprising the steps of: The crystal growth is performed in a state where the upper mesa structure, except for the bottom surface, is covered with a patterning mask.

10. 10. A method for manufacturing a semiconductor optical device according to claim 9, comprising: The patterning mask protrudes beyond the bottom surface along the side surface of the upper mesa structure.

11. 11. A method for manufacturing a semiconductor optical device according to claim 10, comprising: The patterning mask protrudes in a direction away from the uppermost layer of the lower mesa structure at a position spaced from the uppermost layer.

12. A method for manufacturing a semiconductor optical device according to any one of claims 8 to 11, comprising: The step of forming the mesa stripe structure includes: depositing multiple layers that will become the upper mesa structure and the lower mesa structure; etching the stacked layer that will become the upper mesa structure and the layer that will become the top layer of the lower mesa structure so as to leave a region that corresponds to the upper mesa structure; performing a first selective etching step in which etching of the stacked layers other than the top layer of the lower mesa structure is promoted while etching of the top layer of the lower mesa structure is suppressed; performing a second selective etching step in which etching of the etched layer that will become the uppermost layer of the lower mesa structure proceeds while etching of the lowermost layer of the upper mesa structure is suppressed; Including, The first selective etching and the second selective etching are performed so as to leave a region corresponding to the lower mesa structure.

13. 13. A method for manufacturing a semiconductor optical device according to claim 12, comprising the steps of: The method for manufacturing a semiconductor optical device further includes, before the step of performing the first selective etching, forming an etching mask that covers the region corresponding to the upper mesa structure.

14. 14. A method for manufacturing a semiconductor optical device according to claim 12 or 13, comprising the steps of: the layer that will be the base layer on which the multilayer is deposited and the top layer are made of indium phosphide; In the second selective etching, the underlying layer of the multilayer is etched.

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