Active voltage balancing for power modulators.

Abstract

To provide a power modulation device and an active voltage balancing system, and a method of active voltage balancing.SOLUTION: In an electric drive system 200, a power modulation device 206 includes a first semiconductor switch 210A and a second semiconductor switch 210B in series, an active voltage balancing system 212 includes a differential voltage logic configured to detect a voltage difference between the first and second semiconductor switches and edge capture logic configured to detect a time difference between when the first and second semiconductor switches are switched, and a micro-controller configured to output first and second gate drive signals to drive the first and second semiconductor switches. The micro-controller is configured to tune the first and second gate drive signals based on the voltage difference to compensate for voltage imbalance and the time difference to compensate for drive signal asymmetry to actively balance a voltage between the first and second semiconductor switches.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates generally to power modulation devices, and more particularly to actively balancing voltage distribution among multiple semiconductor switches connected in series in a power modulation device. [Background technology]

[0002] In various applications, power modulation devices are employed in electric drive systems that have relatively high voltage and power capabilities for driving large electrical loads. While semiconductor switches are typically used in power modulation devices in such electric drive systems, the voltage limits of these semiconductor switches are insufficient to individually support the high voltages required by large electrical loads. Therefore, multiple semiconductor switches may be connected in series, with each semiconductor switch providing a portion of the required high voltage. However, differences in the physical parameters of individual semiconductor switches due to manufacturing, circuit design, and / or environmental factors can cause voltage imbalances among the series-connected semiconductor switches. Such voltage imbalances can accelerate the degradation of the semiconductor switches and degrade their performance. Summary of the Invention

[0003] To address the above-mentioned problems, one aspect of the present disclosure provides a system including a power modulation device and an active voltage balancing system. The power modulation device includes a first semiconductor switch and a second semiconductor switch connected in series. The active voltage balancing system includes differential voltage logic configured to detect a voltage difference between the first semiconductor switch and the second semiconductor switch, and edge capture logic configured to detect a difference in the time at which the first semiconductor switch and the second semiconductor switch switch switch. The active voltage balancing system further includes a microcontroller configured to output first and second gate drive signals to drive the first and second semiconductor switches. The microcontroller is configured to adjust the first and second gate drive signals based on the voltage difference to compensate for voltage imbalance and the time difference to compensate for drive signal asymmetry, to actively balance the voltages of the first and second semiconductor switches.

[0004] The described features and functions can be achieved individually in various embodiments or may be combined in yet other embodiments, further details of which will become apparent by reference to the following description and drawings. [Brief explanation of the drawings]

[0005] [Figure 1] 1 is a schematic diagram of an exemplary embodiment of an aircraft including an electric drive system; [Figure 2] FIG. 1 is a schematic diagram of an exemplary electric drive system. [Figure 3] 1 is a circuit diagram that schematically illustrates aspects of a power modulation device including a plurality of semiconductor switches and an active voltage balancing system configured to actively balance the voltage distribution among the plurality of semiconductor switches. [Figure 4] 4 is a flowchart illustrating an exemplary method for actively balancing voltage distribution among multiple semiconductor switches in series in a power modulation device. [Figure 5-6]4 is a flowchart illustrating an exemplary method for adjusting the timing of gate drive signals for driving a plurality of semiconductor switches to actively balance voltage distribution among the plurality of semiconductor switches. [Figures 7A-7D] 1 is a graph illustrating semiconductor switching with and without the active voltage balancing method described herein. DETAILED DESCRIPTION OF THE INVENTION

[0006] Electric drive systems including power modulation devices may be implemented in many applications to drive large electrical loads, such as in vehicle applications such as automobiles, personal watercraft, aircraft, etc. As an example, in an aircraft application, the electric drive system may be used to power an all-electric or hybrid aircraft propulsion system.

[0007] FIG. 1 schematically illustrates an exemplary embodiment of an aircraft 100 including a high-voltage (∼kV) and high-power (∼MW) capable electric drive system 102. The electric drive system 102 is disposed in a fuselage 104 of the aircraft 100. The electric drive system 102 is configured to draw power from a pair of batteries 106A, 106B disposed on wings 108A, 108B extending from the fuselage 104 of the aircraft 100. Note that the illustrated location of the batteries 106A, 106B is non-limiting, and other battery locations are possible. For example, the batteries may be disposed below the fuselage. The electric drive system 102 is configured to provide power to a pair of propulsion motors 110A, 110B. The electric drive system 102 includes a power modulation device 112 configured to modulate the power received from the pair of batteries 106A, 106B into a form suitable for driving the pair of propulsion motors 110A, 110B. Because of the high voltage and power requirements of the propulsion motors, power modulator 112 may include, for example, multiple semiconductor switches in series. Power modulator 112 may include virtually any number of semiconductor switches in series, depending on the power / voltage capabilities of the individual semiconductor switches and the overall power / voltage requirements of aircraft 100. In some embodiments, power modulator 112 may include, for example, multiple branches connected in parallel, each branch including one or more switches. In branches including two or more switches, the switches are connected in series.

[0008] The electric drive system described above is a non-limiting example of an electric drive system that includes a high-power, high-voltage power modulation device that includes multiple semiconductor switches configured to cooperatively share the high-voltage demands of the electric drive system. While this example electric drive system is described herein as driving a pair of propulsion motors, in some embodiments, the electric drive system may be configured to drive three or more propulsion motors or even a non-propulsion motor drive (e.g., an engine starter, an air compressor, a hydraulic pump, etc.). Additionally, this example electric drive system is described herein in the context of, but not limited to, use in an aircraft. The electric drive systems of the present disclosure may be used in any other application, including non-aircraft and non-vehicle applications.

[0009] FIG. 2 schematically illustrates an exemplary embodiment of an electric drive system 200. For example, electric drive system 200 may represent electric drive system 102 shown in FIG. 1. Electric drive system 200 is configured to draw power from a power source 202 to drive an electric load 204. Power source 202 may take any suitable form. In some examples, power source 202 may include an alternating current (AC) power source. In other examples, power source 202 may include a direct current (DC) power source. Additionally, electric load 204 may take any suitable form. The electric load is described herein primarily, but not exclusively, in the context of a high-power, high-voltage electric motor.

[0010] The electric drive system 200 includes a power modulator 206 configured to draw power from the power source 202 and modulate the power into a form suitable for driving the electric load 204. The power modulator 206 may take any suitable form. Non-limiting examples of such a power modulator include an inverter or a converter. The power modulator 206 includes one or more switching branches 208. Each switching branch 208 includes a plurality of semiconductor switches (e.g., 1 to N) 210 electrically connected in series. Each switching branch 208 may include any suitable number of semiconductor switches. In embodiments including multiple switching branches, the switching branches are electrically connected in parallel. The total number of switching branches and corresponding semiconductor switches in the power modulator 206 depends, for example, on the voltage and power capabilities of the individual semiconductor switches, such that the total number of semiconductor switches cooperatively shares the voltage requirements of the electric load 204. As an example, an electric drive system for a three-phase motor may include three switching branches comprising a three-phase inverter. As another example, an electric drive system for a four-phase motor may include four switching branches that make up a four-phase inverter. Each of these switching branches may include one or more switches. In switching branches that include more than one switch, the switches are connected in series. Note that for DC power input, the electric drive system is an inverter (DC / AC converter). In embodiments where the input is AC, the electric drive system is an AC / AC converter. The principles described herein apply to both DC / AC converters or AC / AC converters, as well as other types of power modulation devices.

[0011] The electric drive system 200 includes an active voltage balancing system 212 configured to actively balance the voltage distribution among the plurality of series semiconductor switches 210 in a branch of the power modulator 206. As used herein, actively balancing the voltage distribution among the plurality of series semiconductor switches in a branch refers to adjusting the drive signals for driving the semiconductor switches to reduce voltage differences across the individual switches, ideally (though not necessarily) so that the voltages across the individual semiconductor switches are equal to one another. Additionally, actively balancing the voltage distribution among the plurality of series semiconductor switches in a branch refers to adjusting the drive signals to reduce time differences, ideally (though not necessarily) so that the switches switch simultaneously. Specifically, the active voltage balancing system 212 is configured to compensate for voltage imbalances among the plurality of semiconductor switches by detecting voltage differences across the plurality of semiconductor switches and adjusting gate drive signals for switching the semiconductor switches based on the voltage differences. The active voltage balancing system 212 is further configured to compensate for asymmetry in the drive signals of the semiconductor switches by detecting differences in the times at which the semiconductor switches switch and adjusting the gate drive signals based on the differences in the times. By implementing these compensation techniques, the voltage distribution among the semiconductor switches can be actively balanced, even at very high switching frequencies. This can improve the operational performance and lifespan of the semiconductor switches compared to semiconductor switches in a power modulation device that do not include such an active voltage balancing system.

[0012] Figure 3 is a circuit diagram illustrating a non-limiting implementation of electric drive system 200 of Figure 2. In the illustrated example, active voltage balancing system 212 is configured to actively balance the voltage distribution across first and second semiconductor switches 210A and 210B, which are electrically connected in series. However, active voltage balancing system 212 may be configured to actively balance the voltage distribution across any suitable number of electrically connected semiconductor switches.

[0013] The active voltage balancing system 212 includes differential voltage logic 300 configured to detect a voltage difference between the first semiconductor switch 210A and the second semiconductor switch 210B. The active voltage balancing system 212 further includes edge capture logic 302 configured to detect a time difference between the first semiconductor switch 210A and the second semiconductor switch 210B. The active voltage balancing system 212 further includes protection logic 304 configured to protect the first and second semiconductor switches 210A, 210B from an overvoltage condition. The differential voltage logic 300, edge capture logic 302, and protection logic 304 may take any suitable form, including any suitable arrangement of electrical components or functionally equivalent hardware.

[0014] The active voltage balancing system 212 further includes a microcontroller 306 configured to control the switching of the first and second semiconductor switches 210A, 210B to actively balance the voltage distribution between the semiconductor switches based on signals received from the differential voltage logic 300 and the edge capture logic 302. The microcontroller 306 may take any suitable form, including various types of hardware, software, and / or firmware.

[0015] The differential voltage logic 300 includes a first resistive voltage divider circuit 308 including a first pair of resistors 308A, 308B in series electrically intermediate the source terminal 310A of the first semiconductor switch 210A and the drain terminal 312B of the second semiconductor switch 210B. The differential voltage logic 300 further includes a second resistive voltage divider circuit 314 including a second pair of resistors 314A, 314B in series electrically intermediate the source terminal 310B of the second semiconductor switch 210B and the drain terminal 312B of the second semiconductor switch 210B. The drain terminal 312B of the second semiconductor switch 210B is electrically connected to a common ground 316. The resistors in the first and second resistive voltage divider circuits 308, 314 are sized to sense half the drain-source voltage across the first and second semiconductor switches 210A, 210B and the drain-source voltage of the second semiconductor switch 210B.

[0016] The differential voltage logic 300 further includes a differential voltage comparator 318 configured to sense half the drain-source voltages of the first and second semiconductor switches 210A, 210B in the first resistive voltage divider network 308 and to sense the drain-source voltage of the second semiconductor switch 210B in the second resistive voltage divider network 314. The differential voltage comparator 318 is configured to output a differential voltage signal 320 to the microcontroller 306. The differential voltage signal 320 indicates the difference between the voltage across the first semiconductor switch 210A and the voltage across the second semiconductor switch 210B.

[0017] In embodiments including more than two semiconductor switches in series, differential voltage logic 300 may include additional sets of electrical components (e.g., resistor dividers, differential voltage comparators) corresponding to each of the additional semiconductor switches to detect the voltage at each additional semiconductor switch. Also, the electrical component arrangements are provided as non-limiting examples, and differential voltage logic 300 may be configured to detect the voltages at different semiconductor switches in any suitable manner.

[0018] The edge capture logic 302 includes a first gate-source voltage transient detector (GVTD) 322A configured to synthesize a first logic signal 324A corresponding to a change in the gate-source voltage of the first semiconductor switch 210A. The first logic signal 324A indicates a transient change in state of the first semiconductor switch 210A between an open state and a closed state. The first gate-source voltage transient detector 322A is configured to send the first logic signal 324A to a first gate voltage edge capture element 326A. The first gate voltage edge capture element 326A is configured to output a first timing signal 328A indicating the time when the first semiconductor switch 210A changes between an open state and a closed state based on the first logic signal 324A. A first signal isolator 330A is disposed electrically intermediate the first gate voltage edge capture element 326A and the microcontroller 306. The first signal isolator 330A is configured to filter the first timing signal 328A and provide a first filtered timing signal 332A to the microcontroller 306. The first signal isolator 330A is configured to electrically isolate the microcontroller 306 from the portion of the edge capture logic 302 that corresponds to the first semiconductor switch 210A.

[0019] The edge capture logic 302 further includes a second gate-source voltage transient detector (GVTD) 322B configured to synthesize a second logic signal 324B corresponding to a change in the gate-source voltage of the second semiconductor switch 210B. The second logic signal 324B indicates a transient state change between an open state and a closed state of the second semiconductor switch 210B. The second gate-source voltage transient detector 322B is configured to send the second logic signal 324B to a second gate voltage edge capture unit 326B. The second gate voltage edge capture unit 326B is configured to output a second timing signal 328B indicating the time when the second semiconductor switch 210B changes between an open state and a closed state based on the second logic signal 324B. A second signal isolator 330B is disposed electrically intermediate the second gate voltage edge capture unit 326B and the microcontroller 306. The second signal isolator 330B is configured to filter the second timing signal 328B and provide a second filtered timing signal 332B to the microcontroller 306. The second signal isolator 330B is configured to electrically isolate the microcontroller 306 from the portion of the edge capture logic 302 that corresponds to the second semiconductor switch 210B.

[0020] The microcontroller 306 generates a first gate drive signal (S H ) and a second gate drive signal (S L ) to control the switching of these switches. H , S L is a pulse width modulated (PWM) signal. The microcontroller 306 includes a modulator 307 configured to output the first signal to a first summing box 333A. The first summing box 333A performs timing adjustments on the first signal based on the first filtered timing signal 332A to generate a first gate drive signal S HThe modulator 307 is configured to output a second signal to a second summing box 333B. The second summing box 333B is configured to make timing adjustments to the second signal based on the second filtered timing signal 332B. The output of the second summing box 333B is sent to a third summing box 333C. The third summing box 333C makes voltage amplitude adjustments based on the differential voltage signal 320 to generate a second gate drive signal S L The illustrated configuration is provided as a non-limiting example, and the microcontroller 306 may have any suitable configuration for implementing such a voltage balancing function.

[0021] The microcontroller 306 is configured to control the first and second gate voltage edge capture units 326A, 326B during each switching cycle of the semiconductor switches 210A, 210B. Specifically, the microcontroller 306 controls the first and second gate voltage edge capture units 326A, 326B when the microcontroller 306 generates the first gate drive signal S H At the same time as outputting the first auxiliary drive signal (S H _ AUX ), and the microcontroller 306 outputs the second gate drive signal S L At the same time as outputting the second auxiliary drive signal (S L _ AUX ) is configured to output the first gate drive signal S H and the first auxiliary drive signal S H _ AUX are filtered by a first signal isolator 330A, and a first filtered gate drive signal 334A is provided to a first gate driver 336A, and a first filtered auxiliary drive signal 338A is provided to a first gate voltage edge capture unit 326A. H and the first auxiliary drive signal S H _ AUX Both of them are at time T PD2The first filtered auxiliary drive signal 338A activates the first gate voltage edge capture unit 326A. The first filtered gate drive signal 334A activates the first gate driver 336A to control the switching of the first semiconductor switch 210A. The first gate drive signal S H is output by the microcontroller 306 until the first gate driver 336A is activated. PD1 and this is the time T PD2 The gate voltage (V DR _ H When the gate voltage edge capture detector 210B rises due to being driven by the first gate driver 336A, the first GVTD 322A detects this voltage change and sends a first logic signal 324A to the first gate voltage edge capture unit 326A. Because the first gate voltage edge capture unit 326A was previously activated due to receiving the first filtered auxiliary drive signal 338A, the first gate voltage edge capture unit 326A can capture the timing of this gate voltage change. The first gate voltage edge capture unit 326A sends this timing information back to the microcontroller 306 in the form of a first timing signal 328A, and then the edge capture detector is deactivated for the remainder of the switching cycle. The portion of the edge capture logic 302 corresponding to the second semiconductor switch 210B is controlled in the same manner as described above during each switching cycle of the second semiconductor switch 210B.

[0022] In embodiments including more than two semiconductor switches in series, the edge capture logic 302 may include an additional set of electrical components (e.g., GVTDs, edge capture detectors, signal isolators, gate drivers) corresponding to each of the additional semiconductor switches to detect the difference between the switching times of that semiconductor switch and the other semiconductor switches. Again, the electrical component arrangements are provided as non-limiting examples, and the edge capture logic 302 may be configured in any suitable manner to detect the difference between the switching times of different semiconductor switches.

[0023] The protection logic 304 includes a first Zener diode 340A and a second Zener diode 340B. The first Zener diode 340A is electrically connected between the drain terminal 312A and the source terminal 310A of the first semiconductor switch 210A. The second Zener diode 340B is electrically connected between the drain terminal 312B and the source terminal 310B of the second semiconductor switch 210B. The first and second Zener diodes 340A and 340B are configured to limit overvoltage to within the breakdown voltages of the series-connected first and second semiconductor switches 210A and 210B in the event of an extreme voltage imbalance, thereby preventing degradation of the switches.

[0024] The microcontroller 306 generates a first gate drive signal S based on the differential voltage signal 320. H and the second gate drive signal S L to compensate for voltage imbalances between the first semiconductor switch 210A and the second semiconductor switch 210B. For example, such voltage imbalances may arise, at least in part, due to differences in the physical parameters of the individual semiconductor switches caused by manufacturing, circuit design, and / or environmental factors. The microcontroller 306 is further configured to adjust the first gate drive signal S based on timing differences between the first and second filtered timing signals 332A, 332B. H and the second gate drive signal S Lto compensate for the asymmetry in the drive signals of the first semiconductor switch 210A and the second semiconductor switch 210B. The microcontroller 306 is configured to adjust the first and second gate drive signals S for the next switching cycle based on the received differential voltage signal 320 and the first and second filtered timing signals 332A, 332B for the current switching cycle. H and S L is configured to adjust

[0025] The microcontroller 306 generates the first and second gate drive signals S in any suitable manner based on the differential voltage signal 320 and the first and second filtered timing signals 332A, 332B. H , S L As an example, the microcontroller 306 may adjust the second gate drive signal S based on the fact that the drain-source voltage of the second semiconductor switch 210B is lower than half the drain-source voltages of the first and second semiconductor switches 210A and 210B during the turn-off transition of the first and second semiconductor switches 210A and 210B. L The timing of the first gate drive signal S H The turn-off transition is initiated in response to the gate voltages of the first and second semiconductor switches 210A, 210B decreasing based on signals received from the first and second gate drivers 336A, 336B.

[0026] As another example, the microcontroller 306 may adjust the first gate drive signal S based on the drain-source voltage of the first semiconductor switch 210A being lower than half the drain-source voltages of the first and second semiconductor switches during the turn-off transitions of the first and second semiconductor switches. H The timing of the second gate drive signal S L The timing is configured to advance relative to the timing of the time.

[0027] As yet another example, the microcontroller 306 may generate the second gate drive signal S based on the drain-source voltage of the second semiconductor switch 210B being higher than half the drain-source voltages of the first and second semiconductor switches during the turn-on transitions of the first and second semiconductor switches. L The timing of the first gate drive signal S H The turn-on transition is initiated in response to the gate voltages of the first and second semiconductor switches 210A, 210B rising based on signals received from the first and second gate drivers 336A, 336B.

[0028] As yet another example, the microcontroller 306 may generate the first gate drive signal S based on the drain-source voltage of the first semiconductor switch 210A being higher than half the drain-source voltages of the first and second semiconductor switches during the turn-on transitions of the first and second semiconductor switches. H The timing of the second gate drive signal S L The timing is configured to advance relative to the timing of the time.

[0029] The above-described adjustments are provided as non-limiting examples performed by the microcontroller 306 to adjust the first and second gate drive signals to actively balance the voltages of the first and second semiconductor switches based on feedback in the form of the differential voltage signal and the timing difference between the first and second timing signals. The microcontroller 306 may be configured to compensate for voltage imbalances and drive signal asymmetries in any suitable manner to balance the voltages of the first and second semiconductor switches.

[0030] FIG. 4 is a flowchart of an exemplary method 400 for actively balancing voltage distribution among multiple semiconductor switches in series in a power modulation device. For example, method 400 may be performed by the microcontroller 306 of the active voltage balancing system 212 for actively balancing the voltages of the first semiconductor 210A and the second semiconductor 210B shown in FIGS. 2-3 . The method 400 includes, at 402, receiving a first timing signal output by a first gate voltage edge capture unit, the first timing signal indicating a time when the first semiconductor switch changes between an open state and a closed state. The method 400 includes, at 404, receiving a second timing signal output by a second gate voltage edge capture unit, the second timing signal indicating a time when the second semiconductor switch changes between an open state and a closed state. The method 400 includes, at 406, receiving a differential voltage signal output by a differential voltage comparator, the differential voltage signal indicating a difference between a first voltage at the first semiconductor switch and a second voltage at the second semiconductor switch. The method 400 includes outputting a first gate drive signal to a first gate driver to control switching of a first semiconductor switch and outputting a second gate drive signal to a second gate driver to control switching of a second semiconductor switch, at 408. The first gate drive signal and the second gate drive signal are adjusted based on the differential voltage signal to compensate for voltage imbalances and based on timing differences between the first timing signal and the second timing signal to compensate for drive signal asymmetries to actively balance the voltages of the first and second semiconductor switches.

[0031] 5 and 6 are flowcharts illustrating an example method 500 for adjusting first and second gate drive signals to actively balance voltage distribution among a plurality of semiconductor switches. For example, method 500 may be performed by the microcontroller 306 of the active voltage balancing system 212 for actively balancing the voltages of the first semiconductor 210A and the second semiconductor 210B shown in FIGS. 2-3 . Method 500 includes, at 502, determining whether a turn-off transient exists for the first and second semiconductor switches. For example, a turn-off transient may occur when the gate voltage of a semiconductor switch goes from high to low. If a turn-off transient exists, method 500 proceeds to 504. Otherwise, method 500 proceeds to 512. Method 500 includes, at 504, determining whether a drain-source voltage of the second semiconductor switch is less than half the drain-source voltages of the first and second semiconductor switches. If the drain-source voltage of the second semiconductor switch is less than half the drain-source voltages of the first and second semiconductor switches, method 500 proceeds to 506. Otherwise, method 500 proceeds to 508. Method 500 includes, at 506, advancing the timing of the second gate drive signal relative to the timing of the first gate drive signal for the next switching cycle to actively balance the voltages of the first and second semiconductor switches. Method 500 includes, at 508, determining whether the drain-source voltage of the first semiconductor switch is less than half the drain-source voltages of the first and second semiconductor switches. If the drain-source voltage of the first semiconductor switch is less than half the drain-source voltages of the first and second semiconductor switches, method 500 proceeds to 510. Otherwise, method 500 proceeds to 512. The method 500 includes advancing the timing of the first gate drive signal relative to the timing of the second gate drive signal for the next switching cycle to actively balance the voltages of the first and second semiconductor switches at 510. As shown in FIG. 6 at 512, the method 500 includes determining whether there is a turn-on transient of the first and second semiconductor switches.For example, a turn-on transient may occur when the gate voltage of a semiconductor switch goes from low to high. If a turn-on transient is determined to exist, method 500 proceeds to 514. Otherwise, method 500 returns. At 514, method 500 includes determining whether the drain-source voltage of the second semiconductor switch is greater than half the drain-source voltages of the first and second semiconductor switches. If the drain-source voltage of the second semiconductor switch is greater than half the drain-source voltages of the first and second semiconductor switches, method 500 proceeds to 516. Otherwise, method 500 proceeds to 518. At 516, method 500 includes advancing the timing of the second gate drive signal relative to the timing of the first gate drive signal for the next switching cycle to actively balance the voltages of the first and second semiconductor switches. The method 500 includes determining, at 518, whether the drain-source voltage of the first semiconductor switch is greater than half the drain-source voltages of the first and second semiconductor switches. If the drain-source voltage of the first semiconductor switch is greater than half the drain-source voltages of the first and second semiconductor switches, the method 500 proceeds to 520. Otherwise, the method 500 returns. The method 500 also includes, at 520, advancing the timing of the first gate drive signal relative to the timing of the second gate drive signal for the next switching cycle to actively balance the voltages of the first and second semiconductor switches.

[0032] The above-described method may be performed to actively balance the voltages of a first semiconductor switch and a second semiconductor switch by adjusting the first and second gate drive signals to compensate for voltage imbalances and drive signal asymmetries. The method may be extended to actively balance the voltages of any suitable number of semiconductor switches connected in series in a power modulation device. The specific methods described herein may represent one or more of any number of processing techniques, such as event-driven, interrupt-driven, multitasking, multithreading, etc. Accordingly, the various illustrated acts, operations, and / or functions may be performed in the illustrated order, in parallel, or in some cases omitted. Similarly, the order of processing is not necessarily required to achieve the features and advantages of the exemplary embodiments described herein, but is presented for ease of illustration and description. One or more of the illustrated acts, operations, and / or functions may be repeatedly performed depending on the particular technique employed.

[0033] 7A-7D are graphs illustrating semiconductor switching with and without the active voltage balancing techniques described herein. FIG. 7A illustrates an example turn-off transient when the gate voltages of the first and second semiconductor switches transition from high to low without active voltage balancing. In this example, the voltage of the first semiconductor switch is greater than the voltage of the second semiconductor switch during the turn-off transition, resulting in a voltage imbalance between the first and second semiconductor switches. FIG. 7B illustrates an example turn-off transient when active voltage balancing is employed. For example, such active voltage balancing may be performed by the active voltage balancing system 212 shown in FIGS. 2 and 3 using the active voltage balancing method 400 shown in FIG. 4 and the active voltage balancing method 500 shown in FIGS. 5 and 6 for actively balancing the voltages of the first and second semiconductor switches. In this example, the voltages of the first and second semiconductor switches are balanced during the turn-off transient state, reducing the voltage difference between the voltages of the individual switches and reducing the difference in the time it takes for the semiconductor switches to switch from the on state to the off state compared to the turn-off transient state shown in FIG. 7A, where such an active voltage balancing technique is not employed.

[0034] FIG. 7C illustrates an example of a turn-on transient when the gate voltages of the first and second semiconductor switches transition from low to high without active voltage balancing. In this example, the voltage of the first semiconductor switch is greater than the voltage of the second semiconductor switch during the turn-on transient, resulting in a voltage imbalance between the first and second semiconductor switches. FIG. 7D illustrates an example of a turn-on transient when active voltage balancing is employed. For example, such active voltage balancing may be performed by the active voltage balancing system 212 illustrated in FIGS. 2 and 3 using the active voltage balancing method 400 illustrated in FIG. 4 and the active voltage balancing method 500 illustrated in FIGS. 5 and 6 for actively balancing the voltages of the first and second semiconductor switches. In this example, the voltages of the first and second semiconductor switches are balanced during the turn-on transient state, reducing the voltage difference between the voltages of the individual switches and reducing the difference in the time it takes for the semiconductor switches to switch from the on state to the off state compared to the turn-off transient state shown in Figure 7C, where such an active voltage balancing technique is not employed.

[0035] In one example, a system includes a power modulation device including a first semiconductor switch and a second semiconductor switch in series with the first semiconductor switch; and an active voltage balancing system, the active voltage balancing system including a first gate driver configured to control switching of the first semiconductor switch between an open state and a closed state; a second gate driver configured to control switching of the second semiconductor switch between an open state and a closed state; a first gate voltage edge capture unit configured to output a first timing signal indicative of a time when the first semiconductor switch changes between the open state and the closed state; a second gate voltage edge capture unit configured to output a second timing signal indicative of a time when the second semiconductor switch changes between the open state and the closed state; a differential voltage comparator configured to output a differential voltage signal indicative of a difference between a first voltage at the first semiconductor switch and a second voltage at the second semiconductor switch; and a microcontroller. the microcontroller is configured to receive the first timing signal output by the first gate voltage edge capture unit, receive the second timing signal output by the second gate voltage edge capture unit, receive the differential voltage signal output by the differential voltage comparator, output a first gate drive signal to the first gate driver to control switching of the first semiconductor switch, and output a second gate drive signal to the second gate driver to control switching of the second semiconductor switch, and the microcontroller is further configured to adjust the first gate drive signal and the second gate drive signal based on the differential voltage signal to compensate for voltage imbalance and to adjust the first gate drive signal and the second gate drive signal based on a timing difference between the first timing signal and the second timing signal to compensate for drive signal asymmetry, in order to actively balance the voltages of the first semiconductor switch and the second semiconductor switch.In this example and / or other examples, the system may further include a first Zener diode electrically intermediate between the source terminal and the drain terminal of the first semiconductor switch and a second Zener diode electrically intermediate between the source terminal and the drain terminal of the second semiconductor switch. In this example and / or other examples, for example, the differential voltage comparator may include a first resistive voltage divider circuit including a first pair of series resistors electrically intermediate between the source terminal of the first semiconductor switch and the drain terminal of the second semiconductor switch, and a second resistive voltage divider circuit including a second pair of series resistors electrically intermediate between the source terminal of the second semiconductor switch and the drain terminal of the second semiconductor switch, the drain terminal of the second semiconductor switch being electrically connected to a common ground, and the differential voltage comparator may be configured to sense half of the drain-source voltages of the first and second semiconductor switches in the first resistive voltage divider circuit as the first voltage and the drain-source voltage of the second semiconductor switch in the second resistive voltage divider circuit as the second voltage, respectively. In this example and / or other examples, the microcontroller may be further configured to advance the timing of the second gate drive signal relative to the timing of the first gate drive signal based on the drain-source voltage of the second semiconductor switch being lower than half the drain-source voltages of the first and second semiconductor switches during a turn-off transition of the first and second semiconductor switches. In this example and / or other examples, the microcontroller may be further configured to advance the timing of the first gate drive signal relative to the timing of the second gate drive signal based on the drain-source voltage of the first semiconductor switch being lower than half the drain-source voltages of the first and second semiconductor switches during a turn-off transition of the first and second semiconductor switches.In this example and / or other examples, the microcontroller may be further configured to advance the timing of the second gate drive signal relative to the timing of the first gate drive signal based on the drain-source voltage of the second semiconductor switch being higher than half the drain-source voltages of the first and second semiconductor switches during a turn-on transition of the first and second semiconductor switches. In this example and / or other examples, the microcontroller may be further configured to advance the timing of the first gate drive signal relative to the timing of the second gate drive signal based on the drain-source voltage of the first semiconductor switch being higher than half the drain-source voltages of the first and second semiconductor switches during a turn-on transition of the first and second semiconductor switches. In this example and / or other examples, the system may further include, for example, a first gate-source voltage transient detector configured to synthesize a first logic signal corresponding to a change in the gate-source voltage of the first semiconductor switch and send the first logic signal to the first gate voltage edge capture unit, the first gate voltage edge capture unit configured to generate the first timing signal based on the first logic signal; and a second gate-source voltage transient detector configured to synthesize a second logic signal corresponding to a change in the gate-source voltage of the second semiconductor switch and send the second logic signal to the second gate voltage edge capture unit, the second gate voltage edge capture unit configured to generate the second timing signal based on the second logic signal.In this example and / or other examples, for example, the microcontroller is further configured to output a first auxiliary drive signal to the first gate voltage edge capture unit simultaneously with the first gate drive signal being output from the microcontroller, and the first gate voltage edge capture unit is configured to be activated based on receiving the first auxiliary drive signal; the microcontroller is further configured to output a second auxiliary drive signal to the second gate voltage edge capture unit simultaneously with the second gate drive signal being output from the microcontroller, and the second gate voltage edge capture unit is configured to be activated based on receiving the second auxiliary drive signal.In this example and / or other examples, for example, the system may further include a first signal isolator electrically intermediate the first gate voltage edge capture unit and the microcontroller and electrically intermediate the first gate driver and the microcontroller, the first signal isolator filtering the first timing signal output by the first gate voltage edge capture unit to provide a first filtered timing signal to the microcontroller, filtering the first gate drive signal output by the microcontroller to provide a first filtered gate drive signal to the first gate driver, and filtering the first auxiliary drive signal output by the microcontroller to provide a first filtered auxiliary drive signal to the first gate voltage edge capture unit. and further including a second signal isolator electrically intermediate the second gate voltage edge capture unit and the microcontroller and electrically intermediate the second gate driver and the microcontroller, wherein the second signal isolator is configured to: filter the second timing signal output by the second gate voltage edge capture unit to provide a second filtered timing signal to the microcontroller; filter the second gate drive signal output by the microcontroller to provide a second filtered gate drive signal to the second gate driver; and filter the second auxiliary drive signal output by the microcontroller to provide a second filtered auxiliary drive signal to the second gate voltage edge capture unit.

[0036] In one example, an active voltage balancing method for controlling a plurality of series semiconductor switches including at least first and second semiconductor switches in a power modulation device includes receiving a first timing signal output by a first gate voltage edge capture unit, the first timing signal indicating a time when the first semiconductor switch changes between an open state and a closed state; receiving a second timing signal output by a second gate voltage edge capture unit, the second timing signal indicating a time when the second semiconductor switch changes between the open state and the closed state; receiving a differential voltage signal output by a differential voltage comparator, the differential voltage signal indicating a time when the second semiconductor switch changes between the open state and the closed state; and outputting a first gate drive signal to a first gate driver to control switching of the first semiconductor switch and a second gate drive signal to a second gate driver to control switching of the second semiconductor switch, the first gate drive signal and the second gate drive signal being adjusted based on the differential voltage signal to compensate for voltage imbalances and based on a timing difference between the first timing signal and the second timing signal to compensate for drive signal asymmetries, to actively balance the voltages of the first and second semiconductor switches. In this and / or other examples, the active voltage balancing method may further, for example, advance the timing of the second gate drive signal relative to the timing of the first gate drive signal based on a drain-to-source voltage of the second semiconductor switch being lower than half the drain-to-source voltages of the first and second semiconductor switches during a turn-off transition of the first and second semiconductor switches. In this example and / or other examples, the active voltage balancing method may further include, for example, advancing the timing of the first gate drive signal relative to the timing of the second gate drive signal based on the drain-source voltage of the first semiconductor switch being lower than half the drain-source voltages of the first and second semiconductor switches during turn-off transitions of the first and second semiconductor switches.In this example and / or other examples, the active voltage balancing method may further include, for example, advancing the timing of the second gate drive signal relative to the timing of the first gate drive signal based on the drain-source voltage of the second semiconductor switch being higher than half the drain-source voltages of the first and second semiconductor switches during turn-on transitions of the first and second semiconductor switches.In this example and / or other examples, the active voltage balancing method may further include, for example, advancing the timing of the first gate drive signal relative to the timing of the second gate drive signal based on the drain-source voltage of the first semiconductor switch being higher than half the drain-source voltages of the first and second semiconductor switches during turn-on transitions of the first and second semiconductor switches.

[0037] In one example, a system includes a power modulation device including a first semiconductor switch and a second semiconductor switch in series with the first semiconductor switch; and an active voltage balancing system, the active voltage balancing system including a first Zener diode electrically intermediate a source terminal and a drain terminal of the first semiconductor switch, a second Zener diode electrically intermediate a source terminal and a drain terminal of the second semiconductor switch, a first gate driver configured to control switching of the first semiconductor switch between an open state and a closed state, a second gate driver configured to control switching of the second semiconductor switch between an open state and a closed state, a first gate voltage edge capture unit configured to output a first timing signal indicative of a time when the first semiconductor switch changes between the open state and the closed state, a second gate voltage edge capture unit configured to output a second timing signal indicative of a time when the second semiconductor switch changes between the open state and the closed state, and a first voltage across the first semiconductor switch and a second voltage across the second semiconductor switch. and a microcontroller configured to receive the first timing signal output by the first gate voltage edge capture unit, receive the second timing signal output by the second gate voltage edge capture unit, receive the differential voltage signal output by the differential voltage comparator, output a first gate drive signal to the first gate driver to control switching of the first semiconductor switch, and output a second gate drive signal to the second gate driver to control switching of the second semiconductor switch, and the microcontroller is further configured to adjust the first gate drive signal and the second gate drive signal to actively balance the voltages of the first semiconductor switch and the second semiconductor switch, thereby compensating for voltage imbalance based on the differential voltage signal and compensating for drive signal asymmetry based on a timing difference between the first timing signal and the second timing signal.In this example and / or other examples, for example, the differential voltage comparator may include a first resistive voltage divider circuit including a first pair of series resistors electrically intermediate the source terminal of the first semiconductor switch and the drain terminal of the second semiconductor switch, and a second resistive voltage divider circuit including a second pair of series resistors electrically intermediate the source terminal of the second semiconductor switch and the drain terminal of the second semiconductor switch, wherein the drain terminal of the second semiconductor switch is electrically connected to a common ground, and the differential voltage comparator is configured to sense half of the drain-source voltages of the first and second semiconductor switches in the first resistive voltage divider circuit as the first voltage and the drain-source voltage of the second semiconductor switch in the second resistive voltage divider circuit as the second voltage, respectively. In this example and / or other examples, for example, the system may further include a first gate-source voltage transient detector configured to synthesize a first logic signal corresponding to a change in the gate-source voltage of the first semiconductor switch and send the first logic signal to the first gate voltage edge capture unit, the first gate voltage edge capture unit configured to generate the first timing signal based on the first logic signal; and a second gate-source voltage transient detector configured to synthesize a second logic signal corresponding to a change in the gate-source voltage of the second semiconductor switch and send the second logic signal to the second gate voltage edge capture unit, the second gate voltage edge capture unit configured to generate the second timing signal based on the second logic signal.In this example and / or other examples, for example, the microcontroller is further configured to output a first auxiliary drive signal to the first gate voltage edge capture unit simultaneously with the first gate drive signal being output from the microcontroller, and the first gate voltage edge capture unit is configured to be activated based on receiving the first auxiliary drive signal; the microcontroller is further configured to output a second auxiliary drive signal to the second gate voltage edge capture unit simultaneously with the second gate drive signal being output from the microcontroller, and the second gate voltage edge capture unit is configured to be activated based on receiving the second auxiliary drive signal.In this example and / or other examples, for example, the system may further include a first signal isolator electrically intermediate the first gate voltage edge capture unit and the microcontroller and electrically intermediate the first gate driver and the microcontroller, the first signal isolator filtering the first timing signal output by the first gate voltage edge capture unit to provide a first filtered timing signal to the microcontroller, filtering the first gate drive signal output by the microcontroller to provide a first filtered gate drive signal to the first gate driver, and filtering the first auxiliary drive signal output by the microcontroller to provide a first filtered auxiliary drive signal to the first gate voltage edge capture unit. and further including a second signal isolator electrically intermediate the second gate voltage edge capture unit and the microcontroller and electrically intermediate the second gate driver and the microcontroller, wherein the second signal isolator is configured to: filter the second timing signal output by the second gate voltage edge capture unit to provide a second filtered timing signal to the microcontroller; filter the second gate drive signal output by the microcontroller to provide a second filtered gate drive signal to the second gate driver; and filter the second auxiliary drive signal output by the microcontroller to provide a second filtered auxiliary drive signal to the second gate voltage edge capture unit.

[0038] The present disclosure includes all novel and non-obvious combinations and subcombinations of the various features and techniques described herein. The various features and techniques disclosed herein are not necessarily required for every embodiment of the present disclosure. Moreover, the various features and techniques disclosed herein may define patentable subject matter apart from the disclosed embodiments or may find utility in other embodiments not expressly disclosed herein.

Claims

1. a first semiconductor switch; a power modulation device including a second semiconductor switch in series with the first semiconductor switch; an active voltage balancing system, wherein the active voltage balancing system a first gate driver configured to control the switching of the first semiconductor switch between an open state and a closed state; a second gate driver configured to control the switching of the second semiconductor switch between an open state and a closed state; a first gate voltage edge capture unit configured to output a first timing signal indicative of a time at which the first semiconductor switch changes between the open state and the closed state; a second gate voltage edge capture unit configured to output a second timing signal indicating a time at which the second semiconductor switch changes between the open state and the closed state; a differential voltage comparator configured to output a differential voltage signal indicative of a difference between a first voltage on the first semiconductor switch and a second voltage on the second semiconductor switch; a microcontroller, the microcontroller comprising: receiving the first timing signal output by the first gate voltage edge capture unit; receiving the second timing signal output by the second gate voltage edge capture unit; receiving the differential voltage signal output by the differential voltage comparator; outputting a first gate driving signal to the first gate driver to control switching of the first semiconductor switch; and outputting a second gate drive signal to the second gate driver to control switching of the second semiconductor switch; the microcontroller is further configured to adjust the first gate drive signal and the second gate drive signal based on the differential voltage signal to compensate for voltage imbalance and based on a timing difference between the first timing signal and the second timing signal to compensate for drive signal asymmetry to actively balance the voltages of the first semiconductor switch and the second semiconductor switch.

2. a first Zener diode electrically intermediate the source and drain terminals of the first semiconductor switch; 10. The system of claim 1, further comprising a second Zener diode electrically intermediate the source and drain terminals of the second semiconductor switch.

3. The differential voltage comparator a first resistive voltage divider circuit including a first pair of resistors in series electrically intermediate the source terminal of the first semiconductor switch and the drain terminal of the second semiconductor switch; a second resistive voltage divider circuit including a second pair of resistors in series electrically intermediate the source terminal of the second semiconductor switch and the drain terminal of the second semiconductor switch; the drain terminal of the second semiconductor switch is electrically connected to a common ground; The differential voltage comparator a voltage that is half the drain-source voltage of the first and second semiconductor switches in the first resistive voltage divider circuit is defined as the first voltage; 3. The system according to claim 1, wherein the system is configured to sense the drain-source voltage of the second semiconductor switch in the second resistive voltage divider circuit as the second voltage.

4. 4. The system of claim 3, wherein the microcontroller is further configured to advance timing of the second gate drive signal relative to timing of the first gate drive signal based on the drain-source voltage of the second semiconductor switch being lower than half of the drain-source voltages of the first and second semiconductor switches during turn-off transitions of the first and second semiconductor switches.

5. 5. The system of claim 3, wherein the microcontroller is further configured to advance the timing of the first gate drive signal relative to the timing of the second gate drive signal based on a drain-source voltage of the first semiconductor switch being lower than half of the drain-source voltages of the first and second semiconductor switches during a turn-off transition of the first and second semiconductor switches.

6. 6. The system according to claim 3, wherein the microcontroller is further configured to advance timing of the second gate drive signal relative to timing of the first gate drive signal based on the drain-source voltage of the second semiconductor switch being higher than half the voltage of the drain-source voltages of the first and second semiconductor switches during turn-on transitions of the first and second semiconductor switches.

7. 7. The system of claim 3, wherein the microcontroller is further configured to advance timing of the first gate drive signal relative to timing of the second gate drive signal based on the drain-source voltage of the first semiconductor switch being higher than half the voltage of the drain-source voltages of the first and second semiconductor switches during turn-on transitions of the first and second semiconductor switches.

8. a first gate-source voltage transient detector configured to synthesize a first logic signal corresponding to a change in a gate-source voltage of the first semiconductor switch and send the first logic signal to the first gate voltage edge capture unit, the first gate voltage edge capture unit configured to generate the first timing signal based on the first logic signal; 8. The system of claim 1, further comprising a second gate-source voltage transient detector configured to synthesize a second logic signal corresponding to a change in the gate-source voltage of the second semiconductor switch and send the second logic signal to the second gate voltage edge capture unit, wherein the second gate voltage edge capture unit is configured to generate the second timing signal based on the second logic signal.

9. the microcontroller is further configured to output a first auxiliary drive signal to the first gate voltage edge capture unit simultaneously with the first gate drive signal being output from the microcontroller, and the first gate voltage edge capture unit is configured to be activated based on receiving the first auxiliary drive signal; 9. The system of claim 8, wherein the microcontroller is further configured to output a second auxiliary drive signal to the second gate voltage edge capture unit simultaneously with the second gate drive signal being output from the microcontroller, and the second gate voltage edge capture unit is configured to be activated based on receiving the second auxiliary drive signal.

10. the first signal isolator is electrically intermediate the first gate voltage edge capture unit and the microcontroller and electrically intermediate the first gate driver and the microcontroller, the first signal isolator is configured to filter the first timing signal output by the first gate voltage edge capture unit to provide a first filtered timing signal to the microcontroller, filter the first gate drive signal output by the microcontroller to provide a first filtered gate drive signal to the first gate driver, and filter the first auxiliary drive signal output by the microcontroller to provide a first filtered auxiliary drive signal to the first gate voltage edge capture unit; 10. The system of claim 9, further comprising a second signal isolator electrically intermediate the second gate voltage edge capture unit and the microcontroller and electrically intermediate the second gate driver and the microcontroller, the second signal isolator configured to: filter the second timing signal output by the second gate voltage edge capture unit to provide a second filtered timing signal to the microcontroller; filter the second gate drive signal output by the microcontroller to provide a second filtered gate drive signal to the second gate driver; and filter the second auxiliary drive signal output by the microcontroller to provide a second filtered auxiliary drive signal to the second gate voltage edge capture unit.

11. 1. An active voltage balancing method for controlling a plurality of series semiconductor switches, including at least first and second semiconductor switches, in a power modulation device, the active voltage balancing method comprising: receiving a first timing signal output by a first gate voltage edge capture unit, the first timing signal indicating a time when the first semiconductor switch changes between an open state and a closed state; receiving a second timing signal output by a second gate voltage edge capture unit, the second timing signal indicating a time when the second semiconductor switch changes between the open state and the closed state; receiving a differential voltage signal output by a differential voltage comparator, the differential voltage signal indicating a difference between a first voltage on the first semiconductor switch and a second voltage on the second semiconductor switch; outputting a first gate driving signal to a first gate driver to control switching of the first semiconductor switch; outputting a second gate driving signal to a second gate driver to control switching of the second semiconductor switch; the first gate drive signal and the second gate drive signal are adjusted based on the differential voltage signal to compensate for voltage imbalances and based on timing differences between the first timing signal and the second timing signal to compensate for drive signal asymmetries to actively balance voltages across the first and second semiconductor switches.

12. 12. The active voltage balancing method of claim 11, further comprising: advancing a timing of the second gate drive signal relative to a timing of the first gate drive signal based on a drain-source voltage of the second semiconductor switch being lower than half a voltage of the drain-source voltages of the first and second semiconductor switches during a turn-off transition of the first and second semiconductor switches.

13. 13. The active voltage balancing method according to claim 11 or 12, further comprising: advancing a timing of the first gate drive signal relative to a timing of the second gate drive signal based on a drain-source voltage of the first semiconductor switch being lower than half a voltage of the drain-source voltages of the first and second semiconductor switches during a turn-off transition of the first and second semiconductor switches.

14. 14. The active voltage balancing method according to claim 11, further comprising: advancing a timing of the second gate drive signal relative to a timing of the first gate drive signal based on a drain-source voltage of the second semiconductor switch being higher than half a voltage of the drain-source voltages of the first and second semiconductor switches during a turn-on transition of the first and second semiconductor switches.

15. 15. The active voltage balancing method according to claim 11, further comprising: advancing a timing of the first gate drive signal relative to a timing of the second gate drive signal based on a drain-source voltage of the first semiconductor switch being higher than half a voltage of the drain-source voltages of the first and second semiconductor switches during a turn-on transition of the first and second semiconductor switches.

16. a first semiconductor switch; a power modulation device including a second semiconductor switch in series with the first semiconductor switch; an active voltage balancing system, wherein the active voltage balancing system a first Zener diode electrically intermediate the source and drain terminals of the first semiconductor switch; a second Zener diode electrically intermediate the source and drain terminals of the second semiconductor switch; a first gate driver configured to control the switching of the first semiconductor switch between an open state and a closed state; a second gate driver configured to control the switching of the second semiconductor switch between an open state and a closed state; a first gate voltage edge capture unit configured to output a first timing signal indicative of a time at which the first semiconductor switch changes between the open state and the closed state; a second gate voltage edge capture unit configured to output a second timing signal indicating a time at which the second semiconductor switch changes between the open state and the closed state; a differential voltage comparator configured to output a differential voltage signal indicative of a difference between a first voltage on the first semiconductor switch and a second voltage on the second semiconductor switch; a microcontroller, the microcontroller comprising: receiving the first timing signal output by the first gate voltage edge capture unit; receiving the second timing signal output by the second gate voltage edge capture unit; receiving the differential voltage signal output by the differential voltage comparator; outputting a first gate driving signal to the first gate driver to control switching of the first semiconductor switch; and outputting a second gate drive signal to the second gate driver to control switching of the second semiconductor switch; the microcontroller is further configured to adjust the first gate drive signal and the second gate drive signal to actively balance the voltages of the first semiconductor switch and the second semiconductor switch to compensate for voltage imbalances based on the differential voltage signal and to compensate for drive signal asymmetries based on timing differences between the first timing signal and the second timing signal.

17. The differential voltage comparator a first resistive voltage divider circuit including a first pair of resistors in series electrically intermediate the source terminal of the first semiconductor switch and the drain terminal of the second semiconductor switch; a second resistive voltage divider circuit including a second pair of resistors in series electrically intermediate the source terminal of the second semiconductor switch and the drain terminal of the second semiconductor switch; the drain terminal of the second semiconductor switch is electrically connected to a common ground; The differential voltage comparator a voltage that is half the drain-source voltage of the first and second semiconductor switches in a first resistive voltage divider circuit is defined as the first voltage; 17. The system of claim 16, further configured to sense the drain-source voltage of the second semiconductor switch in the second resistor divider circuit as the second voltage.

18. a first gate-source voltage transient detector configured to synthesize a first logic signal corresponding to a change in a gate-source voltage of the first semiconductor switch and send the first logic signal to the first gate voltage edge capture unit, the first gate voltage edge capture unit configured to generate the first timing signal based on the first logic signal; 18. The system of claim 16, further comprising a second gate-source voltage transient detector configured to synthesize a second logic signal corresponding to a change in a gate-source voltage of the second semiconductor switch and send the second logic signal to the second gate voltage edge capture unit, wherein the second gate voltage edge capture unit is configured to generate the second timing signal based on the second logic signal.

19. The microcontroller Furthermore, a first auxiliary driving signal is output to the first gate voltage edge capture unit at the same time as the first gate driving signal is output from the microcontroller, and the first gate voltage edge capture unit is configured to be activated based on receiving the first auxiliary driving signal; The system of any one of claims 16 to 18, wherein the microcontroller is further configured to output a second auxiliary drive signal to the second gate voltage edge capture unit simultaneously with the second gate drive signal being output from the microcontroller, and the second gate voltage edge capture unit is configured to be activated based on receiving the second auxiliary drive signal.

20. the first signal isolator is electrically intermediate the first gate voltage edge capture unit and the microcontroller and electrically intermediate the first gate driver and the microcontroller, the first signal isolator is configured to filter the first timing signal output by the first gate voltage edge capture unit to provide a first filtered timing signal to the microcontroller, filter the first gate drive signal output by the microcontroller to provide a first filtered gate drive signal to the first gate driver, and filter the first auxiliary drive signal output by the microcontroller to provide a first filtered auxiliary drive signal to the first gate voltage edge capture unit; 20. The system of claim 19, further comprising a second signal isolator electrically intermediate the second gate voltage edge capture unit and the microcontroller and electrically intermediate the second gate driver and the microcontroller, the second signal isolator configured to: filter the second timing signal output by the second gate voltage edge capture unit to provide a second filtered timing signal to the microcontroller; filter the second gate drive signal output by the microcontroller to provide a second filtered gate drive signal to the second gate driver; and filter the second auxiliary drive signal output by the microcontroller to provide a second filtered auxiliary drive signal to the second gate voltage edge capture unit.

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