Method for manufacturing nitride semiconductor light emitting device

Abstract

A method for manufacturing a nitride semiconductor light-emitting device is provided that can improve the crystallinity of an n-type semiconductor layer when the V / III ratio during film formation of the n-type semiconductor layer is relatively low. The method for manufacturing a nitride semiconductor light-emitting device 1 is a method for manufacturing a nitride semiconductor light-emitting device 1 in which a substrate 2, an n-type semiconductor layer 4, an active layer 5, and a p-type semiconductor layer 7 are stacked in this order. The method for manufacturing the nitride semiconductor light-emitting device 1 is to III [μmol / min] vs. the flow rate F of the source gas of group V elements v [μmol / min] ratio F v / F III is defined as the V / III ratio, the V / III ratio when the n-type semiconductor layer 4 is formed is less than 95.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a nitride semiconductor light-emitting device. [Background technology]

[0002] Patent Documents 1 and 2 disclose methods for manufacturing a nitride semiconductor light-emitting device in which a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked in this order. In the method for manufacturing a nitride semiconductor light-emitting device disclosed in Patent Document 1, the V / III ratio when forming the n-type semiconductor layer is set to 400 or more and 2500 or less in order to improve the crystallinity of the n-type semiconductor layer. In the method for manufacturing a nitride semiconductor light-emitting device disclosed in Patent Document 2, the V / III ratio when forming the n-type semiconductor layer is set to 10000 or less in order to improve the crystallinity of the n-type semiconductor layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-25253 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-181673 Summary of the Invention [Problem to be solved by the invention]

[0004] As in the manufacturing methods of nitride semiconductor light-emitting devices described in Patent Documents 1 and 2, conventionally, when forming an n-type semiconductor layer, V / III is usually set relatively high, and no consideration is given to the case where V / III is relatively low.

[0005] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a nitride semiconductor light-emitting device that can improve the crystallinity of an n-type semiconductor layer when the V / III ratio during film formation of the n-type semiconductor layer is relatively low. [Means for solving the problem]

[0006] In order to achieve the above object, the present invention provides a method for manufacturing a nitride semiconductor light-emitting device in which a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked in this order, the method comprising the steps of: The n-type semiconductor layer is n-Al q Ga 1-q N (25%≦q≦70%), and the active layer emits ultraviolet light having a center wavelength of 200 nm or more and 365 nm or less, Flow rate of source gas of group III elements F III [μmol / min] vs. the flow rate F of the source gas of group V elements v [μmol / min] ratio F v / F III is defined as the V / III ratio, the V / III ratio when the n-type semiconductor layer is formed is less than 95. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a method for manufacturing a nitride semiconductor light-emitting device that can improve the crystallinity of an n-type semiconductor layer when the V / III ratio during film formation of the n-type semiconductor layer is relatively low. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram illustrating a configuration of a nitride semiconductor light emitting device according to an embodiment. [Figure 2] 10 is a graph showing the AlN mix value of each sample in an experimental example. [Figure 3] 10 is a graph showing the n-AlGaN mix value of each sample in an experimental example. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Embodiment Mode] An embodiment of the present invention will be described with reference to Fig. 1. The embodiment described below is shown as a preferred specific example for carrying out the present invention, and although various technically preferable technical matters are specifically exemplified, the technical scope of the present invention is not limited to this specific embodiment.

[0010] (Nitride semiconductor light emitting device 1) This embodiment relates to a method for manufacturing a nitride semiconductor light emitting device 1. First, a nitride semiconductor light emitting device 1 manufactured by the manufacturing method of this embodiment will be described.

[0011] FIG. 1 is a schematic diagram illustrating the configuration of a nitride semiconductor light-emitting device 1 to be manufactured. Note that in FIG. 1, the dimensional ratios of the layers in the nitride semiconductor light-emitting device 1 (hereinafter also simply referred to as "light-emitting device 1") in the stacking direction do not necessarily match the actual ones. Hereinafter, the stacking direction of the layers in the light-emitting device 1 will be referred to as the vertical direction. Also, one side in the vertical direction, on which the semiconductor layers of the substrate 2 are grown (e.g., the upper side in FIG. 1), will be referred to as the upper side, and the opposite side (e.g., the lower side in FIG. 1) will be referred to as the lower side. Note that the expressions "upper" and "lower" are used for convenience and do not limit the orientation of the light-emitting device 1 relative to the vertical direction, for example, when the light-emitting device 1 is in use.

[0012] The light-emitting element 1 is, for example, a light-emitting diode (LED) or a semiconductor laser (LD: Laser Diode). In this embodiment, the light-emitting element 1 is a light-emitting diode that emits light with a wavelength in the ultraviolet region. In particular, the light-emitting element 1 of this embodiment emits ultraviolet light having a central wavelength of 200 nm or more and 365 nm or less, and more preferably emits deep ultraviolet light having a central wavelength of 200 nm or more and 300 nm or less. The light-emitting element 1 of this embodiment can be used in fields such as sterilization (e.g., air purification, water purification, etc.), medical care (e.g., phototherapy, measurement and analysis, etc.), UV curing, etc.

[0013] The light-emitting element 1 includes a buffer layer 3, an n-type semiconductor layer 4, an active layer 5, an electron blocking layer 6, and a p-type semiconductor layer 7, which are arranged in this order on a substrate 2. The light-emitting element 1 also includes an n-side electrode 8 provided on the n-type semiconductor layer 4, and a p-side electrode 9 provided on the p-type semiconductor layer 7. Note that, although the configuration of the light-emitting element 1 will be described below, the configuration of each layer of the light-emitting element 1 is merely an example, and various modifications are possible.

[0014] The semiconductor constituting the light emitting element 1 is, for example, Al a Ga b In 1-a-b In this embodiment, a group III nitride semiconductor having two to four elements represented by the formula N (0≦a≦1, 0≦b≦1, 0≦a+b≦1) can be used. c Ga 1-c The semiconductor material uses a binary or ternary group III nitride semiconductor represented by N (0≦c≦1). Some of these group III elements may be replaced with boron (B), thallium (Tl), etc. Also, some of the nitrogen may be replaced with phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc.

[0015] The substrate 2 is made of a material that transmits the light emitted by the active layer 5. The substrate 2 is, for example, a sapphire (Al2O3) substrate. The upper surface of the substrate 2 (i.e., the surface on which the semiconductor layers of the light-emitting element 1 are stacked) is a c-plane. This c-plane may have an off-angle. Alternatively, the substrate 2 may be, for example, an aluminum nitride (AlN) substrate or an aluminum gallium nitride (AlGaN) substrate. When the substrate 2 is an aluminum gallium nitride substrate, its Al composition ratio is preferably 80% or more. The Al composition ratio is also referred to as the AlN mole fraction.

[0016] The buffer layer 3 is formed on the substrate 2. In this embodiment, the buffer layer 3 is made of aluminum nitride. When the substrate 2 is an aluminum nitride substrate or an aluminum gallium nitride substrate, the buffer layer 3 is not necessarily provided. The buffer layer 3 may also be made of undoped Al gallium nitride formed on a semiconductor layer made of aluminum nitride. p Ga 1-p It may include a semiconductor layer made of N (0≦p≦1).

[0017] The n-type semiconductor layer 4 is an n-type cladding layer formed on the buffer layer 3. The n-type semiconductor layer 4 is, for example, Al doped with n-type impurities. q Ga 1-qIt is formed by N (0 ≦ q ≦ 1). In this embodiment, silicon (Si) is used as the n-type impurity. Note that as the n-type impurity, germanium (Ge), selenium (Se), tellurium (Te), or the like may be used. The Al composition ratio q of the n-type semiconductor layer 4 can be, for example, 20% or more, more specifically, 25% or more and 70% or less. The absolute value of the difference in the Al composition ratio between the n-type semiconductor layer 4 and the buffer layer 3 is preferably 70% or less. The film thickness of the n-type semiconductor layer 4 can be, for example, 1 μm or more and 4 μm or less.

[0018] The n-type semiconductor layer 4 may have a single-layer structure or a multi-layer structure. When the n-type semiconductor layer 4 has a multi-layer structure, the uppermost semiconductor layer of the n-type semiconductor layer 4 may be a composition gradient layer in which the Al composition ratio increases with the upper position.

[0019] The active layer 5 is formed on the n-type semiconductor layer 4. The active layer 5 has a multiple quantum well structure having a plurality of well layers 521 to 523. The bandgap of the active layer 5 is adjusted so that it can emit ultraviolet light with a central wavelength of 200 nm or more and 365 nm or less, more specifically, deep ultraviolet light of 200 nm or more and 300 nm or less.

[0020] In this embodiment, the active layer 5 has three barrier layers 51 and three well layers 521 to 523, and the barrier layers 51 and the well layers 521 to 523 are alternately laminated. In the active layer 5, the lowermost semiconductor layer is the barrier layer 51, and the uppermost semiconductor layer is the well layer 523. Note that the number of the barrier layers 51 and the number of the well layers 521 to 523 of the active layer 5 are not particularly limited.

[0021] Each barrier layer 51 is formed by Al r Ga 1-r N (0 <r <1). The Al composition ratio r of each barrier layer 51 is, for example, 75% or more and 95% or less. Also, the film thickness of each barrier layer 51 is, for example, 2 nm or more and 50 nm or less.

[0022] The well layers 521 to 523 are Al s Ga 1-sIt is formed by N(0 < s < 1). The Al composition ratio s of each well layer 521 - 523 is smaller than the Al composition ratio r of the barrier layer 51 (i.e., s < r).

[0023] The three well layers 521 - 523 shall be called the first well layer 521, the second well layer 522, and the third well layer 523 in order from the bottom. The film thickness of the first well layer 521 is 1 nm or more greater than the respective film thicknesses of the second well layer 522 and the third well layer 523. Thereby, each semiconductor layer of the active layer 5 is planarized, and the monochromaticity of the output light is improved. The difference between the film thickness of the first well layer 521 and the respective film thicknesses of the second well layer 522 and the third well layer 523 is preferably 2 nm or more and 4 nm or less. In this embodiment, each of the second well layer 522 and the third well layer 523 has a film thickness of 2 nm or more and 4 nm or less, and the first well layer 521 has a film thickness of 4 nm or more and 6 nm or less.

[0024] Also, the Al composition ratio of the first well layer 521 is 2% or more greater than the respective Al composition ratios of the second well layer 522 and the third well layer 523. By making the Al composition ratio of the first well layer 521 greater than the respective Al composition ratios of the second well layer 522 and the third well layer 523, the crystallinity of the first well layer 521 is improved. This is because the difference in the Al composition ratio between the first well layer 521 and the n-type semiconductor layer 4 becomes smaller. When the crystallinity of the first well layer 521 is improved, the crystallinity of each semiconductor layer formed on the first well layer 521 in the active layer 5 is also improved. Thereby, the mobility of carriers in the active layer 5 is improved, and the light emission output is improved. Such an effect is more remarkable as the film thickness of the first well layer 521 increases, but the film thickness of the first well layer 521 is designed to be below a predetermined value from the viewpoint of suppressing an increase in the electrical resistance value of the entire light emitting element 1.

[0025] In this embodiment, each of the second well layer 522 and the third well layer 523 has an Al composition ratio of 25% or more and 45% or less, and the first well layer 521 has an Al composition ratio of 35% or more and 55% or less. The plurality of well layers 521 - 523 may be configured such that, for example, the Al composition ratio increases as the lower ones are.

[0026] The active layer 5 contains silicon. As will be described later, in this embodiment, no silicon source is supplied during the formation of the active layer 5, and silicon present in each semiconductor layer of the active layer 5 is diffused from semiconductor layers below the active layer 5 of the light-emitting element 1. Silicon in the active layer 5 tends to be particularly easily incorporated into positions in the active layer 5 with a low Al composition ratio among the positions in the vertical direction, and also tends to be easily incorporated into layers of the active layer 5 that are close to the n-type semiconductor layer 4.

[0027] The silicon concentration of each barrier layer 51 increases as the layer approaches the n-type semiconductor layer 4, and similarly, the silicon concentration of each well layer 521-523 increases as the layer approaches the n-type semiconductor layer 4. In this embodiment, of the silicon concentrations of the semiconductor layers of the active layer 5, the first well layer 521, which is the well layer of the multiple well layers 521-523 closest to the n-type semiconductor layer 4, has the highest silicon concentration. The maximum value of the silicon concentration distribution of the active layer 5 in the vertical direction is 8.0×10 18 atoms / cm 3 More than 1.0×10 is preferable. 19 atoms / cm 3 Over 6.0 x 10 19 atoms / cm 3 The following is preferable: It has been confirmed that the light output of the light emitting element 1 is likely to improve when the maximum value of the silicon concentration distribution in the active layer 5 in the vertical direction is within the above-mentioned numerical range.

[0028] The active layer 5 has a plurality of pits (for example, so-called V pits) (not shown). As will be described later, during the manufacture of the light-emitting element 1, a silicon source is supplied into the chamber before the active layer 5 is formed (specifically, after the n-type semiconductor layer 4 is formed and before the active layer 5 is formed), which changes the growth mode of the mother phase of the semiconductor layer and forms pits in the active layer 5. The formation of pits in the active layer 5 is thought to facilitate the supply of holes from the p-type semiconductor layer 7 to the active layer 5 through the pits, thereby improving the light emission output of the light-emitting element 1. Furthermore, the inclusion of silicon in the active layer 5 is thought to facilitate the induction of pit formation in the active layer 5.

[0029] The electron blocking layer 6 is formed on the active layer 5. The electron blocking layer 6 has a role of improving the efficiency of electron injection into the active layer 5 by suppressing the occurrence of an overflow phenomenon in which electrons leak from the active layer 5 to the p-type semiconductor layer 7 side (hereinafter also referred to as the electron blocking effect). In this embodiment, the electron blocking layer 6 is made of undoped Al t Ga 1-t N (0.7≦t≦1). That is, the electron blocking layer 6 is composed of a semiconductor layer with an Al composition ratio t of 70% or more. The electron blocking layer 6 has a layered structure in which a first electron blocking layer 61 and a second electron blocking layer 62 are layered in this order from the active layer 5 side.

[0030] The first electron blocking layer 61 is provided so as to be in contact with the active layer 5. Of the multiple semiconductor layers (the first electron blocking layer 61 and the second electron blocking layer 62 in this embodiment) constituting the electron blocking layer 6, the first electron blocking layer 61 has a higher Al composition ratio than the other semiconductor layers (i.e., the second electron blocking layer 62) constituting the electron blocking layer 6 and the barrier layer 51. The Al composition ratio of the first electron blocking layer 61 is, for example, 90% or more and may be 100% (i.e., the first electron blocking layer 61 may be made of AlN). The film thickness of the first electron blocking layer 61 is, for example, 0.5 nm or more and 5.0 nm or less.

[0031] The Al composition ratio of the second electron blocking layer 62 is smaller than that of the first electron blocking layer 61, for example, 70% to 90%. The film thickness of the second electron blocking layer 62 is larger than that of the first electron blocking layer 61, for example, 15 nm to 100 nm.

[0032] Since the electrical resistance of a semiconductor layer increases as the Al composition ratio increases, increasing the thickness of the first electron blocking layer 61, which has a relatively high Al composition ratio, too much increases the overall electrical resistance of the light-emitting element 1. Therefore, it is preferable to reduce the thickness of the first electron blocking layer 61 to a certain extent. On the other hand, reducing the thickness of the first electron blocking layer 61 may increase the probability that electrons will pass through the first electron blocking layer 61 from the active layer 5 side to the p-type semiconductor layer 7 side due to the tunneling effect. Therefore, in the light-emitting element 1 of this embodiment, the second electron blocking layer 62 is formed on the first electron blocking layer 61 to prevent electrons from passing through the entire electron blocking layer 61.

[0033] Each of the first electron blocking layer 61 and the second electron blocking layer 62 can be an undoped layer, a layer containing n-type impurities, a layer containing p-type impurities, or a layer containing both n-type and p-type impurities. Magnesium (Mg) can be used as the p-type impurity, but other elements such as zinc (Zn), beryllium (Be), calcium (Ca), strontium (Sr), barium (Ba), and carbon (C) can also be used. The same applies to semiconductor layers containing other p-type impurities. When each electron blocking layer 6 contains an impurity, the impurity may be contained in the entire electron blocking layer 6 or in part of the electron blocking layer 6. Furthermore, the electron blocking layer 6 may be formed as a single layer, or may be formed as three or more layers, or may be omitted.

[0034] The p-type semiconductor layer 7 is formed on the electron blocking layer 6. The p-type semiconductor layer 7 is made of p-type Al u Ga 1-u N (0≦u<0.7) That is, the p-type semiconductor layer 7 is made of a semiconductor layer in which the Al composition ratio u is less than 70%.

[0035] The p-type semiconductor layer 7 has a p-type contact layer. The p-type contact layer is a layer to which a p-side electrode 9 is connected, and is made of Al doped with a high concentration of p-type impurities. u Ga 1-uThe p-type contact layer is formed of N (0≦u<0.7). The p-type contact layer is configured to have a low Al composition ratio in order to achieve ohmic contact with the p-side electrode 9, and from this perspective, it is preferably formed of p-type gallium nitride (GaN). Since a semiconductor layer made of p-type gallium nitride easily absorbs ultraviolet light, from the perspective of preventing absorption of ultraviolet light and improving the light output of the light-emitting element 1, the thickness of the p-type contact layer is preferably 30 nm or less. Furthermore, from the perspective of suppressing the occurrence of short circuits, the thickness of the p-type contact layer is preferably 5 nm or more.

[0036] The p-type semiconductor layer 7 may further include a p-type cladding layer on the electron block layer 6 side of the p-type contact layer. The p-type cladding layer is composed of p-type AlGaN with an Al composition ratio of less than 70%. The p-type cladding layer may be composed of, for example, a single layer or multiple layers. When the p-type cladding layer is composed of multiple layers, for example, the p-type cladding layer may have a first p-type cladding layer formed on the second electron block layer 62 side and a second p-type cladding layer formed between the first p-type cladding layer and the p-type contact layer. The Al composition ratio at each position in the vertical direction of the second p-type cladding layer may decrease toward the p-type contact layer. Note that the second p-type cladding layer may include a region in which the Al composition ratio does not increase toward the p-type contact layer, for example, in a very small vertical region (for example, a region of 5% or less of the entire vertical direction of the second p-type cladding layer). The Al composition ratio of the second p-type cladding layer at its end on the first p-type cladding layer side is preferably approximately the same (for example, within a difference of 5%) as the Al composition ratio of the first p-type cladding layer at its end on the second p-type cladding layer side.Furthermore, the Al composition ratio of the second p-type cladding layer at its end on the p-type contact layer side is preferably approximately the same (for example, within a difference of 5%) as the Al composition ratio of the p-type contact layer at its end on the second p-type cladding layer side.

[0037] The n-side electrode 8 is formed on an exposed surface 41 that is formed on the upper side of the n-type semiconductor layer 4 and is exposed from the active layer 5. The n-side electrode 8 may be, for example, a multilayer film in which titanium (Ti), aluminum, titanium, and gold (Au) are laminated in this order on the n-type semiconductor layer 4. Furthermore, when the light-emitting element 1 is flip-chip mounted as described below, the n-side electrode 8 may be made of a material that can reflect ultraviolet light emitted from the active layer 5.

[0038] The p-side electrode 9 is formed on the upper surface of the p-type semiconductor layer 7. The p-side electrode 9 can be made of, for example, indium tin oxide (ITO). Furthermore, when the light-emitting element 1 is flip-chip mounted as described below, the p-side electrode 9 may be made of a material capable of reflecting ultraviolet light emitted from the active layer 5.

[0039] The light-emitting element 1 can be flip-chip mounted on a package substrate (not shown). That is, the side of the light-emitting element 1 on which the n-side electrode 8 and the p-side electrode 9 are provided in the vertical direction faces the package substrate, and the n-side electrode 8 and the p-side electrode 9 are mounted on the package substrate via gold bumps or the like. In the flip-chip mounted light-emitting element 1, light is extracted from the substrate 2 side. However, this is not limited thereto, and the light-emitting element may also be mounted on the package substrate by wire bonding or the like. In addition, in this embodiment, the light-emitting element 1 is a so-called horizontal light-emitting element in which both the n-side electrode 8 and the p-side electrode 9 are provided on the upper side of the light-emitting element 1, but this is not limited thereto, and the light-emitting element may also be a vertical light-emitting element. A vertical light-emitting element is a light-emitting element in which an active layer is sandwiched between an n-side electrode and a p-side electrode. When the light-emitting element is vertical, the substrate and buffer layer are preferably removed by laser lift-off or the like.

[0040] (Method of manufacturing the light-emitting element 1) Next, a method for manufacturing the light emitting device 1 of this embodiment will be described. In this embodiment, a buffer layer 3, an n-type semiconductor layer 4, an active layer 5, an electron blocking layer 6, and a p-type semiconductor layer 7 are epitaxially grown in this order on a substrate 2 by metal organic chemical vapor deposition (MOCVD). Note that the MOCVD method is also sometimes called metal organic vapor phase epitaxy (MOVPE).

[0041] When manufacturing the light-emitting element 1, the substrate 2 is placed on a susceptor in a chamber (not shown), and raw material gases are introduced into the chamber while the susceptor is rotating, thereby growing each semiconductor layer on the substrate 2. As raw material gases for epitaxially growing each semiconductor layer, trimethylaluminum (TMA) as an aluminum source, trimethylgallium (TMG) as a gallium source, ammonia (NH3) as a nitrogen source, tetramethylsilane (TMSi) as a silicon source, and biscyclopentadienylmagnesium (Cp2Mg) as a magnesium source can be used.

[0042] In this embodiment, the value of the V / III ratio during the deposition of the n-type semiconductor layer 4 is devised to improve the crystallinity of the n-type semiconductor layer 4. Here, the V / III ratio is the flow rate F of the source gas of the group III element during the deposition of each semiconductor layer. III [μmol / min] vs. the flow rate F of the source gas of group V elements v [μmol / min] ratio F v / F III In this embodiment, the V / III ratio during deposition of the n-type semiconductor layer 4 is the ratio of the flow rate [μmol / min] of ammonia to the total flow rate [μmol / min] of trimethylaluminum and trimethylgallium.

[0043] Since the n-type semiconductor layer 4 is located below the active layer 5 and serves as a base layer for the active layer 5, improving the crystallinity of the n-type semiconductor layer 4 is desirable from the viewpoint of improving the crystallinity of the active layer 5 and, ultimately, improving the light output of the light-emitting element 1. In this embodiment, the V / III ratio of the n-type semiconductor layer 4 as formed is less than 95. Furthermore, to further improve the crystallinity of the n-type semiconductor layer 4, the V / III ratio is preferably 25 or more and less than 95, and more preferably 25 or more and 46 or less. These numerical values ​​are supported by experimental examples described later. Note that, when the n-type semiconductor layer 4 is composed of multiple layers, it is sufficient that the V / III ratio of each semiconductor layer constituting the n-type semiconductor layer 4 as formed satisfies the aforementioned numerical range.

[0044] In the method for manufacturing the light-emitting element 1 of this embodiment, a silicon source is not supplied into the chamber when the active layer 5 is formed, and silicon supplied before the active layer 5 is diffused into the active layer 5. In this embodiment, for example, a silicon source is supplied into the chamber when the n-type semiconductor layer 4 is formed and immediately before the active layer 5 is formed. Immediately before the active layer 5 is formed, only the silicon source is supplied into the chamber as a source gas, and this process is hereinafter referred to as a "silicon source supply process." In the silicon source supply process, it is sufficient that only the silicon source is supplied into the chamber as a source gas, and gases other than the source gas (e.g., a carrier gas such as hydrogen) may be introduced into the chamber. For example, the amount of silicon source supplied in the silicon source supply process is adjusted to adjust the amount of silicon contained in each semiconductor layer of the active layer 5. In addition, in the silicon source supply process, supplying the silicon source to locations where dislocations exist changes the growth mode of the parent phase of the semiconductor layer, resulting in the formation of pits during the formation of the active layer 5.

[0045] Other manufacturing conditions can be adjusted as appropriate to obtain a light-emitting device 1 having desired performance.

[0046] It should be noted that when epitaxially growing a semiconductor layer on the substrate 2, other epitaxial growth methods such as molecular beam epitaxy (MBE) and hydride vapor phase epitaxy (HVPE) can also be used.

[0047] (Actions and Effects of the Embodiments) In the manufacturing method of the light-emitting element 1 of this embodiment, the V / III ratio when forming the n-type semiconductor layer 4 is less than 95. This makes it possible to obtain an n-type semiconductor layer 4 with good crystallinity even if the V / III ratio when forming the n-type semiconductor layer 4 is relatively low. Furthermore, by setting the V / III ratio when forming the n-type semiconductor layer 4 to be equal to or greater than 25 and less than 95, an n-type semiconductor layer 4 with even better crystallinity can be obtained.

[0048] As described above, according to the present embodiment, it is possible to provide a method for manufacturing a nitride semiconductor light-emitting element that can improve the crystallinity of an n-type semiconductor layer when the V / III ratio during film formation of the n-type semiconductor layer is relatively low.

[0049] [Experimental Example] This experimental example is an experimental example for evaluating the relationship between the V / III ratio during the deposition of an n-type semiconductor layer and the crystallinity of the n-type semiconductor layer.

[0050] In this experimental example, samples 1 to 18 were manufactured by laminating a buffer layer made of aluminum nitride and an n-type semiconductor layer on a sapphire substrate. The main properties of the buffer layer and n-type semiconductor layer of samples 1 to 18 are shown in Table 1 below and will be described below.

[0051] [Table 1]

[0052] Samples 1 to 6, 7 to 12, and 13 to 18 differ in the range of the half-width of the X-ray rocking curve (hereinafter referred to as the AlN mix value) obtained by ω-scanning of X-ray analysis of the (10-12) plane of the AlN crystal constituting the buffer layer. The AlN mix value for Samples 1 to 6 is 380 arcsec or more (more specifically, 380 arcsec to 498 arcsec). The AlN mix value for Samples 7 to 12 is 308 arcsec or less (more specifically, 293 arcsec to 308 arcsec). The AlN mix value for Samples 13 to 18 is greater than 308 arcsec but less than 380 arcsec (more specifically, 345 arcsec to 377 arcsec). The AlN mix value is an index of the crystallinity of the buffer layer; a lower value indicates better crystallinity. The AlN mix values ​​for Samples 1 to 18 are shown in a graph in Figure 2. In FIG. 2, the AlN mix values ​​of samples 1 to 6 are plotted with circle symbols, the AlN mix values ​​of samples 7 to 12 are plotted with triangle symbols, and the AlN mix values ​​of samples 13 to 18 are plotted with square symbols.

[0053] The n-type semiconductor layers in Samples 1 to 18 all had a film thickness of 2000±200 nm, an Al composition ratio of 55±10%, and a silicon concentration of (1.50±1.00)×10 19 atoms / cm 3 The film thickness of the n-type semiconductor layer was measured using a transmission electron microscope (TEM). The Al composition ratio of the n-type semiconductor layer was estimated from the Al secondary ion intensity measured using secondary ion mass spectrometry (SIMS). The silicon concentration of the n-type semiconductor layer was obtained using secondary ion mass spectrometry.

[0054] The groups of samples 1 to 6, samples 7 to 12, and samples 13 to 18 each had a V / III ratio of 382, ​​191, 140, 95, 46, and 25 when the n-type semiconductor layer was formed, which were different from each other.

[0055] In this experimental example, the half-width of the X-ray rocking curve (hereinafter referred to as n-AlGaN mix value) obtained by ω-scan of X-ray analysis for the (10-12) plane of the n-AlGaN crystal constituting the n-type semiconductor layer was evaluated for each of Samples 1 to 18. The n-AlGaN mix value is an index showing the crystallinity of the n-type semiconductor layer, and the lower the value, the better the crystallinity of the n-type semiconductor layer. The n-AlGaN mix value results for Samples 1 to 18 are shown in Table 1 and Figure 3.

[0056] As can be seen from Table 1, Figures 2 and 3, among Samples 1 to 18, samples having a V / III ratio of less than 95 during the formation of the n-type semiconductor layer can obtain a highly crystalline n-type semiconductor layer, regardless of the crystallinity of the buffer layer that serves as the underlying layer for the n-type semiconductor layer. Therefore, the V / III ratio during the formation of the n-type semiconductor layer is preferably less than 95. Furthermore, from the same viewpoint, the V / III ratio during the formation of the n-type semiconductor layer is preferably 25 or more and less than 95, and more preferably 25 or more and 46 or less.

[0057] 3, for each group of samples 1 to 6 and samples 7 to 12, the samples in which the V / III ratio during deposition of the n-type semiconductor layer was less than 95 had significantly improved crystallinity of the n-type semiconductor layer compared to samples in which the V / III ratio during deposition of the n-type semiconductor layer was 95 or more. Therefore, when the AlN mix value is 308 arcsec or less or 380 arcsec or more, as in samples 1 to 12, by setting the V / III ratio during deposition of the n-type semiconductor layer to less than 95, the crystallinity of the n-type semiconductor layer can be significantly improved compared to when the V / III ratio during deposition of the n-type semiconductor layer was 95 or more.

[0058] Furthermore, as can be seen from FIG. 3, Samples 13 to 18, which have an AlN mix value of more than 308 arcsec and less than 380 arcsec, have improved crystallinity of the n-type semiconductor layer compared to the other samples.

[0059] (Summary of the embodiment) Next, the technical ideas grasped from the above-described embodiments will be described by using the reference numerals and the like in the embodiments. However, the reference numerals and the like in the following description do not limit the components in the claims to the members and the like specifically shown in the embodiments.

[0060] [1] A first embodiment of the present invention is a method for manufacturing a nitride semiconductor light-emitting device 1 in which a substrate 2, an n-type semiconductor layer 4, an active layer 5, and a p-type semiconductor layer 7 are stacked in this order, III [μmol / min] vs. the flow rate F of the source gas of group V elements v [μmol / min] ratio F v / F III is defined as the V / III ratio, the V / III ratio when the n-type semiconductor layer 4 is formed is less than 95. As a result, an n-type semiconductor layer 4 with good crystallinity is obtained.

[0061] [2] A second embodiment of the present invention is the first embodiment, wherein the V / III ratio when the n-type semiconductor layer 4 is formed is 25 or more and less than 95. As a result, an n-type semiconductor layer 4 with good crystallinity is obtained.

[0062] [3] A third embodiment of the present invention is the first or second embodiment, wherein the substrate 2 is a sapphire substrate, the nitride semiconductor light-emitting element 1 further comprises a buffer layer 3 located between the substrate 2 and the n-type semiconductor layer 4, and the full width at half maximum of an X-ray rocking curve for a (10-12) plane of the buffer layer 3 is 308 arcsec or less or 380 arcsec or more. As a result, an n-type semiconductor layer 4 with good crystallinity is obtained.

[0063] [4] A fourth embodiment of the present invention is the first or second embodiment, wherein the substrate 2 is a sapphire substrate, the nitride semiconductor light-emitting element 1 further comprises a buffer layer 3 located between the substrate 2 and the n-type semiconductor layer 4, and the full width at half maximum of an X-ray rocking curve for a (10-12) plane of the buffer layer 3 is more than 308 arcsec and less than 380 arcsec. As a result, an n-type semiconductor layer 4 with good crystallinity is obtained.

[0064] (Addendum) Although the embodiments of the present invention have been described above, the invention according to the claims is not limited to the above-described embodiments. It should be noted that not all of the combinations of features described in the embodiments are necessarily essential to the means for solving the problems of the invention. Furthermore, the present invention can be appropriately modified and implemented within the scope of its spirit. [Explanation of symbols]

[0065] 1...Nitride semiconductor light emitting device 2...Substrate 3...Buffer layer 4...n-type semiconductor layer 5…Active layer 7...p-type semiconductor layer

Claims

1. A method for manufacturing a nitride semiconductor light emitting device in which a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked in this order, comprising: the n-type semiconductor layer is made of n-Al q Ga 1-q N (25%≦q≦70%), the active layer emits ultraviolet light having a center wavelength of 200 nm or more and 365 nm or less, Flow rate F of source gas of group III element ＩＩＩ Flow rate F of the source gas of the V group element [μmol / min] ｖ Ratio F [μmol / min] ｖ / F ＩＩＩ is defined as the V / III ratio, The V / III ratio when forming the n-type semiconductor layer is less than 95. A method for manufacturing a nitride semiconductor light-emitting device.

2. the V / III ratio when forming the n-type semiconductor layer is 25 or more and less than 95; The method for manufacturing the nitride semiconductor light-emitting device according to claim 1 .

3. the substrate is a sapphire substrate, the nitride semiconductor light emitting device further includes a buffer layer located between the substrate and the n-type semiconductor layer, the full width at half maximum of an X-ray rocking curve for the (10-12) plane of the buffer layer is 308 arcsec or less or 380 arcsec or more; The method for manufacturing the nitride semiconductor light-emitting device according to claim 1 or 2.

4. the substrate is a sapphire substrate, the nitride semiconductor light emitting device further includes a buffer layer located between the substrate and the n-type semiconductor layer, the full width at half maximum of the X-ray rocking curve for the (10-12) plane of the buffer layer is more than 308 arcsec and less than 380 arcsec; The method for manufacturing the nitride semiconductor light-emitting device according to claim 1 or 2.

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