Quantum bit array and method for fabricating the quantum bit array

Abstract

To expand quantum bits in two dimensions using a current semiconductor manufacturing method, in a quantum information processing device.SOLUTION: A first layer has a first gate electrode row arranged in a first direction to control quantum bits of a quantum bit row, and a second gate electrode row arranged in the first direction to control quantum bit interactions of an interaction row. The second layer has a third gate electrode row arranged in a second direction, and a fourth gate electrode row arranged adjacent to the third gate electrode row in the second direction. The third gate electrode row and the fourth gate electrode row control some of the quantum bits of the multiple quantum bits and some of the multiple quantum bit interactions, respectively.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a quantum information processing device. [Background technology]

[0002] Currently, many groups around the world are conducting research with the aim of realizing quantum computers. Experiments are being conducted using a variety of physical systems, but regardless of which physical system is used, the first thing that is required to realize a quantum computer is to create quantum bits in an isolated system that does not exchange matter or energy with the outside world, and to be able to maintain the coherence of the quantum system for a long period of time.

[0003] In order to operate quantum bits as a quantum computer, it is essential not only to pursue the performance of a single quantum bit, but also to construct a device that includes multiple quantum bits.

[0004] There have been reports of semiconductor quantum bits being made multi-qubit (see, for example, Patent Document 1), but these structures are simply a horizontal extension of the single quantum bit structure. A large number of electrodes are placed above and below, and the state of the quantum bits and the interactions between the quantum bits are controlled by applying a DC voltage to these electrodes.

[0005] However, with this structure, as the number of quantum bits increases, the number of electrodes also increases proportionally. When operating at extremely low temperatures in a refrigerator, the number of electrodes to which DC voltage or RF pulses can be applied from the outside is limited, which places a limit on the number of quantum bits that can be increased.

[0006] Furthermore, the quantum bits are arranged in a one-dimensional line, but if we try to arrange the quantum bits in a two-dimensional plane while keeping this structure, it would be impossible because there would be no place to place the control electrodes.

[0007] As such, it is difficult to array quantum bits on a two-dimensional plane by extending the quantum bit structures proposed so far. Nevertheless, it is widely recognized that two-dimensional expansion is necessary to operate as a quantum computer. For this reason, proposals have been made for such quantum bit array structures (see, for example, Patent Document 2). This aims to individually control quantum bit arrays expanded two-dimensionally by switching using wiring and transistors formed on the upper layer. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] WO2009 / 072550 publication [Patent Document 2] Special Publication No. 2018-532255 Summary of the Invention [Problem to be solved by the invention]

[0009] However, in the structure of the quantum bit array in Patent Document 2, if quantum bits with a complex structure are formed in the lower layer, the crystallinity of the substrate cannot be maintained up to the upper layer, making it difficult to form transistors in the upper layer using current semiconductor manufacturing methods.

[0010] An object of the present invention is to enable quantum bits to be expanded two-dimensionally using current semiconductor manufacturing methods in a quantum information processing device. [Means for solving the problem]

[0011] One aspect of the present invention The quantum bit array includes a fin and a plurality of quantum bit arrays provided on the fin. and a gate electrode array, wherein the fin has a two-dimensional planar shape. and a first element having a shape extending in the first direction so that the quantum bits interact in the first direction. A portion of the qubits interact with the fin in a second direction different from the first direction. The second fin is partially provided with a shape extending in the second direction. It is characterized by: [Effects of the Invention]

[0012] According to one aspect of the present invention, in a quantum information processing device, quantum bits can be made two-dimensionally expandable using current semiconductor manufacturing methods. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a bird's-eye view of the structure of a quantum bit string that constitutes a quantum information processing device. [Figure 2] FIG. 1 is a plan view of a quantum information processing device. [Figure 3] FIG. 1 is a plan view of a quantum information processing device. [Figure 4A] 1A and 1B are plan views showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 4B] 1 is a cross-sectional view A showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 4C] 1B is a cross-sectional view showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 5A] 1A and 1B are plan views showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 5B] 1 is a cross-sectional view A showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 5C] 1B is a cross-sectional view showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 6A] 1A and 1B are plan views showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 6B] 1 is a cross-sectional view A showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 6C] 1B is a cross-sectional view showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 7A] 1A and 1B are plan views showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 7B] 1 is a cross-sectional view A showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 7C] 1B is a cross-sectional view showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 8A] 1A and 1B are plan views showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 8B] 1 is a cross-sectional view A showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 8C] 1B is a cross-sectional view showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 9A] 1A and 1B are plan views showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 9B] 1 is a cross-sectional view A showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 9C] 1B is a cross-sectional view showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 10A] 1A and 1B are plan views showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 10B] 1 is a cross-sectional view A showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 10C] 1B is a cross-sectional view showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 11A] 1A and 1B are plan views showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 11B] 1 is a cross-sectional view A showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 11C] 1B is a cross-sectional view showing a method for fabricating a quantum bit string that constitutes a quantum information processing device. [Figure 12] FIG. 2 is a detailed cross-sectional view of a fin of a quantum bit that constitutes a quantum information processing device. [Figure 13] 1A and 1B are a cross-sectional view and an electron energy level diagram of a quantum bit string that constitutes a quantum information processing device, illustrating a method for performing initialization in the quantum bit string. [Figure 14] 1A and 1B are a cross-sectional view and an electron energy level diagram of a quantum bit string that constitutes a quantum information processing device, illustrating a method for performing a rotation gate operation in the quantum bit string. [Figure 15]FIG. 1 is a plan view of a quantum bit array that constitutes a quantum information processing device, illustrating individual operability when performing a rotation gate operation in the quantum bit array. [Figure 16] 1A and 1B are a cross-sectional view and an electron energy level diagram of a quantum bit string that constitutes a quantum information processing device, illustrating a method for performing a control gate operation in the quantum bit string. [Figure 17] 1A and 1B are a cross-sectional view and an electron energy level diagram of a quantum bit string that constitutes a quantum information processing device, illustrating a method for performing a control gate operation in the quantum bit string. [Figure 18] FIG. 1 is a plan view of a quantum bit string that constitutes a quantum information processing device, illustrating individual operability when performing a controlled NOT gate operation in the quantum bit string. [Figure 19] FIG. 1 is a plan view of a quantum bit string constituting a quantum information processing device of the present invention, illustrating individual operability when performing a controlled NOT gate operation in the quantum bit string. [Figure 20] 1A and 1B are a cross-sectional view and an electron energy level diagram of a quantum bit string that constitutes a quantum information processing device, illustrating a method for reading out the quantum bit string. [Figure 21] 1A and 1B are a cross-sectional view and an electron energy level diagram of a quantum bit string that constitutes a quantum information processing device of the present invention, illustrating a method for performing readout in the quantum bit string. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, an embodiment will be described with reference to the drawings. First, the structure of the quantum bit string that constitutes the quantum information processing device will be described.

[0015] As shown in Figure 1, the quantum bit string has a five-layer structure. From the bottom up, the layers are the first, second, third, fourth, and fifth layers. Each layer is insulated by a layer of insulator (e.g., SiO2).

[0016] The first layer is a semiconductor (for example, p-type Si) initialization gate 101. A DC voltage can be applied to the entire surface of the second layer from below.

[0017] The second layer has fins 102 made of a semiconductor (for example, intrinsic Si). As shown in Fig. 2, quantum bits 201 are formed in a two-dimensional square lattice pattern on the top surface of the fins 102. Interactions 202 between quantum bits are formed according to the shape of the fins 102. The fins 102 are shaped so that all quantum bits 201 interact with each other in the horizontal direction and some quantum bits 201 interact with each other in the vertical direction.

[0018] The third layer is divided into an upper layer and a lower layer, each having a semiconductor (e.g., poly-Si) gate electrode. There are two types of gate electrodes: quantum bit control gates 103 and 105 and interaction control gates 104 and 106. In the lower layer, the gate electrodes are linearly shaped extending vertically, with quantum bit control gates 103 and interaction control gates 104 arranged alternately. However, no gate electrodes are formed on the linearly shaped fins 102 extending horizontally in the second layer. In the upper layer, the gate electrodes are linearly shaped extending horizontally, with quantum bit control gates 105 and interaction control gates 106 arranged alternately. The quantum bit control gates 105 and interaction control gates 106 in the upper layer contact the fins 102 in the second layer in areas where no gate electrodes were formed in the lower layer.

[0019] The fourth layer has a conductive wire 107 made of a conductor (for example, Al) that has a linear shape extending horizontally.

[0020] The fifth layer has magnets 108 made of a ferromagnetic material (for example, Co), which have a shape with varying size extending in the horizontal direction so that different static magnetic fields are applied to the quantum bit 201.

[0021] Electrodes are connected to the initialization gate 101, fin 102, quantum bit control gate 103, interaction control gate 104, quantum bit control gate 105, interaction control gate 106, and conductor 107 shown in FIG. 1, as shown in FIG. 2. This allows DC voltages and RF pulses to be applied, and RF pulses to be output. A switch 203 is provided outside the quantum bit string to switch input and output signals. Therefore, the number of terminals for connection to the outside does not increase in proportion to the number of quantum bits 201.

[0022] The number of qubits 201 can be expanded to any number of columns in the horizontal and vertical directions. For example, in Figure 2, five columns are arranged horizontally and three columns are arranged vertically, for a total of 15 qubit columns, but by repeating the same structure as in Figure 3, it is also possible to configure 10 columns horizontally and six columns vertically, for a total of 60 qubit columns.

[0023] Next, a method for producing a quantum bit string will be explained step by step. As shown in Figures 4A, 4B, and 4C, an initialization gate 101 made of a semiconductor (e.g., p-type Si formed by implanting impurities) is formed on the entire surface of a semiconductor (e.g., crystalline Si) substrate. The initialization gate 101 is used to initialize the quantum bit 201. An insulator (e.g., SiO2) layer 402 is formed on the initialization gate 101. A semiconductor (e.g., crystalline Si) fin 102 is formed on the insulator layer 402. The shape of the fin 102 ultimately determines the coupling relationship between each quantum bit. All columns are coupled in a straight line in the horizontal direction, and coupling is formed in several columns in the vertical direction as needed. Finally, a gate insulating film 403 made of an insulator (e.g., SiO2) is formed to insulate the fin 102 from the gate electrodes to be formed subsequently.

[0024] As shown in Figures 5A, 5B, and 5C, quantum bit control gates 103 made of semiconductor (e.g., poly-Si) are formed on fins 102. The quantum bit control gates 103 have a linear shape extending vertically. This allows discrete junctions with quantum bit control gates 103 to be formed on the linear fins 102 extending horizontally, allowing them to operate as quantum bits 201 by confining single electrons. Spacers 501 made of an insulator (e.g., Si3N4) are formed on quantum bit control gates 103 to insulate them from the gate electrode to be formed later.

[0025] As shown in Figures 6A, 6B, and 6C, interaction control gates 104 made of semiconductor (e.g., poly-Si) are formed between each quantum bit control gate 103. Like the quantum bit control gates 103, they are shaped like straight lines extending vertically. This forms discrete junctions with the interaction control gates 104 on the linear fins 102 extending horizontally, making it possible to control the interactions 202 between the quantum bits 201 aligned horizontally. After that, an insulator (e.g., SiO2) layer 601 is formed, and a planarization process is performed.

[0026] 7A, 7B, and 7C, since gates are not formed discretely on the vertically extending linear fin 102, the quantum bit control gate 103 is removed by masking and etch-back processing. By adjusting the etching conditions so that the etch-back stops on the gate insulating film 403, the gate insulating film 403 on the fin 102 is exposed again.

[0027] As shown in Figures 8A, 8B, and 8C, a semiconductor (e.g., poly-Si) quantum bit control gate 105 is formed on a linear fin 102 extending vertically. Unlike quantum bit control gate 103, this time it is formed in a linear shape extending horizontally. This process forms discrete junctions with quantum bit control gate 105 on the linear fin 102 extending vertically, enabling it to operate as quantum bit 201 by confining a single electron. Spacer 501 insulates quantum bit control gate 103 from quantum bit control gate 103 and interaction control gate 104. Spacer 801 made of an insulator (e.g., Si3N4) is formed on quantum bit control gate 105 to insulate it from the gate electrode to be formed later.

[0028] As shown in Figures 9A, 9B, and 9C, semiconductor (e.g., poly-Si) interaction control gates 106 are formed between each quantum bit control gate 105. Similar to the quantum bit control gates 104, they are formed in a linear shape extending horizontally. This forms discrete junctions with the interaction control gates 106 on the linear fins 102 extending vertically, making it possible to control the interactions 202 between quantum bits 201 aligned vertically. After that, an insulator (e.g., SiO2) layer 901 is formed, and a planarization process is performed.

[0029] As shown in Figures 10A, 10B, and 10C, a conductive (e.g., Al) lead 107 is formed on the quantum bit control gate 105 and the interaction control gate 106. Like the quantum bit control gate 103 and the interaction control gate 104, this is formed into a linear shape extending horizontally. This makes it possible to apply RF pulses to the quantum bits 201. RF pulses of the same frequency and duration are applied to the quantum bits 201 aligned horizontally. After that, an insulator (e.g., SiO2) layer 1001 is formed, and a planarization process is performed.

[0030] As shown in Figures 11A, 11B, and 11C, a magnet 108 made of a ferromagnetic material (e.g., Co) is formed on a conductive wire 107 and magnetized. The magnet is shaped to extend horizontally, but by continuously changing its width or thickness, a different static magnetic field is applied to each of the quantum bits 201 aligned horizontally. By using the above method, a quantum bit string with the structure shown in Figure 1 can be fabricated.

[0031] As such, the quantum information processing device of the above embodiment includes the fin 102, a first layer provided on the fin 102, and a second layer provided on the first layer, as shown in FIG.

[0032] As shown in FIG. 2, the fin 102 has a quantum bit column in which a plurality of quantum bits are arranged in a row in a first direction (e.g., the vertical direction), and an interaction column in which a plurality of quantum bit interactions are arranged in a row in the first direction (e.g., the vertical direction), and the quantum bit column and the interaction column are arranged alternately in a second direction (e.g., the horizontal direction) different from the first direction (e.g., the vertical direction).

[0033] As shown in FIG. 1, the first layer has a first gate electrode row (quantum bit control gates 103) arranged in a first direction (e.g., vertical direction) to control the quantum bits of the quantum bit row, and a second gate electrode row (interaction control gates 104) arranged in the first direction (e.g., vertical direction) to control the quantum bit-to-quantum bit interaction of the interaction row.

[0034] As shown in FIG. 1, the second layer has a third gate electrode row (qubit control gates 105) arranged in a second direction (e.g., horizontal direction) and a fourth gate electrode row (interaction control gates 106) arranged adjacent to the third gate electrode row (qubit control gates 105) in the second direction (e.g., horizontal direction).

[0035] The third gate electrode row (quantum bit control gate 105) and the fourth gate electrode row (interaction control gate 106) respectively control some of the multiple quantum bits and some of the multiple quantum bit interactions (see Figure 2).

[0036] Here, in the second layer, a part of the third gate electrode row (qubit control gates 105) and a part of the fourth gate electrode row (interaction control gates 106) extend in a first direction (e.g., vertically) as an electrode row (see FIG. 8B). These electrode rows control some of the qubits and some of the interactions between the qubits, respectively (see FIG. 2).

[0037] As shown in FIGS. 2 and 3, for example, the electrode arrays are provided discretely in a second direction (for example, horizontally) so as to two-dimensionally expand the number of quantum bits.

[0038] 8B, for example, the electrode array forms a protrusion, and the protrusion is in contact with the fin 102. For example, the protrusion is in contact with the fin 102 in a portion of the first layer where the first gate electrode array (quantum bit control gate 103) and the second gate electrode array (interaction control gate 104) are not formed.

[0039] According to the above embodiment, in a quantum information processing device, quantum bits can be made two-dimensionally expandable using current semiconductor manufacturing methods. Hereinafter, an embodiment will be described with reference to the drawings. [Example]

[0040] In the first embodiment, a method for initializing a quantum bit string in a quantum information processing device will be described.

[0041] To enable initialization of the quantum bit 201, the fin 102 has a three-layer structure as shown in Fig. 12. From the bottom up, the first layer 1201 is made of an n-type semiconductor (e.g., n-type Si), the second layer 1202 is made of an insulator, and the third layer 1203 is made of a semiconductor (e.g., intrinsic Si). The first layer 1201 serves as an electron reservoir.

[0042] Figure 13 shows the change in the electronic state when three quantum bits 201 arranged horizontally in a quantum bit string are initialized. The quantum bits 201 formed below quantum bit control gates 1301, 1302, and 1303 shown in the cross-sectional view of the quantum bit string in the upper part of Figure 13 are designated as quantum bits A, B, and C, respectively. Here, quantum bits A, B, and C are all initialized.

[0043] Shown at the bottom of FIG. 13 are the energy levels of the quantum bits A, B, and C and the reservoir (note that this does not correspond to the spatial arrangement of the quantum bits A, B, and C and the reservoir).

[0044] The effect of magnet 108 applies a static magnetic field to quantum bits A, B, and C, which causes a difference in energy between |↓> and |↓> due to Zeeman splitting. Furthermore, because the magnitude of the static magnetic field applied to quantum bits A, B, and C differs, a gradient is formed in the energy difference between |↑> and |↓>.

[0045] When a positive DC voltage is applied to the initialization gate 101 and a negative DC voltage is applied to the quantum bit control gates 1301, 1302, and 1303, electrons in the first layer 1201 of the fin 102 migrate across the second layer 1202 of the fin 102 to the junctions of the quantum bit control gates 1301, 1302, and 1303 in the third layer 1203 of the fin 102. When the DC voltage applied to the initialization gate 101 is returned to zero after one electron has migrated, the electron is trapped in the junctions of the quantum bit control gates 1301, 1302, and 1303 in the third layer 1203 of the fin 102, and begins to function as quantum bits 201. All electron spins are in the low-energy |↓> state. Because the quantum bit array is cooled to extremely low temperatures by a dilution refrigerator, thermal energy rarely causes a change to |↑>. By the above method, all quantum bits 201 are prepared in the |↓> state, and initialization can be performed.

[0046] In the first embodiment, the reservoir is formed below the quantum bit, but it may be formed next to the quantum bit instead. In this case, the initialization gate 101 is not necessary. All quantum bits can be initialized by sequentially sending electrons from the edge of the quantum bit array to the inside. [Example]

[0047] In the second embodiment, a method for performing a rotation gate operation in a quantum bit string of a quantum information processing device will be described.

[0048] Figure 14 shows the change in the electron state when a rotation gate operation is performed on three selected qubits 201 arranged horizontally in a qubit string. The qubits 201 formed below qubit control gates 1301, 1302, and 1303 shown in the cross-sectional view of the qubit string at the top of Figure 14 are designated qubits A, B, and C, respectively. Here, rotation gate operation is performed on qubits A and B, respectively. The energy levels of qubits A, B, and C are shown at the bottom of Figure 14.

[0049] When an RF pulse is applied to the conductor 107, the RF pulse is applied to all of the horizontally aligned quantum bits A, B, and C. Then, when the energy difference between |↑> and |↓> matches the energy difference hν (h is Planck's constant), which corresponds to the frequency ν of the RF pulse, electron spin rotation occurs. By using the above method, rotation gate operation can be performed.

[0050] By controlling the magnitude and duration of the RF pulse, it is possible to perform rotation gate operation of any size. For example, adding an RF pulse equivalent to a phase of π results in a NOT gate operation.

[0051] The individual operability of the rotary gate operation will be explained using FIG. Since the energy difference between |↑> and |↓> of the horizontally aligned qubits 201 is different, a rotation gate operation can be performed on any qubit 201 in the qubit string. For the vertically aligned qubits 201, RF pulses can be applied selectively because the conductors 107 are physically separated. This allows the operation of any qubit 201 in the qubit string.

[0052] In the second embodiment, the energy difference of the quantum bits is changed (by the Zeeman effect) using the magnet 108, but the energy difference may be changed by changing the voltage applied to the quantum bit control gate (by the Stark effect). In this case, the magnet 108 is not necessary.

[0053] Furthermore, although in the second embodiment an RF pulse is applied through conductive wire 107, an RF pulse may be applied through quantum bit control gate 103. In this case, conductive wire 107 becomes unnecessary. [Example]

[0054] In the third embodiment, a method for performing a controlled NOT gate operation on a quantum bit string in a quantum information processing device will be described.

[0055] 16 and 17 show the change in the state of electrons when a controlled NOT gate operation is performed on three selected quantum bits 201 arranged horizontally in the quantum bit string.

[0056] The quantum bits 201 formed below quantum bit control gates 1301, 1302, and 1303 shown in the cross-sectional views of the quantum bit strings in the upper part of Figure 16 and the upper part of Figure 17 are designated as quantum bits A, B, and C, respectively. Here, a controlled NOT gate operation is performed using quantum bit A as the target bit and quantum bit B as the control bit. The energy levels of quantum bits A, B, and C are shown in the lower part of Figure 16 and the lower part of Figure 17.

[0057] Figure 16 shows the change in the state of electrons when a NOT gate operation occurs in the target bit because the control bit is |↑>. In (1), the energy of the electrons in the target bit and the control bit is drawn separately, but it is also possible to draw the energy of the electrons in the target bit and the control bit together as in (2). (1) and (2) are equivalent. The energy is highest when both electrons are |↑>, and lowest when both electrons are |↓>. When the electron spins are antiparallel, an intermediate value is taken, but because the energy difference between |↑> and |↓> differs between the target bit and the control bit due to the effect of magnet 108, an energy difference also occurs between |↑↓> and |↓↑>.

[0058] (3) shows the state of electrons when a controlled NOT gate operation is performed. When a negative DC voltage is applied to the interaction control gate 104 between the target bit and the control bit, the energy decreases because the electron spins are stable when they are antiparallel. Therefore, the energy difference between |↑↑> and |↑↓> can be adjusted to any value by changing the magnitude of the DC voltage applied to the interaction control gate 104.

[0059] The energy difference between |↑↑> and |↓↑> is set to a value greater than the energy difference between the other combinations of electron states, and an RF pulse with a frequency ν corresponding to this energy difference hν is applied through the conductor 107. This causes the electron spin to rotate between |↑↑> and |↓↑>. After applying an RF pulse corresponding to a phase π, the DC voltage applied to the interaction control gate 104 is returned to zero, resulting in a state in which a NOT gate operation is applied to the target bit, as shown in (4).

[0060] Figure 17 shows the change in the state of electrons when a NOT gate operation does not occur at the target bit because the control bit is |↓>. The only difference from Figure 16 is that the initial control bit state is |↓> instead of |↑>; there is no difference in the applied DC voltage or RF pulse. However, since the |↑↑> and |↓↑> states do not exist in (2) and (3), no rotation of the electron spin occurs. Using the above method, a controlled NOT gate operation can be performed.

[0061] The individual operability of the controlled NOT gate operation will be explained using Figures 18 and 19. Figure 18 shows the case where the target bit and control bit are arranged horizontally. The interaction control gates 104 are separated horizontally, while the conductors 107 are separated vertically. The state of the electrons does not change unless a DC voltage and an RF pulse are applied to each simultaneously. Therefore, the controlled NOT gate operation can be performed on any two adjacent quantum bits 201 in the quantum bit string. Furthermore, by changing the magnitude of the DC voltage applied to the interaction control gate 104, it is possible to select which of the two adjacent quantum bits 201 will be the target bit or the control bit.

[0062] Figure 19 shows the case where the target bit and control bit are aligned vertically. Because the interaction control gate 104 and the conductor 107 are both separated vertically, the controlled NOT gate operation is simultaneously applied to the two horizontally aligned quantum bits 201. [Example]

[0063] In the fourth embodiment, a method for reading out a quantum bit string in a quantum information processing device will be described.

[0064] 20 and 21 show the change in the state of electrons when three quantum bits 201 arranged horizontally in a quantum bit string are selected and read out. The quantum bits 201 formed below quantum bit control gates 1301, 1302, and 1303 shown in the cross-sectional views of the quantum bit strings at the top of Figure 20 and at the top of Figure 21 are designated as quantum bits A, B, and C, respectively. Here, quantum bit C is used as the readout control bit, and quantum bit B is used as the quantum bit to be measured and read out.

[0065] Figure 20 shows the change in the state of an electron when the measured state of quantum bit B is |↑>. As shown in (2), applying a negative DC voltage to the interaction control gate 104 between quantum bits B and C lowers the energy barrier between the two quantum bits. Furthermore, increasing the negative DC voltage applied to the quantum bit control gate 1303 promotes the transfer of electrons from quantum bit B to quantum bit C. Since the electron state of quantum bit B is |↑> while the electron state of quantum bit C is |↓>, Pauli spin blockade does not occur, and electron transfer occurs. After that, when the DC voltage applied to the interaction control gate 104 is returned to zero, two electrons are trapped in quantum bit C.

[0066] Figure 21 shows the change in the state of an electron when the measured state of quantum bit B is |↓>. Performing the same operation as in Figure 20 encourages the transfer of an electron from quantum bit B to quantum bit C, but because the electron spin states of quantum bits B and C are both |↓>, the transfer of the electron does not occur due to Pauli spin blockade. If the DC voltage applied to the interaction control gate 104 is then returned to zero, one electron is confined in quantum bit C.

[0067] 20 and 21, an RF pulse is finally applied to quantum bit control gate 103. Because the impedance differs between the cases of one electron and two electrons, the number of electrons in quantum bit C can be estimated by examining the phase of the reflected RF pulse, and the state of the electron spin in quantum bit B can be measured indirectly. A readout operation can be performed using the above method.

[0068] Since all of the qubits 201 have the same structure, any qubit in the qubit string can be used for readout. However, since the qubit control gates 103 and 105 have a linear shape extending vertically or horizontally, readout is performed simultaneously on all of the qubits 201 aligned in the direction of the qubit control gate 103 or qubit control gate 105.

[0069] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the positional relationship between the first quantum bit control gate and the second quantum bit control gate may be at any angle, rather than perpendicular. In this case, a triangular or hexagonal lattice may be formed instead of a two-dimensional square lattice. Furthermore, the number of layers of quantum bit control gates and interaction control gates may be three or more, rather than two. In this case, interactions between quantum bits can occur not only in the horizontal and vertical directions, but also in directions at any angle. [Explanation of symbols]

[0070] 101 Initialization gate 102···Fin 103···Qubit control gate 104···Interaction control gate 105···Qubit control gate 106···Interaction control gate 107...Conductor 108 Magnet 201... qubits 202...interaction 203···Switch 401 Semiconductor crystal substrate 402....Insulator layer 403 Gate insulating film 501···Spacer 601: Insulator layer 801···Spacer 901....Insulator layer 1001... Insulator layer 1201···n-type semiconductor layer 1202 Insulator layer 1203 Semiconductor layer 1301···Qubit control gate 1302···Qubit control gate 1303···Qubit control gate

Claims

1. Finn and a plurality of gate electrode arrays provided on the fins, the fins have a two-dimensional planar shape, and include a first fin that extends in a first direction so that quantum bits interact in the first direction, and a second fin that extends in a second direction different from the first direction so that some of the quantum bits interact in the second direction.

2. 2. The quantum bit array according to claim 1, wherein the number of the second fins is smaller than the number of the first fins in the two-dimensional planar shape.

3. 2. The quantum bit array according to claim 1, wherein in the two-dimensional planar shape, the fins have a lattice shape extending in the first direction.

4. 2. The quantum bit array according to claim 1, wherein a protruding portion of a gate electrode row extending in the first direction is provided on an upper portion of the second fin.

5. Finn and a plurality of gate electrode arrays provided on the fins, the fins have a lattice shape extending in a first direction; the fins include at least three or more first fins that extend in the first direction and are aligned in a second direction different from the first direction, and at least three or more second fins that extend in the second direction and are aligned in the first direction.

6. a first step of forming a semiconductor fin on a first layer of insulator; a second step of forming a gate insulating film on the fin; a third step of forming a semiconductor quantum bit control gate extending in a first direction and a semiconductor interaction control gate extending in the first direction on the gate insulating film; a fourth step of removing a portion of the qubit control gate extending in the first direction; a fifth step of forming a semiconductor quantum bit control gate and a semiconductor interaction control gate extending in a second direction different from the first direction on the fin exposed by the removal; 1. A method for fabricating a quantum bit array, comprising:

7. 7. The method for fabricating a quantum bit array according to claim 6, wherein in the fourth step, the quantum bit control gates extending in the first direction are removed by mask processing and etch-back processing.

8. 8. The method for fabricating a quantum bit array according to claim 7, wherein in the fourth step, the etch-back process is performed by adjusting conditions under which the etch-back stops on the gate insulating film.

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