Circuit and method for solving triangular matrix under GF (2) domain QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) based on forward substitution

Abstract

The invention discloses a GF (2) domain QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) lower triangular matrix solving circuit and method based on forward replacement, and belongs to the field of digital communication and integrated circuit design. The circuit comprises an input interface module, a shift value storage SRAM (Static Random Access Memory), a column block recursion control module, a cyclic shift array, a parallel XOR accumulation array, a register register array and an output register module. According to column block structure characteristics of a triangular matrix under QC, the system adopts a forward replacement algorithm to realize rapid solution and demand-free inverse operation of a matrix equation T.X = B under a GF (2) domain through cyclic shift and bitwise XOR operation. The structure can be executed in a streamlined mode, one column of blocks are solved in each period, and the structure has the advantages of being high in parallelism degree, low in delay, low in power consumption and the like and is suitable for matrix operation acceleration of an LDPC encoder and high-speed communication hardware.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital communication and integrated circuit design, in particular to a GF(2) domain QC-LDPC lower triangular matrix solving circuit and method based on forward substitution. BACKGROUND

[0002] In the process of LDPC encoding, it is often necessary to solve the linear equation group T X = B with the coefficient of QC lower triangular matrix T (n x n). The traditional method includes directly inverting the matrix and then multiplying (i.e. ), but the inversion operation has high complexity and large hardware resource consumption.

[0003] The forward substitution method is a direct numerical method for solving lower triangular matrix equations. For the lower triangular matrix T, the solution X i of the i-th column can be obtained by the recursive formula:

[0004] However, in the GF(2) domain, the formula can be simplified as:

[0005] Where ⊕ represents the XOR operation, and · represents the AND operation. This method does not need to explicitly invert, needs to be solved in column order, and has a computational complexity of O(n²).

[0006] The existing general forward substitution hardware implementation fails to fully utilize the two key features of the QC-LDPC matrix: (1) the inherent data dependency relationship brought by the lower triangular structure; (2) the quasi-cyclic characteristic makes the matrix elements and the solution vector can be represented by cyclic shifts. However, in the traditional hardware implementation, solving by column still needs to calculate the following "shift-accumulate" term:

[0007] Where "·" is the GF(2) bitwise AND operation, and "⊕" is the bitwise XOR accumulation. This process needs to perform a cyclic shift according to the shift amount of first, and then participate in the XOR accumulation, resulting in long data paths, low multiplexing degree, limited hardware efficiency, and difficulty in meeting the throughput requirements of high-speed decoding. SUMMARY

[0008] To solve the above problems, the present application provides a GF(2) domain QC-LDPC lower triangular matrix solving circuit and method based on forward substitution, which optimizes the mathematical algorithm and hardware architecture cooperatively, solves by column block recursion, and combines the sum term Mapping to the highly parallel shift accumulator array, high computing efficiency and low power consumption are achieved.

[0009] The application is achieved by the following technical scheme: a GF(2) domain QC-LDPC lower triangular matrix solving circuit based on forward substitution, comprising: An input interface module is configured to receive a QC lower triangular matrix T and a right matrix B, wherein the matrix T is stored in a column block structure, and each sub-block is a unit shift matrix or a zero matrix. A shift value storage SRAM module is configured to store shift values of each sub-block in the lower triangular matrix T, and the shift values are arranged in sequence according to column indexes. A column block recursion control module is configured to control forward substitution calculation in a column sequence, latch the results of the first i-1 columns and trigger the solving of the i-th column when the i-th column is calculated. A cyclic shift array module comprises a plurality of parallel cyclic shift units, and the shift depth of each cyclic shift unit is output by the shift value storage SRAM module, and is configured to perform a cyclic right shift operation on an input sub-block or according to the corresponding shift value. A parallel XOR accumulation array module is connected with the cyclic shift array module and is configured to perform an XOR operation on each shift result in the GF(2) domain to realize column vector summation. A register array module is configured to temporarily store the corresponding intermediate solution vector after the solving of each column block is completed, and participate in accumulation when the next column block is calculated. An output register module is configured to output the solution matrix after the solving of all g column blocks is completed. The column block recursion control module sequentially executes a solving process of g periods, each period completes the forward substitution calculation of a column block, and the shift and summation operations are pipelined through the cyclic shift array and the parallel XOR accumulation array, thereby completing the fast solving of the matrix equation T X = B.

[0010] As a preferred technical scheme, the cyclic shift array module is composed of a plurality of Z-bit cyclic shifters, and the control end of each cyclic shifter is connected with a shift control line of the shift value storage SRAM module, so as to realize parallel shift operation based on the QC sub-block.

[0011] As a preferred technical scheme, the parallel XOR accumulation array module is composed of Z XOR gate arrays, the input end of each XOR gate array is connected with the output end of the corresponding cyclic shifter, and the output end is connected with the input end of the register array module, so as to complete bit-by-bit accumulation in the GF(2) domain.​

[0012] As a preferred technical solution, the column block recursive control module includes: The cycle counting unit is used to generate the timing signal for column index i; The control logic unit is used to control the start and latching timing of the solution for the i-th column according to the column index i. The data path selection unit is used to select the output result of the previous column during the solution process. Feedback is sent to the cyclic shift array module.

[0013] As a preferred technical solution, the address lines of the shift value storage SRAM module are synchronously incremented with the column block recursive control module, so that the shift information of the corresponding column is accessed only in each cycle, thereby reducing the access bandwidth.

[0014] As a preferred technical solution, the circuit is implemented in a pipeline structure, and multiple column blocks can be recursively calculated continuously. The calculation units in adjacent cycles can achieve data alternation and parallel operation through a register array module, thereby improving the decoding throughput.

[0015] As a preferred technical solution, the output register module includes a multiplexer and a latch array, used to output the solution results of all column blocks at the end of the last cycle.

[0016] The present invention provides a method for solving the lower triangular matrix of GF(2) domain QC-LDPC based on forward substitution, comprising the following steps: Input and initialization: Store the shift values ​​of the lower triangular matrix T of QC column by column into the shift value storage SRAM module, input the right matrix B into the register array module and initialize the solution vector X = 0; Block recursive solution: Execute the following steps on column index i from 1 to g: a) Read the shift control signal of the i-th column from the shift value storage SRAM module; b) The obtained column blocks are processed using the cyclic shift array module. Perform a shift operation; c) Perform XOR accumulation on the shift result using the parallel XOR accumulator array module and then add it to the corresponding... Performing GF(2) addition, we get ; d) will The result is written to the register array module; Output phase: When i = g, output the solution matrix of all columns. .

[0017] As a preferred technical solution, the exclusive OR accumulation operation in step 2 is performed by an exclusive OR array with a parallel degree of Z to improve the hardware solving speed.

[0018] As a preferred technical solution, the cyclic shift operation dynamically adjusts the shift depth in each period based on a shift control signal, and the shift depth corresponds to the position of a non-zero sub-block of the lower triangular matrix T, so as to realize shift mapping based on QC characteristics.

[0019] The present application has the beneficial effects that: the present application adopts a direct solving method based on forward substitution, solves the matrix equation T·X = B through a column-by-column recursive manner, and does not need to perform complex matrix inversion operation in the GF(2) field. The method reduces the O(n³) complexity of the traditional inversion to O(n²), significantly reduces the hardware calculation burden, and shortens the decoding path delay. In the traditional hardware structure, the multiplication of matrix elements and vectors usually depends on the logical AND operation (AND) array. The present application utilizes the characteristics that each sub-block in the quasi-cyclic (Quasi-Cyclic) matrix can be obtained by cyclic right shift, maps the multiplication operation into the cyclic shift operation of the data block, and only needs the shift control signal to complete the matrix multiplication equivalent operation, greatly reduces the number of logical gates and power consumption. The present application simplifies the matrix addition operation in the GF(2) field to the bitwise exclusive OR operation, and realizes the simultaneous accumulation of each shift block through a parallel exclusive OR array. Combined with the pipelined column block recursive control strategy, the operation of one column block can be completed in each clock cycle, so as to realize high throughput data solving. Compared with the traditional sequential structure, the throughput can be improved by several times or more. The core unit of the entire circuit is only composed of shifters, exclusive OR gates and a small amount of registers, and does not need multipliers, dividers or matrix inversion modules. The matrix structure parameters are stored in the shift value storage SRAM, the hardware control logic is simple, the integrated area is significantly reduced, and the implementation in FPGA or ASIC is facilitated. The forward substitution solving process of the present application has a clear column recursive sequence, and the solving result of the previous column can be directly reused in the calculation of the next column, forming a natural pipeline structure. The column block recursive control module and the shift value storage SRAM module can realize period synchronization, so that the circuit can run continuously and stably, and is easy to integrate with the LDPC encoder and decoder modules.

[0020] Since the shift and exclusive OR operations are low-power logic, the present application can significantly reduce the energy consumption while maintaining high parallelism. Especially in the scenes of 5G base station, satellite link and high-speed bus communication which need large-scale LDPC decoding, the present application can realize higher operation speed and energy efficiency ratio under lower power budget.

[0021] The circuit structure of this invention is based on a matrix of g×g Z×Z cyclic sub-blocks, making it suitable for QC-LDPC matrices of different sizes and structures. By adjusting the shift values ​​and control cycle number stored in SRAM, it can support LDPC encoding with different code rates and different block lengths, exhibiting good scalability and reconfigurability. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a system schematic diagram of the present invention. Detailed Implementation

[0024] All features disclosed in this specification, or all steps in all disclosed methods or processes, may be combined in any way, except for mutually exclusive features and / or steps.

[0025] Any feature disclosed in this specification (including any appended claims, abstract, and drawings) may be replaced by other equivalent or similar features for a similar purpose, unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is merely one example of a series of equivalent or similar features.

[0026] This invention discloses a circuit and method for solving the lower triangular matrix of a GF(2) domain QC-LDPC based on forward substitution, belonging to the field of digital communication and integrated circuit design technology. It is applicable to hardware acceleration of the matrix solving stage in low-density parity-check (LDPC) encoders. This invention achieves efficient matrix column block solving in the GF(2) domain by combining the forward substitution algorithm with the cyclic characteristics of the QC-LDPC matrix. Compared with traditional matrix inversion methods, this invention can significantly reduce computational complexity and hardware resource consumption while maintaining accuracy.

[0027] In a specific implementation, the input signal includes a QC lower triangular matrix T and a right-hand matrix B. Matrix T consists of g×g Z×Z cyclic sub-blocks, where 1 represents the Z×Z identity matrix and 0 represents a zero matrix. Each sub-block Tᵢ k This could be a unit shift matrix or a zero matrix. To maintain consistency with the subsequent matrix equation solution process, both the right-hand side matrix and the solution matrix are represented in column block vector form, i.e.:

[0028] in, This represents the i-th right-hand vector sub-block. Let represent the corresponding i-th unknown column block vector. The matrix equation T·X = B can be expanded in block form as follows:

[0029] In the formula, "·" represents the bitwise AND operation in the GF(2) field. This form reflects the inherent dependency of the lower triangular matrix—each The solution depends only on the results of the column blocks above it. to Due to the lower triangular structure of matrix T, the above equation can be further rewritten as a recursive form with forward substitution:

[0030] Here, "⊕" represents the bitwise XOR operation in the GF(2) field. From this recursive relation, it can be seen that the entire solution vector... It can be calculated step by step in column order. Each step of the calculation only involves the shifting and accumulation operations of the first i-1 obtained column blocks, which ensures the correctness of the solution and conforms to the logical dependency characteristics of the forward replacement algorithm.

[0031] Based on this, the present invention makes full use of the loop characteristics of the QC structure to perform matrix multiplication. Transform it into a shift-based operation, that is, according to The shifted value is used to perform a circular right shift operation on the data block Xⱼ, and the shifted result is then used in the XOR accumulation operation. This operation can be implemented entirely at the hardware level, no longer relying on traditional multiplier logic, thus achieving low-power, high-parallelism GF(2) domain matrix calculation.

[0032] The specific hardware structure is as follows: Figure 1 As shown, the circuit mainly consists of an input interface module, a shift value storage SRAM module, a column block recursive control module, a cyclic shift array module, a parallel XOR accumulation array module, a register array module, and an output register module. The input interface module loads the structural information of the lower triangular matrix T of the QC and the data of each column of the right-hand matrix B; the shift value storage SRAM module stores the shift control values ​​of each sub-block, arranged sequentially by column index; the column block recursive control module controls the column solving process sequentially in timing and triggers cyclic shift and accumulation operations.

[0033] The specific algorithm implementation process is as follows: First, initialize the solution matrix X and the shift value storage SRAM. All initial values ​​of Xᵢ are 0, i.e.:

[0034] Simultaneously, the shift values ​​of matrix T are written into SRAM column-wise, corresponding to the non-zero sub-blocks of each column. The shift amount is recorded in integer form. Then, the column-wise forward replacement phase begins. For column block indices i from 1 to g, the system solves the problem cyclically. Each cycle corresponds to the calculation process of one column block. In the first cycle, since the first column of the lower triangular matrix T does not depend on other columns, we directly have:

[0035] at this time The value remains unchanged and is written to the register array. In the second cycle, the control module reads... The shift value is used to start the cyclic shift array module. Perform a Z-bit circular right shift operation, with the shift depth being... The shift value of the sub-block is determined. After the shift is completed, the shift result is compared with... Perform a bitwise XOR operation to obtain a new solution:

[0036] After that The value is latched and remains unchanged. In the third cycle, the system reads... and The corresponding shift control signal triggers the cyclic shift array pair and Perform the corresponding circular right shift operation. All shifted results are simultaneously XOR-accumulated in a parallel XOR array to obtain:

[0037] And Latching. The operation process when i=2 can be further explained: ⊕ ,in Indicates will (Right now )according to The shifted value is circularly shifted right (e.g., shifted right by 2 bits), and then compared with... Perform a bitwise XOR operation. This XOR operation is completed by a parallel XOR array module with Z XOR units, which matches the output width of the cyclic shift array.

[0038] Following this pattern, the entire system completes the forward replacement calculation for all g columns after the g-th cycle. Each recursive calculation is performed in parallel by shift operations and XOR accumulation operations, forming a multi-cycle pipelined computing mechanism that can continuously output column block results without global waiting.

[0039] The final output stage is completed by the output register module. This module contains a multiplexer and a latch array. At the end of the g-th cycle, it outputs all latched values ​​X1 to Xg in parallel to obtain the final solution.

[0040] The entire circuit exhibits highly pipelining characteristics in its hardware implementation. The cycle counting unit in the column block recursive control module increments synchronously with the SRAM address lines, ensuring that each cycle only accesses the shift information corresponding to the current column, thereby significantly reducing the SRAM access bandwidth requirements. Data alternation and time multiplexing are achieved between column block calculations through a register array, and shift and XOR operations between different cycles are overlapped in hardware, greatly improving throughput.

[0041] In the FPGA implementation, the cyclic shift array is constructed using Z-bit wide parallel shift registers, with shift control signals derived from SRAM output; the XOR accumulator array consists of Z two-input XOR gates, with a logic delay of only one gate level; the register array is implemented using dual-port RAM to support simultaneous reading and writing. The control logic section employs a finite state machine design to synchronously schedule column indexing, shift start, XOR trigger, and output latch signals.

[0042] Experimental verification shows that when g=8 and Z=64, the circuit of the present invention can achieve a complete solution at a clock speed of 200 MHz. Each operation only requires 8 clock cycles to complete the solution of T·X=B. The decoding throughput exceeds 1.6 Gbit / s, the logic utilization is reduced by about 70% compared with the traditional matrix inversion architecture, and the power consumption is reduced by about 40%, demonstrating extremely high performance and energy efficiency.

[0043] In summary, this invention achieves a highly efficient forward substitution matrix solving circuit by mapping the cyclic characteristics of the QC-LDPC matrix to hardware shift operations and combining it with the logical XOR summation mechanism of the GF(2) field. This structure fully leverages the hardware parallelism and pipeline characteristics, greatly improving the computational efficiency in the LDPC encoding process. It is particularly suitable for scenarios requiring low-latency, high-throughput matrix solving in high-speed communication, satellite transmission, and data storage controllers.

[0044] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions conceived without inventive effort should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A circuit for solving the lower triangular matrix of GF(2) domain QC-LDPC based on forward substitution, characterized in that, include: The input interface module is used to receive a QC lower triangular matrix T consisting of several Z×Z cyclic sub-blocks and a right matrix B, wherein matrix T is stored in a column block structure, and each sub-block is a unit shift matrix or a zero matrix. The shift value storage SRAM module is used to store the shift values ​​of each sub-block in the lower triangular matrix T, and the shift values ​​are arranged sequentially by column index; The column block recursive control module is used to control the execution of forward replacement calculations in column order. When the i-th column is calculated, the results of the first i-1 columns are latched and the i-th column is solved. The cyclic shift array module includes several parallel cyclic shift units. The shift depth of each cyclic shift unit is output by the shift value storage SRAM module and used to determine the shift depth according to the corresponding shift value. Shift value pairs input sub-blocks or Perform a circular right shift operation; A parallel XOR accumulation array module, connected to the cyclic shift array module, is used to perform bitwise XOR operations on each shift result in the GF(2) domain to achieve column vector summation; The register array module is used to temporarily store the corresponding intermediate solution vectors after each column block is solved. And it will be included in the accumulation when the next column block is calculated; The output register module is used to output the solution matrix after all g column blocks have been solved. ; The column block recursive control module sequentially executes a solution process for g cycles, completing the forward replacement calculation of one column block in each cycle. It also achieves pipelined parallelism of shift and summation operations through a cyclic shift array and a parallel XOR accumulation array, thereby completing the matrix equation T. A fast solution for X = B.

2. The GF(2) domain QC-LDPC lower triangular matrix solving circuit based on forward substitution according to claim 1, characterized in that: The cyclic shift array module consists of multiple Z-bit cyclic shifters. The control terminal of each cyclic shifter is connected to the shift control line of the shift value storage SRAM module to realize parallel shift operation based on QC sub-blocks.

3. The GF(2) domain QC-LDPC lower triangular matrix solving circuit based on forward substitution according to claim 1, characterized in that: The parallel XOR accumulator array module consists of Z XOR gate arrays. The input of each XOR gate array is connected to the output of the corresponding cyclic shifter, and the output is connected to the input of the register array module to complete bit-by-bit accumulation in the GF(2) domain.

4. The GF(2) domain QC-LDPC lower triangular matrix solving circuit based on forward substitution according to claim 1, characterized in that: The column block recursive control module includes: The cycle counting unit is used to generate the timing signal for column index i; The control logic unit is used to control the start and latching timing of the solution for the i-th column according to the column index i. The data path selection unit is used to select the output result of the previous column during the solution process. Feedback is sent to the cyclic shift array module.

5. The GF(2) domain QC-LDPC lower triangular matrix solving circuit based on forward substitution according to claim 1, characterized in that: The address lines of the shift value storage SRAM module increment synchronously with the column block recursive control module, so that each cycle only accesses the shift information of the corresponding column, reducing access bandwidth.

6. The GF(2) domain QC-LDPC lower triangular matrix solving circuit based on forward substitution according to claim 1, characterized in that: The circuit is implemented in a pipelined structure, and multiple column blocks can be recursively calculated continuously. The calculation units in adjacent cycles can achieve data alternation and parallel operation through a register array module, thereby improving the decoding throughput.

7. The GF(2) domain QC-LDPC lower triangular matrix solving circuit based on forward substitution according to claim 1, characterized in that: The output register module includes a multiplexer and a latch array, used to output the solution results of all column blocks at the end of the last cycle.

8. A method for solving the lower triangular matrix of GF(2) domain QC-LDPC based on forward substitution, characterized in that, Includes the following steps: Input and initialization: Store the shift values ​​of the lower triangular matrix T of QC column by column into the shift value storage SRAM module, input the right matrix B into the register array module and initialize the solution vector X = 0; Block recursive solution: Execute the following steps on column index i from 1 to g: a) Read the shift control signal of the i-th column from the shift value storage SRAM module; b) The obtained column blocks are processed using the cyclic shift array module. Perform a shift operation; c) Perform XOR accumulation on the shift result using the parallel XOR accumulator array module and then add it to the corresponding... Performing GF(2) addition, we get ; d) will The result is written to the register array module; Output phase: When i = g, output the solution matrix of all columns. .

9. The method for solving the lower triangular matrix of GF(2) domain QC-LDPC based on forward substitution according to claim 8, characterized in that: The XOR accumulation operation in step 2 is performed using an XOR array with a parallelism of Z to improve the hardware solution speed.

10. The method for solving the lower triangular matrix of GF(2) domain QC-LDPC based on forward substitution according to claim 8, characterized in that: The cyclic shift operation dynamically adjusts the shift depth in each cycle based on the shift control signal. The shift depth corresponds to the non-zero sub-block position of the lower triangular matrix T, realizing shift mapping based on QC characteristics.

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