Semiconductor memory device including conductive layers with reduced surface energy

Abstract

A semiconductor memory device includes a plurality of semiconductor patterns, a plurality of bit lines, a plurality of word lines, and a plurality of cell capacitors. Each of the plurality of semiconductor patterns includes a first end portion and a second end portion. Each of the plurality of bit lines is coupled with the first end portion of each of the plurality of semiconductor patterns. Each of the plurality of word lines includes a first conductive layer including a first molybdenum (Mo) derivative having a first composition, a second conductive layer including a second molybdenum (Mo) derivative having a second composition different from the first composition, and a third conductive layer including a third molybdenum (Mo) derivative having a third composition different from the second composition. Each of the plurality of cell capacitors is coupled with the second end portion of each of the plurality of semiconductor patterns.