Semiconductor device including double side word line

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, a first word line, a second word line, and a channel layer. The bit line is disposed on the substrate and extends along a first direction. The first word line is disposed on the substrate and extends along a second direction substantially perpendicular to the first direction. The second word line is disposed on the substrate and extends along the second direction. The channel layer is disposed between the first word line and the second word line and extends along the second direction.

Description

Technical Field

[0001] This application is a division of U.S. Application No. 113128011, filed on July 29, 2024, which claims priority and benefits from U.S. Official Application No. 18 / 653,129, filed on May 2, 2024, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device comprising double-sided word lines. Prior Technology

[0003] With the rapid growth of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Technological advancements in IC materials and design have resulted in generation after generation of ICs, each generation being smaller and more complex than the last.

[0004] Dynamic Random Access Memory (DRAM) devices store each bit of data in an independent capacitor within an integrated circuit. Typically, DRAM cells are arranged in a square array, with each cell having one capacitor and one transistor. Traditional DRAM has evolved into a 6F² DRAM cell, where F represents the minimum feature width or critical dimension (CD). However, in recent years, with the continuous reduction of word line pitch, DRAM manufacturers have faced a significant challenge in shrinking the area of ​​memory cells.

[0005] The discussion in the preceding technical paragraphs is provided for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes the prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion in the preceding technical paragraphs, constitutes the prior art of this disclosure. Summary of the Invention

[0006] One aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a substrate, a bit line, a first word line, a second word line, and a channel layer. The bit line is disposed on the substrate and extends along a first direction. The first word line is disposed on the substrate and extends along a second direction substantially perpendicular to the first direction. The second word line is disposed on the substrate and extends along the second direction. The channel layer is disposed between the first word line and the second word line and extends along the second direction.

[0007] Another aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a substrate, a bit line, a first word line, and a channel layer. The bit line is disposed on the substrate and extends along a first direction. The channel layer is connected to the bit line and extends along a second direction substantially perpendicular to the first direction. The first word line is disposed on a first side of the channel layer. An upper surface of the first word line is substantially aligned with an upper surface of the channel layer.

[0008] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. This method includes: providing a substrate; forming a bit line on the substrate, wherein the bit line extends along a first direction; forming a first word line and a second word line on the bit line, wherein each of the first word line and the second word line extends along a second direction different from the first direction; and forming a channel layer between the first word line and the second word line.

[0009] The embodiments disclosed herein provide a semiconductor device and a method for manufacturing the same. This semiconductor device includes a common channel and two word lines disposed on opposite sides of the common channel. This arrangement eliminates the need for capacitive contacts. Furthermore, compared to conventional semiconductor devices (e.g., a 6F2 dynamic random access memory cell), the cell area of ​​the semiconductor device can be reduced by up to 30% while maintaining the same performance.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0011] When referring to the drawings in conjunction with the embodiments and the scope of the claim, a more comprehensive understanding of the disclosure of this application can be obtained, wherein in all the drawings, the same element symbols represent similar elements, and: Figure 1A is a top view illustrating a semiconductor element of some embodiments of this disclosure. Figure 1B illustrates a cross-sectional view taken along section line A-A' in Figure 1A of some embodiments of this disclosure. Figure 2A illustrates one or more stages of an exemplary manufacturing method for a semiconductor element of some embodiments disclosed herein. Figure 2B illustrates a cross-sectional view taken along section line A-A' in Figure 2A of some embodiments of this disclosure. Figure 3A illustrates one or more stages of an exemplary manufacturing method for a semiconductor element of some embodiments disclosed herein. Figure 3B illustrates a cross-sectional view taken along section line A-A' in Figure 2A of some embodiments of this disclosure. Figure 4A illustrates one or more stages of an exemplary manufacturing method for a semiconductor element of some embodiments disclosed herein. Figure 4B illustrates a cross-sectional view taken along section line A-A' in Figure 2A of some embodiments of this disclosure. Figure 5A illustrates one or more stages of an exemplary manufacturing method for a semiconductor element of some embodiments disclosed herein. Figure 5B illustrates a cross-sectional view taken along section line A-A' in Figure 2A of some embodiments of this disclosure. Figure 6A illustrates one or more stages of an exemplary manufacturing method for a semiconductor element of some embodiments disclosed herein. Figure 6B illustrates a cross-sectional view taken along section line A-A' in Figure 2A of some embodiments of this disclosure. Figure 7A illustrates one or more stages of an exemplary manufacturing method for a semiconductor element of some embodiments disclosed herein. Figure 7B illustrates a cross-sectional view taken along section line A-A' in Figure 2A of some embodiments of this disclosure. Figure 8A illustrates one or more stages of an exemplary manufacturing method for a semiconductor element of some embodiments disclosed herein. Figure 8B illustrates a cross-sectional view taken along section line A-A' in Figure 2A of some embodiments of this disclosure. Figure 9A illustrates one or more stages of an exemplary manufacturing method for a semiconductor element of some embodiments disclosed herein. Figure 9B illustrates a cross-sectional view taken along section line A-A' in Figure 2A of some embodiments of this disclosure. Figure 10A illustrates one or more stages of an exemplary manufacturing method for a semiconductor element of some embodiments disclosed herein. Figure 10B illustrates a cross-sectional view taken along section line A-A' in Figure 2A of some embodiments of this disclosure. Figure 11 is a flowchart of a method for manufacturing a memory device according to some embodiments of the present disclosure. Implementation

[0012] The embodiments or exemplary cases of this disclosure shown in the drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally occur to those skilled in the art to which this disclosure pertains. Component symbols may be repeated throughout the embodiments, but this does not necessarily mean that one(s) feature of one embodiment is applicable to another embodiment, even if they share the same component symbols.

[0013] It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, this starting component may be directly connected to or coupled to this other component or other intermediate components.

[0014] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, the first component, part, region, layer, or section discussed below may be referred to as the second component, part, region, layer, or section without departing from the teachings of this disclosure.

[0015] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the concept of the invention. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context otherwise requires. It should be further understood that the terms "comprising" and "including," when used in this specification, indicate the presence of stated features, integers, steps, operations, components, or elements, but do not preclude the presence or addition of a further feature, integer, step, operation, component, element, or group thereof.

[0016] It should be noted that the term "about," used to modify the amount of ingredients, components, or reactants disclosed herein, refers, for example, to numerical variations that may occur through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to unintentional errors in the measurement procedures, differences in the manufacture, source, or purity of the ingredients used to prepare the composition or to carry out the method, etc. On one hand, the term "about" means within 10% of the reported value. On another hand, the term "about" means within 5% of the reported value. And yet another hand, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0017] Figure 1A is a top view illustrating a semiconductor element 1a according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 1a may be adapted to a memory element, such as a dynamic random access memory (DRAM) element, a one-time programming (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element.

[0018] In some embodiments, semiconductor element 1a may include a plurality of circuit units 10. Each circuit unit 10 may include bit lines 110, channel layer 120, gate dielectrics 132a and 132b, word lines 136a and 136b, and capacitor assembly 150.

[0019] Bit line 110 may extend along the X direction. Channel layer 120 may extend along the Y direction, thus presenting an elongated shape extending along the Y direction, which may be substantially perpendicular to the X direction. In some embodiments, gate dielectric 132a may be located at one side 120s1 of channel layer 120 and extend along the Y direction. In some embodiments, gate dielectric 132b may be located at one side 120s2 of channel layer 120 and extend along the Y direction. In some embodiments, word line 136a may be located at one side 120s1 of channel layer 120 and extend along the Y direction. In some embodiments, word line 136b may be located at one side 120s2 of channel layer 120 and extend along the Y direction. Capacitor assembly 150 may overlap with bit line 110 along the Z direction. Capacitor assembly 150 may overlap with channel layer 120 along the Z direction.

[0020] In some embodiments, channel layer 120 may have a generally stripe-shaped cross-sectional profile. In some embodiments, gate dielectric 132a (or gate dielectric 132b) may have a generally stripe-shaped cross-sectional profile. In some embodiments, word line 136a (or word line 136b) may have a generally stripe-shaped cross-sectional profile.

[0021] Channel layer 120 may have a width W1 along the X direction. Character line 136a (or character line 136b) may have a width W2 along the X direction. In some embodiments, width W1 may be greater than width W2.

[0022] During a read operation, the word lines can be activated, thereby turning on the transistors. An activated transistor allows the sense amplifier to read the voltage across the capacitor via the bit lines. During a write operation, when the word lines are activated, the data to be written can be provided on the bit lines.

[0023] Figure 1B illustrates a cross-sectional view taken along section line A-A' of semiconductor element 1a in Figure 1A, which discloses some embodiments of the present invention.

[0024] Semiconductor element 1a may include substrate 102. Substrate 102 may be a semiconductor substrate, such as a host semiconductor, semiconductor-on-insulator (SOI) substrate, or similar substrate. Substrate 102 may include elemental semiconductors, including monocrystalline, polycrystalline, or amorphous silicon or germanium; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, and indium gallium arsenide phosphide; any other suitable materials; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a silicon-germanium alloy having a gradient silicon characteristic structure, wherein the silicon and germanium composition changes from one ratio at one location of the gradient silicon-germanium characteristic structure to another ratio at another location. In another embodiment, the silicon-germanium alloy is formed on a silicon substrate. In some embodiments, the silicon-germanium alloy can be mechanically strained by another material in contact with the silicon-germanium alloy. In some embodiments, the substrate 102 may have a multilayer structure, or the substrate 102 may include a multilayer compound semiconductor structure.

[0025] Semiconductor device 1a may include a dielectric layer 106. The dielectric layer 106 may be disposed on substrate 102. The dielectric layer 106 may include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof.

[0026] Bit lines 110 can be disposed on dielectric layer 106. Bit lines 110 may include copper (Cu), tungsten (W), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or combinations thereof.

[0027] Semiconductor device 1a may include a capping layer 112. The capping layer 112 may be disposed on or above bit line 110 and extend along the X direction. The capping layer 112 may include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof.

[0028] A channel layer 120 (or active layer) may be disposed on bit line 110. Channel layer 120 may penetrate capping layer 112. Channel layer 120 may be connected to bit line 110. In other embodiments, the channel layer may include a metal oxide.Metal oxides may include, but are not limited to: indium oxide; tin oxide; zinc oxide; two-component metal oxides, such as: indium-zinc (In-Zn-based) oxides, tin-zinc (Sn-Zn-based) oxides, aluminum-zinc (Al-Zn-based) oxides, zinc-magnesium (Zn-Mg-based) oxides, tin-magnesium (Sn-Mg-based) oxides, indium-magnesium (In-Mg-based) oxides, or indium-gallium (In-Ga-based) oxides; three-component metal oxides, such as: indium-gallium-zinc (In-Ga-Zn-based) oxides (also represented as IGZO), indium-aluminum-zinc (In... —Al—Zn-based oxides, Indium Tin (In—Sn-based) oxides (also represented as ITO), Indium Tin Zinc (In—Sn—Zn-based) oxides, Tin Gallium Zinc (Sn—Ga—Zn-based) oxides, Al Gallium Zinc (Al—Ga—Zn-based) oxides, Tin Aluminum Zinc (Sn—Al—Zn-based) oxides, Indium Hafnium Zinc (In—Hf—Zn-based) oxides, Indium Lanthanum Zinc (In—La—Zn-based) oxides, Indium Cerium Zinc (In—Ce—Zn-based) oxides, Indium Pr—Zn-bas Indium-Nd-Zn based oxides, Indium-Sm-Zn based oxides, Indium-Eu-Zn based oxides, Indium-Gd-Zn based oxides, Indium-Tb-Zn based oxides, Indium-Dy-Zn based oxides, Indium-Ho-Zn based oxides, Indium-Er-Zn based oxides, Indium-Tm-Zn based oxides, Indium-Ytterbium-Zn based oxides, Indium-Ho-Zn based oxides, Indium-Er-Zn based oxides, Indium-Tm-Zn based oxides, Indium-Ytterbium-Zn based oxides, Indium-Nd-Zn based oxides, Indium-Sm-Zn based oxides, Indium-Tm-Zn based oxides, Indium-Ytterbium-Zn based oxides, Indium-Nd-Zn based oxides, Indium-Er-Zn based oxides, Indium-Tm-Zn based oxides, Indium-Ytterbium-Zn based oxides, Indium-Nd-Zn based oxides, Indium-Sm-Zn based oxides, Indium-Eu-Zn based oxides, Indium-Gd-Zn based oxides, Indium-Tbium ...Sm-Zn based oxides, Indium-Eu-Zn based oxides, Indium-Gd-Zn based oxides, Indium-Sm-Zn based oxides, Indium-Sm-Zn based oxides, Indium-Eu-Zn based oxides, Indium-Gd-Zn based oxides, Indium-Sm-Zn based oxides, Indium-Sm-Zn based oxides, Indium-Eu-Zn based oxides —Yb—Zn-based) oxides or indium-ludium-zinc (In—Lu—Zn-based) oxides; and four-component metal oxides, such as: indium-tin-gallium-zinc (In—Sn—Ga—Zn-based) oxides, indium-hafium-gallium-zinc (In—Hf—Ga—Zn-based) oxides, indium-aluminum-gallium-zinc (In—Al—Ga—Zn-based) oxides, indium-tin-aluminum-zinc (In—Sn—Al—Zn-based) oxides, indium-tin-hafium-zinc (In—Sn—Hf—Zn-based) oxides or indium-hafium-aluminum-zinc (In—Hf—Al—Zn-based) oxides, but this disclosure is not limited thereto.

[0029] Gate dielectric 132a may be disposed on capping layer 112. Gate dielectric 132a may be disposed on side 120s1 of channel layer 120. Capping layer 112 is located between gate dielectric 132a and bit line 110. Gate dielectric 132b may be disposed on capping layer 112. Gate dielectric 132b may be disposed on side 120s2 of channel layer 120. Each of gate dielectric 132a and gate dielectric 132b may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof. In some embodiments, gate dielectric 132a and gate dielectric 132b may include a high-k dielectric material. The high-k dielectric material may have a dielectric constant (k value) greater than 4. High dielectric constant dielectric materials may include hafnium dioxide (HfO2), zirconium dioxide (ZrO2), lanthanum trioxide (La2O3), yttrium trioxide (Y2O3), aluminum trioxide (Al2O3), titanium dioxide (TiO2), or other suitable materials. The gate dielectric 132a may have a surface 132s1 (or lower surface), a surface 132s2 (or upper surface), and a surface 132s3 (or side surface or sidewall) extending between surfaces 132s1 and 132s2.

[0030] Character line 136a may be disposed on capping layer 112. Character line 136a may be disposed on side 120s1 of channel layer 120. Character line 136a may be separated from channel layer 120 by gate dielectric 132a. Character line 136b may be disposed on capping layer 112. Character line 136b may be disposed on side 120s2 of channel layer 120. Character line 136b may be separated from channel layer 120 by gate dielectric 132b. Character lines 136a and 136b may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, or combinations thereof. In some embodiments, character lines 136a and 136b may include semiconductor materials with or without dopant. Semiconductor materials may include monocrystalline, polycrystalline, or amorphous silicon or germanium. The character line 136a may have a surface 136s1 (or lower surface), a surface 136s2 (or upper surface), and a surface 136s3 (or side surface or sidewall) extending between the surface 136s1 and the surface 136s2.

[0031] In some embodiments, the surface 132s1 of the gate dielectric 132a may be substantially aligned with or coplanar with the surface 136s1 of the word line 136a. In some embodiments, the surface 132s2 of the gate dielectric 132a may be substantially aligned with or coplanar with the surface 136s2 of the word line 136a. In some embodiments, the surface 132s2 of the gate dielectric 132a may be substantially aligned with or coplanar with the surface 120s3 (or upper surface) of the channel layer 120. In some embodiments, the surface 136s2 of the word line 136a may be substantially aligned with or coplanar with the surface 120s3 of the channel layer 120.

[0032] The gate dielectric 132a may have a length L1 along the Z direction. The word line 136a may have a length L2 along the Z direction. In some embodiments, the length L1 may be approximately equal to the length L2.

[0033] In some embodiments, semiconductor element 1a may include a dielectric pattern 140. The dielectric pattern 140 may be disposed on a capping layer 112. The dielectric pattern 140 may include a plurality of segments 140a. The capping layer 112 is located between the plurality of segments 140a and the bit lines 110. In some embodiments, segments 140a may extend along the Y direction, as shown in FIG1A. Segments 140a may be disposed between two word lines. The dielectric pattern 140 may include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof. Segments 140a may have a surface 140s1 (or a lower surface), a surface 140s2 (or an upper surface), and a surface 140s3 (or a side surface or sidewall) extending between surfaces 140s1 and 140s2. In some embodiments, surface 140s1 of segment 140a may be substantially aligned with or coplanar with surface 136s1 of word line 136a. In some embodiments, the surface 140s1 of segment 140a may be substantially aligned with or coplanar with the surface 132s1 of gate dielectric 132a. In some embodiments, the surface 140s2 of segment 140a may be substantially aligned with or coplanar with the surface 136s2 of word line 136a. In some embodiments, the surface 140s2 of segment 140a may be substantially aligned with or coplanar with the surface 132s2 of gate dielectric 132a. Segment 140a may have a length L3 along the Z direction. In some embodiments, the length L2 may be substantially equal to the length L3.

[0034] Semiconductor element 1a may include a dielectric structure 144. The dielectric structure 144 may be disposed on a dielectric pattern 140. The dielectric structure 144 may include one or more dielectric layers for accommodating a capacitor assembly. The dielectric structure 144 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials (k<4), or other suitable materials.

[0035] In some embodiments, the capacitor assembly 150 may be disposed on the channel layer 120. The capacitor assembly 150 may overlap with the channel layer 120 along the Z direction. The capacitor assembly 150 may be embedded within the dielectric structure 144. In some embodiments, the capacitor assembly 150 may include a first electrode, a capacitor dielectric material, and a second electrode (not shown in the figures). In some embodiments, the capacitor dielectric material may be disposed between the first electrode and the second electrode.

[0036] The first electrode and / or the second electrode may comprise a semiconductor material or a conductive material. The semiconductor material may comprise polycrystalline silicon or other suitable materials. The conductive material may comprise tungsten, copper, aluminum, tantalum, or other suitable materials.

[0037] The dielectric material of a capacitor may include dielectric materials such as silicon oxide, tungsten oxide, zirconium oxide, copper oxide, aluminum oxide, hafnium oxide, or similar materials.

[0038] In this embodiment, semiconductor element 1a includes a common channel (e.g., channel layer 120) and two word lines (e.g., word line 136a and word line 136b) disposed on opposite sides of the common channel. Semiconductor element 1a can define or present a 4F2 dynamic random access memory cell. Compared to conventional semiconductor elements (e.g., 6F2 dynamic random access memory cells), the area of ​​semiconductor element 1a can be reduced by up to 30% while maintaining the same performance.

[0039] Figures 2A to 10A and Figures 2B to 10B illustrate one or more stages of an exemplary manufacturing method of a semiconductor element according to some embodiments of the present disclosure, wherein Figures 2A to 10A are top views, and Figures 2B to 10B are cross-sectional views taken along section line A-A' in Figures 2A to 10A. It should be noted that some elements may be omitted in the top views for clarity.

[0040] Referring to Figures 2A and 2B, a substrate 102 can be provided. A dielectric layer 106 can be formed on the substrate 102. The dielectric layer 106 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, flow-through chemical vapor deposition, or other suitable processes.

[0041] Bit lines 110 can be formed on dielectric layer 106. In some embodiments, a conductive layer (e.g., copper (Cu), tungsten (W), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination thereof) can be formed on dielectric layer 106, and an etching technique (e.g., dry etching) can be performed to pattern this conductive layer. In this way, bit lines 110 can be formed and extend along the X direction.

[0042] Referring to Figures 3A and 3B, a capping layer 112 can be formed on the bit lines 110. In some embodiments, the capping layer 112 can fill the openings between the bit lines 110. The capping layer 112 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, flow chemical vapor deposition, or other suitable processes.

[0043] A dielectric pattern 140 may be formed on the capping layer 112. In some embodiments, a dielectric material (e.g., silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof) may be formed on the capping layer 112 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or other suitable processes, and the dielectric material may be patterned to form segments 140a extending along the Y direction. The dielectric pattern 140 may define trenches 140t that expose the capping layer 112. The trenches 140t may extend along the Y direction.

[0044] Referring to Figures 4A and 4B, a conductive or semiconductor material 136' can be formed on surfaces 140s2 and 140s3 of the dielectric pattern 140. In some embodiments, the conductive or semiconductor material 136' can be formed within a trench 140t. The conductive or semiconductor material 136' can be formed through physical vapor deposition, chemical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, flow chemical vapor deposition, electroplating, or other suitable processes.

[0045] Referring to Figures 5A and 5B, etching technique E1 can be performed to pattern the conductive or semiconductor material 136'. In some embodiments, the portion 136c of the conductive or semiconductor material 136' located within the trench 140t, as shown in Figure 4B, can be removed. The capping layer 112 can be exposed.

[0046] Referring to Figures 6A and 6B, a gate dielectric material 132' can be formed on the upper surface and sidewalls of the conductive or semiconductor material 136'. The gate dielectric material 132' can be formed within the trench 140t. In some embodiments, the gate dielectric material 132' can be formed on the capping layer 112. The gate dielectric material 132' can be formed by atomic layer deposition, chemical vapor deposition, low-pressure chemical vapor deposition, flow-through chemical vapor deposition, physical vapor deposition, or other suitable processes.

[0047] Referring to Figures 7A and 7B, etching technique E2 can be performed. In some embodiments, the portion 136d of the conductive or semiconductor material 136' shown in Figure 6B, located above the surface 140s3 of the dielectric pattern 140, can be removed. In some embodiments, the portion 136c of the gate dielectric material 132' shown in Figure 6B, located above the conductive or semiconductor material 136', can be removed. In some embodiments, the portion 132d of the gate dielectric material 132', located within the trench 140t, shown in Figure 6B, can be removed. In some embodiments, the portion 112a of the capping layer 112 shown in Figure 6B can be removed. Thus, word lines 136a and 136b can be defined on the surface 140s3 of the dielectric pattern 140. Gate dielectrics 132a and 132b can be defined on the surface 136s3 of the word lines 136a and 136b, respectively.

[0048] Referring to Figures 8A and 8B, etching technique E3 can be performed. In some embodiments, the portion 112b of the capping layer 112 exposed by the trench 140t, as shown in Figure 7B, can be removed. In this way, the bit line 110 can be exposed by the trench 140t.

[0049] Referring to Figures 9A and 9B, a channel layer 120 can be formed within the trench 140t. The channel layer 120 can be formed on the surface 132s3 of the gate dielectric 132a and / or the gate dielectric 132b. In some embodiments, a metal oxide material (e.g., IGZO) can be formed on the surface 140s2 of the dielectric pattern 140, the surface 136s2 of the word lines 136a and 136b, the surface 132s2 of the gate dielectric 132a and 132b, and within the trench 140t by chemical vapor deposition, low-pressure chemical vapor deposition, flow-through chemical vapor deposition, physical vapor deposition, or other suitable processes. In some embodiments, chemical mechanical polishing (CMP) can be performed to remove the channel layer 120 located on surface 140s2 of dielectric pattern 140, surface 136s2 of word lines 136a and 136b, and surface 132s2 of gate dielectric 132a. In this way, the upper surfaces of the channel layer 120 (e.g., surface 120s3), the upper surfaces of word lines 136a and 136b (e.g., surface 136s2), and the upper surfaces of gate dielectrics 132a and 132b (e.g., surface 132s2) can be substantially aligned.

[0050] Referring to Figures 10A and 10B, a dielectric structure 144 can be formed on the dielectric pattern 140 by chemical vapor deposition, low-pressure chemical vapor deposition, flow-through chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The dielectric structure 144 can be patterned to form a framework defining a capacitor assembly 150. The capacitor assembly 150 can be formed within the dielectric structure 144 and connected to the channel layer 120. In this way, a semiconductor device (e.g., semiconductor device 1a as shown in Figures 1A and 1B) can be manufactured.

[0051] Figure 11 is a flowchart illustrating a method 2 for manufacturing a semiconductor element according to some embodiments of the present disclosure.

[0052] Method 2 begins at operation 202, in which a substrate can be provided. A plurality of bit lines can be formed on the substrate. The bit lines can extend along a first direction.

[0053] Method 2 proceeds to operation 204, wherein a dielectric pattern may be formed on the bit line. The dielectric pattern may include a plurality of segments extending along a second direction generally perpendicular to the first direction. The dielectric pattern may define a plurality of trenches extending along the second direction.

[0054] Method 2 continues with operation 206, wherein a conductive or semiconductor material can be formed on the upper surface and sidewalls of the dielectric pattern. A conductive or semiconductor material can be formed within the trenches of the dielectric pattern.

[0055] Method 2 continues with operation 208, in which conductive or semiconductor material can be removed from the trench.

[0056] Method 2 continues with operation 210, wherein a gate dielectric material can be formed on a conductive or semiconductor material. The gate dielectric material can be formed within a trench.

[0057] Method 2 continues with operation 212, wherein a portion of the conductive or semiconductor material located within the trench may be removed. A portion of the gate dielectric material located within the trench may be removed. A first word line and a second word line may be formed on the sidewalls of the dielectric pattern. A first gate dielectric and a second gate dielectric may be formed on the sidewalls of the first word line and the second word line, respectively.

[0058] Method 2 continues with operation 214, which can form a channel layer within the trench.

[0059] Method 2 continues with operation 216, which allows the formation of capacitor components on the channel layer. This enables the fabrication of semiconductor devices.

[0060] Method 2 is merely an example and is not intended to limit this disclosure beyond what is expressly stated in the claims. Additional operations may be provided before, during, or after each operation of Method 2, and some described operations may be substituted, omitted, or reordered for other embodiments of this method.

[0061] One aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a substrate, a bit line, a first word line, a second word line, and a channel layer. The bit line is disposed on the substrate and extends along a first direction. The first word line is disposed on the substrate and extends along a second direction substantially perpendicular to the first direction. The second word line is disposed on the substrate and extends along the second direction. The channel layer is disposed between the first word line and the second word line and extends along the second direction.

[0062] Another aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a substrate, a bit line, a first word line, and a channel layer. The bit line is disposed on the substrate and extends along a first direction. The channel layer is connected to the bit line and extends along a second direction substantially perpendicular to the first direction. The first word line is disposed on a first side of the channel layer. An upper surface of the first word line is substantially aligned with an upper surface of the channel layer.

[0063] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. This method includes: providing a substrate; forming a bit line on the substrate, wherein the bit line extends along a first direction; forming a first word line and a second word line on the bit line, wherein each of the first word line and the second word line extends along a second direction different from the first direction; and forming a channel layer between the first word line and the second word line.

[0064] The embodiments disclosed herein provide a semiconductor device and a method for manufacturing the same. This semiconductor device includes a common channel and two word lines disposed on opposite sides of the common channel. This arrangement eliminates the need for capacitive contacts. Furthermore, compared to conventional semiconductor devices (e.g., a 6F2 dynamic random access memory cell), the cell area of ​​the semiconductor device can be reduced by up to 30% while maintaining the same performance.

[0065] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0066] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0067] 1a: Semiconductor components 2: Method 10: Circuit Unit 102:Substrate 106: Dielectric layer 110: Bit line 112: Cap layer 112a: Part 112b: Part 120: Channel Layer 120s1: Side view 120s2: Side View 120s3: Surface 132': Gate dielectric material 132a: Gate dielectric 132b: Gate dielectric 132c: Partial 132d: Partial 132s1: Surface 132s2: Surface 132s3: Surface 136': Conductive or semiconductor material 136a: Character Line 136b: Character line 136c: Partial 136d: Partial 136s1: Surface 136s2: Surface 136s3: Surface 140: Dielectric pattern 140a: Fragment 140s1: Surface 140s2: Surface 140s3: Surface 140t: Trench 144: Dielectric Structure 150: Capacitor assembly 202: Operation 204: Operation 206: Operation 208: Operation 210: Operation 212: Operation 214: Operation 216: Operation E1: Etching Technology E2: Etching Technology E3: Etching Technology L1: Length L2: Length L3: Length W1: Width W2: Width

Claims

1. A semiconductor device, comprising: One substrate; A bit line is disposed on the substrate and extends along a first direction; A capping layer is disposed on the bit line and extends along the first direction; a channel layer is connected to the bit line and is an elongated strip extending along a second direction substantially perpendicular to the first direction, wherein the channel layer penetrates the capping layer; a first character line is disposed on a first side of the channel layer and extends along the second direction, wherein an upper surface of the first character line is substantially aligned with an upper surface of the channel layer; a first gate dielectric is disposed between the first character line and the channel layer, wherein the capping layer is located between the first gate dielectric and the bit line; a dielectric pattern having a plurality of segments, wherein the capping layer is located between the plurality of segments and the bit line; and a capacitor assembly is located on the channel layer in a third direction, wherein the third direction is substantially perpendicular to the first direction and the second direction.

2. The semiconductor device as claimed in claim 1 further includes: a second word line disposed on a second side of the channel layer.

3. The semiconductor element as claimed in claim 1, wherein the first gate dielectric extends along the second direction.

4. The semiconductor device as claimed in claim 3, wherein an upper surface of the first gate dielectric is substantially aligned with the upper surface of the channel layer.

5. The semiconductor device as claimed in claim 3, wherein an upper surface of the first gate dielectric is substantially aligned with the upper surface of the first word line.

6. The semiconductor element as claimed in claim 3, wherein a lower surface of the first gate dielectric is substantially aligned with a lower surface of the first word line.

7. The semiconductor element as claimed in claim 3, wherein the length of the first word line along the third direction is substantially the same as the length of the first gate dielectric along the third direction.

8. The semiconductor element as claimed in claim 3, wherein the first gate dielectric has a strip-shaped cross-sectional profile.

9. The semiconductor element as claimed in claim 1, wherein the first character line has a strip-shaped cross-sectional profile.

10. The semiconductor device as claimed in claim 1, wherein the channel layer has a strip-shaped cross-sectional profile.

11. The semiconductor element as claimed in claim 1, wherein the width of the first word line along the first direction is smaller than the width of the channel layer along the first direction.

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