System and method for interrupt command queuing and ordering

a command and system technology, applied in the field of system and method for interrupt command queuing and ordering, can solve the problems of reduced system performance, software complexity required to detect and reset various, and deadlock conditions

US20010027502A1Inactive Publication Date: 2001-10-04LINKEDIN
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
Publication Date
2001-10-04
Estimated Expiration
Not applicable · inactive patent

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Abstract

An input / output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.
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Description

[0001] 1. Technical Field of the Invention

[0002] This invention pertains to an input / output bus bridge and command queuing system. More particularly, it relates to a system for strictly ordering EOI commands relative to MMIO accesses while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses

[0003] 2. Background Art

[0004] In a PowerPC computer system which is Common Hardware Reference Platform (CHRP) compliant, the external interrupt router receives interrupt commands from Bus Unit Controllers (BUCs) and responds with commands that include:

[0005] End of Interrupt (EOI)

[0006] INterrupt Return (INR)

[0007] Interrupt Reissue Request (IRR)

[0008] The function of the memory mapped I / O (MMIO) command is to send command information to, and retrieve status information from, Bus Unit Controllers and I / O devices. In some low performance devices, MMIO commands may be to transmit program data. The bridge unit responds to an MMIO command by determining the correct target (i...

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Embodiment Construction

[0070] It will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. In particular, it is within the scope of the invention to provide a memory device, such as a transmission medium, magnetic or optical tape or disc, or the like, for storing signals for controlling the operation of a computer according to the method of the invention and / or to structure its components in accordance with the system of the invention.

[0071] Accordingly, the scope of protection of this invention is limited only by the following claims and their equivalents.