Back-contact cell and manufacturing method therefor, and photovoltaic module

Abstract

A back-contact cell and a manufacturing method therefor, and a photovoltaic module, which belong to the technical field of photovoltaics. The back-contact cell comprises: a semiconductor substrate, which has a first surface and a second surface, which are arranged opposite each other, wherein the first surface is of a textured structure; and a tunneling passivation layer and an N-type doped polycrystalline silicon layer, which are sequentially stacked in a local region of the second surface in the thickness direction of the semiconductor substrate, wherein the ratio of the thickness of the part of the N-type doped polycrystalline silicon layer that is located in an edge region of the second surface to the thickness of the part of the N-type doped polycrystalline silicon layer that is located in the central region of the second surface is greater than or equal to 1 and is less than or equal to 1.2.

Description

Back contact cell and manufacturing method thereof, and photovoltaic module

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 13, 2023, with application number 202310702158.2 and invention name “A back-contact battery, its manufacturing method, and photovoltaic module”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0003] Tunneling passivated back-contact solar cells (TPBCSs) are solar cells with both the positive and negative electrodes on the back side of the cell, free from metal electrodes on the front side, and employing a tunneling passivated contact structure. Due to their advantages, such as a large light-absorbing surface and low rear-side carrier recombination rate, TPBCSs have attracted widespread attention in both the photovoltaic academic and industrial sectors, becoming a hot development direction for high-efficiency solar cell technology.

[0004] However, in the tunneling passivated back-contact solar cell formed by the related manufacturing method, the morphology of the N-type doped polysilicon layer containing phosphorus as the doping element is poor, resulting in poor working performance of the tunneling passivated back-contact solar cell.

[0005] Summary of the Invention

[0006] The purpose of this application is to provide a back-contact cell and a manufacturing method thereof, and a photovoltaic module.

[0007] Specifically, this application involves the following aspects:

[0008] In a first aspect, the present application discloses a back-contact cell, comprising: a semiconductor substrate having a first surface and a second surface disposed opposite each other, the first surface having a textured structure, and a tunneling passivation layer and an N-type doped polysilicon layer stacked sequentially along the thickness direction of the semiconductor substrate and disposed on a localized region of the second surface. The ratio of the thickness of the N-type doped polysilicon layer located on an edge region of the second surface to the thickness of the N-type doped polysilicon layer located on a central region of the second surface is greater than or equal to 1 and less than or equal to 1.2.

[0009] When the above technical solution is adopted, the tunneling passivation contact structure composed of the above tunneling passivation layer and the N-type doped polysilicon layer can achieve excellent interface passivation and carrier selective collection, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery. In addition, compared with the thickness ratio of the edge portion to the middle portion of the N-type doped polysilicon layer in the related art being greater than 1.3, the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge region of the second surface to the portion of the N-type doped polysilicon layer located on the central region of the second surface in the present application is greater than or equal to 1 and less than or equal to 1.2. At this time, the difference in thickness between the edge portion and the central portion of the N-type doped polysilicon layer is small. In this case, in the actual manufacturing process, chemical vapor deposition and other processes are usually used to form the tunneling passivation material layer and the intrinsic amorphous silicon material layer used to manufacture the tunneling passivation layer and the N-type doped polysilicon layer. Based on this, when the difference between the thickness of the edge portion and the thickness of the central portion of the N-type doped polycrystalline silicon layer is small, the difference between the thickness of the edge portion and the thickness of the central portion of the intrinsic amorphous silicon material layer forming the N-type doped polycrystalline silicon layer is also small. Because the intrinsic amorphous silicon material layer is formed simultaneously along each portion parallel to the second surface, the chemical dosage ratio of the intrinsic amorphous silicon material located in the edge region of the second surface and the intrinsic amorphous silicon material located in the central region of the second surface are substantially the same. Therefore, when the difference between the thickness of the edge portion and the central portion of the intrinsic amorphous silicon material layer is small, the difference in structural density between the edge portion and the central portion of the intrinsic amorphous silicon material layer is small. Accordingly, when the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment, the density of the edge portion of the phosphosilicate glass layer obtained by the reaction of silicon in the intrinsic amorphous silicon material layer with oxygen in the diffusion environment is also slightly different from the density of its own central portion, so that the edge portion of the phosphosilicate glass layer has a high corrosion resistance that is roughly the same as that of its own central portion, so that during the texturing process of at least the first side of the semiconductor substrate, the phosphosilicate glass layer can well protect the portion of the N-type doped polycrystalline silicon material layer located therebelow for forming the N-type doped polycrystalline silicon layer, so that the morphology and formation range of the obtained N-type doped polycrystalline silicon layer meet the target requirements, which is beneficial to the collection of carriers, reduces reverse leakage, and further helps to improve the photoelectric conversion efficiency of the back contact battery.

[0010] As a possible implementation manner, the size uniformity of the suede structure in each area of ​​the first surface is greater than or equal to 85% and less than 100%.

[0011] When the above technical solution is adopted, the velvet surface on each area of ​​the first surface has a high degree of size uniformity, which is conducive to making each area of ​​the first surface have a high light transmittance, so that more light can be transmitted through the first surface into the semiconductor substrate, further improving the photoelectric conversion efficiency of the back contact battery.

[0012] As a possible implementation manner, the area on the second surface where the tunneling passivation layer and the N-type doped polysilicon layer are not stacked is a polished surface or has a suede structure.

[0013] As a possible implementation manner, the thickness of a portion of the N-type doped polysilicon layer located on the edge region of the second surface is greater than or equal to 175 nm and less than or equal to 225 nm.

[0014] When the above technical solution is adopted, the thickness of the portion of the N-type doped polysilicon layer located on the edge region of the second surface is within the above range. This can prevent the overall thickness of the N-type doped polysilicon layer from being too small and failing to meet the target requirements due to the aforementioned smaller thickness value, and prevent the difficulty in manufacturing an N-type doped polysilicon layer with high thickness uniformity, thereby facilitating the production of a back-contact battery. At the same time, it can also prevent the poor corrosion resistance of the phosphosilicate glass layer located on the edge portion of the N-type doped polysilicon material layer after phosphorus diffusion treatment due to the aforementioned larger thickness value, ensuring that the phosphosilicate glass layer can well encompass all portions of the N-type doped polysilicon material layer used to form the N-type doped polysilicon layer during the texturing process, ensuring that the N-type doped polysilicon layer has a good morphology and a formation range that meets the target requirements.

[0015] As a possible implementation manner, the thickness of the portion of the N-type doped polysilicon layer located in the central area of ​​the second surface is greater than or equal to 150 nm and less than or equal to 200 nm.

[0016] As a possible implementation, the average doping concentration of impurities in the N-type doped polysilicon layer is greater than or equal to 3.5×10 20 / cm 3 and less than or equal to 4.0×10 20 / cm 3 .

[0017] When the above technical solution is adopted, the average doping concentration of impurities in the N-type doped polysilicon layer is within the above range. Under the premise of ensuring that the N-type doped polysilicon layer has excellent carrier selective collection effect and does not affect the contact resistance between the N-type doped polysilicon layer and the negative electrode, the average doping concentration of impurities in the N-type doped polysilicon layer is greater than that in the N-type doped polysilicon layer in the related art (where the average doping concentration of impurities in the N-type doped polysilicon layer is greater than 5.0×10 20 / cm 3), appropriately reduce the impurity doping concentration in the N-type doped polysilicon layer in this application. Correspondingly, the average doping concentration of impurities in the N-type doped polysilicon material layer used to manufacture the N-type doped polysilicon layer is also low. Based on this, in the actual manufacturing process, the average doping concentration of impurities in the N-type doped polysilicon material layer after the phosphorus diffusion treatment is proportional to the average doping concentration of impurities in the phosphosilicate glass layer formed on itself, so appropriately reducing the impurity doping concentration in the N-type doped polysilicon layer also means that the average doping concentration of impurities (the impurities include phosphorus) in the phosphosilicate glass layer is reduced. In this case, because the phosphorus doping concentration in the phosphosilicate glass layer is inversely proportional to its own corrosion resistance, appropriately reducing the phosphorus doping concentration in the phosphosilicate glass layer can also improve its own corrosion resistance, further ensuring that the N-type doped polysilicon layer has a good morphology and meets the target formation range.

[0018] In a second aspect, the present application further discloses a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0019] The beneficial effects of the second aspect of this application can be analyzed by referring to the beneficial effects of the first aspect and its various implementation methods, and will not be repeated here.

[0020] On the third aspect, the present application also discloses a method for manufacturing a back-contact battery, which comprises the following steps: first, providing a semiconductor substrate having a first surface and a second surface arranged opposite to each other. Next, a tunneling passivation material layer and an intrinsic amorphous silicon material layer are sequentially formed on one side of the second surface of the semiconductor substrate along the thickness direction of the semiconductor substrate. Next, the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment so that the intrinsic amorphous silicon material layer forms an N-type doped polycrystalline silicon material layer, and a phosphosilicate glass layer is formed on the N-type doped polycrystalline silicon material layer. The thickness ratio of the portion of the N-type doped polycrystalline silicon material layer located on the edge area of ​​the second surface to the portion of the N-type doped polycrystalline silicon material layer located on the central area of ​​the second surface is greater than or equal to 1 and less than or equal to 1.2. Next, under the masking action of the phosphosilicate glass layer, the first surface of the semiconductor substrate is subjected to a texturing treatment so that a velvet structure is formed on the first surface. Then, the phosphosilicate glass layer, the stacked tunnel passivation material layer, and the N-type doped polysilicon material layer are patterned to form a tunnel passivation layer and an N-type doped polysilicon layer stacked on a local area of ​​the second surface.

[0021] The beneficial effects of the third aspect of this application can be analyzed by referring to the beneficial effects of the first aspect and its various implementation methods, and will not be repeated here.

[0022] As a possible implementation manner, the ambient pressure for forming the intrinsic amorphous silicon material layer is greater than or equal to 100 mTorr and less than or equal to 150 mTorr.

[0023] When employing the above-described technical solution, during the actual manufacturing process of the intrinsic amorphous silicon material layer, reducing the ambient pressure within a certain range can increase the molecular free path, allowing reactive molecular groups to more quickly reach various areas on the surface of the tunneling passivation material layer, rather than concentrating at the same location. Therefore, when the ambient pressure for forming the intrinsic amorphous silicon material layer is within the above-described range, the thickness of the edge portion of the intrinsic amorphous silicon material layer, which would otherwise be caused by high ambient pressure, can be prevented from increasing. This ensures a small difference in thickness between the edge and center portions of the intrinsic amorphous silicon material layer, ensuring that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as that of its center portion. This, in turn, ensures that all portions of the phosphosilicate glass layer formed after the phosphorus diffusion treatment along a direction parallel to the second surface have high corrosion resistance, ensuring that the morphology and formation range of the formed N-type doped polycrystalline silicon meet target requirements. Furthermore, it can prevent low process efficiency due to low ambient pressure.

[0024] As a possible implementation manner, the gas flow rate for forming the intrinsic amorphous silicon material layer is greater than or equal to 0.9 slm and less than or equal to 1.2 slm.

[0025] Using the above technical solution, during the actual fabrication of the intrinsic amorphous silicon material layer, reducing the gas flow rate within a certain range can reduce the total gas flow rate within the diffusion device, thereby reducing the degree of disturbance caused by the gas flow within the diffusion device. This helps optimize the deposition quality of the portion of the intrinsic amorphous silicon material layer located at the edge of the second surface, ensuring that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as that of the central portion. This ensures that all portions of the phosphosilicate glass layer formed after the phosphorus diffusion treatment along the direction parallel to the second surface have high corrosion resistance, ensuring that the morphology and formation range of the formed N-type doped polycrystalline silicon meet target requirements. Furthermore, this prevents low process efficiency caused by low gas flow rates.

[0026] As one possible implementation, after phosphorus diffusion treatment is performed on the intrinsic amorphous silicon material layer, only the phosphosilicate glass layer is patterned under the mask of the phosphosilicate glass layer before texturing the first surface of the semiconductor substrate, so that the remaining portion of the phosphosilicate glass layer is formed on a localized area of ​​the N-type doped polysilicon material layer. In this case, while texturing the first surface of the semiconductor substrate under the mask of the phosphosilicate glass layer, the stacked tunnel passivation material layer and the N-type doped polysilicon material layer are patterned.

[0027] When adopting the above technical solution, the phosphosilicate glass layer located on one side of the second surface is patterned before the texturing treatment, so that in the subsequent texturing process, the texturing etching liquid can not only form a velvet surface on at least the first surface, but also can pattern the N-type doped polysilicon material layer under the masking effect of the remaining part of the phosphosilicate glass layer to obtain an N-type doped polysilicon layer, thereby improving the process efficiency of the back contact battery while ensuring that the morphology and formation range of the N-type doped polysilicon layer meet the target requirements.

[0028] As a possible implementation method, while forming an intrinsic amorphous silicon material layer on one side of the second surface of the semiconductor substrate along the thickness direction of the semiconductor substrate, a wrap-around amorphous silicon layer is formed on the side and part of the first surface of the semiconductor substrate. The width of the formation area of ​​the wrap-around amorphous silicon layer on the first surface is greater than or equal to 0 and less than 10 mm. The width direction of the formation area is parallel to the radial direction of the semiconductor substrate. Moreover, after the phosphorus diffusion treatment, the wrap-around amorphous silicon layer forms a wrap-around doped layer, and a wrap-around phosphosilicate glass layer is formed on the wrap-around doped layer. In the above case, after the phosphorus diffusion treatment is performed on the intrinsic amorphous silicon material layer, and before the first surface of the semiconductor substrate is subjected to the texturing treatment under the masking action of the phosphosilicate glass layer, the manufacturing method of the back contact battery also includes: removing the wrap-around phosphosilicate glass layer and the wrap-around doped layer.

[0029] When the above technical solution is adopted, before the texturing treatment is carried out, the phosphosilicate glass layer and the doped layer formed by the plating need to be removed in sequence, and the etching solution for removing the doped layer will also affect the surface of the portion of the first surface of the semiconductor substrate covered by the plating doped layer, so that a porous structure is formed on the surface of this portion, and the surface of the central area of ​​the first surface of the semiconductor substrate that is not covered by the plating doped layer is relatively flat, resulting in inconsistent sizes of the velvet structures located on the edge area and the central area of ​​the first surface after the subsequent texturing treatment, thereby affecting the light trapping effect of the first surface. In this case, compared with the related art in which the width of the formation area of ​​the plating doped layer formed on the first surface when manufacturing the back-contact battery is greater than 10 mm, in the present application, when the width of the formation area of ​​the plating amorphous silicon layer on the first surface is greater than or equal to 0 and less than 10 mm, its plating width is smaller, which is beneficial to improving the size uniformity of the velvet structure located on each area of ​​the first surface, thereby improving the light trapping effect of the first surface and further improving the photoelectric conversion efficiency of the back-contact battery.

[0030] As a possible implementation manner, the thickness of the phosphosilicate glass layer is greater than or equal to 60 nm and less than or equal to 65 nm.

[0031] When using the above technical solution, the thickness of the phosphosilicate glass layer is within the above range, which can prevent the poor corrosion resistance of the phosphosilicate glass layer caused by a thin phosphosilicate glass layer, ensuring that the morphology and formation range of the formed N-type doped polysilicon layer meet the target requirements. At the same time, it can also prevent the large amount of consumables used in the manufacture of the intrinsic amorphous silicon material layer and the phosphosilicate glass layer caused by a thick phosphosilicate glass layer, thereby helping to control the manufacturing cost of the back-contact cell.

[0032] As a possible implementation, the average thickness of the intrinsic amorphous silicon material layer is H1, the average thickness of the phosphosilicate glass layer is H2, the average thickness of the N-type doped polysilicon material layer is H3, and 40% H2

[0033] When the above technical solution is adopted, as described above, the formation of the phosphosilicate glass layer requires the consumption of silicon elements in the N-type doped polysilicon material layer. Based on this, the average thickness of the intrinsic amorphous silicon material layer, the phosphosilicate glass layer, and the N-type doped polysilicon material layer meeting the above conditions indicates that the thickness of the intrinsic amorphous silicon material layer is appropriate, and the density and structural uniformity of each region of the intrinsic amorphous silicon material layer along the direction parallel to the second surface are both high. This is conducive to ensuring that after the phosphosilicate glass layer is formed, the consumed thickness of the N-type doped polysilicon material layer can meet the theoretical consumption of the high-density N-type doped polysilicon material layer (i.e., the thickness of the phosphosilicate glass layer is approximately equal to half of the reduction in the thickness of the N-type doped polysilicon material layer) or is close to the theoretical consumption. This further indicates that the optimized phosphosilicate glass layer is formed with high quality, ensuring that the formed N-type doped polysilicon layer has good morphology and meets the target formation range.

[0034] As a possible implementation method, the treatment conditions of the phosphorus diffusion treatment are as follows:

[0035] The deposition process temperature is greater than or equal to 850°C and less than or equal to 900°C. And / or, the deposition process ambient pressure is greater than or equal to 150 mbar and less than or equal to 200 mbar. And / or, the deposition process phosphorus source pressure is greater than or equal to 250 mbar and less than or equal to 450 mbar. And / or, the deposition process nitrogen flow rate is greater than or equal to 1500 sccm and less than or equal to 2000 sccm. And / or, the deposition process oxygen flow rate is greater than or equal to 750 sccm and less than or equal to 1000 sccm. And / or, the post-oxidation process temperature is greater than or equal to 850°C and less than or equal to 900°C. And / or, the post-oxidation process oxygen flow rate is greater than or equal to 5000 sccm and less than or equal to 10000 sccm.

[0036] ​When the above technical solution is adopted, in the actual manufacturing process, the average doping concentration of impurities in the formed phosphosilicate glass layer and N-type doped polysilicon material can be regulated by changing the deposition process temperature, deposition process ambient pressure, deposition process phosphorus source pressure, deposition process nitrogen flow rate, and deposition process oxygen flow rate during the above phosphorus diffusion process. Based on this, when at least one of the deposition process temperature, deposition process ambient pressure, deposition process phosphorus source pressure, deposition process nitrogen flow rate, and deposition process oxygen flow rate is within the above corresponding range, the average doping concentration of phosphorus in the phosphosilicate glass layer can be appropriately reduced, so that the phosphosilicate glass layer has higher corrosion resistance, thereby ensuring that the N-type doped polysilicon layer formed based on the N-type doped polysilicon material layer has a good morphology and meets the target formation range. In addition, the thickness of the formed phosphosilicate glass layer can be regulated by changing the post-oxidation process temperature and post-oxidation process oxygen flow rate during the phosphorus diffusion process. Based on this, when at least one of the post-oxidation process temperature and post-oxidation process oxygen flow rate is within the above corresponding range, the thickness of the formed phosphosilicate glass layer can be appropriately increased, thereby improving the corrosion resistance of the phosphosilicate glass layer.

[0037] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] FIG1 is a schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0040] FIG2 is a schematic SEM morphology diagram of a portion of an N-type doped polysilicon layer formed in the related art and located on an edge region of the second surface;

[0041] FIG3 is a schematic SEM morphology diagram of a portion of the N-type doped polysilicon layer located on the edge region of the second surface in an embodiment of the present application;

[0042] FIG4 is a first schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

[0043] FIG5 is a second schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0044] FIG6 is a third schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0045] FIG7 is a fourth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0046] FIG8 is a fifth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0047] FIG9 is a sixth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

[0048] FIG10 is a seventh schematic longitudinal cross-sectional view of the structure of the back-contact battery provided in an embodiment of the present application during the manufacturing process.

[0049] Figure numerals: 11 is a semiconductor substrate, 12 is a tunneling passivation material layer, 13 is an intrinsic amorphous silicon material layer, 14 is a wound-plated amorphous silicon layer, 15 is an N-type doped polysilicon material layer, 16 is a phosphosilicate glass layer, 17 is a wound-plated doped layer, 18 is a wound-plated phosphosilicate glass layer, 19 is a velvet surface, 20 is a tunneling passivation layer, 21 is an N-type doped polysilicon layer, 22 is a positive electrode, and 23 is a negative electrode. Specific embodiments

[0050] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0051] Tunneling passivated back-contact solar cells (TPBCSs) are solar cells with both the positive and negative electrodes on the back side of the cell, no metal electrodes blocking the front side, and a tunneling passivated contact structure. Due to their advantages, such as a large light-absorbing area and a low rear-side carrier recombination rate, TPBCSs have attracted widespread attention in the photovoltaic academic and industrial communities, becoming a hot development direction for high-efficiency solar cell technology.

[0052] Specifically, tunneling passivated back-contact solar cells in the related art typically include at least a semiconductor substrate, and a tunneling passivation layer and an N-type doped polycrystalline silicon layer, which are sequentially stacked along the thickness of the semiconductor substrate on a localized area of ​​the backlight surface of the semiconductor substrate. In this case, during the actual manufacturing process of the tunneling passivated back-contact solar cell, after the tunneling passivation material layer and the intrinsic amorphous silicon material layer are sequentially formed to cover the backlight surface of the semiconductor substrate, a phosphorus diffusion treatment is performed on the intrinsic amorphous silicon material layer to form an N-type doped polycrystalline silicon material layer, and a phosphosilicate glass layer is formed on the N-type doped polycrystalline silicon material layer. Next, under the masking action of the phosphosilicate glass layer, a texturing treatment is performed on at least the light-facing surface of the semiconductor substrate to form a texturing surface. This allows more light to be transmitted into the semiconductor substrate through the light-facing surface, thereby improving the photoelectric conversion efficiency of the tunneling passivated back-contact solar cell. At the same time, the phosphosilicate glass layer formed in the phosphorus diffusion process is directly used as a mask layer to protect the N-type doped polysilicon layer. There is no need to form other additional mask layers to protect the N-type doped polysilicon layer, so as to simplify the process steps of the tunneling passivated back-contact solar cell and improve the process efficiency.

[0053] However, the intrinsic amorphous silicon material layer formed using the relevant manufacturing method has a greater thickness at its edge and a smaller thickness at its center; and the thickness difference between the edge and center portions of the intrinsic amorphous silicon material layer is relatively large (the thickness ratio between the two is generally greater than 1.3). In this case, because the intrinsic amorphous silicon material layer is formed simultaneously along all portions parallel to the backlight surface, the chemical dosage ratio of the intrinsic amorphous silicon material located at the edge of the backlight surface is approximately the same as that of the intrinsic amorphous silicon material located at the center of the backlight surface. Therefore, when the thickness difference between the edge and center portions of the intrinsic amorphous silicon material layer is relatively large, the structure of the edge portion of the intrinsic amorphous silicon material layer is more loose. When the phosphorus diffusion treatment is carried out, the formation of the phosphosilicate glass layer is obtained by consuming the silicon element in the intrinsic amorphous silicon material layer and reacting it with the oxygen in the diffusion environment. Therefore, when the structure of the edge part of the intrinsic amorphous silicon material layer is looser, the formation quality of the phosphosilicate glass layer on the edge part of the intrinsic amorphous silicon material layer is also poor, which makes the corrosion resistance of the phosphosilicate glass layer in this part poor, resulting in the phosphosilicate glass layer being difficult to protect the N-type doped polysilicon material layer underneath it during the texturing process, thereby making the morphology of the N-type doped polysilicon layer formed based on the N-type doped polysilicon material layer poor and the formation range of the edge area small, which is not conducive to the collection of carriers, resulting in poor working performance of the tunneling passivated back-contact solar cell.

[0054] To address the above-mentioned technical issues, in a first aspect, an embodiment of the present application provides a back-contact cell. As shown in FIG1 , the back-contact cell comprises: a semiconductor substrate 11 having a first surface and a second surface disposed opposite each other, the first surface having a velvet structure; and a tunneling passivation layer 20 and an N-type doped polysilicon layer 21 stacked sequentially along the thickness direction of the semiconductor substrate 11 and disposed on a local region of the second surface. The doping element in the N-type doped polysilicon layer 21 includes phosphorus, and the thickness ratio of the portion of the N-type doped polysilicon layer 21 located on the edge region of the second surface to the portion of the N-type doped polysilicon layer 21 located on the center region of the second surface is greater than or equal to 1 and less than or equal to 1.2.

[0055] It should be noted that when the first surface of the semiconductor substrate 11 is the light-facing surface, the second surface is the backlight surface. When the first surface of the semiconductor substrate 11 is the backlight surface, the second surface is the light-facing surface. This application does not impose specific limitations on this. The following description will take the case where the first surface of the semiconductor substrate 11 is the light-facing surface and the second surface is the backlight surface as an example.

[0056] Specifically, in terms of material, the semiconductor substrate may be made of semiconductor materials such as silicon, silicon germanium, or germanium. In terms of conductivity type, the semiconductor substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate.

[0057] From a structural perspective, the specific structure of the semiconductor substrate can be determined according to the conductivity type of the semiconductor substrate and the actual application scenario.

[0058] For example, in the case where the semiconductor substrate is a P-type semiconductor substrate, along the direction parallel to the backlight surface, the backlight surface of the semiconductor substrate has a P-type region that is alternately spaced with the stacked tunnel passivation layer and the N-type doped polysilicon layer. At this time, the P-type region is the back surface field of the back contact battery. In other words, the back surface field in the back contact battery provided by the embodiment of the present application is a region possessed by the P-type semiconductor substrate, and there is no need for additional doping treatment to form the back surface field, which simplifies the process steps of the back contact battery and improves the process efficiency. At the same time, it can also prevent the occurrence of problems such as low minority carrier lifetime of the semiconductor substrate and difficulty in removing edge PN junctions due to the need to perform two high-temperature doping of N-type and P-type on the backlight side, which is beneficial to improving the yield of the back contact battery.

[0059] Of course, if the semiconductor substrate is a P-type semiconductor substrate, a P-type doped region may also be formed on a local area of ​​the backlight surface of the semiconductor substrate. Along a direction parallel to the backlight surface, the P-type doped region is alternately distributed with the stacked tunnel passivation layer and the N-type doped polysilicon layer.

[0060] For example, when the semiconductor substrate is an N-type semiconductor substrate, a P-type doped region is formed in or on a local region of the backlight surface of the semiconductor substrate. Along a direction parallel to the backlight surface, the P-type doped region is alternately distributed with the stacked tunneling passivation layer and the N-type doped polysilicon layer.

[0061] In terms of morphology, the light-facing surface of the semiconductor substrate is a velvet surface. The side surfaces of the semiconductor substrate can be polished or velvet-finished. The surface of the semiconductor substrate's backlight surface not covered by the stacked tunnel passivation layer and N-type doped polysilicon layer can be a velvet surface or a polished surface.

[0062] The material and thickness of the tunnel passivation layer can be set according to actual needs and are not specifically limited here. For example, the material of the tunnel passivation layer can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride.

[0063] For the above-mentioned N-type doped polysilicon layer, the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge region of the backlight surface to the portion of the N-type doped polysilicon layer located on the central region of the backlight surface may be any value greater than or equal to 1 and less than or equal to 1.2. For example, the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge region of the backlight surface to the portion of the N-type doped polysilicon layer located on the central region of the backlight surface may be 1, 1.12, 1.14, 1.16, 1.18, or 1.2, etc.

[0064] When the above technical solution is adopted, the tunneling passivation contact structure composed of the above tunneling passivation layer and the N-type doped polysilicon layer can achieve excellent interface passivation and carrier selective collection, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery. In addition, compared with the thickness ratio of the edge portion to the middle portion of the N-type doped polysilicon layer (see Figure 2) in the related art being greater than 1.3, the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge area of ​​the backlight surface to the portion of the N-type doped polysilicon layer located on the central area of ​​the backlight surface in the embodiment of the present application is greater than or equal to 1 and less than or equal to 1.2. As shown in Figure 1, at this time, the difference in thickness between the edge portion and the central portion of the N-type doped polysilicon layer 21 is small. In this case, in the actual manufacturing process, as shown in Figure 4, a process such as chemical vapor deposition is usually used to form the tunneling passivation material layer 12 and the intrinsic amorphous silicon material layer 13 used to manufacture the tunneling passivation layer and the N-type doped polysilicon layer. Based on this, when the difference in thickness between the edge portion and the center portion of the N-type doped polycrystalline silicon layer is small, the difference in thickness between the edge portion and the center portion of the intrinsic amorphous silicon material layer 13 forming the N-type doped polycrystalline silicon layer is also small. Because the intrinsic amorphous silicon material layer 13 is formed simultaneously along all portions parallel to the backlight surface, the chemical dosage ratio of the intrinsic amorphous silicon material located in the edge region of the backlight surface is roughly the same as that of the intrinsic amorphous silicon material located in the center region of the backlight surface. Therefore, when the difference in thickness between the edge portion and the center portion of the intrinsic amorphous silicon material layer 13 is small, the structural density of the edge portion and the center portion of the intrinsic amorphous silicon material layer 13 is relatively small (see FIG. 3 ). Accordingly, as shown in FIG5 , when the intrinsic amorphous silicon material layer 13 is subjected to phosphorus diffusion treatment, the density of the edge portion of the phosphosilicate glass layer 16 obtained by the reaction of silicon in the intrinsic amorphous silicon material layer 13 with oxygen in the diffusion environment is also slightly different from the density of its own central portion, so that the edge portion of the phosphosilicate glass layer 16 has a high corrosion resistance that is roughly the same as that of its own central portion, so that during the texturing treatment of at least the light-facing surface of the semiconductor substrate 11, the phosphosilicate glass layer 16 can well protect the portion of the N-type doped polycrystalline silicon material layer 15 located thereunder for forming the N-type doped polycrystalline silicon layer 21 (see FIG7 and FIG8 ), so that the morphology and formation range of the obtained N-type doped polycrystalline silicon layer 21 meet the target requirements, are beneficial to the collection of carriers, reduce reverse leakage, and further contribute to improving the photoelectric conversion efficiency of the back-contact battery.

[0065] From the above, it can be seen that the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge area of ​​the backlight surface to the portion of the N-type doped polysilicon layer located in the central area of ​​the backlight surface will affect the corrosion resistance of the phosphosilicate glass layer formed after the phosphorus diffusion process, thereby affecting its own morphology and its own formation range on the backlight side. Based on this, along the direction parallel to the backlight surface, the specific thickness of each portion of the N-type doped polysilicon layer can be determined based on the morphology of the N-type doped polysilicon layer and the formation range on the backlight side in the actual application scenario, as long as it can be applied to the back-contact battery provided in the embodiments of the present application.

[0066] For example, as shown in FIG1 , the thickness of the portion of the N-type doped polysilicon layer 21 located on the edge region of the backlight surface may be greater than or equal to 175 nm and less than or equal to 225 nm. For example, the thickness of the portion of the N-type doped polysilicon layer 21 located on the edge region of the backlight surface may be 175 nm, 185 nm, 195 nm, 205 nm, 215 nm, or 225 nm, etc. In this case, the thickness of the portion of the N-type doped polysilicon layer 21 located on the edge region of the backlight surface is within the above range, which can prevent the overall thickness of the N-type doped polysilicon layer 21 from being too small and failing to meet the target requirements due to the smaller thickness value, and prevent the difficulty in manufacturing the N-type doped polysilicon layer 21 with higher thickness uniformity, thereby facilitating the acquisition of a back-contact battery. At the same time, it can also prevent the poor corrosion resistance of the phosphosilicate glass layer located on the edge part of the N-type doped polysilicon material layer after the phosphorus diffusion treatment due to the large thickness value mentioned above, and ensure that the phosphosilicate glass layer can well include the various parts of the N-type doped polysilicon material layer used to form the N-type doped polysilicon layer 21 during the texturing process, and ensure that the N-type doped polysilicon layer 21 has a good morphology and a formation range that meets the target requirements.

[0067] For example, as shown in FIG1 , the thickness of the portion of the N-type doped polysilicon layer 21 located in the central region of the backlight surface may be greater than or equal to 150 nm and less than or equal to 200 nm. For example, the thickness of the portion of the N-type doped polysilicon layer 21 located in the central region of the backlight surface may be 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm.

[0068] In terms of doping, the N-type doped polysilicon layer may be doped with only phosphorus, an N-type impurity, or may be doped with nitrogen, arsenic, or other N-type impurities. The doping concentration of the impurities in the N-type doped polysilicon layer may be set according to actual needs and is not specifically limited here.

[0069] For example, the average doping concentration of impurities in the N-type doped polysilicon layer may be greater than or equal to 3.5×10 20 / cm3 and less than or equal to 4.0×10 20 / cm 3 For example, the average doping concentration of impurities in an N-type doped polysilicon layer can be 3.5×10 20 / cm 3 , 3.6×10 20 / cm 3 , 3.7×10 20 / cm 3 , 3.8×10 20 / cm 3 , 3.9×10 20 / cm 3 or 4.0×10 20 / cm 3 In this case, the average doping concentration of impurities in the N-type doped polysilicon layer is within the above range, which can ensure that the N-type doped polysilicon layer has excellent carrier selective collection effect and does not affect the contact resistance between the N-type doped polysilicon layer and the negative electrode. Compared with the N-type doped polysilicon layer in the related art (where the average doping concentration of impurities in the N-type doped polysilicon layer is greater than 5.0×10 20 / cm 3 ), appropriately reduce the impurity doping concentration in the N-type doped polysilicon layer in the embodiment of the present application. Correspondingly, the average doping concentration of impurities in the N-type doped polysilicon material layer used to manufacture the N-type doped polysilicon layer is also low. Based on this, in the actual manufacturing process, the average doping concentration of impurities in the N-type doped polysilicon material layer after the phosphorus diffusion treatment is proportional to the average doping concentration of impurities in the phosphosilicate glass layer formed on itself, so appropriately reducing the impurity doping concentration in the N-type doped polysilicon layer also means that the average doping concentration of impurities (the impurities include phosphorus) in the phosphosilicate glass layer is reduced. In this case, because the phosphorus doping concentration in the phosphosilicate glass layer is inversely proportional to its own corrosion resistance, appropriately reducing the phosphorus doping concentration in the phosphosilicate glass layer can also improve its own corrosion resistance, further ensuring that the N-type doped polysilicon layer has a good morphology and meets the formation range of the target requirements.

[0070] In actual application, in the process of forming an N-type doped polysilicon layer on the backlight side, a wrap-coated doped layer and a wrap-coated phosphosilicate glass layer will be formed on the side and part of the light-facing surface of the semiconductor substrate due to wrap-coating. Moreover, before performing a texturing treatment on at least the light-facing surface of the semiconductor substrate, the wrap-coated phosphosilicate glass layer and the wrap-coated doped layer need to be removed in sequence, and the etching solution for removing the wrap-coated doped layer will also affect the surface of the portion of the light-facing surface of the semiconductor substrate covered by the wrap-coated doped layer, so that a porous structure is formed on the surface of this portion, and the surface of the central area of ​​the light-facing surface of the semiconductor substrate that is not covered by the wrap-coated doped layer is relatively flat, resulting in inconsistent sizes of the velvet structures on the edge area and the central area of ​​the light-facing surface after the subsequent texturing treatment, thereby affecting the light-trapping effect of the light-facing surface. Specifically, the size uniformity of the velvet structure on each area of ​​the light-facing surface can be determined according to the formation of the N-type doped polysilicon layer, which is not specifically limited here.

[0071] For example, as shown in Figure 1, the dimensional uniformity of the velvet structure on each region of the light-facing surface is greater than or equal to 85% and less than 100%. The specific value of the dimensional uniformity of the velvet structure on each region of the light-facing surface can be determined based on the actual manufacturing process and is not specifically limited here. In this case, the dimensional uniformity of the velvet structure on each region of the light-facing surface is high, which facilitates high light transmittance in each region of the light-facing surface, allowing more light to be transmitted through the light-facing surface into the semiconductor substrate 11, further improving the photoelectric conversion efficiency of the back-contact cell.

[0072] In some cases, as shown in FIG10 , the back-contact cell provided in embodiments of the present application may further include a positive electrode 22 and a negative electrode 23. The positive electrode 22 forms an ohmic contact with the P-type region of the semiconductor substrate 11. The negative electrode 23 forms an ohmic contact with the N-type doped polysilicon layer 21. The positive electrode 22 and the negative electrode 23 may be made of conductive materials such as copper, aluminum, or silver.

[0073] In a second aspect, an embodiment of the present application further provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0074] The beneficial effects of the second aspect in the embodiments of the present application can be analyzed by referring to the beneficial effects of the first aspect and its various implementation methods, and will not be repeated here.

[0075] In a third aspect, embodiments of the present application further provide a method for manufacturing a back-contact battery. The manufacturing process will be described below based on the cross-sectional views of the operations shown in FIG4 to FIG10 .

[0076] Specifically, the manufacturing method of the back-contact battery includes: first, providing a semiconductor substrate. Next, as shown in FIG4 , a tunnel passivation material layer 12 and an intrinsic amorphous silicon material layer 13 are sequentially formed in a stacked manner on the backlight side of the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11. Next, as shown in FIG5 , the intrinsic amorphous silicon material layer is subjected to a phosphorus diffusion treatment so that the intrinsic amorphous silicon material layer forms an N-type doped polycrystalline silicon material layer 15, and a phosphosilicate glass layer 16 is formed on the N-type doped polycrystalline silicon material layer 15. The thickness ratio of the portion of the N-type doped polycrystalline silicon material layer 15 located on the central area of ​​the backlight surface is greater than or equal to 1 and less than or equal to 1.2. Next, as shown in FIG8 , under the masking action of the phosphosilicate glass layer 16, the light-facing surface of the semiconductor substrate 11 is subjected to a texturing treatment so that a velvet surface 19 is formed on the light-facing surface. Then, as shown in FIG8 , the phosphosilicate glass layer 16, and the stacked tunnel passivation material layer and N-type doped polysilicon material layer are patterned to form a tunnel passivation layer 20 and an N-type doped polysilicon layer 21 stacked on a local area of ​​the backlight surface. Next, as shown in FIG9 , the remaining phosphosilicate glass layer is removed.

[0077] The beneficial effects of the third aspect in the embodiments of the present application can be analyzed by referring to the beneficial effects of the first aspect and its various implementation methods, and will not be repeated here.

[0078] Specifically, the specific structure, conductivity type, and material of the semiconductor substrate can be referred to above and will not be repeated here. After providing the semiconductor substrate, the tunnel passivation material layer and the intrinsic amorphous silicon material layer can be formed by chemical vapor deposition or other processes. The material and thickness of the tunnel passivation material layer can be referred to above. As for the intrinsic amorphous silicon material layer, the intrinsic amorphous silicon material layer is used to manufacture the N-type doped polysilicon layer included in the back contact battery. In addition, the phosphosilicate glass layer formed after the phosphorus diffusion treatment consumes part of the silicon in the intrinsic amorphous silicon material layer, resulting in a reduction in the thickness of the N-type polysilicon material layer formed based on the intrinsic amorphous silicon material layer after the phosphorus diffusion treatment. Based on this, the thickness of each part of the intrinsic amorphous silicon material layer can be determined based on the thickness of each part of the N-type doped polysilicon material layer and the phosphosilicate glass layer, as well as the thickness ratio of the intrinsic amorphous silicon material required to form the phosphosilicate glass layer of corresponding thickness.

[0079] For example, when the average thickness of the intrinsic amorphous silicon material layer is H1, the average thickness of the phosphosilicate glass layer is H2, and the average thickness of the N-type doped polysilicon material layer is H3, 40% H2 < H1 - H3 < 60% H2. In this case, the average thicknesses of the intrinsic amorphous silicon material layer, the phosphosilicate glass layer, and the N-type doped polysilicon material layer satisfy the above conditions, indicating that the intrinsic amorphous silicon material layer is appropriately formed, and that the intrinsic amorphous silicon material layer has high density and structural uniformity in various regions parallel to the backlight surface. This facilitates that, after the phosphosilicate glass layer is formed, the consumed thickness of the N-type doped polysilicon material layer meets the theoretically high density N-type doped polysilicon material layer consumption (i.e., the thickness of the phosphosilicate glass layer is approximately equal to half the amount of thickness reduction of the N-type doped polysilicon material layer), or has a small difference from the theoretical consumption. This further indicates that the optimized phosphosilicate glass layer has high formation quality, ensuring that the formed N-type doped polysilicon layer has good morphology and meets the target formation range.

[0080] In addition, the N-type doped polycrystalline silicon material layer formed based on the intrinsic amorphous silicon material layer has a thickness ratio of the portion located on the edge area of ​​the backlight surface to the portion located on the central area of ​​the backlight surface that is greater than or equal to 1 and less than or equal to 1.2. Correspondingly, the thickness ratio of the portion located on the edge area of ​​the backlight surface to the portion located on the central area of ​​the backlight surface of the intrinsic amorphous silicon material layer also satisfies the requirement of being greater than or equal to 1 and less than or equal to 1.2. In this case, in the actual manufacturing process, the thickness of the corresponding area of ​​the intrinsic amorphous silicon material layer can be controlled by adjusting any parameters such as the ambient pressure and gas flow rate when forming the intrinsic amorphous silicon material layer, which can affect the thickness of different areas of the intrinsic amorphous silicon material layer. Specifically, the specific parameter values ​​that affect the thickness of different areas of the intrinsic amorphous silicon material layer can be determined based on the specific thickness of different areas of the intrinsic amorphous silicon material layer, as long as they can be applied to the manufacturing method of the back contact battery provided in the embodiment of the present application.

[0081] Exemplarily, the ambient pressure for forming the intrinsic amorphous silicon material layer can be greater than or equal to 100 mTorr and less than or equal to 150 mTorr. For example, the ambient pressure for forming the intrinsic amorphous silicon material layer can be 100 mTorr, 110 mTorr, 120 mTorr, 130 mTorr, 140 mTorr, or 150 mTorr. In this case, during the actual manufacturing process of the intrinsic amorphous silicon material layer, within a certain range, lowering the ambient pressure can increase the molecular free path, allowing the reactive molecular groups to reach various regions of the tunnel passivation material layer surface more quickly, rather than concentrating at the same location. Based on this, the ambient pressure during formation of the intrinsic amorphous silicon material layer is within the aforementioned range. This prevents the edge portion of the intrinsic amorphous silicon material layer from becoming thicker due to higher ambient pressure, ensuring a smaller thickness difference between the edge and center portions of the intrinsic amorphous silicon material layer. This ensures that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as that of the center portion. Consequently, the phosphosilicate glass layer formed after the phosphorus diffusion process exhibits high corrosion resistance in all portions parallel to the backlight surface, ensuring that the morphology and formation range of the formed N-type doped polycrystalline silicon meet target requirements. Furthermore, this prevents lower process efficiency due to lower ambient pressure.

[0082] Exemplarily, the gas flow rate for forming the intrinsic amorphous silicon material layer can be greater than or equal to 0.9 slm and less than or equal to 1.2 slm. For example, the gas flow rate for forming the intrinsic amorphous silicon material layer can be 0.9 slm, 1.0 slm, 1.1 slm, or 1.2 slm. In this case, during the actual manufacturing process of the intrinsic amorphous silicon material layer, reducing the gas flow rate within a certain range can reduce the total gas flow rate within the diffusion device, thereby reducing the degree of disturbance caused by the airflow within the diffusion device, which is beneficial for optimizing the deposition quality of the portion of the intrinsic amorphous silicon material layer located on the edge area of ​​the backlight surface, ensuring that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as the structure of its central portion, thereby ensuring that the phosphosilicate glass layer formed after the phosphorus diffusion treatment has high corrosion resistance in all portions parallel to the backlight surface, ensuring that the morphology and formation range of the formed N-type doped polycrystalline silicon meet the target requirements. At the same time, it can also prevent low process efficiency due to low gas flow rate.

[0083] It should be noted that, as shown in FIG4 , along the thickness direction of the semiconductor substrate 11, while the intrinsic amorphous silicon material layer 13 is formed on the backlight side of the semiconductor substrate 11, a wrap-around amorphous silicon layer 14 is formed on the side and part of the light-facing surface of the semiconductor substrate 11. The width of the formation area of ​​the wrap-around amorphous silicon layer 14 on the light-facing surface (the width direction of the formation area is parallel to the radial direction of the semiconductor substrate 11) is affected by parameters such as the ambient pressure and gas flow rate when manufacturing the intrinsic amorphous silicon material layer 13. For example, within a certain range, the smaller the ambient pressure when manufacturing the intrinsic amorphous silicon material layer 13, the smaller the width of the formation area of ​​the wrap-around amorphous silicon layer 14 on the light-facing surface. In the above case, the width of the formation area of ​​the wrap-around amorphous silicon layer 14 on the light-facing surface can be determined based on the manufacturing conditions of the intrinsic amorphous silicon material layer 13.

[0084] Exemplarily, the width of the formation area of ​​the above-mentioned plated amorphous silicon layer on the light-facing surface can be greater than or equal to 0 and less than 10 mm. For example, the width of the formation area of ​​the plated amorphous silicon layer on the light-facing surface can be 1 mm, 3 mm, 6 mm, 9 mm or 9.5 mm, etc. In this case, before the texturing process is performed, the plated phosphorus silicon glass layer and the plated doping layer formed by the plated coating need to be removed in sequence, and the etching solution for removing the plated doping layer will also affect the surface of the portion of the semiconductor substrate that is covered by the plated doping layer on the light-facing surface, so that a porous structure is formed on the surface of the portion, and the surface of the central area of ​​the semiconductor substrate that is not covered by the plated doping layer on the light-facing surface is relatively flat, resulting in inconsistent sizes of the velvet structures on the edge area and the central area of ​​the light-facing surface after the subsequent texturing process, thereby affecting the light trapping effect of the light-facing surface. In this case, compared to the width of the formation area of ​​the doped layer on the light-facing surface formed during the related manufacturing of the back-contact cell, which is greater than 10 mm, when the width of the formation area of ​​the amorphous silicon layer on the light-facing surface in the embodiment of the present application is greater than or equal to 0 and less than 10 mm, the coating width is smaller, which is beneficial to improving the dimensional uniformity of the velvet structure located in various areas of the light-facing surface, thereby improving the light trapping effect of the light-facing surface and further improving the photoelectric conversion efficiency of the back-contact cell. It can be seen that the specific value of the dimensional uniformity of the velvet structure on various areas of the light-facing surface of the semiconductor substrate can be determined based on the width of the formation area of ​​the amorphous silicon layer on the light-facing surface during the actual manufacturing process and the size of the semiconductor substrate, and is not specifically limited here.

[0085] In the actual manufacturing process, after forming the above-mentioned intrinsic amorphous silicon material layer, it is necessary to perform a phosphorus diffusion treatment on the intrinsic amorphous silicon material layer to form the above-mentioned N-type doped polycrystalline silicon material layer and phosphosilicate glass layer. The phosphorus diffusion treatment includes a phosphorus source deposition step, a crystallization step, and a post-oxidation step, which are performed in sequence. The above-mentioned phosphorus source deposition step can adjust the phosphorus doping concentration in the N-type doped polycrystalline silicon material layer and the phosphosilicate glass layer, and the above-mentioned post-oxidation step can adjust the thickness of the N-type doped polycrystalline silicon material layer and the phosphosilicate glass layer. In addition, the phosphorus doping concentration in the N-type doped polycrystalline silicon material layer and the phosphosilicate glass layer, as well as the thickness of the phosphosilicate glass layer, all affect the corrosion resistance of the phosphosilicate glass layer during the texturing process. Based on this, the specific process parameters of the phosphorus diffusion treatment can be determined based on the thickness and doping concentration of the N-type doped polycrystalline silicon material layer and the phosphosilicate glass layer, as well as the morphology and formation range requirements of the N-type doped polycrystalline silicon layer in the actual application scenario, and are not specifically limited here.

[0086] Exemplarily, the treatment conditions of the phosphorus diffusion treatment are:

[0087] The deposition process temperature is greater than or equal to 850° C. and less than or equal to 900° C. For example, the deposition process temperature may be 850° C., 860° C., 870° C., 880° C., 890° C., or 900° C.

[0088] The deposition process environment pressure is greater than or equal to 150 mbar and less than or equal to 200 mbar. For example, the deposition process environment pressure may be 150 mbar, 160 mbar, 170 mbar, 180 mbar, 190 mbar, or 200 mbar.

[0089] The pressure of the phosphorus source in the deposition process is greater than or equal to 250 mbar and less than or equal to 450 mbar. For example, the pressure of the phosphorus source in the deposition process can be 250 mbar, 300 mbar, 350 mbar, 400 mbar, or 450 mbar.

[0090] The nitrogen flow rate during the deposition process is greater than or equal to 1500 sccm and less than or equal to 2000 sccm. For example, the nitrogen flow rate during the deposition process may be 1500 sccm, 1600 sccm, 1700 sccm, 1800 sccm, 1900 sccm, or 2000 sccm.

[0091] The oxygen flow rate during the deposition process is greater than or equal to 750 sccm and less than or equal to 1000 sccm. For example, the oxygen flow rate during the deposition process may be 750 sccm, 800 sccm, 850 sccm, 900 sccm, 950 sccm, or 1000 sccm.

[0092] The post-oxidation process temperature is greater than or equal to 850° C. and less than or equal to 900° C. For example, the post-oxidation process temperature may be 850° C., 860° C., 870° C., 880° C., 890° C., or 900° C.

[0093] The oxygen flow rate in the post-oxidation process is greater than or equal to 5000 sccm and less than or equal to 10000 sccm. For example, the oxygen flow rate in the post-oxidation process may be 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, or 10000 sccm.

[0094] Among them, any one of the above process parameters may meet the corresponding range requirements, or at least two of the above process parameters may meet the corresponding range requirements.

[0095] When the above technical solution is adopted, in the actual manufacturing process, the average doping concentration of impurities in the formed phosphosilicate glass layer and N-type doped polysilicon material can be regulated by changing the deposition process temperature, deposition process ambient pressure, deposition process phosphorus source pressure, deposition process nitrogen flow rate, and deposition process oxygen flow rate during the above phosphorus diffusion process. Based on this, when at least one of the deposition process temperature, deposition process ambient pressure, deposition process phosphorus source pressure, deposition process nitrogen flow rate, and deposition process oxygen flow rate is within the above corresponding range, the average doping concentration of phosphorus in the phosphosilicate glass layer can be appropriately reduced, so that the phosphosilicate glass layer has higher corrosion resistance, thereby ensuring that the N-type doped polysilicon layer formed based on the N-type doped polysilicon material layer has a good morphology and meets the target formation range. In addition, the thickness of the formed phosphosilicate glass layer can be regulated by changing the post-oxidation process temperature and post-oxidation process oxygen flow rate during the phosphorus diffusion process. Based on this, when at least one of the post-oxidation process temperature and post-oxidation process oxygen flow rate is within the above corresponding range, the thickness of the formed phosphosilicate glass layer can be appropriately increased, thereby improving the corrosion resistance of the phosphosilicate glass layer.

[0096] Exemplarily, the thickness of the phosphosilicate glass layer may be greater than or equal to 60 nm and less than or equal to 65 nm. For example, the thickness of the phosphosilicate glass layer may be 60 nm, 61 nm, 62 nm, 63 nm, 64 nm, or 65 nm, etc. In this case, the thickness of the phosphosilicate glass layer is within the above range, which can prevent the poor corrosion resistance of the phosphosilicate glass layer due to the small thickness of the phosphosilicate glass layer, and ensure that the morphology and formation range of the formed N-type doped polysilicon layer meet the target requirements. At the same time, it can also prevent the large amount of consumables used in the manufacture of the intrinsic amorphous silicon material layer and the phosphosilicate glass layer due to the large thickness of the phosphosilicate glass layer, which is beneficial to controlling the manufacturing cost of the back contact battery.

[0097] It should be noted that, as shown in FIG5 , after the phosphorus diffusion treatment, the wrap-around amorphous silicon layer forms a wrap-around doped layer 17, and a wrap-around phosphosilicate glass layer 18 is formed on the wrap-around doped layer 17. In this case, after forming the above-mentioned N-type doped polysilicon material layer 15 and before texturing at least the light-facing surface of the semiconductor substrate 11, as shown in FIG6 , a process such as wet etching can be used to sequentially remove the wrap-around phosphosilicate glass layer and the wrap-around doped layer.

[0098] In addition, after the phosphorus diffusion treatment is performed on the intrinsic amorphous silicon material layer, before the texturing treatment is performed on at least the light-facing surface of the semiconductor substrate, as shown in FIG7 , laser etching or other methods can be used to pattern only the phosphosilicate glass layer 16, so that the remaining portion of the phosphosilicate glass layer 16 is formed on a local area of ​​the N-type doped polysilicon material layer 15. In this case, as shown in FIG8 , while the texturing treatment is performed on the light-facing surface of the semiconductor substrate 11, the stacked tunnel passivation material layer and the N-type doped polysilicon material layer can be patterned simultaneously under the masking effect of the phosphosilicate glass layer 16. In other words, the phosphosilicate glass layer 16 located on the backlight side is patterned before the texturing treatment, so that in the subsequent texturing process, the texturing etching liquid can not only form a velvet surface 19 at least on the light side, but also can pattern the N-type doped polysilicon material layer and the tunnel passivation material layer under the masking effect of the remaining part of the phosphosilicate glass layer 16 to obtain the N-type doped polysilicon layer 21 and the tunnel passivation layer 20, thereby improving the process efficiency of the back contact battery while ensuring that the morphology and formation range of the N-type doped polysilicon layer 21 meet the target requirements.

[0099] Of course, after removing the coated phosphosilicate glass layer and the coated doped layer, a texturing process can be performed on at least the light-facing surface of the semiconductor substrate directly under the mask of the entire phosphosilicate glass layer. In this case, the texturing etchant will not affect each area of ​​the N-type doped polysilicon material layer parallel to the backlight surface. In this case, after the texturing process, the phosphosilicate glass layer can be patterned using methods such as laser etching. Then, the tunneling passivation material layer and the N-type doped polysilicon material layer can be patterned using methods such as wet etching or dry etching under the mask of the remaining portion of the phosphosilicate glass layer to obtain the tunneling passivation layer and the N-type doped polysilicon layer.

[0100] Next, as shown in FIG9 , a process such as wet etching or dry etching can be used to remove the remaining portion of the phosphosilicate glass layer. Then, as shown in FIG10 , a positive electrode 22 and a negative electrode 23 can be formed on the backlight side by methods such as screen printing or electroplating. The positive electrode 22 makes ohmic contact with the P-type region of the semiconductor substrate 11 , while the negative electrode 23 makes ohmic contact with the N-type doped polysilicon layer 21 .

[0101] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0102] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Furthermore, please note that examples of the phrase "in one embodiment" herein do not necessarily all refer to the same embodiment. In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0103] In the claims, any reference signs placed between brackets shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A back contact battery, in, include: A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface arranged opposite to each other, and the first surface has a velvet structure; And along the thickness direction of the semiconductor substrate, a tunneling passivation layer and an N-type doped polysilicon layer are stacked in sequence on a local area of ​​the second surface; the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge area of ​​the second surface to the portion of the N-type doped polysilicon layer located on the central area of ​​the second surface is greater than or equal to 1 and less than or equal to 1.

2.

2. The back contact cell according to claim 1, in, The size uniformity of the suede structure in each area of ​​the first surface is greater than or equal to 85% and less than 100%.

3. The back contact cell according to claim 1, in, The area on the second surface where the tunnel passivation layer and the N-type doped polysilicon layer are not stacked is a polished surface or has a suede structure.

4. The back contact cell according to claim 1, in, The thickness of the portion of the N-type doped polysilicon layer located on the edge region of the second surface is greater than or equal to 175 nm and less than or equal to 225 nm; and / or, The thickness of a portion of the N-type doped polysilicon layer located in the central region of the second surface is greater than or equal to 150 nm and less than or equal to 200 nm.

5. The back contact cell according to any one of claims 1 to 4, in, The average doping concentration of impurities in the N-type doped polysilicon layer is greater than or equal to 3.5×10 20 / cm 3 and less than or equal to 4.0×10 20 / cm 3 .

6. A photovoltaic module, in, include: A back contact cell as claimed in any one of claims 1 to 5.

7. A method for manufacturing a back contact battery, in, include: Providing a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface disposed opposite to each other; A tunnel passivation material layer and an intrinsic amorphous silicon material layer are sequentially formed in a stacked manner on one side of the second surface along a thickness direction of the semiconductor substrate; The intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment to form an N-type doped polysilicon material layer from the intrinsic amorphous silicon material layer, and a phosphorus silicon glass layer is formed on the N-type doped polysilicon material layer. The thickness ratio of the portion of the N-type doped polysilicon material layer located on the edge region of the second surface to the portion of the N-type doped polysilicon material layer located on the central region of the second surface is greater than or equal to 1 and less than or equal to 1.2; Under the masking action of the phosphosilicate glass layer, performing a texturing process on the first surface so as to form a texturing surface on the first surface; Patterning the phosphosilicate glass layer, and the stacked tunneling passivation material layer and N-type doped polysilicon material layer to form a tunneling passivation layer and an N-type doped polysilicon layer stacked on a local area of ​​the second surface; The remaining phosphosilicate glass layer is removed.

8. The method for manufacturing a back contact battery according to claim 7, in, The ambient pressure for forming the intrinsic amorphous silicon material layer is greater than or equal to 100 mTorr and less than or equal to 150 mTorr; and / or, The gas flow rate for forming the intrinsic amorphous silicon material layer is greater than or equal to 0.9 slm and less than or equal to 1.2 slm.

9. The method for manufacturing a back contact battery according to claim 7, in, After the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment, the phosphosilicate glass layer is subjected to patterning treatment only before the first surface is subjected to texturing treatment under the masking effect of the phosphosilicate glass layer, so that the remaining part of the phosphosilicate glass layer is formed on a local area of ​​the N-type doped polysilicon material layer; Under the masking effect of the phosphosilicate glass layer, the first surface is subjected to the texturing treatment, and at the same time, the stacked tunnel passivation material layer and the N-type doped polysilicon material layer are subjected to the patterning treatment.

10. The method for manufacturing a back contact battery according to claim 7, in, Along the thickness direction of the semiconductor substrate, while forming an intrinsic amorphous silicon material layer on one side of the second surface, a plated amorphous silicon layer is formed on the side surface of the semiconductor substrate and part of the first surface; the width of the formation area of ​​the plated amorphous silicon layer on the first surface is greater than or equal to 0 and less than 10 mm; the width direction of the formation area is parallel to the radial direction of the semiconductor substrate; After the phosphorus diffusion treatment, the wrap-around amorphous silicon layer forms a wrap-around doped layer, and a wrap-around phosphorus silicon glass layer is formed on the wrap-around doped layer; After the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment, and before the first surface is subjected to texturing treatment under the masking action of the phosphosilicate glass layer, the manufacturing method of the back contact battery further includes: removing the wrap-around phosphosilicate glass layer and the wrap-around doping layer.

11. A method for manufacturing a back contact cell according to any one of claims 7 to 10, in, The thickness of the phosphosilicate glass layer is greater than or equal to 60 nm and less than or equal to 65 nm; and / or, The average thickness of the intrinsic amorphous silicon material layer is H1, the average thickness of the phosphosilicate glass layer is H2, the average thickness of the N-type doped polysilicon material layer is H3, and 40% H2<H1-H3<60% H2.

12. A method for manufacturing a back contact cell according to any one of claims 7 to 10, in, The treatment conditions of the phosphorus diffusion treatment are: The deposition process temperature is greater than or equal to 850° C. and less than or equal to 900° C.; and / or the deposition process environment pressure is greater than or equal to 150 mbar and less than or equal to 200 mbar; and / or, the phosphorus source pressure of the deposition process is greater than or equal to 250 mbar and less than or equal to 450 mbar; and / or, the nitrogen flow rate of the deposition process is greater than or equal to 1500 sccm and less than or equal to 2000 sccm; and / or, the oxygen flow rate of the deposition process is greater than or equal to 750 sccm and less than or equal to 1000 sccm; and / or, the post-oxidation process temperature is greater than or equal to 850°C and less than or equal to 900°C; and / or, the oxygen flow rate of the post-oxidation process is greater than or equal to 5000 sccm and less than or equal to 10000 sccm.

Images