Photodetection device and electronic apparatus

Abstract

The present invention increases the degree of freedom in arranging pixel transistors in a photoelectric conversion region. This photodetection device comprises: a semiconductor layer having a first surface portion and a second surface portion that are positioned on mutually opposite sides in the thickness direction; a photoelectric conversion region that is provided to the semiconductor layer in a manner of being divided by a separation region extending in the thickness direction of the semiconductor layer, and that has an upper surface portion positioned on the first surface portion side of the semiconductor layer, and a first lateral surface portion positioned on the separation region side; a transfer transistor that is provided on the upper surface portion side of the photoelectric conversion region and transfers, to a charge retention unit, a signal charge obtained through photoelectric conversion at the photoelectric conversion region; and a plurality of pixel transistors provided to the upper surface portion of the photoelectric conversion region. At least one of the plurality of pixel transistors has a gate electrode that is provided to the separation region so as to be adjacent to the first lateral surface portion of the photoelectric conversion region across a gate insulating film.

Description

Photodetector and electronic equipment

[0001] The present technology (technology related to the present disclosure) relates to a photodetector device and an electronic device, and in particular to a technology that is effective when applied to a photodetector device in which pixel transistors are provided in a photoelectric conversion region and an electronic device including the same.

[0002] Photodetection devices such as solid-state imaging devices and distance measuring devices include a transfer transistor that transfers photoelectrically converted signal charges to a charge storage section, and a pixel circuit that outputs a pixel signal based on the signal charges stored in the charge storage section. Patent Document 1 discloses a solid-state imaging device in which a transfer transistor and a pixel transistor included in the pixel circuit are provided in a photoelectric conversion region of a semiconductor layer. Patent Document 1 also discloses a photoelectric conversion region partitioned by a trench-type isolation region.

[0003] On the other hand, Patent Document 2 discloses an imaging device in which a trench for shallow trench isolation (STI) is formed in a substrate, and a voltage is applied to a buried polysilicon electrode buried in this trench via an insulating film, thereby strengthening the pinning of the STI sidewall during accumulation, and a voltage is applied to a pixel region P well and the buried polysilicon electrode, thereby improving the transfer of signal charges during transfer.

[0004] JP 2021-101491 A JP 2006-120804 A

[0005] In recent years, there has been a demand in the market for high-resolution image sensors, and development of image sensors with reduced pixel size is underway.

[0006] However, as the pixel size is reduced, it becomes difficult to arrange active elements such as transfer transistors and pixel transistors in the photoelectric conversion region, and the degree of freedom in arranging the active elements decreases.

[0007] An object of the present technology is to provide a technology that can increase the degree of freedom in arranging active elements in a photoelectric conversion region.

[0008] (1) A photodetector according to one aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located on opposite sides in a thickness direction; and a photoelectric conversion region provided in the semiconductor layer and partitioned by an isolation region extending in the thickness direction of the semiconductor layer. The photoelectric conversion region includes: an upper surface portion located on the first surface portion side of the semiconductor layer and a first side surface portion located on the isolation region side; a transfer transistor provided on the upper surface portion side of the photoelectric conversion region and configured to transfer signal charges photoelectrically converted in the photoelectric conversion region to a charge storage portion; and a plurality of pixel transistors provided on the upper surface portion of the photoelectric conversion region. At least one pixel transistor of the plurality of pixel transistors has a gate electrode provided in the isolation region adjacent to the first side surface portion of the photoelectric conversion region with a gate insulating film interposed therebetween.

[0009] (2) A photodetector according to another aspect of the present technology includes: a semiconductor layer; and a photoelectric conversion region provided in the semiconductor layer and partitioned by an isolation region extending in a thickness direction of the semiconductor layer. The photoelectric conversion region includes: an upper surface portion and a side surface portion; a charge retention portion provided on the upper surface portion side and retaining signal charges transferred from the photoelectric conversion portion via a transfer transistor; and a pixel transistor provided on the upper surface portion side. In two photoelectric conversion regions adjacent to each other in a planar view via the isolation region, the pixel transistor provided in one of the photoelectric conversion regions has a gate electrode provided across the upper surface portion and the isolation region of one of the photoelectric conversion regions in a planar view, and connected to the charge retention portion of the other photoelectric conversion region at the side surface portion of the other photoelectric conversion region.

[0010] (3) An electronic device according to another aspect of the present technology includes the above-mentioned photodetector; an optical lens that focuses image light from a subject on an imaging surface of the detection device; and a signal processing circuit that performs signal processing on a signal output from the photodetector.

[0011] 5A . FIG. 4A is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 4B is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 4C is an equivalent circuit diagram showing a configuration example of a pixel and a pixel circuit according to a first embodiment of the present technology. FIG. 5D is a plan view schematically showing a configuration example of four pixels included in the pixel array section of FIG. 1. FIG. 4A is an enlarged plan view of a part of FIG. 4A. FIG. 5D is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a4-a4 cutting line of FIG. 4A. FIG. 5E is a longitudinal sectional view schematically showing an enlarged part of the longitudinal sectional structure taken along the b4-b4 cutting line of FIG. 4A. FIG. 5F is a longitudinal sectional view schematically showing an enlarged part of the longitudinal sectional structure taken along the c4-c4 cutting line of FIG. 4A. FIG. 5G is a longitudinal sectional view schematically showing an enlarged part of the longitudinal sectional structure taken along the d4-d4 cutting line of FIG. 4A. FIG. 5G is a diagram (longitudinal sectional view at the same position as the a4-a4 cutting line of FIG. 4A) schematically showing a process of a method for manufacturing a solid-state imaging device according to a first embodiment of the present technology. 4A )。

[0033] FIG. 13 is a diagram schematically showing a process subsequent to the process of FIG. 9 (a longitudinal cross-sectional view taken at the same position as the a4-a4 cutting line of FIG. 4A). FIG. 14 is a diagram schematically showing a process subsequent to the process of FIG. 10 (a longitudinal cross-sectional view taken at the same position as the a4-a4 cutting line of FIG. 4A). FIG. 15 is a diagram schematically showing a process subsequent to FIG. 11 (a longitudinal cross-sectional view taken at the same position as the a4-a4 cutting line of FIG. 4A).

[0034] FIG. 16 is a diagram schematically showing a process subsequent to FIG. 15 (a longitudinal cross-sectional view taken at the same position as the a4-a4 cutting line of FIG. 4A). 17A (a longitudinal sectional view at the same position as the a4-a4 cutting line of FIG. 4A ). FIG. 17B (a longitudinal sectional view at the same position as the b4-b4 cutting line of FIG. 4A ). FIG. 17C (a longitudinal sectional view at the same position as the a4-a4 cutting line of FIG. 4A ). FIG. 17D (a longitudinal sectional view at the same position as the b4-b4 cutting line of FIG. 4A ). FIG. 17D (a longitudinal sectional view at the same position as the b4-b4 cutting line of FIG. 4A ). FIG. 17E (a longitudinal sectional view at the same position as the b4-b4 cutting line of FIG. 4A ). FIG. 17F ...23 is a plan view schematically showing a configuration example of one pixel block in a solid-state imaging device according to a third embodiment of the present technology. FIG. 24 is a longitudinal cross-sectional view schematically showing a portion of the longitudinal cross-sectional structure taken along the a20-a20 cutting line of FIG. 20. FIG. 25 is a plan view schematically showing a portion of the longitudinal cross-sectional structure of a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 26 is a plan view schematically showing a configuration example of two pixel blocks in a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 27 is a longitudinal cross-sectional view schematically showing, on an enlarged scale, a portion of the longitudinal cross-sectional structure taken along the a23-a23 cutting line of FIG. 23. FIG. 28 is a plan view schematically showing a configuration example of two pixel blocks in a solid-state imaging device according to a sixth embodiment of the present technology. FIG. 29 is a longitudinal cross-sectional view schematically showing, on an enlarged scale, a portion of the longitudinal cross-sectional structure taken along the a25-a25 cutting line of FIG. 25. FIG. 29 is a longitudinal cross-sectional view schematically showing, on an enlarged scale, a portion of the longitudinal cross-sectional structure taken along the b25-b25 cutting line of FIG. 25. FIG. 29 is a longitudinal cross-sectional view schematically showing, on an enlarged scale, a portion of the longitudinal cross-sectional structure taken along the c25-c25 cutting line of FIG. 25. 30. It is an equivalent circuit diagram showing an example of a configuration of a pixel and a pixel circuit in a solid-state imaging device according to a seventh embodiment of the present technology. It is a plan view showing an example of a configuration of two pixel blocks in a solid-state imaging device according to the seventh embodiment of the present technology. It is a longitudinal cross-sectional view showing an enlarged schematic view of a part of the longitudinal cross-sectional structure taken along the a30-a30 cutting line of FIG. 30. It is an equivalent circuit diagram showing an example of a configuration of a pixel and a pixel circuit in a solid-state imaging device according to an eighth embodiment of the present technology. It is a plan view showing an example of a configuration of two pixel blocks in a solid-state imaging device according to the eighth embodiment of the present technology. It is a longitudinal cross-sectional view showing an enlarged schematic view of a part of the longitudinal cross-sectional structure taken along the a34-a34 cutting line of FIG. 34. It is a longitudinal cross-sectional view of a main part schematically showing a modified example 8-1 according to the eighth embodiment of the present technology. It is a longitudinal cross-sectional view of a main part schematically showing a modified example 8-2 according to the eighth embodiment of the present technology. It is a longitudinal cross-sectional view of a main part schematically showing a modified example 8-3 according to the eighth embodiment of the present technology. 19A to 19C are longitudinal cross-sectional views of a main portion schematically showing a modified example 8-4 according to an eighth embodiment of the present technology; a modified example 8-5 according to an eighth embodiment of the present technology; and a longitudinal cross-sectional view of a main portion schematically showing a modified example 8-6 according to an eighth embodiment of the present technology.FIG. 43 is a longitudinal cross-sectional view of a main portion schematically showing a modified example 8-7 according to an eighth embodiment of the present technology. FIG. 44 is a plan view schematically showing a configuration example of two pixel blocks in a solid-state imaging device according to a ninth embodiment of the present technology. FIG. 45 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a43-a43 cutting line of FIG. 43. FIG. 46 is a plan view schematically showing a configuration example of two pixel blocks in a solid-state imaging device according to a tenth embodiment of the present technology. FIG. 47 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a45-a45 cutting line of FIG. 45. FIG. 48 is a diagram showing a configuration example of an electronic device according to an eleventh embodiment of the present technology.

[0012] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0013] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0014] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0015] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0016] In the following embodiments, among the three mutually orthogonal directions in space, a first direction and a second direction that are orthogonal to each other in the same plane are defined as the X direction and the Y direction, respectively, and a third direction that is orthogonal to each of the first and second directions is defined as the Z direction. In the following embodiments, the thickness direction of a semiconductor layer 21, which will be described later, is defined as the Z direction. In the following description, "planar view" refers to a view from a direction along the thickness direction of the semiconductor layer 21, which will be described later. In addition, "thickness direction of the semiconductor layer" refers to a direction that represents the thickness of the semiconductor layer 21.

[0017] In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector will be described. Also, in this first embodiment, a case will be described in which, among a plurality of pixel transistors included in a pixel circuit, gate electrodes of a selection transistor and a reset transistor are provided in an isolation region.

[0018] <Overall Configuration of Solid-State Imaging Device> First, the overall configuration of the solid-state imaging device 1A will be described. As shown in Fig. 1 , the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as the solid-state imaging device 1A. As shown in Fig. 47 , this solid-state imaging device 1A (101) captures image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 formed on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0019] As shown in FIG. 1 , a semiconductor chip 2 on which a solid-state imaging device 1A is mounted includes, in a two-dimensional plane including mutually orthogonal X and Y directions, a rectangular pixel array section 2A provided in the center and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A. The semiconductor chip 2 is formed in a manufacturing process by dicing a semiconductor wafer including a semiconductor layer 21 (described below) into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in the wafer state before the semiconductor wafer is diced. In other words, the present technology can be applied to both the semiconductor chip state and the semiconductor wafer state.

[0020] The pixel array unit 2A is a light receiving surface that receives light collected by, for example, an optical lens (optical system) 102 shown in Fig. 47. The pixel array unit 2A has a plurality of pixels 3 (sensor pixels) arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

[0021] 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 functions as an input / output terminal that electrically connects the semiconductor chip 2 to an external device.

[0022] <Logic Circuit> The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0023] 2 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section of each pixel 3 in accordance with the amount of received light to the column signal processing circuit 5 via vertical signal lines 11.

[0024] 2 is arranged for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0025] 2 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0026] 2 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 via the horizontal signal line 12, and outputs the processed signals. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0027] 2 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0028] <Pixel Block> The semiconductor chip 2 includes a pixel block 15 and a pixel circuit (readout circuit) 16 shown in Fig. 3. As shown in Fig. 3 and Fig. 4A, the pixel block 15 includes a plurality of pixels 3. The pixel block 15 of the first embodiment includes, for example, two pixels 3 (3a, 3b) arranged adjacent to each other in the X direction in a plan view, but is not limited thereto. Fig. 3 mainly illustrates one pixel block 15, and Fig. 4A mainly illustrates two pixel blocks 15 arranged adjacent to each other in the Y direction, but the pixel blocks 15 are repeatedly arranged in both the X direction and the Y direction to form the pixel array unit 2A shown in Fig. 1.

[0029] As shown in FIG. 3 , two pixels 3 a and 3 b included in one pixel block 15 each have common components. Specifically, each of the two pixels 3 a and 3 b included in one pixel block 15 includes a photoelectric conversion unit 25, a floating diffusion region FD serving as a charge storage unit for storing (accumulating) signal charges photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR for transferring the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. Each of the two pixels 3 a and 3 b included in one pixel block 15 also includes a photoelectric conversion region 22 of a semiconductor layer 21 shown in FIG. 5A . The photoelectric conversion unit 25, the floating diffusion region FD, and the transfer transistor TR are each provided in the photoelectric conversion region 22, as shown in FIG. 5A .

[0030] 3 is configured by, for example, a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The photoelectric conversion unit 25 also temporarily holds (accumulates) the generated signal charge.

[0031] The photoelectric conversion unit 25 has a cathode side electrically connected to the source region of the transfer transistor TR, and an anode side electrically connected to a reference potential line (for example, ground).

[0032] 3 transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line of the pixel drive lines 10 shown in FIG.

[0033] (Floating Diffusion Region) The floating diffusion region FD shown in FIG. 3 temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR.

[0034] <Pixel Circuit> As shown in FIG. 3, the pixel circuit 16 is provided for each pixel 3, for example, but is not limited to this, and the input side thereof is electrically connected to the floating diffusion region FD.

[0035] In the first embodiment, as an example, a circuit configuration is shown in which a pixel circuit 16 is assigned to each pixel 3, but the present invention is not limited to this first embodiment. For example, a circuit configuration may be used in which one pixel circuit 16 is assigned to one pixel block 15, each unit of which includes two pixels 3 (3a, 3b), or a circuit configuration may be used in which one pixel circuit 16 is assigned to one pixel block 15, each unit of which includes two or more pixels 3. Furthermore, a circuit configuration may be used in which one pixel circuit 16 is assigned to a plurality of pixel blocks 15, each unit of which includes a plurality of pixels 3.

[0036] 4A , in the first embodiment, the pixel block 15 is configured such that two pixels 3 a and 3 b arranged adjacent to each other in the X direction form one unit, but the number of pixels 3 and the arrangement direction of the pixels 3 are not limited to those in the first embodiment. For example, the pixel block 15 may be configured such that four pixels 3 arranged two by two in each of the X and Y directions form one unit.

[0037] 3 has an input stage electrically connected to the floating diffusion region FD of the pixel 3. The pixel circuit 16 reads out the signal charge held in the floating diffusion region FD of the pixel 3 and outputs a pixel signal based on the read signal charge. In other words, the pixel circuit 16 converts the signal charge photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charge and outputs the pixel signal.

[0038] 3, the pixel circuit 16 includes, but is not limited to, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors Q. That is, the pixel circuit 16 of the first embodiment has a three-transistor configuration.

[0039] The pixel transistor Q (AMP, RST, SEL) and the transfer transistor TR are insulated gate field effect transistors, and the gate insulating film is made of silicon oxide (SiO ２ The pixel transistors and transfer transistors TR are configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of a silicon nitride (Si) film. ３ N ４ Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0040] Of the pixel transistors Q (AMP, RST, SEL) included in the pixel circuit 16, the selection transistor SEL and the reset transistor RST mainly function as switching elements, and the remaining amplification transistor AMP mainly functions as an amplification element.

[0041] 3, the source region of the amplifier transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplifier transistor AMP is electrically connected to the floating diffusion region FD of the pixel 3 (photoelectric conversion region 22) and the source region of the reset transistor RST.

[0042] 3, the source region of the select transistor SEL is electrically connected to the vertical signal line 11 (VSL), the drain region is electrically connected to the source region of the amplification transistor AMP, and the gate electrode of the select transistor SEL is electrically connected to the select transistor drive line of the pixel drive lines 10 shown in FIG.

[0043] 3, the source region of the reset transistor RST is electrically connected to the gate electrode of the amplifier transistor AMP and the floating diffusion region FD of the pixel 3, and the drain region is electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive lines 10 shown in FIG.

[0044] The selection transistor SEL may be omitted if necessary. In the case where the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).

[0045] When the transfer transistor TR shown in FIG. 3 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0046] 3 resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd when the reset transistor RST is turned on. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 16.

[0047] 3 generates a pixel signal having a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplifier transistor AMP constitutes a source-follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0048] During operation of the solid-state imaging device 1A according to the first embodiment, signal charges generated in the photoelectric conversion unit 25 of the pixel 3 are held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 3. The signal charges held in the floating diffusion region FD are then read out by the pixel circuit 16 and applied to the gate electrode of the amplifier transistor AMP of the pixel circuit 16. A horizontal line selection control signal is applied to the gate electrode of the select transistor SEL of the pixel circuit 16 from the vertical shift register. By setting the selection control signal to a high (H) level, the select transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD, amplified by the amplifier transistor AMP, flows through the vertical signal line 11. Furthermore, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 16 to a high (H) level, the reset transistor RST becomes conductive, resetting the signal charges accumulated in the floating diffusion region FD.

[0049] 3 are mounted on a semiconductor layer 21 (see FIG. 5A ) described later. Although not limited thereto, the pixel transistors Q (AMP, RST, SEL) included in the pixel circuit 16 of FIG. 3 are also mounted on the semiconductor layer 21, for example.

[0050] As will be described in detail later, in this first embodiment, one reset transistor RST is shared by two pixels 3 (3 a, 3 b) included in one pixel block 15. Also, in this first embodiment, one select transistor SEL is shared by two pixel blocks 15 aligned in the X direction.

[0051] <<Specific Configuration of Solid-State Imaging Device>> Next, a specific configuration of the semiconductor chip 2 (solid-state imaging device 1A) will be described with reference to FIGS. 4A to 8. FIG.

[0052] 4A omits the illustration of a multilayer wiring layer 55, which will be described later, for ease of viewing the drawings, and Fig. 5A omits the illustration of layers above a first wiring layer 57 included in the multilayer wiring layer 55. Also, Fig. 1 illustrates the light incident surface side of the semiconductor chip 2, but Fig. 4A is a plan view seen from the opposite side to the light incident surface side (the multilayer wiring layer side) of the semiconductor chip 2.

[0053] As shown in Figure 5A, the semiconductor chip 2 comprises a semiconductor layer 21 having a first surface portion S1 and a second surface portion S2 located on opposite sides of each other in the thickness direction (Z direction), an inter-pixel isolation region 31 as an isolation region extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 partitioned by the inter-pixel isolation region 31 and provided in the semiconductor layer 21.

[0054] 5A, the semiconductor chip 2 further includes a multilayer wiring layer 55 provided on the first surface S1 side of the semiconductor layer 21. The semiconductor chip 2 further includes a planarization film 61, an optical filter 63, and a microlens (on-chip lens) 64 provided in this order from the second surface S2 side of the semiconductor layer 21.

[0055] Here, the first surface S1 of the semiconductor layer 21 is sometimes referred to as a main surface or an element forming surface, and the second surface S2 is sometimes referred to as a back surface. The solid-state imaging device 1A according to the first embodiment photoelectrically converts incident light incident from the second surface S2 side of the semiconductor layer 21 by a photoelectric conversion unit 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 is sometimes referred to as a light incident surface.

[0056] In the first embodiment, the inter-pixel isolation region 31 corresponds to a specific but not limitative example of "isolation region" in the present technology.

[0057] 4A, two pixels 3 (3a, 3b) included in one pixel block 15 are arranged adjacent to each other in the X direction in plan view. That is, in the pixel array section 2A shown in FIG. 1, pixel blocks 15, each consisting of two pixels 3 (3a, 3b), are repeatedly arranged in both the X and Y directions.

[0058] <Planarization film, optical filter, and microlens> The planarization film 61 shown in FIG. 5A is provided on the second surface S2 side of the semiconductor layer 21 so as to cover the second surface S2 of the semiconductor layer 21, and planarizes the second surface S2 side of the semiconductor layer 21.

[0059] 5A is provided for each pixel 3. The optical filter 63 separates the color of the incident light that is incident from the light incident surface side (second surface portion S2 side) of the semiconductor chip 2. The microlens 64 condenses the irradiated light and allows the condensed light to be efficiently incident on the pixel 3.

[0060] 5A , the semiconductor layer 21 includes an inter-pixel isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 partitioned by the inter-pixel isolation region 31. The photoelectric conversion region 22 is provided for each pixel 3. The semiconductor layer 21 may be a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the first embodiment, a p-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 21, although the present invention is not limited thereto.

[0061] 4A , the inter-pixel isolation region 31 includes a first planar portion (planar extending portion) 31x extending in the X direction in a plan view, and a second planar portion (planar extending portion) 31y extending in the Y direction. The inter-pixel isolation region 31 further includes an intersection portion (point of intersection) where the first planar portion 31x and the second planar portion 31y intersect with each other on the same plane. In this first embodiment, the first planar portion 31x and the second planar portion 31y are, for example, perpendicular to each other.

[0062] The first planar portions 31x are repeatedly arranged at predetermined intervals in the Y direction, and the second planar portions 31y are repeatedly arranged at predetermined intervals in the X direction. That is, the inter-pixel isolation region 31 has a grid-like planar pattern in plan view.

[0063] 4A , the inter-pixel isolation region 31 corresponding to one photoelectric conversion region 22 has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds the periphery of one photoelectric conversion region 22. The inter-pixel isolation region 31 corresponding to one pixel block 15 has a composite planar pattern including the rectangular annular planar pattern surrounding the outer peripheries of the two pixels 3 a and 3 b and the planar pattern of a second planar portion 31 y arranged between the two pixels 3 a and 3 b.

[0064] 5A , the inter-pixel isolation region 31 extends in the thickness direction (Z direction) of the semiconductor layer 21, and electrically and optically isolates two adjacent photoelectric conversion regions 22 in a plan view. The inter-pixel isolation region 31 is, for example, an indented type, a so-called trench type, in which an indented portion 33 is formed in the semiconductor layer 21 to partition and isolate the photoelectric conversion regions 22.

[0065] The inter-pixel isolation region 31 includes, but is not limited to, for example, a recessed portion 33 extending across the first surface S1 and the second surface S2 of the semiconductor layer 21, and an isolation insulating film 34 provided in this recessed portion 33. In other words, the inter-pixel isolation region 31 extends across the first surface S1 and the second surface S2 of the semiconductor layer 21. The isolation insulating film 34 can be, for example, a silicon oxide film. In this first embodiment, the recessed portion 33 is filled with, for example, the isolation insulating film 34.

[0066] 4A and 4B , the photoelectric conversion region 22 is surrounded by the inter-pixel isolation region 31 in a plan view and has a rectangular planar shape. Specifically, the photoelectric conversion region 22 is surrounded by two first planar portions 31x that extend in the X direction and are spaced apart in the Y direction, and two second planar portions 31y that extend in the Y direction and are spaced apart in the X direction, in the inter-pixel isolation region 31. The photoelectric conversion region 22 is partitioned by the first planar portions 31x and the second planar portions 31y, and is separated from other photoelectric conversion regions 22.

[0067] As shown in FIGS. 5A and 5B , the photoelectric conversion region 22 has an upper surface portion 22 a located on the first surface portion S1 side of the semiconductor layer 21 and a first side surface portion (outer wall surface portion) 22 b located on the inter-pixel isolation region 31 side. The photoelectric conversion region 22 also includes the above-described photoelectric conversion unit 25, floating diffusion region FD, and transfer transistor TR. As shown in FIGS. 4A to 5B , the photoelectric conversion region 22 also includes an inter-element isolation region (field isolation region) 41 located on the upper surface portion 22 a side, and an island-shaped element formation region (active region) 43 located on the upper surface portion 22 a side (the first surface portion S1 side of the semiconductor layer 21) and partitioned by the inter-element isolation region 41 and the inter-pixel isolation region 31. The photoelectric conversion region 22 also includes an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors Q included in the above-described pixel circuit 16. The photoelectric conversion region 22 also has a second side surface portion 22c located on the opposite side to the first side surface portion 22b in a plan view and adjacent to the inter-element isolation region 41. The photoelectric conversion region 22 also has a p-type semiconductor region (well region) 23, an n-type semiconductor region 24, and a p-type power supply contact region WC (see FIG. 4B ).

[0068] 5A and 5B , the p-type semiconductor region 23 is provided over a wide area in the photoelectric conversion region 22, extending from the first surface S1 side to the second surface S2 side of the semiconductor layer 21. The p-type semiconductor region 23 is in contact with the inter-pixel isolation region 31 along the depth direction (Z direction) of the semiconductor layer 21.

[0069] 5A and 5B , the n-type semiconductor region 24 is provided in the p-type semiconductor region 23 in the photoelectric conversion region 22. That is, six sides of the n-type semiconductor region 24, including the top surface, bottom surface, and four side surfaces, are surrounded by the p-type semiconductor region 23. The n-type semiconductor region 24 is separated from the first surface S1 and second surface S2 of the semiconductor layer 21 and the inter-pixel isolation region 31.

[0070] 5A and 5B includes a p-type semiconductor region 23 and an n-type semiconductor region 24 in the photoelectric conversion region 22. The photoelectric conversion unit 25 is configured as a p-n junction photodiode (PD) including a p-n junction between the p-type semiconductor region 23 and the n-type semiconductor region 24.

[0071] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface S2 side of the semiconductor layer 21 into signal charges in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charges at the pn junction between the p-type semiconductor region 23 and the n-type semiconductor region 24.

[0072] 7, the floating diffusion region FD is provided in the p-type semiconductor region 23 on the first surface portion S1 side of the semiconductor layer 21 (the upper surface portion 22a side of the photoelectric conversion region 22). The floating diffusion region FD overlaps with the n-type semiconductor region 24 in a plan view, and is spaced apart from the n-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21. That is, the p-type semiconductor region 23 is provided between the floating diffusion region FD and the n-type semiconductor region 24. The floating diffusion region FD also serves as a main electrode region 52r of the reset transistor RST, which will be described later, and is made of an n-type semiconductor region.

[0073] 5A to 7 , the element isolation region 41 is provided in a surface layer portion on the upper surface portion 22 a side of the photoelectric conversion region 22, i.e., a surface layer portion on the first surface portion S1 side of the semiconductor layer 21. The element isolation region 41 has, but is not limited to, an STI (Shallow Trench Isolation) structure in which an isolation insulating film 42 b is buried inside a shallow groove portion 42 a recessed from the first surface portion S1 toward the second surface portion S2 side of the semiconductor layer 21, for example.

[0074] As shown in FIG. 4B, the inter-element isolation region 41 has an island-shaped planar pattern separated from the inter-pixel isolation region 31 except for a part thereof in a plan view, and defines an element formation region 43 together with the inter-pixel isolation region 31.

[0075] 5A to 7, the element formation region 43 is provided in a surface layer portion on the upper surface portion 22a side of the photoelectric conversion region 22, i.e., a surface layer portion on the first surface portion S1 side of the semiconductor layer 21. Then, as shown in Fig. 4B, the element formation region 43 is partitioned by the inter-element isolation region 41 and the inter-pixel isolation region 31, and has a planar pattern extending in a ribbon shape along the four sides of the photoelectric conversion region 22 in a plan view.

[0076] The planar patterns of the element formation region 43 are different between the two pixels 3a and 3b included in the pixel block 15. That is, as shown in Fig. 4B , in the two pixels 3a and 3b included in the pixel block 15, the planar pattern of the element formation region 43 in one pixel 3a and the planar pattern of the element formation region 43 in the other pixel 3b are inverted with respect to the boundary between the pixels 3a and 3b aligned in the X direction.

[0077] (P-Type Power Supply Contact Region) As shown in FIG. 4B , the p-type power supply contact region WC is provided on a corner side between two sides of the photoelectric conversion region 22 in a plan view. Although not shown in detail, the p-type power supply contact region WC is provided in a surface layer portion on the upper surface portion 22a side of the photoelectric conversion region 22, i.e., on the surface layer portion on the first surface portion S1 side of the semiconductor layer 21. The p-type power supply contact region WC is provided in an island-shaped power supply region partitioned by the inter-element isolation region 41 and the inter-pixel isolation region 31 on the upper surface portion 22a side of the photoelectric conversion region 22. The p-type power supply contact region WC is composed of a p-type semiconductor region with a higher impurity concentration than the p-type semiconductor region 23. The p-type power supply contact region WC is connected to the p-type semiconductor region 23 and is electrically conductive.

[0078] A first reference potential of, for example, 0 V is applied to this p-type power supply contact region WC as a reference potential within the semiconductor chip 2 (within the solid-state imaging device 1A) during operation, and the potential is fixed to this first reference potential.

[0079] 4B and 5B , the transfer transistor TR is provided on the first surface S1 side of the semiconductor layer 21, i.e., on the upper surface 22a side of the photoelectric conversion region 22. The transfer transistor TR has a gate electrode 47t provided on the upper surface 22a side of the photoelectric conversion region 22, spanning the inside and outside of the photoelectric conversion region 22, and a gate insulating film 46 provided between the gate electrode 47t and the semiconductor layer 21. The transfer transistor TR also has an n-type semiconductor region 24 functioning as a source region, an n-type floating diffusion region FD functioning as a drain region, and a p-type semiconductor region 23 functioning as a channel formation region. The transfer transistor TR is configured as, for example, a vertical type, although not limited thereto.

[0080] As shown in FIG. 5B, the gate electrode 47t of the transfer transistor TR has a head portion 47t provided on the outer side of the first surface portion S1 of the semiconductor layer 21 with the gate insulating film 46 interposed therebetween. １ And this head is 47 tons. １ leg portions 47r protruding from the gate insulating film 46 into the semiconductor layer 21 and adjacent to the semiconductor layer 21 with the gate insulating film 46 interposed therebetween; ２ The gate electrode 47t of the first embodiment has, but is not limited to, for example, a leg portion 47t ２ The width of the head is 47t １ It has a T-shaped cross section that is narrower than the width of the

[0081] Legs 47t of gate electrodes 47t ２ is provided in the recessed portion 45a of the semiconductor layer 21 with the gate insulating film 46 interposed therebetween, and its tip extends into the n-type semiconductor region 24 with being insulated and isolated.

[0082] 4B and 5B , a plurality of pixel transistors Q (AMP, SEL, RST) included in the pixel circuit 16 are provided in the element formation region 43. At least one pixel transistor Q of the plurality of pixel transistors Q has a gate electrode provided in the inter-pixel isolation region 31. In the first embodiment, of the three pixel transistors Q (AMP, SEL, RST), the gate electrodes 47s and 47r of the selection transistor SEL and the reset transistor RST are provided in the inter-pixel isolation region 31.

[0083] 4B and 7 , the amplifier transistor AMP includes a gate electrode 47a provided on the upper surface portion 22a of the photoelectric conversion region 22 (the first surface portion S1 side of the semiconductor layer 21) so as to overlap the element formation region 43 (semiconductor layer 21) in a planar view, and a gate insulating film 46 interposed between the gate electrode 47a and the element formation region 43. The amplifier transistor AMP also includes a pair of main electrode regions 52as and 52ar provided in the element formation region 43 on both sides of the gate electrode 47a in the gate length direction and functioning as a source region and a drain region. The amplifier transistor AMP also includes a channel formation region 53a (see FIG. 7 ) provided in the element formation region 43 so as to overlap the gate electrode 47a in a planar view. The pair of main electrode regions 52as and 52ar are spaced apart from each other via the channel formation region 53a. The pair of main electrode regions 52 as and 52 ar are formed of n-type semiconductor regions provided in the element forming region 43 , and the channel forming portion 53 a is formed of a p-type semiconductor region 23 provided in the element forming region 43 .

[0084] (Reset Transistor RST) As shown in FIGS. 4B , 5B , 6 , and 8 , the reset transistor RST is provided on the inter-pixel isolation region 31 side between two photoelectric conversion regions 22 included in the pixel block 15. The reset transistor RST includes a gate electrode 47r provided in the inter-pixel isolation region 31 adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, and a pair of main electrode regions 52r and 52ar provided on the upper surface portion 22a of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47r in a plan view and functioning as a source region and a drain region. The reset transistor RST also includes a channel formation portion 53r provided in the element formation region 43 (semiconductor layer 21) adjacent to the gate electrode 47r in a plan view. The pair of main electrode regions 52r and 52ar are formed of n-type semiconductor regions, and the channel formation portion 53r is formed of a p-type semiconductor region 23.

[0085] The gate electrode 47r of the reset transistor RST is selectively provided in the inter-pixel isolation region 31 and is buried in the inter-pixel isolation region 31, for example, although this is not limited to the first embodiment.

[0086] 4B and 5B, the reset transistor RST and the amplifier transistor AMP share a main electrode region 52as of the reset transistor RST and a main electrode region 52as of the amplifier transistor AMP, and are connected in series and provided in the element formation region 43. 4B, 5B, and 8, the reset transistor RST has a pair of main electrode regions 52r and 52ar, of which one main electrode region 52r also serves as a floating diffusion region FD.

[0087] 4B and 5B , the reset transistor RST is shared by two pixels 3a and 3b (two photoelectric conversion regions 22) included in the pixel block 15. The gate electrode 47r of the reset transistor RST is adjacent to each first side surface portion 22b of each of the two photoelectric conversion regions 22 adjacent to each other in a planar view, with the gate insulating film 46 interposed between them. That is, the reset transistor RST of the first embodiment has a gate electrode 47r provided in the inter-pixel isolation region 31 between the two photoelectric conversion regions 22 adjacent to each other in a planar view, and a pair of main electrode regions 52r, 52ar and a channel formation portion 53r provided in each of the two photoelectric conversion regions 22 adjacent to each other in a planar view.

[0088] (Selection Transistor SEL) As shown in FIGS. 4B , 5B , and 8 , the selection transistor SEL is provided on the side of the photoelectric conversion region 22 opposite the reset transistor TST side in a plan view. The selection transistor SEL includes a gate electrode 47s provided in the inter-pixel isolation region 31 adjacent to the first side portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, and a pair of main electrode regions 52s and 52as provided on the upper surface portion 22a of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47s in a plan view and functioning as a source region and a drain region. The selection transistor SEL also includes a channel formation portion 53s provided in the element formation region 43 (semiconductor layer 21) adjacent to the gate electrode 47s in a plan view. The pair of main electrode regions 52s and 52as are formed of n-type semiconductor regions, and the channel formation portion 53s is formed of a p-type semiconductor region 23.

[0089] The gate electrode 47 s of the selection transistor SEL is selectively provided in the inter-pixel isolation region 31 and is buried in the inter-pixel isolation region 31 , for example, although this is not limited to the first embodiment.

[0090] As shown in FIGS. 4B and 5B, the selection transistor SEL and the amplification transistor AMP share the main electrode region 52as of the selection transistor SEL and the main electrode region 52as of the amplification transistor AMP, and are provided in the element formation region 43 in series connection.

[0091] 4B and 5B , in two pixel blocks 15 aligned in the X direction, the select transistor SEL is shared by the pixel 3 a in one pixel block 15 and the pixel 3 b in the other pixel block 15. In other words, in two pixel blocks 15 aligned in the X direction, the select transistor SEL is shared by the pixel circuit 16 a assigned to the pixel 3 a in one pixel block 15 and the pixel circuit 16 b assigned to the pixel 3 b in the other pixel block 15. The gate electrodes 47 s of the select transistor SEL are adjacent to each other with the gate insulating film 46 interposed between them and the first side surface portions 22 b of the two photoelectric conversion regions 22 adjacent to each other in a planar view. That is, the select transistor SEL of this first embodiment has a gate electrode 47s provided in the inter-pixel isolation region 31 between two photoelectric conversion regions 22 adjacent to each other in a planar view, and a pair of main electrode regions 52s, 52as and a channel formation portion 53s provided in each of the two photoelectric conversion regions 22 adjacent to each other in a planar view.

[0092] 4B and 5B , the channel formation portions 53r, 53s of the reset transistor RST and the select transistor SEL are formed in the semiconductor layer 21 between the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22. That is, the reset transistor TRS and the select transistor SEL each have the channel formation portions 53r, 53s between the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22. In other words, the reset transistor RST and the select transistor SEL each have the channel formation portions 53r, 53s in the semiconductor layer 21 between the inter-pixel isolation region 31 and the inter-device isolation region 41. The thickness of the channel formation portions 53r, 53s in a planar view can be reduced by reducing the distance between the inter-pixel isolation region 31 and the inter-device isolation region 41. The thickness of the channel formation portions 53r, 53s is preferably less than 100 nm.

[0093] (Gate electrode material) The gate electrodes 47a, 47s, 47r, and 47t of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the transfer transistor TR are each made of, for example, a polycrystalline silicon film (doped polysilicon film) into which impurities that reduce the resistance value have been introduced.

[0094] (Enhancement Type) The reset transistor RST and the select transistor SEL can each be configured as an enhancement type (normally off type) in which a drain current flows when a gate voltage equal to or higher than the threshold voltage is applied to the gate electrodes 47r and 47s. Alternatively, the reset transistor RST and the select transistor SEL can each be configured as a depletion type (normally on type) in which a drain current flows even when no voltage is applied to the gate electrodes 47r and 47s. In the first embodiment, the reset transistor RST and the select transistor SEL are configured as, for example, an enhancement type, although this is not limited to this. In the case of the enhancement type, in each of the reset transistor RST and the select transistor SEL, a channel (inversion layer) electrically connecting the pair of main electrode regions 52r (52s) and 52ar (52as) is formed (induced) in the channel formation portions 53r and 53s by a voltage applied to the gate electrodes 47r and 47s, and a current (drain current) flows from the drain region side (e.g., the main electrode regions 52r and 52s side) through the channel of the channel formation portions 53r and 53s to the source region side (e.g., the main electrode regions 52ar and 52as side). Note that, like each of the reset transistor RST and the select transistor SEL, the amplification transistor AMP is also configured as, for example, an enhancement type.

[0095] 5A to 7 , the multilayer wiring layer 55 is provided on the first surface S1 side of the semiconductor layer 21. The multilayer wiring layer 55 includes an interlayer insulating film 56 provided on the first surface S1 side of the semiconductor layer 21 so as to cover the inter-element isolation region 41 and the element formation region 43, contact electrodes 57a, 57f, 57r, 57s, and 57t provided in the interlayer insulating film 56, and a first-layer wiring layer 58 provided on the side of the interlayer insulating film 56 opposite the semiconductor layer 21 side. The first-layer wiring layer 58 includes wires 58a, 58r, 58s, and 58t. The contact electrodes 57a, 57f, 57r, 57s, and 57t can be made of, for example, tungsten (W), a high-melting-point metal. The first wiring layer 58 may be made of a metal material such as aluminum (Al) or copper (Cu), or an alloy material mainly containing Al or Cu. The interlayer insulating film 56 may be made of a silicon oxide film, for example. The gate electrode 47t of the transfer transistor TR and the gate electrodes (47a, 47s, 47r) of the plurality of pixel transistors Q (AMP, SEL, RST) are covered with the interlayer insulating film 56.

[0096] <Contact electrode and wiring> As shown in Figures 5B and 7, the gate electrode 47t of the transfer transistor TR is electrically connected to a wiring 58t provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57t provided in the interlayer insulating film 56.

[0097] As shown in FIG. 5B, the gate electrode 47r of the reset transistor RST is electrically connected to a wiring 58r provided in the wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57r provided in the interlayer insulating film 56.

[0098] As shown in FIG. 5B, the gate electrode 47s of the select transistor SEL is electrically connected to a wiring 58s provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57s provided in the interlayer insulating film 56.

[0099] 7 , in two pixels 3 a and 3 a aligned in the Y direction, the gate electrode 47 a of the amplifier transistor AMP provided in the photoelectric conversion region 22 of one pixel 3 a is electrically connected to a wiring 58 a provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57 a provided in the interlayer insulating film 56. The wiring 58 a is then electrically connected to the floating diffusion region FD (main electrode region 52 r) provided in the photoelectric conversion region 22 of the other pixel 3 a via a contact electrode 57 f provided in the interlayer insulating film 56. That is, in two pixels 3 a and 3 a aligned in the Y direction, the gate electrode 47 a of the amplifier transistor AMP provided in one photoelectric conversion region 3 a and the floating diffusion region FD (main electrode region 52 r) provided in the other photoelectric conversion region 22 are electrically connected via the contact electrode 57 a, the wiring 58 a, and the contact electrode 57 f.

[0100] <<Method for Manufacturing Solid-State Imaging Device>> Next, a method for manufacturing the solid-state imaging device 1A according to the first embodiment of the present technology will be described with reference to Fig. 9 to Fig. 19. In this first embodiment, the description will be focused on the manufacture of pixel transistors included in the method for manufacturing the solid-state imaging device 1A.

[0101] 9 to 13, 16, 17A, and 18A are longitudinal cross-sectional views schematically showing a part of the longitudinal cross-sectional structure at the same position as the a4-a4 cutting line in FIG. 4A.

[0102] 14, 15, 17B, and 18B are longitudinal cross-sectional views each showing a part of the longitudinal cross-sectional structure at the same position as the b4-b4 cutting line in FIG. 4A.

[0103] First, as shown in Figure 9, a photoelectric conversion region 22 partitioned by an inter-pixel isolation region 31 is formed in the semiconductor layer 21, and an element formation region 43 partitioned by an inter-element isolation region 41 is formed on the upper surface portion 22a side of the photoelectric conversion region 22, which is the first surface portion S1 side of the semiconductor layer 21.

[0104] The photoelectric conversion region 22 has an upper surface portion 22a located on the first surface portion S1 side of the semiconductor layer 21, a first side surface portion 22b located on the inter-pixel isolation region 31 side, and a second side surface portion 22c located on the opposite side of the first side surface portion 22b in a planar view and adjacent to the inter-element isolation region 41.

[0105] The inter-pixel isolation region 31 can be formed by forming a recessed portion 33 in the semiconductor layer 21, extending in the thickness direction (Z direction) of the semiconductor layer 21, and then selectively filling this recessed portion 33 with an isolation insulating film 34. The inter-element isolation region 41 can be formed by forming a shallow groove portion 42a on the first surface portion S1 side of the semiconductor layer 21, and then selectively filling this shallow groove portion 42a with an isolation insulating film 42b. By forming the inter-pixel isolation region 31 and the inter-element isolation region 41, a photoelectric conversion region 22 is formed that is partitioned by the inter-pixel isolation region 31 and the inter-element isolation region 41 and has a top surface portion 22a, a first side surface portion 22b, and a second side surface portion 22c.

[0106] 10 , dug portion 45a and dug portion 45b are formed, extending in the thickness direction (Z direction) of semiconductor layer 21. Dug portion 45a is for forming gate electrode 47t of transfer transistor TR and is formed in the center of photoelectric conversion region 22, spaced apart from inter-pixel isolation region 31 in plan view. Dug portion 45b is for forming gate electrode 47r of pixel transistor Q and is formed in inter-pixel isolation region 31. In this first embodiment, dug portion 45b is formed in inter-pixel isolation region 31 in a first gate electrode formation portion where gate electrode 47r of reset transistor RST is formed and in a second gate electrode formation portion where gate electrode 47s of select transistor SEL is formed. Dug portion 45a can be formed by selectively etching semiconductor layer 21 using well-known photolithography and anisotropic dry etching techniques. The recessed portion 45b can be formed by selectively etching the pixel isolation region 31 using well-known photolithography and anisotropic dry etching techniques. The recessed portion 45a and the recessed portion 45b are basically formed in separate steps, but either one can be formed first.

[0107] In this step, the dug portion 45 a is formed so that the semiconductor layer 21 is exposed from the inner wall surface portion including the side wall surface portion and the bottom wall surface portion of the dug portion 45 a. In addition, in this step, the dug portion 45 b is formed so that the first side surface portion 22 b of the photoelectric conversion region 22 is exposed from the side wall surface portion of the dug portion 45 b.

[0108] Furthermore, in this process, the depth of the recess 45a determines the length of the leg 42t2 of the gate electrode 42t in the transfer transistor TR, so it is preferable that the recess 45a be formed to a depth that allows the tip to penetrate into the n-type semiconductor region 24.

[0109] In this step, the depth of the recessed portion 45b determines the gate width of the gate electrodes 42r, 42s of the reset transistor RST and the select transistor SEL, so the recessed portion 45b is preferably formed to a depth of about 0.1 μm to 1 μm.

[0110] Next, the native oxide film and excess insulating film on the first surface S1 side of the semiconductor layer 21 and on the upper surface 22a side of the photoelectric conversion region 22 are removed by, for example, wet etching to expose the first surface S1 (the upper surface 22a of the photoelectric conversion region 22) of the semiconductor layer 21, and then, as shown in FIG. 11 , a gate insulating film 46 is formed. The gate insulating film 46 is formed on the upper surface 22a of the photoelectric conversion region 22 and the inner wall surface of the recessed portion 45a, as well as on the first side surface 22b of the photoelectric conversion region 22 exposed inside the recessed portion 45b. The gate insulating film 46 may be, for example, a silicon oxide film. A silicon oxide film can be formed by thermal oxidation or deposition, but in this first embodiment, a silicon oxide film formed by thermal oxidation is used as the gate insulating film 46. Thermal oxidation can form a silicon oxide film with better film quality than deposition.

[0111] 12, a gate electrode film 47 is formed. The gate electrode film 47 is formed on the first surface S1 side of the semiconductor layer 21 so as to fill the interiors of the recessed portions 45a and 45b. The gate electrode film 47 may be a polycrystalline silicon film that can be formed by a CVD method.

[0112] Next, the gate electrode film 47 is patterned to form gate electrodes 47t, 47r, and 47s as shown in FIG. 13, and also form a gate electrode 47a (see FIG. 4B) although not shown.

[0113] In this step, the gate electrode 47t is formed by forming a head portion 47t on the outer side of the first surface portion S1 of the semiconductor layer 21 (outside the upper surface portion 22a of the photoelectric conversion region 22) with the gate insulating film 46 interposed therebetween. １ And this head 47a １ a leg portion 47t protruding from the recess 45a into the recess 45a of the semiconductor layer 21 and adjacent to the semiconductor layer 21 with the gate insulating film 46 interposed therebetween; ２ and is formed in a T-shaped vertical cross section.

[0114] In this step, each of the gate electrodes 47r and 47s is formed on the top surface 47r of the semiconductor layer 21 (on the top surface 22a of the photoelectric conversion region 22) with the gate insulating film 46 interposed therebetween. １ , 47s １ And this head 47r １ , 47s １ a leg portion 47r provided in the inter-pixel isolation region 31, which protrudes from the first side surface portion 22b of the photoelectric conversion region 22 into the inside of the recessed portion 45b of the semiconductor layer 21 and is adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween; ２ , 47s ２ In this step, the gate electrode 47a is formed on the element forming region 43 with the gate insulating film 46 interposed therebetween.

[0115] 14, a recessed portion 51 is formed in the inter-pixel isolation region 31. Although not shown in detail, the recessed portion 51 is formed along the periphery of the photoelectric conversion region 22 in plan view, excluding the regions of the gate electrodes 47r and 47s.

[0116] In this step, the depth of the recessed portion 51 defines the depth of the pair of main electrode regions of the pixel transistor Q (AMP, SEL, RST), so it is preferable to form it to a depth of about 0.1 μm to 1 μm.

[0117] Furthermore, in this process, it is preferable that the recessed portion 51 is formed so that the isolation insulating film 34 remains with a thin film thickness on the first side portion 22b of the photoelectric conversion region 22, in other words, so that the first side portion 22b of the photoelectric conversion region 22 is covered with the isolation insulating film 34 with a thin film thickness.

[0118] Next, referring to FIGS. 15 and 4B , main electrode regions 52as, 52ar, 52r, and 52s made of n-type semiconductor regions are formed in the element formation region 43 of the photoelectric conversion region 22, as shown in FIGS. 15 and 4B . Specifically, the main electrode regions 52as, 52ar, 52r, and 52s are formed by implanting impurity ions into the element formation region 43 from the top surface 22a of the photoelectric conversion region 22 shown in FIG. 15 and from the first side surface 22b of the photoelectric conversion region 22 through the recessed portion 51 shown in FIG. 15 , followed by heat treatment to activate the implanted impurity ions. The impurity ions are implanted using the inter-pixel isolation region 31, the inter-element isolation region 41, and the gate electrodes 47a, 47r, and 47s as masks. The impurity ions are implanted in a direction inclined with respect to the top surface 22a and the first side surface 22b of the photoelectric conversion region 22. The impurity ions include, for example, phosphorus (P ＋ ) and arsenic (As ＋ ) can be used.

[0119] 4B and 7, this process forms a channel formation portion 53a in the semiconductor layer 21 between the main electrode regions 52as and 52ar and overlapping with the gate electrode 47a in plan view. Then, an amplification transistor AMP is formed, which has the gate insulating film 46, the gate electrode 47a, the pair of main electrode regions 52as, 52ar, and the channel formation portion 53a.

[0120] 4B, 5B, and 8, this process forms a channel formation portion 53r adjacent to the gate electrode 47r with the gate insulating film 46 interposed therebetween in the semiconductor layer 21 between the main electrode regions 52r and 52ar and between the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22. Then, a reset transistor RST is formed, which has the gate insulating film 46, the gate electrode 47r, the pair of main electrode regions 52r and 52ar, and the channel formation portion 53r.

[0121] 4B and 5B, this process forms a channel formation portion 53r adjacent to the gate electrode 47r with the gate insulating film 46 interposed therebetween in the semiconductor layer 21 between the main electrode regions 52s and 52as and between the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22. Then, a reset transistor RST is formed, which has the gate insulating film 46, the gate electrode 47r, the pair of main electrode regions 52r and 52ar, and the channel formation portion 53r.

[0122] Next, the top portion 47r of each of the gate electrodes 47r and 47s １ , 47s １ are selectively removed to form gate electrodes 47r and 47s buried in the inter-pixel isolation region 31, as shown in FIG.

[0123] 17A and 17B , an interlayer insulating film 56 is formed on the first surface S1 side of the semiconductor layer 21. The interlayer insulating film 56 covers the inter-element isolation region 41 and the element formation region 43, as well as the gate electrode 47t of the transfer transistor TR and the gate electrodes 47a, 47s, and 47r of each of the plurality of pixel transistors Q (AMP, SEL, RST), and is formed so as to fill the recessed portion 51. A silicon oxide film that can be formed by CVD can be used as the interlayer insulating film 56.

[0124] Next, as shown in Figures 18A and 18B, contact electrodes 57t, 57a, 57r, and 57s are formed on the interlayer insulating film 56, and also a contact electrode 57f (not shown) is formed, and then wirings 58t, 58a, 58s, and 58r are formed on the interlayer insulating film 56, thereby resulting in the state shown in Figures 5A to 7.

[0125] 4A and 5B , in the solid-state imaging device 1A according to the first embodiment, among the plurality of pixel transistors Q (AMP, RST, SEL) included in the pixel circuit 16, the reset transistor RSE and the select transistor SEL each have gate electrodes 47r, 47s that are provided in the inter-pixel isolation region 31 adjacent to each other with the first side surface portion 22b of the photoelectric conversion region 22 and the gate insulating film 46 interposed therebetween. Therefore, compared to a case where the gate electrodes 47r, 47s of the reset transistor RST and the select transistor SEL are arranged in the photoelectric conversion region 22, the area occupied by each of the reset transistor RST and the select transistor SEL can be reduced, and the degree of freedom (layout freedom) in arranging active elements including the pixel transistors Q (AMP, RST, SEL) and the transfer transistor TR in the photoelectric conversion region 22 can be increased. Therefore, according to the solid-state imaging device 1A according to the first embodiment, the degree of freedom in arranging active elements in the photoelectric conversion region 22 can be increased.

[0126] Furthermore, since the area occupied by each of the reset transistor RST and the select transistor SEL in the photoelectric conversion region 22 can be reduced, the photoelectric conversion region 22 can be miniaturized without miniaturizing the pixel transistor Q provided in the photoelectric conversion region 22. This makes it possible to miniaturize the photoelectric conversion region 22 while suppressing deterioration in characteristics that accompanies miniaturization of the pixel transistor Q provided in the photoelectric conversion region 22.

[0127] Furthermore, the gate electrodes 47r, 47s of the reset transistor RST and the select transistor SEL are provided in the inter-pixel isolation region 31 adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween. This allows the gate width Wg of the gate electrodes 47r, 47s to be widened in the thickness direction (Z direction) of the semiconductor layer 21, thereby improving the mutual conductance (gm) without expanding the planar size of each of the reset transistor RST and the select transistor SEL.

[0128] Furthermore, the pair of main electrode regions 52r and 52ar of the reset transistor RST and the pair of main electrode regions 52s and 52as of the select transistor SEL are spaced apart from each other along the sides (edges) of the photoelectric conversion region 22 in a plan view and are provided on the upper surface portion 22a side (the first surface portion S1 side of the semiconductor layer 21) of the photoelectric conversion region 22. This makes it possible to easily electrically connect the pair of main electrode regions 52r and 52ar of the reset transistor RST to the wiring of the multilayer wiring layer 55, and also to easily electrically connect the pair of main electrode regions 52s and 52as of the select transistor SEL to the wiring of the multilayer wiring layer 55, thereby increasing the degree of freedom in routing the wiring in the multilayer wiring layer 55.

[0129] Furthermore, the main electrode region 52ar of the reset transistor RST and the main electrode region 52ar of the amplifier transistor AMP are shared. Furthermore, the main electrode region 52as of the select transistor SEL and the main electrode region 52as of the amplifier transistor AMP are shared. Furthermore, the floating diffusion region FD is also used as the main electrode region 52r of the transfer transistor TR. This allows the planar size of the photoelectric conversion region 22 to be reduced, and the number of pixels in the pixel array section 1A to be increased without increasing the planar size of the pixel array section 1A. In recent years, there has been a demand in the market for image sensors capable of high resolution, and this can contribute to increasing the resolution of image sensors.

[0130] The photoelectric conversion region 22 also has a first side surface portion 22b on the inter-pixel isolation region 31 side and a second side surface portion 22c located on the opposite side from the first side surface portion 22b and adjacent to the inter-element isolation region 41. The reset transistor RST and the select transistor SEL each have a channel formation portion 53r, 53s between the first side surface portion 22b and the second side surface portion 22c of the photoelectric conversion region 22. This allows the thickness of the channel formation portions 53r, 53s in the planar direction to be easily adjusted by adjusting the separation distance between the inter-pixel isolation region 31 and the inter-element isolation region 41, thereby making it possible to thin the channel formation portions 53r, 53s. This prevents depletion layers from almost extending from the main electrode regions 52r, 52ar, 52s, and 52as, which function as source and drain regions. This reduces the short channel effect and the back bias effect from the semiconductor layer 21 in each of the reset transistor RST and the select transistor SEL. As a result, the transistor characteristics of each of the reset transistor RST and the select transistor SEL can be improved.

[0131] Furthermore, in two photoelectric conversion regions 22 (pixels 3) aligned in the Y direction in plan view, the floating diffusion region FD of one photoelectric conversion region 22 and the amplification transistor AMP of the other photoelectric conversion region 22 are arranged adjacent to each other, thereby shortening the conductive path electrically connecting the floating diffusion region FD of one photoelectric conversion region 22 and the gate electrode 47 a of the amplification transistor AMP of the other photoelectric conversion region 22, and reducing the wiring capacitance added to the floating diffusion region FD. As a result, the conversion efficiency can be increased and random noise characteristics can be improved.

[0132] Here, in the amplifier transistor AMP, random noise is affected by defects at the interface of the gate insulating film 46. Since there are fewer defects at the interface of the gate insulating film 46 on the upper surface portion 22a side than on the second side surface portion 22c side of the photoelectric conversion region 22, it is preferable to provide the amplifier transistor AMP on the upper surface portion side of the photoelectric conversion region.

[0133] <<Variation of First Embodiment>> In the above-described first embodiment, the case where the gate electrodes 47r, 47s of the reset transistor RST and the select transistor SEL are provided in the inter-pixel isolation region 31 has been described; however, the present technology is not limited to the above-described first embodiment.

[0134] For example, the gate electrode 47 a of the amplification transistor AMP may be provided in the inter-pixel isolation region 31. That is, the present technology is configured such that the gate electrode of at least one pixel transistor among the plurality of pixel transistors Q included in the pixel circuit 16 is provided in the inter-pixel isolation region 31.

[0135] Furthermore, in the above-described first embodiment, the case has been described in which the gate electrodes 47r, 47s of the reset transistor RST and the select transistor SEL are embedded in the inter-pixel isolation region 31, but the gate electrodes 47r, 47s of the reset transistor RST and the select transistor SEL may be configured so that a portion thereof overlaps with the inter-pixel isolation region 31 and the other portion thereof is embedded in the inter-pixel isolation region 31. In other words, the gate electrodes 47r, 47s of the reset transistor RST and the select transistor SEL may be configured to extend from the inside to the outside of the inter-pixel isolation region 31 in the thickness direction (Z direction) of the semiconductor layer 21.

[0136] [Second embodiment] As shown in Figure 19, a solid-state imaging device 1B according to a second embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but the configuration of the inter-pixel isolation region is different.

[0137] That is, as shown in Figures 5A and 5B, the inter-pixel isolation region 31 of the first embodiment described above is composed of one vertical portion extending linearly across the first surface portion S1 side and the second surface portion S2 side of the semiconductor layer 21.

[0138] In contrast, as shown in FIG. 19, the inter-pixel isolation region 31B of the second embodiment has a first vertical portion 31b provided on the first surface portion S1 side of the semiconductor layer 21. １ and this first vertical portion 31b １ the first vertical portion 31b extending from the first vertical portion 31b toward the second surface portion S2 of the semiconductor layer 21 and having a width １The second vertical portion 31b is narrower than the width of the ２ and this first vertical portion 31b １ and the width of the second vertical portion 31b ２ and a step portion 31bz due to the difference in width between the first and second electrodes.

[0139] The gate electrodes 47r and 47s of the reset transistor RST and the select transistor SEL are connected to the first vertical portion 31b of the inter-pixel isolation region 31B. １ The gate electrodes 47r and 47s are adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween.

[0140] This inter-pixel isolation region 31B can be formed, for example, by forming a shallow groove portion on the first surface S1 side of the semiconductor layer 21, then forming a recessed portion extending from the bottom surface of this shallow groove portion toward the second surface S2 side of the semiconductor layer 21, and then selectively embedding an isolation insulating film 34 in this recessed portion and shallow groove portion.

[0141] Furthermore, this inter-pixel isolation region 31B can be formed, for example, by forming a recessed portion extending from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side, then selectively embedding an isolation insulating film 34 in this recessed portion, and then selectively etching the semiconductor layer 21 on the first surface S1 side of the semiconductor layer 21 in the region overlapping the recessed portion in which the isolation insulating film 34 is embedded and in the surrounding area to form a shallow groove portion, and then selectively embedding an isolation insulating film in this shallow groove portion.

[0142] The present technology can also be applied to the inter-pixel isolation region 31B of the second embodiment. Furthermore, by applying the present technology, the solid-state imaging device 1B of the second embodiment can also achieve the same effects as the solid-state imaging device 1A of the first embodiment. Furthermore, in the case of the inter-pixel isolation region 31B of the second embodiment, the volume of the n-type semiconductor region 24 can be increased compared to the inter-pixel isolation region 31 of the first embodiment, thereby further improving the saturation signal amount Qs.

[0143] [Third Embodiment] As shown in Figures 20 and 21 , a solid-state imaging device 1C according to a third embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, except for the configurations of the gate electrodes of the reset transistor RST and the select transistor SEL.

[0144] 20 and 21, the reset transistor RST and the select transistor SEL of the third embodiment include gate electrodes 71r and 71s instead of the gate electrodes 47r and 47s of the first embodiment shown in FIGS. 4B and 5B. Other configurations are generally similar to those of the first embodiment.

[0145] As shown in FIGS. 20 and 21, the gate electrode 71r of the reset transistor RST is provided across the upper surface portion 22a and the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween.

[0146] Specifically, the gate electrode 71r has a head portion 71r extending from the outside of the first surface portion S1 of the semiconductor layer 21 across the photoelectric conversion region 22 and the inter-pixel isolation region 31 in a plan view. １ And this head 71r １ a leg portion 71r that protrudes from the first side surface portion 22b of the photoelectric conversion region 22 toward the inter-pixel isolation region 31 and is adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween; ２ The head 71r １ A gate insulating film 46 is provided between the upper surface 22 a of the photoelectric conversion region 22 and the upper surface 22 a of the photoelectric conversion region 22 .

[0147] As shown in Figures 20 and 21, similar to the gate electrode 71r, the gate electrode 71s of the select transistor SEL is also provided across the upper surface portion 22a and the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween.

[0148] Specifically, like the gate electrode 71r, the gate electrode 71s also has a head portion 71s extending outside the first surface portion S1 of the semiconductor layer 21 across the photoelectric conversion region 22 and the inter-pixel isolation region 31 in a plan view. １ And this head 71s １leg portions 71s protruding from the first side surface portion 22b of the photoelectric conversion region 22 toward the inter-pixel isolation region 31 and adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween; ２ and a head portion 71s. １ A gate insulating film 46 is also provided between the upper surface 22 a of the photoelectric conversion region 22 and the upper surface 22 a of the photoelectric conversion region 22 .

[0149] The gate electrodes 71r and 71s of the reset transistor RST and the select transistor SEL in the third embodiment have a head portion 71r, similar to the gate electrode 47r of the transfer transistor TR. １ , 71s １ The width of the leg 71r ２ , 71r ２ The width is wider than the width of the first embodiment, and the vertical cross section is T-shaped.

[0150] The solid-state imaging device 1C according to the third embodiment also provides the same effects as those of the solid-state imaging device 1A according to the first embodiment.

[0151] Furthermore, the gate electrodes 71r, 71s of the reset transistor RST and the select transistor SEL in this third embodiment are provided across the upper surface portion 22a and the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, so that the gate width Wg of the gate electrodes 71r, 71s can be made wider compared to the first embodiment.

[0152] In the third embodiment, the case where the present technology is applied to each of the reset transistor RST and the select transistor SEL has been described, but the present technology can also be applied to the amplifier transistor AMP.

[0153] [Fourth embodiment] As shown in Figure 22, a solid-state imaging device 1D according to a fourth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but the configurations of the gate electrodes of the reset transistor RST and the select transistor SEL are different.

[0154] 22, the reset transistor RST and the select transistor SEL of the fourth embodiment include gate electrodes 72r and 72s instead of the gate electrodes 47r and 47s of the first embodiment shown in FIGS. 4B and 5B. The other configurations are generally similar to those of the first embodiment.

[0155] As shown in FIG. 22, the gate electrode 72r of the reset transistor RST is provided across the top surface portion 22a, the first side surface portion 22b, and the second side surface portion 22c of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween.

[0156] Specifically, the gate electrode 72r has a head portion 72r that is located outside the first surface portion S1 of the semiconductor layer 21 and extends across the inter-pixel isolation region 31 and the inter-element isolation region 41 across the upper surface portion 22a (element formation region 43) of the photoelectric conversion region 22 in a plan view. １ And this head 72r １ a first leg portion 72r that protrudes from the first leg portion 72r toward the inter-pixel isolation region 31 and is adjacent to the first side portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween; ２ and head 72r １ a second leg portion 72r that protrudes from the second side portion 22c of the photoelectric conversion region 22 toward the element isolation region 41 and is adjacent to the second side portion 22c of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween; ３ and a head portion 72r. １ and the upper surface portion 22a of the photoelectric conversion region 22. Also in this fourth embodiment, the reset transistor RST is shared by two pixels 3a and 3b arranged adjacent to each other in the X direction, so the gate electrode 72r is provided at the top portion 72r １ Two second legs 72r ３ It has.

[0157] As shown in Figure 22, the gate electrode 72s of the select transistor SEL, like the gate electrode 72r of the reset transistor RST, is provided across the upper surface portion 22a, the first side surface portion 22b, and the second side surface portion 22c of the photoelectric conversion region 22, with a gate insulating film 46 interposed therebetween.

[0158] Specifically, the gate electrode 72s is provided on the outside of the first surface portion S1 of the semiconductor layer 21, and has a head portion 72s extending across the inter-pixel isolation region 31 and the inter-element isolation region 41 across the upper surface portion 22a of the photoelectric conversion region 22 in a plan view. １ And this head 72s １ a first leg portion 72s that protrudes from the first leg portion 72s toward the inter-pixel isolation region 31 and is adjacent to the first side portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween; ２ and head 72sr １ a second leg portion 72r that protrudes from the second side portion 22c of the photoelectric conversion region 22 toward the element isolation region 41 and is adjacent to the second side portion 22c of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween; ３ and a head portion 72r. １ and the upper surface portion 22a of the photoelectric conversion region 22. Also in this fourth embodiment, in two pixel blocks 15 arranged adjacent to each other in the X direction, the pixel 3b of one pixel block 15 and the pixel 3a of the other pixel block 15 share the selection transistor SEL, so the gate electrode 72s also has a single head portion 72s １ Two second legs 72s ３ It has.

[0159] The solid-state imaging device 1D according to the fourth embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment.

[0160] Furthermore, the gate electrodes 72r, 72s of the reset transistor RST and the select transistor SEL in this fourth embodiment are provided across the upper surface portion 22a, the first side surface portion 22b, and the second side surface portion 22c of the photoelectric conversion region 22, with the gate insulating film 46 interposed therebetween, so that the gate width Wg of the gate electrodes 72r, 72s can be made wider compared to the third embodiment.

[0161] In the fourth embodiment, the case where the present technology is applied to each of the reset transistor RST and the selection transistor SEL has been described, but the present technology can also be applied to the amplification transistor AMP.

[0162] Fifth Embodiment As shown in FIGS. 23 and 24 , a solid-state imaging device 1E according to a fifth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but has a different configuration for the amplification transistor AMP.

[0163] That is, as shown in Figures 23 and 24, the amplification transistor AMP of this fifth embodiment has a gate electrode 47a provided in the inter-pixel isolation region 31 between two photoelectric conversion regions 22 adjacent to each other in the Y direction in plan view.

[0164] Specifically, the amplifier transistor AMP of the fifth embodiment includes a gate electrode 47a provided in the inter-pixel isolation region 31 adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween, and a pair of main electrode regions 52as and 52ar provided on the upper surface portion 22a of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47a in a plan view and functioning as a source region and a drain region. The amplifier transistor AMP also includes a channel formation portion 53a provided in the element formation region 43 (semiconductor layer 21) adjacent to the gate electrode 47a in a plan view. The pair of main electrode regions 52as and 52ar are formed of n-type semiconductor regions, and the channel formation portion 53r is formed of a p-type semiconductor region 23.

[0165] The amplification transistor AMP of this fifth embodiment has two photoelectric conversion regions 22 aligned in the Y direction via an inter-pixel isolation region 31 in a plan view, and has a gate electrode 47a that is connected to and adjacent to the floating diffusion region FD of one of the photoelectric conversion regions 22, and is provided in the inter-pixel isolation region 31 adjacent to the first side portion 22b of the other photoelectric conversion region 22 with a gate insulating film 46 interposed therebetween.

[0166] The solid-state imaging device 1E according to the fifth embodiment also provides the same effects as those of the solid-state imaging device 1A according to the first embodiment.

[0167] Furthermore, in the amplification transistor AMP of the fifth embodiment, the gate electrode 47 a is connected to the floating diffusion region FD so as to be adjacent to each other in a plan view. This allows the gate electrode 47 a and the floating diffusion region FD to be electrically connected over the shortest distance, thereby reducing the wiring capacitance added to the floating diffusion region FD compared to when the gate electrode 47 a and the floating diffusion region FD are electrically connected via wiring in the multilayer wiring layer 55. This allows the conversion efficiency to be increased and random noise to be reduced.

[0168] 25 to 29 , a solid-state imaging device 1F according to a sixth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, but differs in the configuration of the amplification transistor AMP. In addition, the solid-state imaging device 1F according to the sixth embodiment of the present technology further includes relay conductor portions 74 a and 74 b provided in the inter-pixel isolation region 31.

[0169] 25 and 26, the amplification transistor AMP of the sixth embodiment includes a gate electrode 73a instead of the gate electrode 47a of the first embodiment shown in Figures 4A and 7. Other configurations are generally similar to those of the first embodiment.

[0170] As shown in Figures 25 and 26, in two photoelectric conversion regions 22 that are adjacent to each other and lined up in the Y direction with an inter-pixel isolation region 31 interposed therebetween in a planar view, the amplification transistor AMP provided in one of the photoelectric conversion regions 22 has a gate electrode 73a that is provided across the upper surface portion 22a of one of the photoelectric conversion regions 22 and the inter-pixel isolation region 31 in a planar view, and is electrically and mechanically connected to the floating diffusion region FD provided in the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22.

[0171] Specifically, as shown in FIGS. 25 and 26, the gate electrode 73a of the amplification transistor AMP according to the sixth embodiment has a head portion 73a extending from the outside of the first surface portion S1 of the semiconductor layer 21 across one photoelectric conversion region 22 and the inter-pixel isolation region 31 in a plan view. １ And this head 73a １a relay protrusion 73a protruding from the other photoelectric conversion region 22 toward the inter-pixel isolation region 31 and electrically and mechanically connected to the floating diffusion region FD of the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22. ３ and a head portion 73a. １ The gate insulating film 46 is interposed between the relay protrusion 73a and the upper surface 22a of one of the photoelectric conversion regions 22. ３ are embedded in the inter-pixel isolation region 31 .

[0172] 25 , 27 , and 29 , the relay conductor 74a is provided in the inter-pixel isolation region 31 between two photoelectric conversion regions 22 included in one pixel block 15. The relay conductor 74a is electrically and mechanically connected to the main electrode region 52ar of the amplifier transistor AMP in one of the two photoelectric conversion regions 22 included in one pixel block 15 at the first side surface portion 22b of the one photoelectric conversion region 22, and is also electrically and mechanically connected to the main electrode region 52ar of the amplifier transistor AMP in the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22. That is, the relay conductor 74a is electrically and mechanically connected to the main electrode regions 52ar of the two amplifier transistors AMP adjacent to each other across the inter-pixel isolation region 31 at the first side surface portion 22b of each of the two photoelectric conversion regions 22 adjacent to each other in a planar view.

[0173] 27 and 29 , the relay conductor 74a is embedded in the inter-pixel isolation region 31, penetrates the inter-pixel isolation region 31 in the X direction, and is connected to the first side surface portions 22b of each of the two photoelectric conversion regions 22 included in one pixel block 15. The relay conductor 74a is electrically connected to a wiring 58ar provided in the wiring layer 58 on the inter-layer insulating film 56 via a contact electrode 57ar provided in the inter-layer insulating film 56.

[0174] 25 and 28, the relay conductor 74b is provided in the inter-pixel isolation region 31 between two pixel blocks 15 aligned adjacent to each other in the X direction. In two adjacent photoelectric conversion regions 22 in the two pixel blocks 15 aligned in the X direction, the relay conductor 74b is electrically and mechanically connected to the power supply contact region WC of one photoelectric conversion region 22 at the first side surface portion 22b of one photoelectric conversion region 22, and is also electrically and mechanically connected to the power supply contact region WC of the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22. In other words, the relay conductor 74b is electrically and mechanically connected to two power supply contact regions WC adjacent to each other across the inter-pixel isolation region 31 at the first side surface portion 22b of each of the two photoelectric conversion regions 22 adjacent to each other in a planar view.

[0175] 28 , similar to the relay conductor 74a, the relay conductor 74b is embedded in the inter-pixel isolation region 31, penetrates the inter-pixel isolation region 31 in the X direction, and is connected to the first side surface portions 22b of each of two photoelectric conversion regions 22 adjacent to each other with the inter-pixel isolation region 31 in between. Similarly to the relay conductor 74a, the relay conductor 74b is electrically connected, via a contact electrode 57wc provided in the interlayer insulating film 56, to a wiring 58wc provided in the wiring layer 58 on the interlayer insulating film 56. A reference potential of, for example, 0 V is supplied from the wiring 58wc through the contact electrode 57wc to the relay conductor 74b.

[0176] Each of the relay conductors 74a and 74b is made of, for example, a polycrystalline silicon film doped with impurities that reduce the resistance. Although a metal film may be used for each of the relay conductors 74a and 74b, it is preferable to use a polycrystalline silicon film in consideration of the difference in thermal expansion coefficient between the inter-pixel isolation region 31 and the semiconductor layer 21.

[0177] <<Major Effects of the Sixth Embodiment>> As described above, the amplifier transistor AMP of the sixth embodiment has two photoelectric conversion regions 22 aligned in the Y direction with the inter-pixel isolation region 31 interposed therebetween in a plan view. The amplifier transistor AMP has a gate electrode 73a that is disposed across the upper surface portion 22a of one of the photoelectric conversion regions 22 and the inter-pixel isolation region 31, and is electrically and mechanically connected to the floating diffusion region FD of the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22. This eliminates the need for wiring in the multilayer wiring layer 55 to electrically connect the gate electrode 73a of the amplifier transistor AMP to the floating diffusion region FD, thereby reducing the wiring density of the multilayer wiring layer 55 that overlaps the photoelectric conversion region 22 in a plan view. This increases the degree of freedom in routing the wiring connecting to the pixel transistors Q in the photoelectric conversion region 22 and alleviates restrictions on the placement of the pixel transistors Q due to the wiring routing. Therefore, the solid-state imaging device 1F of the sixth embodiment increases the degree of freedom in the placement of the pixel transistors Q in the photoelectric conversion region 22.

[0178] The solid-state imaging device 1F according to the sixth embodiment also includes a relay conductor 74a provided in the inter-pixel isolation region 31 between two photoelectric conversion regions 22 aligned in the X direction in one pixel block 15. The relay conductor 74a is electrically and mechanically connected to the main electrode region 52ar of the amplifier transistor AMP in one of the two photoelectric conversion regions 22 included in one pixel block 15 at the first side surface portion 22b of one of the photoelectric conversion regions 22, and is also electrically and mechanically connected to the main electrode region 52ar of the amplifier transistor AMP in the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22. Therefore, in the connection between the relay conductor 74a and the contact electrode 57ar, a sufficient impurity concentration for connection can be achieved, and connection defects due to etching damage, silicide abnormalities, etc. can be suppressed, and the generation of dark current due to leakage current can be suppressed.

[0179] The solid-state imaging device 1F according to the sixth embodiment also includes a relay conductor 74b provided in the inter-pixel isolation region 31 between two pixel blocks 15 arranged adjacent to each other in the X direction. Similarly to the relay conductor 74a, in two adjacent photoelectric conversion regions 22 in the two pixel blocks 15 arranged adjacent to each other in the X direction, the relay conductor 74b is electrically and mechanically connected to the power supply contact region WC of one photoelectric conversion region 22 at the first side surface portion 22b of one photoelectric conversion region 22, and is also electrically and mechanically connected to the power supply contact region WC of the other photoelectric conversion region 22 at the first side surface portion 22b of the other photoelectric conversion region 22. Therefore, in the connection between the relay conductor 74b and the contact electrode 57WC, a sufficient impurity concentration for connection can be achieved, and connection defects due to etching damage, silicide abnormalities, and the like can be suppressed, and dark current due to leakage current can be suppressed.

[0180] [Seventh embodiment] As shown in Figures 30 to 32, a solid-state imaging device 1G according to a seventh embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration.

[0181] That is, the solid-state imaging device 1G of the seventh embodiment includes a pixel circuit 16G shown in Fig. 30 instead of the pixel circuit 16 of the first embodiment shown in Fig. 3. In the seventh embodiment, the transistor layout of the photoelectric conversion region 22 is slightly different from that of the first embodiment. The other configurations are generally similar to those of the first embodiment.

[0182] 30, the pixel circuit 16G has a circuit configuration in which a switching transistor FDG is newly added to the configuration of the above-described pixel circuit 16. That is, the pixel circuit 16G includes, as pixel transistors Q, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG.

[0183] 30, the switching transistor FDG has a source region electrically connected to the gate electrode of the amplifier transistor AMP and the floating diffusion region FD, and a drain region electrically connected to the source region of the reset transistor RST. The gate electrode of the switching transistor FDG is electrically connected to a switching transistor drive line of the pixel drive lines 10 shown in Fig. 2. The switching transistor FDG controls charge retention by the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplifier transistor AMP.

[0184] 31 and 32 , the switching transistor FDG has a gate electrode 47f provided in the inter-pixel isolation region 31 between two photoelectric conversion regions 22 adjacent to each other in the Y direction in a plan view. Specifically, the switching transistor FDG has: a gate electrode 47f provided in the inter-pixel isolation region 31 adjacent to the first side surface portion 22b of the photoelectric conversion region 22 with a gate insulating film 46 interposed therebetween; and a pair of main electrode regions 52f and 52r provided on the upper surface portion 22a of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47f in a plan view, and functioning as a source region and a drain region. The switching transistor FDG also has a channel formation portion 53f provided in the element formation region 43 (semiconductor layer 21) adjacent to the gate electrode 47f in a plan view. The pair of main electrode regions 52f and 52r are formed of n-type semiconductor regions, and the channel formation portion 53f is formed of a p-type semiconductor region 23.

[0185] The switching transistor FDG is used to switch the conversion efficiency. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, when performing charge-to-voltage conversion, if the FD capacitance C (floating diffusion capacitance C) of the floating diffusion region FD is large, the voltage V converted to a voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, pixel signals are large, so if the FD capacitance C of the floating diffusion region FD is not large, the floating diffusion region FD cannot fully absorb the charge of the photoelectric conversion unit 25 (photodiode PD). Furthermore, the FD capacitance C of the floating diffusion region FD must be large so that the voltage V converted to a voltage by the amplifier transistor AMP does not become too large (in other words, to reduce it). Based on these considerations, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, thereby increasing the overall FD capacitance C. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the switching transistor FDG on and off, the FD capacitance C can be made variable, and the conversion efficiency can be changed.

[0186] In the seventh embodiment, the floating diffusion region FD also serves as the main electrode region 52f of the switching transistor FDG. The reset transistor RST and the switching transistor FDG share the main electrode region 52r of the reset transistor RST and the main electrode region 52r of the switching transistor FDG, and are connected in series.

[0187] The solid-state imaging device 1G according to the seventh embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

[0188] In the seventh embodiment, the gate electrodes 47f, 47r, and 47s of the switching transistor FDG, the reset transistor RST, and the selection transistor SEL are provided in the inter-pixel isolation region 31 as the pixel transistors Q included in the pixel circuit 16G. However, the gate electrode of at least one of the pixel transistors Q included in the pixel circuit 16G may be provided in the inter-pixel isolation region 31.

[0189] [Eighth Embodiment] As shown in Figures 33 to 35 , a solid-state imaging device 1H according to an eighth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration.

[0190] That is, the solid-state imaging device 1H of the eighth embodiment includes a pixel circuit 16H shown in Fig. 33 instead of the pixel circuit 16 of the first embodiment shown in Fig. 3. In the eighth embodiment, the planar layout of the pixel transistors Q included in the pixel circuit 16H is slightly different from that of the first embodiment. All of the gate electrodes of the pixel transistors Q included in this pixel circuit 16H are provided in the element formation region 43 of the photoelectric conversion region 22. The other configurations are generally similar to those of the first embodiment.

[0191] As shown in Fig. 33, the pixel circuit 16H has a circuit configuration in which two switching transistors FDG and FCG are newly added to the configuration of the pixel circuit 16 shown in Fig. 3 described above. That is, the pixel circuit 16H includes, as pixel transistors Q that constitute the circuit, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and two switching transistors FCG and FDG. While the pixel circuit 16G of the seventh embodiment described above (see Fig. 30) includes one switching transistor FDG, the pixel circuit 16H of this eighth embodiment includes two switching transistors FCG and FDG.

[0192] 33, the source region of the switching transistor FCG is electrically connected to the drain region of the switching transistor FDG, and the drain region is electrically connected to the source region of the reset transistor RST. The gate electrode of the switching transistor FCG is electrically connected to the first switching transistor drive line of the pixel drive lines 10 shown in FIG.

[0193] 33, the source region of the switching transistor FDG is electrically connected to the gate electrode of the amplification transistor AMP and the floating diffusion region FD, and the drain region is electrically connected to the source region of the switching transistor FCG. The gate electrode of the switching transistor FDG is electrically connected to the second switching transistor drive line of the pixel drive line 10 shown in FIG.

[0194] 33 controls charge retention by the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplifier transistor AMP, similar to the switching transistor FDG of the seventh embodiment. By switching on / off each of these two switching transistors FCG and FDG, the FD capacitance C can be made variable and the conversion efficiency can be switched, similar to the pixel circuit 16G of the seventh embodiment.

[0195] 34 , the switching transistor FCG includes a gate electrode 47fc provided in the element formation region 43 (first side surface portion 22b of the photoelectric conversion region 22) of the photoelectric conversion region 22 with a gate insulating film interposed therebetween, and a pair of main electrode regions 52fc and 52r provided in the element formation region 43 (upper surface portion 22a) of the photoelectric conversion region 22 and spaced apart from each other in the gate length direction of the gate electrode 47fc in a plan view, and functioning as a source region and a drain region. The switching transistor FCG also includes a channel formation portion provided in the element formation region 43 (semiconductor layer 21) overlapping with the gate electrode 47fc in a plan view. The pair of main electrode regions 52fc and 52r are formed of n-type semiconductor regions, and the channel formation portion is formed of a p-type semiconductor region 23.

[0196] 34 , the switching transistor FDG includes a gate electrode 47f provided in the element formation region 43 (first side surface portion 22b of the photoelectric conversion region 22) of the photoelectric conversion region 22 with a gate insulating film interposed therebetween, and a pair of main electrode regions 52f and 52fc provided in the element formation region 43 (top surface portion 22a) of the photoelectric conversion region 22 and spaced apart from each other in the gate length direction of the gate electrode 47f in a plan view, and functioning as a source region and a drain region. The switching transistor FDG also includes a channel formation portion provided in the element formation region 43 (semiconductor layer 21) overlapping with the gate electrode 47f in a plan view. The pair of main electrode regions 52f and 52fc are formed of n-type semiconductor regions, and the channel formation portion is formed of a p-type semiconductor region 23.

[0197] In the eighth embodiment, the floating diffusion region FD also serves as the main electrode region 52f of the switching transistor FDG. Furthermore, the reset transistor RST and the switching transistor FCG share the main electrode region 52r of the reset transistor RST and the main electrode region 52r of the switching transistor FCG, and are connected in series. Furthermore, the switching transistor FCG and the switching transistor FDG share the main electrode region 52fc of the switching transistor FCG and the main electrode region 52fc of the switching transistor FDG, and are connected in series. That is, the reset transistor RST and the two switching transistors FCG and FDG are provided in the element formation region 43 of the photoelectric conversion region 22, and are connected in series.

[0198] As shown in FIGS. 34 and 35, the amplifier transistor AMP of the eighth embodiment has a configuration basically similar to that of the amplifier transistor AMP of the first embodiment, but differs in the configuration of the gate electrode.

[0199] That is, two photoelectric conversion regions 22 (22X １ and 22X ２ ) in one photoelectric conversion region 22X １ The amplifier transistor AMP is provided in one of the photoelectric conversion regions 22X in plan view. １and the inter-pixel isolation region 31, and the other photoelectric conversion region 22X ２ The other photoelectric conversion region 22X in the first side surface portion 22b ２ The gate electrode 75a is connected to the floating diffusion region FD.

[0200] 35, the gate electrode 75a has a head portion 75a provided across one photoelectric conversion region 22X1 and the inter-pixel isolation region 31 in a plan view. １ And this head 75a １ protrudes from the inter-pixel isolation region 31 side, and the other photoelectric conversion region 22X ２ The relay connection portion 75a is connected to the floating diffusion region FD at the first side surface portion 22b. ３ In other words, the gate electrode 75a is formed on the outer side of the first surface S1 of the semiconductor layer 21, and is connected to one of the photoelectric conversion regions 22X １ and extending across the inter-pixel isolation region 31 and having a head 75a １ into the inter-pixel isolation region 31, and the other photoelectric conversion region 22X ２ The gate electrode 75a of the eighth embodiment is electrically and mechanically connected to the floating diffusion region FD at the first side portion 22b of the gate electrode 75a. As with the gate electrode 47a of the amplification transistor AMP of the first embodiment, the gate electrode 75a of the eighth embodiment is made of, for example, a polycrystalline silicon film (doped polysilicon film) into which an impurity that reduces the resistance value is introduced. The gate electrode 75a of the eighth embodiment is made of, for example, a polycrystalline silicon film (doped polysilicon film) into which an impurity that reduces the resistance value is introduced. １ side and the other photoelectric conversion region 22X ２ In the eighth embodiment, the first side portion 22b of the photoelectric conversion region 22 corresponds to a specific but not limitative example of "side portion of a photoelectric conversion region" in the present technology.

[0201] <<Major Effects of Eighth Embodiment>> As described above, the amplification transistor AMP of the eighth embodiment has two photoelectric conversion regions 22 (22X １ , 22X ２ ) in one photoelectric conversion region 22X １and the inter-pixel isolation region 31, and the other photoelectric conversion region 22X ２ The first side surface portion 22b of the amplifier transistor AMP has a gate electrode 75a electrically and mechanically connected to the floating diffusion region FD of the other photoelectric conversion region 22. Therefore, it is not necessary to electrically connect the gate electrode 75a of the amplifier transistor AMP to the floating diffusion region FD using wiring in the multilayer wiring layer 55, and the wiring density of the multilayer wiring layer 55 that overlaps with the photoelectric conversion region 22 in a planar view can be reduced. This increases the degree of freedom in routing the wiring connecting to the pixel transistors Q (AMP, SEL, RST, FCG, FDG) in the photoelectric conversion region 22, thereby easing constraints on the placement of the pixel transistors Q due to the routing of the wiring. Therefore, in the solid-state imaging device 1H according to the eighth embodiment, as in the solid-state imaging device 1A according to the first embodiment described above, the degree of freedom in the placement of the pixel transistors Q in the photoelectric conversion region 22 can be increased.

[0202] Furthermore, the gate electrode 75a and the floating diffusion region FD can be electrically connected over the shortest distance, and the wiring capacitance added to the floating diffusion region FD can be reduced compared to when the gate electrode 47a and the floating diffusion region FD are electrically connected via wiring in the multilayer wiring layer 55. This makes it possible to increase the conversion efficiency and reduce random noise.

[0203] Here, in a CMOS image sensor, high conversion efficiency is an effective means for achieving high sensitivity and low noise. In order to increase the conversion efficiency, it is necessary to reduce the FD capacitance and increase the Source-Follower Gain (SF Gain). However, SF-Gain is generally about 0.8 to 0.9, and a significant improvement is not expected. On the other hand, a significant reduction in the FD capacitance can be expected with a structural approach. The FD capacitance is mainly composed of the sum of the FD diffusion layer capacitance in the floating diffusion region FD, the amplifier gate capacitance in the amplifying transistor AMP, and the FD wiring capacitance in the wiring connected to the floating diffusion region FD. The reduction of the FD diffusion layer capacitance can be achieved by reducing the area of ​​the floating diffusion region FD. Although reducing the density or density is effective, there are concerns about the occurrence of FD white spots and the deterioration of FD dark current. Reducing the gate electrode size of the amplifying transistor AMP and increasing the thickness of the gate insulating film 46 are effective in reducing the amplifier gate capacitance, but there are concerns about the deterioration of random noise (RN). However, reducing the FD wiring capacitance does not cause concerns about the deterioration of pixel characteristics, and high conversion efficiency can be achieved. Therefore, to further improve conversion efficiency, reducing the FD wiring capacitance, as in the eighth embodiment, is effective in reducing the FD capacitance.

[0204] In the eighth embodiment, the wiring capacitance component of the FD capacitance can be almost eliminated, and further, the coupling of signals via other wiring can be reduced, and fixed pattern noise (FPN) can also be suppressed.

[0205] Modification of Eighth Embodiment Next, a modification of the eighth embodiment will be described. Modification 8-1 Fig. 36 is a longitudinal cross-sectional view of a main part that schematically illustrates a modification 8-1 according to the eighth embodiment of the present technology. In the above-described eighth embodiment, the impurity concentration of the gate electrode 75a of the amplification transistor AMP is set to 1 / 200 . １ side and the other photoelectric conversion region 22X ２ Although the case where the impurity concentration distributions are substantially the same on both sides has been described, the present technology is not limited to the above-described eighth embodiment.

[0206] For example, the gate electrode 75a is １ The impurity concentration of the other photoelectric conversion region 22X ２ The impurity concentration distribution may be such that the impurity concentration on the side is lower than that on the side of the impurity.

[0207] In this case, as shown in FIG. 36, the gate electrode 75a is connected to one of the photoelectric conversion regions 22X １ The first portion 75X located on the side １ and the other photoelectric conversion region 22X ２ The first portion 75X is located on the side of the １ The second portion 75X has a lower impurity concentration than ２ The first portion 75X has １ and the second part 75X ２ A boundary 75Z between the first portion 75X and the inter-pixel isolation region 31 overlaps with the inter-pixel isolation region 31 in a plan view. １ is the head portion 75a of the gate electrode 75a １ One of the photoelectric conversion regions 22X １ The second portion 75X includes the side. ２ is the head portion 75a of the gate electrode 75a １ The other photoelectric conversion region 22X ２ side and the relay connection portion 75a ３ That is, the gate electrode 75a of this modification 8-1 includes the relay connection portion 75a ３ The impurity concentration of one photoelectric conversion region 22X １ The impurity concentration is lower than that on the other side.

[0208] In the case of this modification 8-1, the channel forming portion side (the portion on one photoelectric conversion region 22 side) of the gate electrode 75a is made low resistance, and the relay connecting portion 75a ３ This can suppress the diffusion of impurities from the gate electrode to the floating diffusion region FD, thereby reducing the FD diffusion layer capacitance.

[0209] 37 is a longitudinal cross-sectional view of a main portion schematically illustrating a modification 8-2 according to the eighth embodiment of the present technology. In the above-described eighth embodiment, the inter-pixel isolation region 31 has been described as including an engraved portion 33 that is provided in the semiconductor layer 21 and extends in the thickness direction (Z direction) of the semiconductor layer 21, and an isolation insulating film 34 that is provided in the engraved portion 33 of the semiconductor layer 21 so as to bury the engraved portion 33, as shown in FIGS.

[0210] 37, the inter-pixel isolation region 31 of this modification 8-2 includes a recessed portion 33 provided in the semiconductor layer 21 and extending in the thickness direction (Z direction) of the semiconductor layer 21, an isolation insulating film 34 provided in the recessed portion 33 of the semiconductor layer 21 along the inner wall of the recessed portion 33, and a conductor 35 provided in the recessed portion 33 of the semiconductor layer 21 via the isolation insulating film 34. Although not shown, the conductor 35 is electrically connected to a wiring to which a reference potential is applied. That is, the inter-pixel isolation region 31 of this modification 8-2 includes the conductor 35 to which a reference potential is applied. For example, a negative bias potential is applied as the reference potential.

[0211] 37 , the gate electrode 75a of the amplifier transistor AMP overlaps, in plan view, the conductor 35 of the inter-pixel isolation region 31. The conductor 35 of the inter-pixel isolation region 31 extends along the thickness direction (Z direction) of the semiconductor layer 21, and one end thereof located on the first surface portion S1 side of the semiconductor layer 21 faces (is adjacent to) the gate electrode 75a of the amplifier transistor AMP via the isolation insulating film 34.

[0212] If the parasitic capacitance of the floating diffusion region FD is too small, the FD potential will fluctuate due to coupling from other signal lines, which will likely lead to a deterioration in RN (on-resistance). Therefore, by applying a constant potential to the conductor 35 of the inter-pixel isolation region 31 and stabilizing the potential of the capacitively coupled floating diffusion region FD, it is possible to reduce or eliminate the potential fluctuation due to coupling with other signal lines, thereby achieving low noise. Therefore, in this modification 8-2, the same effects as those of the eighth embodiment described above can be obtained, and low noise can also be achieved.

[0213] <Modification 8-3> FIG. 38 is a longitudinal cross-sectional view of a main part that schematically illustrates Modification 8-3 according to the eighth embodiment of the present technology.

[0214] In the above-described eighth embodiment, the head portion 75a is used as the gate electrode of the amplification transistor AMP. １ and relay connection section 75a ３ However, the present technology is not limited to the gate electrode 75a of the above-described eighth embodiment.

[0215] For example, as shown in FIG. 38, the gate electrode 75a has a head 75a １ and relay connection section 75a ３ and further includes a head 75a １ one photoelectric conversion region 22X １ Legs 75a protruding to the side ２ The leg portion 75a may be configured to include the following. ２ is one of the photoelectric conversion regions 22X １ In the element forming region 43, the head 75a １ 38, one leg portion 75a protrudes from the gate insulating film 46 into the semiconductor layer 21 and is adjacent to the channel forming portion 53a of the semiconductor layer 21 with the gate insulating film 46 interposed therebetween. ２ is shown as an example, but the leg 75a ２ Two or more may be provided.

[0216] By using the amplification transistor AMP of this modification 8-3, flicker noise and thermal noise can be reduced, and a low on-resistance can be achieved.

[0217] <Modification 8-4> FIG. 39 is a longitudinal cross-sectional view of a main part that schematically illustrates Modification 8-4 according to the eighth embodiment of the present technology.

[0218] In the above-described eighth embodiment, one of the photoelectric conversion regions 22X １ The gate electrode 75a of the amplifier transistor AMP provided in the other photoelectric conversion region 22X ２ The other photoelectric conversion region 22X in the first side surface portion 22b ２In the eighth embodiment, the semiconductor device is electrically and mechanically connected to the floating diffusion region FD. However, the present technology is not limited to the above-described eighth embodiment.

[0219] For example, as shown in FIG. 39, one photoelectric conversion region 22X １ The gate electrode 75a of the amplifier transistor AMP provided in the other photoelectric conversion region 22X ２ The other photoelectric conversion region 22X is located on the top surface portion 22a and the first side surface portion 22b. ２ The floating diffusion region FD may be electrically and mechanically connected to the floating diffusion region FD.

[0220] In the case of this modification 8-4, the contact area between the gate electrode 75a and the floating diffusion region FD can be increased, thereby achieving a lower resistance.

[0221] <Modification 8-5> Fig. 40 is a longitudinal cross-sectional view of a main part schematically illustrating Modification 8-5 according to the eighth embodiment of the present technology. This modification is a combination of the impurity concentration distribution technique of Modification 8-1 shown in Fig. 36 and the parasitic capacitance addition technique of Modification 8-2 shown in Fig. 37. Modification 8-5 can obtain the effects of each of Modifications 8-1 and 8-2 described above.

[0222] <Modification 8-6> Fig. 41 is a longitudinal cross-sectional view schematically illustrating a main portion of Modification 8-6 according to the eighth embodiment of the present disclosure. This modification is a combination of the impurity concentration distribution technique of Modification 8-1 shown in Fig. 36 and the channel width expansion technique of Modification 8-3 shown in Fig. 38. Modification 8-6 can obtain the effects of both Modification 8-1 and Modification 8-3.

[0223] <Modification 8-7> Fig. 42 is a longitudinal cross-sectional view schematically illustrating a main portion of Modification 8-7 according to the eighth embodiment of the present disclosure. Modification 8-7 is a combination of the impurity concentration distribution technique of Modification 8-1 shown in Fig. 36 and the floating diffusion region connection technique of Modification 8-4 shown in Fig. 39. Modification 8-7 can obtain the effects of both Modification 8-1 and Modification 8-4.

[0224] <Other Modifications> Although not shown, the parasitic capacitance addition technique of modification 8-2 shown in FIG. 37 can be combined with the channel width expansion technique of modification 8-3 shown in FIG. 38 or the floating diffusion region connection technique of modification 8-4 shown in FIG. 39.

[0225] Although not shown, the channel width widening technique of Modification 8-3 shown in FIG. 38 can be combined with the floating diffusion region connection technique of Modification 8-4 shown in FIG.

[0226] [Ninth Embodiment] Next, a solid-state imaging device 1I according to a ninth embodiment of the present technology will be described with reference to Fig. 43 and Fig. 44. Fig. 43 is a plan view schematically showing a configuration example of two pixel blocks in a solid-state imaging device according to the ninth embodiment of the present technology. Fig. 44 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a43-a43 cutting line in Fig. 43.

[0227] A solid-state imaging device 1I according to a ninth embodiment of the present technology includes a pixel block 15I shown in Fig. 43. The pixel block 15I of the ninth embodiment mainly includes two pixels 3 (3a １ , 3b １ ) as a unit.

[0228] Two pixels 3 (3a) included in one pixel block 15I １ , 3b １ ) are photoelectric conversion regions 22 (22X) partitioned by inter-pixel isolation regions 31. ３ , 22X ４ ) in the photoelectric conversion region 22 (22X ３ , 22X ４ ) has basically the same configuration as the photoelectric conversion region 22 of the eighth embodiment described above, but differs in the following configuration.

[0229] That is, the photoelectric conversion region 22 (22X) of this ninth embodiment ３ , 22X ４ ) is different from the photoelectric conversion region 22 of the eighth embodiment in the transistor layout and the planar shape of the element formation region 43.３ , 22X ４ ) in one photoelectric conversion region 22X ３ The plane pattern of the element forming region 43 in the other photoelectric conversion region 22X ４ The plane pattern of the element formation region 43 in the pixel 3a is aligned in the Y direction. １ and pixel 3b １ It is inverted around the boundary between

[0230] In addition, the photoelectric conversion region 22 (22X ３ , 22X ４ ), the element formation region 43 is provided with an amplification transistor AMP, a selection transistor SEL, and a switching transistor FDG as pixel transistors, but the switching transistor FCG shown in Fig. 34 of the above-mentioned eighth embodiment is not provided. In this ninth embodiment, the configuration of the amplification transistor AMP is slightly different from that of the above-mentioned eighth embodiment.

[0231] Specifically, the amplification transistor AMP of the ninth embodiment is configured to amplify two photoelectric conversion regions 22 (22X) included in one pixel block 15I. ３ , 22X ４ ) in one pixel block 15I. １ , 3b １ ) is shared.

[0232] As shown in FIG. 44, the amplification transistor AMP of the ninth embodiment has two photoelectric conversion regions 22 (22X ３ , 22X ４ ) in one photoelectric conversion region 22X ３ The first side surface portion 22b has one photoelectric conversion region 22X ３ and the other photoelectric conversion region 22X. ４ The other photoelectric conversion region 22X ４That is, the gate electrode 75a of the amplification transistor AMP of the ninth embodiment has a head portion 75a extending outside the first surface portion S1 of the semiconductor layer 21 across the photoelectric conversion region 22 and the inter-pixel isolation region 31. １ And this head 75a １ into the inter-pixel isolation region 31 and are adjacent to each other with the inter-pixel isolation region 31 interposed therebetween in a plan view. ３ , 22X ４ ) and a relay connection portion 75a electrically and mechanically connected to the first side surface portion 22b of each of the first side surface portions 22a and the second side surface portion 22b. ３ and,

[0233] The solid-state imaging device 1I according to the ninth embodiment also provides the same effects as those of the solid-state imaging device 1H according to the eighth embodiment.

[0234] Tenth Embodiment Next, a solid-state imaging device 1I according to a tenth embodiment of the present technology will be described with reference to Fig. 45 and Fig. 46. Fig. 45 is a plan view schematically showing a configuration example of two pixel blocks in a solid-state imaging device according to the tenth embodiment of the present technology. Fig. 46 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a45-a45 cutting line in Fig. 45.

[0235] A solid-state imaging device 1J according to a tenth embodiment of the present technology includes a pixel block 15J shown in Fig. 45. The pixel block 15J of the tenth embodiment mainly includes two pixels 3 (3a ２ , 3b ２ ) as a unit.

[0236] Two pixels 3 (3a) included in one pixel block 15J ２ , 3b ２ ) are photoelectric conversion regions 22 (22X) partitioned by inter-pixel isolation regions 31. ５ , 22X ６ ) in the photoelectric conversion region 22 (22X ５ , 22X ６ ) has basically the same configuration as the photoelectric conversion region 22 of the eighth embodiment described above, but differs in the following configuration.

[0237] That is, the photoelectric conversion region 22 (22X) of this tenth embodiment ５ , 22X ６ ) is different from the photoelectric conversion region 22 of the eighth embodiment in the transistor layout and the planar shape of the element formation region 43. ５ , 22X ６ ) in one photoelectric conversion region 22X ５ The plane pattern of the element forming region 43 in the other photoelectric conversion region 22X ６ The plane pattern of the element formation region 43 in the pixel 3a is aligned in the Y direction. ２ and pixel 3b ２ It is inverted around the boundary between

[0238] In addition, the photoelectric conversion region 22 (22X ５ , 22X ６ ), the element formation region 43 is provided with an amplification transistor AMP, a selection transistor SEL, and a switching transistor FDG as pixel transistors, but the switching transistor FCG shown in Fig. 34 of the above-mentioned eighth embodiment is not provided. In this tenth embodiment, the configuration of the amplification transistor AMP is slightly different from that of the above-mentioned eighth embodiment.

[0239] Specifically, the amplification transistor AMP of the tenth embodiment is configured to amplify two photoelectric conversion regions 22 (22X) included in one pixel block 15J. ５ , 22X ６ ) in one pixel block 15J. ２ , 3b ２ ) is shared.

[0240] As shown in FIG. 46, the amplifying transistor AMP of the tenth embodiment has two photoelectric conversion regions 22 (22X ５ , 22X ６ ) in one photoelectric conversion region 22X ５ The upper surface portion 22a and the first side surface portion 22b of one photoelectric conversion region 22X５ and the other photoelectric conversion region 22X. ６ The other photoelectric conversion region 22X is located on the top surface portion 22a of the first side surface portion 22b. ６ That is, the gate electrode 75a of the amplification transistor AMP of the tenth embodiment has a head portion 75a extending outside the first surface portion S1 of the semiconductor layer 21 across the photoelectric conversion region 22 and the inter-pixel isolation region 31. １ And this head 75a １ into the inter-pixel isolation region 31 and are adjacent to each other with the inter-pixel isolation region 31 interposed therebetween in a plan view. ５ , 22X ６ ) and the upper surface portion 22a and the first side surface portion 22b of each of the relay connection portions 75a. ３ and,

[0241] The solid-state imaging device 1J according to the tenth embodiment also provides the same effects as the solid-state imaging device 1H according to the eighth embodiment, and can achieve low resistance as in the above-described modification 8-4.

[0242] Eleventh Embodiment Example of Application to Electronic Devices The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0243] FIG. 47 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a fourth embodiment of the present technology.

[0244] 47 , the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 illustrates an embodiment in which the solid-state imaging device 1A according to the first embodiment of the present technology is used as the solid-state imaging device 101 in an electronic device (for example, a camera).

[0245] The optical lens 102 focuses image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 cause charge transfer in the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0246] With this configuration, the mutual conductance (gm) of the transfer transistor TR is improved in the solid-state imaging device 101, and therefore the image quality performance of the electronic device 100 of the eleventh embodiment can be improved.

[0247] The electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0248] Furthermore, the present technology can be applied to not only the solid-state imaging device as the image sensor described above, but also to photodetection devices in general, including distance measurement sensors called ToF (Time of Flight) sensors that measure distance. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The pixel transistor described above can also be used in this distance measurement sensor.

[0249] The present technology may be configured as follows: (1) A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located on opposite sides in a thickness direction; and a photoelectric conversion region provided in the semiconductor layer and partitioned by an isolation region extending in the thickness direction of the semiconductor layer, wherein the photoelectric conversion region comprises: an upper surface portion located on the first surface portion side of the semiconductor layer and a first side surface portion located on the isolation region side; a transfer transistor provided on the upper surface portion side and transferring signal charges photoelectrically converted in the photoelectric conversion portion to a charge storage portion; and a plurality of pixel transistors provided on the upper surface portion side, wherein at least one pixel transistor of the plurality of pixel transistors has a gate electrode provided in the isolation region adjacent to the first side surface portion of the photoelectric conversion region with a gate insulating film interposed therebetween. (2) The photodetector according to (1), wherein at least one pixel transistor of the plurality of pixel transistors further comprises a pair of main electrode regions provided on the upper surface portion side of the photoelectric conversion region and spaced apart from each other in a gate length direction of the gate electrode in a plan view. (3) The photodetector according to (1) or (2), wherein the gate electrode is selectively provided in the isolation region. (4) The photodetector according to any one of (1) to (3), wherein the gate electrode is provided across the top surface portion and side surface portion of the photoelectric conversion region with the gate insulating film interposed therebetween. (5) The photodetector according to (4), wherein the gate electrode includes: a head portion extending across the photoelectric conversion region and the isolation region outside the first surface portion of the semiconductor layer in a planar view; and a leg portion protruding from the head portion toward the isolation region and adjacent to the first side surface portion of the photoelectric conversion region with the gate insulating film interposed therebetween. (6) The photodetector device described in (1) above, wherein the photoelectric conversion region further has an inter-element isolation region provided on the top surface portion side and a second side portion located opposite the first side portion in a planar view and adjacent to the inter-element isolation region, and the gate electrode is provided across each of the top surface portion, the first side portion, and the second side portion with the gate insulating film interposed therebetween.(7) The photodetector according to (6), wherein the gate electrode includes: a head portion extending across the isolation region and the inter-element isolation region outside the first surface portion of the semiconductor layer in a planar view, a first leg portion protruding from the head portion toward the isolation region and adjacent to the first side surface portion of the photoelectric conversion region with the gate insulating film interposed therebetween, and a second leg portion protruding from the head portion toward the inter-element isolation region and adjacent to the second side surface portion of the photoelectric conversion region with the gate insulating film interposed therebetween. (8) The photodetector according to (6), wherein at least one of the pixel transistors has a channel formation portion between the first side surface portion and the second side surface portion of the photoelectric conversion region. (9) The photodetector according to (1), wherein the isolation region includes a first vertical portion provided on the first surface portion side of the semiconductor layer and a second vertical portion extending from the first vertical portion toward the second surface portion side of the semiconductor layer and having a width narrower than that of the first vertical portion, and the gate electrode is entirely provided on the first vertical portion. (10) The photodetector according to (1), wherein the isolation region includes a first vertical portion provided on the first surface portion side of the semiconductor layer and a second vertical portion extending from the first vertical portion toward the second surface portion side of the semiconductor layer and having a width narrower than that of the first vertical portion, and the gate electrode is partially provided on the first vertical portion. (11) The photodetector according to (1), wherein the gate electrodes are adjacent to the first side surface portions of two of the photoelectric conversion regions adjacent to each other in a planar view, with the gate insulating film interposed therebetween. (12) The photodetector according to (2), wherein one of the pair of main electrode regions also serves as the charge storage portion. (13) The photodetector according to (1), wherein in two of the photoelectric conversion regions adjacent to each other in a plan view with the isolation region interposed therebetween, the gate electrode is adjacent to the first side surface portion of one of the photoelectric conversion regions with the gate insulating film interposed therebetween and is connected to the charge storage portion of the other of the photoelectric conversion regions so as to be adjacent to each other.(14) The photodetector device according to (1), further comprising a relay conductor provided in the separation region between two of the photoelectric conversion regions adjacent to each other in a planar view, wherein the relay conductor is connected to a semiconductor region provided in each of the two photoelectric conversion regions at the first side portion of each of the two photoelectric conversion regions adjacent to each other in a planar view. (15) A photodetector comprising: a semiconductor layer; and photoelectric conversion regions provided in the semiconductor layer and partitioned by separation regions extending in a thickness direction of the semiconductor layer, wherein the photoelectric conversion regions comprise: an upper surface portion and a side surface portion; a charge holding portion provided on the upper surface portion side and holding signal charges transferred from the photoelectric conversion portion via a transfer transistor; and a pixel transistor provided on the upper surface portion side, wherein in two photoelectric conversion regions adjacent to each other via the separation region in a planar view, the pixel transistor provided in one of the photoelectric conversion regions has a gate electrode that is provided across the upper surface portion and the separation region of one of the photoelectric conversion regions in a planar view, and is connected to the charge holding portion of the other photoelectric conversion region at the side surface portion of the other photoelectric conversion region. (16) The photodetector according to (15), wherein the gate electrode includes a head portion provided across one of the photoelectric conversion regions and the separation region, and a relay connection portion protruding from the head portion toward the separation region and connected to the charge retention portion at the side surface portion of the other of the photoelectric conversion regions. (17) The photodetector according to (15) or (16), wherein the gate electrode has a lower impurity concentration on the other of the photoelectric conversion regions than on one of the photoelectric conversion regions. (18) The photodetector according to any of (15) to (17), wherein the gate electrode has a first portion located on the one of the photoelectric conversion regions and a second portion located on the other of the photoelectric conversion regions and having a lower impurity concentration than the first portion, and wherein a boundary portion between the first portion and the second portion overlaps the separation region in a planar view. (19) The photodetector according to any one of (16) to (18), wherein the gate electrode further includes a leg portion protruding from the head portion toward one of the photoelectric conversion regions.(20) The photodetector according to any one of (15) to (19), wherein the gate electrode is connected to the charge storage portion across the top surface portion and the side surface portion of the other of the photoelectric conversion regions. (21) The photodetector according to any one of (15) to (20), wherein the isolation region includes a conductor to which a potential is applied. (22) An electronic device comprising: a photodetector; an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that performs signal processing on a signal output from the photodetector, wherein the photodetector comprises: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in a thickness direction; a photoelectric conversion region that is provided in the semiconductor layer and partitioned by an isolation region extending in the thickness direction of the semiconductor layer, and has an upper surface portion located on the first surface portion side of the semiconductor layer and a first side surface portion located on the isolation region side; a transfer transistor that is provided on the upper surface portion side of the photoelectric conversion region and transfers signal charges photoelectrically converted in the photoelectric conversion region to a charge holding portion; and a plurality of pixel transistors that are provided on the upper surface portion of the photoelectric conversion region, wherein at least one pixel transistor of the plurality of pixel transistors has a gate electrode that is provided in the isolation region and adjacent to the first side surface portion of the photoelectric conversion region via a gate insulating film.

[0250] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0251] 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J... solid-state imaging device 2... semiconductor chip 2A... pixel array section 2B... peripheral section 3, 3a, 3a １ , 3a ２ , 3b, 3b １ , 3b ２Pixel 4: Vertical drive circuit 5: Column signal processing circuit 6: Horizontal drive circuit 7: Output circuit 8: Control circuit 10: Pixel drive line 11: Vertical signal line 12: Horizontal signal line 13: Logic circuit 14: Bonding pad 15, 15, 15I, 15J: Pixel block, 15H 16, 16G, 16H: Pixel circuit (readout circuit) 21: Semiconductor layer 22: Photoelectric conversion region 22a: Upper surface portion 22b: First side surface portion 22c: Second side surface portion 23: P-type semiconductor region 24: N-type semiconductor region 25: Photoelectric conversion section 31, 31B: Inter-pixel isolation region (isolation region) 31b １ ...First vertical portion 31b ２ ...second vertical portion 31bz...step portion 31x...first plane portion 31y...second plane portion 31z1...first vertical portion 31z2...second vertical portion 33...grooved portion 34...isolation insulating film 35...conductor 41...inter-element isolation region (field isolation region) 42a...shallow trench portion 42b...isolation insulating film 43...element formation region (active region) 45a, 45b...grooved portion 46...gate insulating film 47...gate electrode film 47a, 47r, 47s, 47t...gate electrode 47t １ …Head 47t ２ ...leg portion 51...dug portion 52as, 52as, 52r, 52s...main electrode region 53r, 53s...channel forming portion 55...multilayer wiring layer 56...interlayer insulating film 57...first wiring layer 57a, 57f, 57r, 57s, 57t...contact electrodes 58a, 58r, 58s, 58t...wiring 61...planarization film 63...optical filter 64...microlens 71r...gate electrode, 71r １ ...Head, 71r ２ Leg 71s...gate electrode, 71s １ …Head, 71s ２ ... Leg 72r... Gate electrode, 72r １ ...Head, 72r ２ ...first leg, 72r ３ ... Second leg 72s... Gate electrode, 72s １ ...Head, 72s ２ ...First leg, 72s ３ ... Second leg portion 73a... Gate electrode, 73a１ ...Head, 73a ２ ...leg portions 74a, 74b...relay conductor portion 75a...gate electrode, 75a １ ...Head, 75a ３ ... relay connection section 100... electronic device 101... solid-state imaging device 102... optical lens (optical system) 103... shutter device 104... drive circuit 105... signal processing circuit AMP... amplification transistor FD... n-type floating diffusion region FCG, FDG... switching transistor Q... pixel transistor RST... reset transistor SEL... selection transistor S1... first surface portion S2... second surface portion TR... transfer transistor WC... power supply contact region

Claims

1. A photodetection device comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in a thickness direction; and a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in the thickness direction of the semiconductor layer, wherein the photoelectric conversion region comprises: an upper surface portion located on the first surface portion side of the semiconductor layer and a first side portion located on the separation region side; a transfer transistor provided on the upper surface portion side and transferring signal charges photoelectrically converted in the photoelectric conversion portion to a charge holding portion; and a plurality of pixel transistors provided on the upper surface portion side, wherein at least one pixel transistor of the plurality of pixel transistors has a gate electrode provided in the separation region adjacent to the first side portion of the photoelectric conversion region with a gate insulating film interposed therebetween.

2. The photodetection device according to claim 1, wherein at least one of the plurality of pixel transistors further has a pair of main electrode regions spaced apart from each other in a gate length direction of the gate electrode in a plan view and provided on the upper surface side of the photoelectric conversion region.

3. The photodetector according to claim 1, wherein said gate electrode is selectively provided in said isolation region.

4. The photodetector according to claim 1, wherein the gate electrode is provided across the top and side surfaces of the photoelectric conversion region with the gate insulating film interposed therebetween.

5. The photodetector device described in claim 4, wherein the gate electrode includes: a head extending across the photoelectric conversion region and the isolation region in a planar view outside the first surface portion of the semiconductor layer; and a leg protruding from the head toward the isolation region and adjacent to the first side portion of the photoelectric conversion region with the gate insulating film interposed therebetween.

6. The photodetection device described in claim 1, wherein the photoelectric conversion region further has an inter-element isolation region provided on the top surface portion side, and a second side portion located opposite the first side portion in a planar view and adjacent to the inter-element isolation region, and the gate electrode is provided across each of the top surface portion, the first side portion and the second side portion with the gate insulating film interposed therebetween.

7. The photodetector device of claim 6, wherein the gate electrode includes: a head extending across the isolation region and the inter-element isolation region in a planar view outside the first surface portion of the semiconductor layer; a first leg protruding from the head toward the isolation region and adjacent to the first side portion of the photoelectric conversion region with the gate insulating film interposed; and a second leg protruding from the head toward the inter-element isolation region and adjacent to the second side portion of the photoelectric conversion region with the gate insulating film interposed.

8. The photodetection device according to claim 6, wherein at least one of the plurality of pixel transistors has a channel forming portion between the first side portion and the second side portion of the photoelectric conversion region.

9. The photodetector device of claim 1, wherein the isolation region includes a first vertical portion provided on the first surface side of the semiconductor layer, and a second vertical portion extending from the first vertical portion toward the second surface side of the semiconductor layer and having a width narrower than that of the first vertical portion, and the gate electrode is entirely provided on the first vertical portion.

10. The photodetector device of claim 1, wherein the isolation region includes a first vertical portion provided on the first surface side of the semiconductor layer, and a second vertical portion extending from the first vertical portion toward the second surface side of the semiconductor layer and having a width narrower than that of the first vertical portion, and a portion of the gate electrode is provided in the first vertical portion.

11. The photodetector according to claim 1, wherein the gate electrodes are adjacent to each other with the gate insulating film interposed between the first side portions of each of the two photoelectric conversion regions adjacent to each other in a planar view.

12. The photodetector according to claim 2, wherein one of the pair of main electrode regions also serves as the charge retaining portion.

13. The photodetection device described in claim 1, wherein in two of the photoelectric conversion regions adjacent to each other in a planar view with the isolation region interposed therebetween, the gate electrode is adjacent to the first side portion of one of the photoelectric conversion regions with the gate insulating film interposed therebetween, and is connected adjacent to the charge retention portion of the other of the photoelectric conversion regions.

14. The photodetection device of claim 1, further comprising a relay conductor portion provided in the separation region between two of the photoelectric conversion regions adjacent to each other in a planar view, the relay conductor portion being connected to a semiconductor region provided in each of the two photoelectric conversion regions at the first side portion of each of the two photoelectric conversion regions adjacent to each other in a planar view.

15. A photodetection device comprising: a semiconductor layer; and a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in a thickness direction of the semiconductor layer, wherein the photoelectric conversion region comprises: a top surface portion and a side surface portion; a charge holding portion provided on the top surface portion side and holding signal charges transferred from the photoelectric conversion portion via a transfer transistor; and a pixel transistor provided on the top surface portion side, wherein two photoelectric conversion regions are adjacent to each other via the separation region in a planar view, and the pixel transistor provided in one of the photoelectric conversion regions has a gate electrode that is provided across the top surface portion and the separation region of one of the photoelectric conversion regions in a planar view, and is connected to the charge holding portion of the other photoelectric conversion region at the side portion of the other photoelectric conversion region.

16. The photodetection device described in claim 15, wherein the gate electrode includes a head portion provided across one of the photoelectric conversion regions and the isolation region, and a relay connection portion protruding from the head portion toward the isolation region and connected to the charge holding portion at the side portion of the other photoelectric conversion region.

17. The photodetector according to claim 15, wherein the gate electrode has a lower impurity concentration on one of the photoelectric conversion regions than on the other of the photoelectric conversion regions.

18. The photodetector device described in claim 15, wherein the gate electrode has a first portion located on one of the photoelectric conversion regions and a second portion located on the other of the photoelectric conversion regions and having a lower impurity concentration than the first portion, and a boundary between the first portion and the second portion overlaps the isolation region in a planar view.

19. The photodetector according to claim 16, wherein the gate electrode further includes a leg portion protruding from the head portion toward one of the photoelectric conversion regions.

20. The photodetector according to claim 15, wherein the gate electrode is connected to the charge retaining portion across the top surface and the side surface of the other of the photoelectric conversion regions.

21. The optical detection device of claim 15, wherein the isolation region comprises a conductor to which an electrical potential can be applied.

22. An electronic device comprising: a photodetection device; an optical lens that focuses image light from a subject on an imaging surface of the photodetection device; and a signal processing circuit that performs signal processing on a signal output from the photodetection device, wherein the photodetection device comprises: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in a thickness direction; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in the thickness direction of the semiconductor layer, the photoelectric conversion region having an upper surface portion located on the first surface portion side of the semiconductor layer and a first side portion located on the separation region side; a transfer transistor provided on the upper surface side of the photoelectric conversion region and transferring signal charges photoelectrically converted in the photoelectric conversion portion to a charge holding portion; and a plurality of pixel transistors provided on the upper surface portion of the photoelectric conversion region, wherein at least one pixel transistor of the plurality of pixel transistors has a gate electrode provided in the separation region adjacent to the first side portion of the photoelectric conversion region via a gate insulating film.

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