Method for low-temperature solid-phase connection of chip under air condition

Abstract

Provided in the present invention is a method for the low-temperature solid-phase connection of a chip under air conditions. The method comprises the following steps: step S1, cleaning and drying the surfaces of a chip and a substrate; step S2, depositing a nano metal layer on the back surface of the chip, and depositing a nano metal layer on the substrate, wherein the nano metal layer is a nano Ag coating layer or a nano Au coating layer; step S3, placing the chip on the substrate, such that the nano metal layer of the chip is opposite to the nano metal layer of the substrate, thereby forming a packaging structure which sequentially comprises the chip, the nano metal layer on the chip, the nano metal layer on the substrate, and the substrate from top to bottom; and step S4, placing the assembled packaging structure in a hot-pressing diffusion welding device to perform hot-pressing heat preservation in an air atmosphere, and cooling same to room temperature to finish interconnection, wherein the hot-pressing temperature does not exceed 300°C. The joint interconnection interface obtained by using the technical solution of the present invention is well bonded, the connection layer is dense without any pore defects, the thermal conductivity is good, and the strength is high.

Description

A method for realizing low-temperature solid-phase connection of chips under air conditions Technical Field

[0001] The present invention relates to the technical field of chip connection, and in particular to a method for realizing low-temperature solid-phase connection of chips under air conditions. Background Art

[0002] As packaging technology evolves towards miniaturization, high-density integration, and high reliability, the demanding service environments of high currents, high temperatures, and thermal stress within packaging structures are placing higher demands on packaging technology and materials. Currently, transient liquid phase processes based on lead-free tin-based solders and silver nanoparticle sintering are the primary interconnect technologies for chip-to-substrate interconnection within packaging structures. This mainstream transient liquid phase connection technology utilizes lead-free solders such as AuSn and CuSn, held at temperatures above the solder's melting point for a long period of time to allow interdiffusion between low-melting-point and high-melting-point elements in the connection layer to form intermetallic compounds, enabling low-temperature interconnection and high-temperature service. However, this interconnection technology requires a long holding time to achieve a fully compound joint and presents reliability issues such as the generation of thermal stress, difficulty controlling intermetallic compounds, and void initiation. Furthermore, chip interconnection technologies based on silver nanoparticle sintering suffer from the inevitable presence of pores in the sintering layer and the difficulty in evaporating the organic coating, which compromises the thermal conductivity and strength of the joint. Therefore, in the face of the high reliability requirements of chip packaging structures, it is of great significance to develop a chip packaging method that can achieve low-temperature interconnection, high-temperature service, high reliability, and high strength and high thermal conductivity of the joints.

[0003] Summary of the Invention

[0004] In response to the above technical problems, the present invention discloses a method for realizing low-temperature solid-phase connection of chips under air conditions, realizing low-temperature interconnection and high-temperature service, with good interconnection interface bonding without defects, dense interconnection layer without gaps, and excellent thermal conductivity.

[0005] To this end, the technical solution adopted in the present invention is:

[0006] A method for achieving low-temperature solid-phase bonding of chips under air conditions comprises the following steps:

[0007] Step S1, cleaning and drying the surface of the chip and substrate;

[0008] Step S2, depositing a nano-metal layer on the back of the chip; depositing a nano-metal layer on the substrate, wherein the nano-metal layer is a nano-Ag coating or a nano-Au coating;

[0009] Step S3, placing the chip on the substrate, and making the nano-metal layer of the chip face the nano-metal layer of the substrate, to form a packaging structure that is, from top to bottom, the chip, the nano-metal layer on the chip, the nano-metal layer on the substrate, and the substrate;

[0010] Step S4: placing the assembled package structure into a hot pressing diffusion bonding device, hot pressing and keeping warm in an air atmosphere, and then cooling to room temperature to complete the interconnection, wherein the hot pressing temperature does not exceed 300 degrees.

[0011] This technical solution utilizes the high activity and high diffusion rate of the nanometal layer at low temperatures, and uses the nanometal layer deposited on the back of the chip and the surface of the substrate as the interconnection transition layer. It can achieve low-temperature solid interconnection between the chip and the substrate under air conditions, and the interconnection interface is well bonded and defect-free.

[0012] As a further improvement of the present invention, step S1 includes placing the chip and substrate into a vacuum plasma cleaning machine to remove surface impurities, organic matter and other pollutants to improve the cleanliness of the surface to be deposited.

[0013] As a further improvement of the present invention, in step S2, the nano-metal layer is deposited by magnetron sputtering or ion plating technology.

[0014] As a further improvement of the present invention, in step S3, the nanometal layer is deposited by magnetron sputtering, with a magnetron sputtering power of 100-200 W, a gas pressure of 0.1-5 Pa, and an argon gas flow rate of 10-40 sccm.

[0015] As a further improvement of the present invention, the thickness of the nanometal layer is 0.1-10 μm, and the average grain diameter of the nanometal is 10-100 nm.

[0016] As a further improvement of the present invention, the thickness of the nano-metal layer on the substrate is greater than the thickness of the nano-metal layer on the chip.

[0017] As a further improvement of the present invention, in step S4, the pressure is 1-10 MPa, the temperature is 180-300° C., and the holding time is 5-30 min.

[0018] As a further improvement of the present invention, in step S4, the heating rate is 5-15°C / min.

[0019] As a further improvement of the present invention, the chip is a semiconductor chip of Si or SiC with Ni / Au or Ni / Ag plated on the back.

[0020] As a further improvement of the present invention, the surface roughness Ra of the nano-metal film deposited on the chip and substrate is less than 50 nm.

[0021] As a further improvement of the present invention, the substrate is a metal substrate, a ceramic substrate with a metal coating, or a lead frame.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The technical solution of the present invention utilizes a dense nanometal layer as the interconnection layer. The interconnection interface is well bonded, and the connection layer is dense and free of pore defects, resulting in a highly thermally conductive and high-strength interconnection structure. This avoids the problems of high porosity and residual organic coatings found in nanosilver particle sintering technology. Furthermore, the method provided by the invention enables short-term solid-state interconnection in air, avoiding the long heat preservation time and poor reliability associated with traditional tin-based solder interconnection processes. Furthermore, the deposition process for the nanometal layer is compatible with CMOS processes, eliminating the need for redundant process flows. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a schematic diagram of the low-temperature solid-phase connection method for a chip provided by the present invention.

[0025] FIG2 is a scanning electron microscope (SEM) image of the cross section of the joint obtained in Example 1 of the present invention.

[0026] FIG3 is an electron backscattered diffraction-inverse pole figure (EBSD-IPF) of the cross section of the joint obtained in Example 1 of the present invention.

[0027] Reference numerals include:

[0028] 1-chip, 2-nanometallic film deposited on the back of the chip, 3-nanometallic film on the surface of the substrate, 4-substrate. DETAILED DESCRIPTION

[0029] The preferred embodiments of the present invention are described in further detail below.

[0030] A method for achieving low-temperature solid-phase bonding of chips under air conditions, comprising the following steps:

[0031] S1. Place the chip and substrate into a vacuum plasma cleaning machine to remove surface impurities, organic matter and other pollutants to improve the cleanliness of the surface to be deposited;

[0032] S2. Use magnetron sputtering or ion plating technology to deposit a layer of nano-Ag or Au thin film on the back of the plated chip. At the same time, a thick nano-Ag or Au thin film is also deposited on the substrate;

[0033] S3. Place the nano-metal coating layer of the substrate deposited with the nano-metal film upward and on the lower layer, and place the metal film layer of the chip deposited with the nano-metal film downward on the substrate, thereby forming a packaging structure that, from top to bottom, comprises chip 1, nano-metal film 2 deposited on the back of the chip, nano-metal film 3 on the surface of the substrate, and substrate 4, as shown in FIG1 ;

[0034] S4. Place the assembled package structure into a hot pressing diffusion bonding device, apply a certain pressure, heat it to a specified temperature in an air atmosphere, and then keep it warm for a period of time. Finally, stop heating and cool it to room temperature to complete the interconnection.

[0035] The following describes the invention with reference to embodiments.

[0036] Example 1

[0037] A low-temperature solid-phase bonding method for a chip based on a nanosilver film, the implementation steps are as follows:

[0038] S1. Place the chip and substrate in a vacuum plasma cleaning machine and perform argon ion cleaning on the surface of the Ni / Ag plated chip and copper metal substrate before deposition under the conditions of power 100W, vacuum degree 10Pa, and flow rate 100ml / min to remove surface impurities, organic matter and other pollutants to improve the cleanliness of the surface to be deposited;

[0039] S2. Place the Ni / Ag-plated chip and the copper substrate in a magnetron sputtering deposition system with a sputtering power of 200 W, a substrate temperature of 25°C, an argon flow rate of 40 sccm, a sputtering chamber vacuum of 0.5 Pa, and a deposition time of 20 min. A nanosilver film with a thickness of ~3.0 μm is then formed on the back of the chip and the surface of the substrate.

[0040] S3, assembling the connection materials into a packaging structure comprising, from top to bottom, a Ni / Ag-plated chip, a nanosilver film on the chip, a nanosilver film on the substrate, and a copper metal substrate;

[0041] S4. Place the assembled package structure into a hot pressing diffusion bonding device, apply a pressure of 10 MPa, and heat it to 200°C at a heating rate of 10°C / min in an air atmosphere. Keep it warm for 30 minutes, then release the pressure and cool it to room temperature to complete the interconnection.

[0042] The scanning electron microscope image of the cross section of the joint obtained in this embodiment is shown in Figure 1, the backscattered electron diffraction-inverse pole figure of the cross section of the joint obtained is shown in Figure 2, and the backscattered electron diffraction-inverse pole figure (EBSD-IPF) of the cross section of the joint obtained is shown in Figure 3. It can be seen that the interconnection interface is well bonded without defects, and the interconnection layer is dense and has no gaps.

[0043] Example 2

[0044] A low-temperature solid-phase bonding method for chips based on nano-gold film, wherein the bonding materials include a Ni / Au-plated chip, a nano-gold film deposited on the back of the chip, a nano-gold film on the surface of a substrate, and a metal copper substrate. The specific implementation steps are as follows:

[0045] S1. Place the Ni / Au plated chip and the copper metal substrate in a vacuum plasma cleaning machine, and perform argon ion surface cleaning on the surface of the Ni / Au plated chip-1 and the copper metal substrate before deposition under the conditions of power 100W, vacuum degree 10Pa, and flow rate 100ml / min to remove surface impurities, organic matter and other pollutants, thereby improving the cleanliness of the surface to be deposited;

[0046] S2. Place the Ni / Au plated chip and the copper substrate in a magnetron sputtering deposition system with a sputtering power of 100 W, a substrate temperature of 25°C, an argon flow rate of 20 sccm, a sputtering chamber vacuum of 0.5 Pa, and a deposition time of 10 min. A nano-gold film with a thickness of ∼0.5 μm is then formed on the back of the chip and the surface of the substrate.

[0047] S3, assembling the connection materials into a packaging structure comprising, from top to bottom, a Ni / Ag-plated chip, a nanosilver film on the chip, a nanosilver film on the substrate, and a copper metal substrate;

[0048] S4. Place the assembled package structure into a hot pressing diffusion bonding device, apply a pressure of 5 MPa, and heat it to 200°C at a heating rate of 10°C / min in an air atmosphere. Keep it warm for 20 minutes, then release the pressure and cool it to room temperature to complete the interconnection.

[0049] Comparative Example 1

[0050] The existing technology is used, such as the nano silver paste prepared according to CN113560562A, to weld the Ni / Au plated chip to the metal copper substrate at 300° C. / 60 min.

[0051] Comparative Example 2

[0052] In the literature Li M, Xiao Y, Zhang Z, et al. Bimodal sintered silver nanoparticle paste with ultrahigh thermal conductivity and shear strength for high temperature thermal interface material applications [J]. ACS applied materials & interfaces, 2015, 7 (17): 9157-9168., a nanosilver particle sintering method was used to solder a Ni / Au plated chip to a metal copper substrate at 250°C / 30min.

[0053] The porosity, shear strength, and thermal conductivity of the above-described examples and comparative examples were tested. Specifically, a scanning electron microscope was used to observe multiple areas of the connection layer of the chip / Ag / Ag / substrate interconnect structure. The porosity was calculated as the ratio of the area of ​​pores at the Ag / Ag interface to the total area. A push-pull force tester was used to test the shear strength of the chip / Ag / Ag / substrate interconnect structure at a test speed of 0.1 mm / s. A laser thermal conductivity meter was used to test the thermal conductivity of the Ag connection layer in the interconnect structure.

[0054] Table 1

[0055] The test results are shown in Table 1. Unlike existing nanosilver sintering interconnect technologies, which form numerous pores between particles after sintering, the nano-Ag interconnect layers deposited by magnetron sputtering in Examples 1 and 2 exhibit no pores, with only a small number of small pores forming at the Ag / Ag interface. Consequently, the layers exhibit low porosity. In terms of shear strength, Example 1 achieves solid-state bonding at only 200°C, achieving a shear strength exceeding 60 MPa, significantly higher than the shear strength achieved in Comparative Example 2, which utilizes a 250°C / 30 minute process. Furthermore, the thermal conductivity is also higher than that of Comparative Example 2.

[0056] Through the comparison of thermal conductivity test data, it can be seen that Comparative Example 1 adopts the process conditions of 300℃ / 60min to achieve connection, but its thermal conductivity is only 164.3w / mK, while the embodiment of the present application adopts a lower temperature of 200℃ / 20min to achieve solid-phase connection, and the thermal conductivity can reach more than 290w / mK, which is much higher than Comparative Example 1. This is due to the fact that the porosity in the connection layer of the embodiment is very low, and there is no organic coating layer in the deposited layer that affects the thermal conductivity. Therefore, the thermal conductivity is significantly higher than the existing nano-Ag particle sintering technology.

[0057] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A method for realizing low-temperature solid-phase connection of chips under air conditions, characterized in that: The steps include: Step S1, cleaning and drying the surface of the chip and the substrate; Step S2, depositing a nano-metal layer on the back of the chip; depositing a nano-metal layer on the substrate, wherein the nano-metal layer is a nano-Ag coating or a nano-Au coating; Step S3, placing the chip on the substrate, and making the nano-metal layer of the chip face the nano-metal layer of the substrate, to form a packaging structure which is, from top to bottom, the chip, the nano-metal layer on the chip, the nano-metal layer on the substrate, and the substrate; Step S4, placing the assembled packaging structure into a hot pressing diffusion welding device, hot pressing and heat preservation in an air atmosphere, and then cooling to room temperature to complete the interconnection, wherein the hot pressing temperature does not exceed 300 degrees.

2. The method for realizing low-temperature solid-phase bonding of chips under air conditions according to claim 1, characterized in that: Step S1 includes placing the chip and substrate into a vacuum plasma cleaning machine to remove surface impurities, organic matter and other pollutants to improve the cleanliness of the surface to be deposited.

3. The method for realizing low-temperature solid-phase bonding of chips under air conditions according to claim 1, characterized in that: In step S2, a nano-metal layer is deposited by using magnetron sputtering or ion plating technology.

4. The method for realizing low-temperature solid-phase bonding of chips under air conditions according to claim 3, characterized in that: In step S3, the nanometal layer is deposited by magnetron sputtering, the power of the magnetron sputtering is 100-200 W, the gas pressure is 0.1-5 Pa, and the argon gas flow rate is 10-40 sccm.

5. The method for realizing low-temperature solid-phase bonding of chips under air conditions according to claim 1, characterized in that: The thickness of the nano metal layer is 0.1-10 μm, and the average grain diameter of the nano metal is 10-100 nm.

6. The method for realizing low-temperature solid-phase bonding of chips under air conditions according to claim 5, characterized in that: The thickness of the nano-metal layer on the substrate is greater than the thickness of the nano-metal layer on the chip.

7. The method for realizing low-temperature solid-phase bonding of chips under air conditions according to claim 1, characterized in that: In step S4, the pressure is 1-10 MPa, the temperature is 180-300° C., and the insulation time is 5-30 min.

8. The method for realizing low-temperature solid-phase bonding of chips under air conditions according to claim 1, characterized in that: The chip is a semiconductor chip of Si or SiC with Ni / Au or Ni / Ag plated on the back.

9. The method for realizing low-temperature solid-phase bonding of chips under air conditions according to claim 1, characterized in that: The surface of the chip and substrate on which the nano-metal film is deposited has a surface roughness Ra of less than 50 nm.

10. The method for realizing low temperature solid phase connection of chips under air conditions according to any one of claims 1 to 9, characterized in that: The substrate is a metal substrate, a ceramic substrate with a metal coating or a lead frame. 。

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