Gate drive circuit and display panel

Abstract

A gate drive circuit and a display panel. In the gate drive circuit, under the control of one of a fourth node (P), an output end of a second output module (70), or a first node of a next-stage shift register, a voltage regulation module (71) can stabilize or reduce the gate potential of a second transistor (T10) by means of a low voltage signal, thus keeping the potential of a second gate drive signal (Nout[N]) at a high potential or pulse amplitude.

Description

Gate drive circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] In a display panel, a gate driving circuit is generally used to provide corresponding gate driving signals for different transistors. The stability of the gate driving signals is particularly critical to the operating stability of the transistors.

[0003] However, the jump of the corresponding signal potential in the gate driving circuit is likely to affect the potential stability of the internal node, and the potential stability of the internal node will further affect the stability of the gate driving signal. SUMMARY OF THE INVENTION

[0004] The present application provides a gate driving circuit and a display panel to alleviate the technical problem of low potential stability of a gate driving signal.

[0005] In the first aspect, the present application provides a gate drive circuit, which includes multiple shift registers, and the shift register includes a level transmission signal selection module, a pull-up control module, a first filter module, a second filter module, a first inversion module, a first output module, a second output module and a voltage regulation module. The level transmission signal selection module is electrically connected between the first wiring and the first node; the pull-up control module controls the potential of the second node according to the potential of the first node and the potential of the first clock signal; the first filter module is electrically connected between the second node and the third node, and the control end of the first filter module is connected to the reset signal; the second filter module is electrically connected between the first filter module and the third node, and the control end of the second filter module is connected to the filter control signal; the first inversion module is connected between the second node and the third node. Four nodes; the first output module outputs a first gate drive signal according to the potential of the third node and the potential of the fourth node; the second output module includes a first P-channel transistor and an N-channel second transistor, the first electrode of the first transistor is electrically connected to the first high potential line, the second electrode of the first transistor is electrically connected to the first electrode of the second transistor to output the second gate drive signal, the second electrode of the second transistor is connected to the first low potential signal, and the second node is electrically connected to the gate of the first transistor and the gate of the second transistor; one end of the voltage regulating module is connected to the low voltage signal, the other end of the voltage regulating module is connected to the gate of the second transistor, and the control end of the voltage regulating module is electrically connected to the fourth node, the output end of the second output module or one of the first nodes of the next stage shift register.

[0006] In a second aspect, the present application provides a display panel, which includes a pixel circuit and a gate driving circuit in at least one of the above-mentioned embodiments, the pixel circuit includes a write transistor for controlling the input of a data signal and a compensation transistor for controlling the input of the data signal to the gate of the driving transistor; the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor. Beneficial effects

[0007] The gate drive circuit and display panel provided in the present application can stabilize or reduce the gate potential of the second transistor through a low-voltage signal by the voltage regulation module under the control of one of the fourth node, the output end of the second output module, or the first node of the next-stage shift register, so that the second transistor is stabilized or better in the cut-off state to reduce leakage current, and the potential of the second gate drive signal can be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG1 is a schematic structural diagram of a pixel circuit in related art.

[0009] FIG. 2 is a timing diagram of the pixel circuit shown in FIG. 1 .

[0010] FIG3 is a schematic diagram of a first structure of a gate driving circuit in the related art.

[0011] FIG4 is a timing diagram of the gate driving circuit shown in FIG3 .

[0012] FIG. 5 is a schematic diagram of the gate driving circuit shown in FIG. 3 in the first stage shown in FIG. 4 .

[0013] FIG. 6 is a schematic diagram illustrating the state of the gate driving circuit shown in FIG. 3 in the second stage shown in FIG. 4 .

[0014] FIG. 7 is a schematic diagram showing the state of the gate driving circuit shown in FIG. 3 in the third stage shown in FIG. 4 .

[0015] FIG. 8 is a schematic diagram illustrating the state of the gate driving circuit shown in FIG. 3 in the fourth stage shown in FIG. 4 .

[0016] FIG. 9 is a schematic diagram illustrating the state of the gate driving circuit shown in FIG. 3 in the fifth stage shown in FIG. 4 .

[0017] FIG. 10 is a schematic diagram illustrating the state of the gate driving circuit shown in FIG. 3 in the sixth stage shown in FIG. 4 .

[0018] FIG. 11 is a schematic diagram showing the state of the gate driving circuit shown in FIG. 3 in the seventh stage shown in FIG. 4 .

[0019] FIG. 12 is a schematic diagram showing the state of the gate driving circuit shown in FIG. 3 in the eighth stage shown in FIG. 4 .

[0020] FIG. 13 is a schematic diagram showing the gate driving circuit shown in FIG. 3 in the ninth stage shown in FIG. 4 .

[0021] FIG. 14 is a schematic diagram illustrating the gate driving circuit shown in FIG. 3 in the tenth stage shown in FIG. 4 .

[0022] FIG. 15 is a schematic diagram showing the gate driving circuit shown in FIG. 3 in the eleventh stage shown in FIG. 4 .

[0023] FIG. 16 is a schematic diagram illustrating the gate driving circuit shown in FIG. 3 in the twelfth stage shown in FIG. 4 .

[0024] FIG. 17 is a schematic diagram showing the gate driving circuit shown in FIG. 3 in the thirteenth stage shown in FIG. 4 .

[0025] FIG. 18 is a schematic diagram illustrating the state of the gate driving circuit shown in FIG. 3 in the fourteenth stage shown in FIG. 4 .

[0026] FIG19 is a schematic diagram showing the state of the gate driving circuit shown in FIG3 in the fifteenth stage shown in FIG4.

[0027] FIG20 is a second structural diagram of a gate driving circuit in the related art.

[0028] FIG21 is a timing diagram of the gate driving circuit shown in FIG20 .

[0029] FIG22 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the first stage in FIG21 .

[0030] FIG23 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the second stage in FIG21 .

[0031] FIG24 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the third stage in FIG21 .

[0032] FIG25 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the fourth stage in FIG21 .

[0033] FIG26 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the fifth stage in FIG21 .

[0034] FIG27 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the sixth stage in FIG21 .

[0035] FIG28 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the seventh stage in FIG21 .

[0036] FIG29 is a schematic diagram showing the state of the gate driving circuit shown in FIG20 in the eighth stage shown in FIG21.

[0037] Figure 30 is a timing diagram of the generation of the Nth level negative pulse gate drive signal provided in an embodiment of the present application.

[0038] FIG31 is a timing diagram of some nodes in the gate driving circuit shown in FIG3 or FIG20.

[0039] Figure 32 is a first structural schematic diagram of the gate drive circuit provided in an embodiment of the present application.

[0040] FIG33 is a second structural diagram of the gate drive circuit provided in an embodiment of the present application.

[0041] FIG34 is a timing diagram of the gate drive circuit shown in FIG32 and FIG33.

[0042] FIG35 is a schematic diagram showing the state of the gate drive circuit shown in FIG32 in the first stage in FIG34 .

[0043] FIG36 is a schematic diagram showing the state of the gate drive circuit shown in FIG32 in the second stage in FIG34 .

[0044] FIG37 is a schematic diagram showing the state of the gate drive circuit shown in FIG32 in the third stage in FIG34 .

[0045] FIG38 is a schematic diagram showing the state of the gate drive circuit shown in FIG32 in the fourth stage in FIG34 .

[0046] FIG39 is a schematic diagram showing the state of the gate drive circuit shown in FIG32 in the fifth stage in FIG34 .

[0047] FIG40 is a schematic diagram showing the state of the gate driving circuit shown in FIG32 in the sixth stage in FIG34 .

[0048] FIG41 is a schematic diagram showing the state of the gate driving circuit shown in FIG32 in the seventh stage in FIG34 .

[0049] FIG42 is a schematic diagram showing the state of the gate driving circuit shown in FIG32 in the eighth stage in FIG34 .

[0050] FIG43 is a schematic diagram showing the state of the gate driving circuit shown in FIG32 in the ninth stage in FIG34.

[0051] FIG44 is a schematic diagram showing the state of the gate driving circuit shown in FIG32 in the tenth stage in FIG34 .

[0052] FIG45 is a schematic diagram showing the state of the gate driving circuit shown in FIG32 in the eleventh stage in FIG34.

[0053] FIG46 is a schematic diagram showing the state of the gate driving circuit shown in FIG32 in the twelfth stage in FIG34 .

[0054] FIG47 is a schematic diagram showing the state of the gate driving circuit shown in FIG32 in the thirteenth stage in FIG34.

[0055] FIG48 is a schematic diagram showing the state of the gate driving circuit shown in FIG32 in the fourteenth stage in FIG34.

[0056] FIG49 is a schematic diagram showing the state of the gate driving circuit shown in FIG32 in the fifteenth stage in FIG34.

[0057] FIG50 is a third structural diagram of the gate drive circuit provided in this embodiment.

[0058] FIG51 is a timing diagram of the gate drive circuit shown in FIG50 .

[0059] FIG52 is a schematic diagram showing the state of the gate drive circuit shown in FIG50 in the first stage in FIG51 .

[0060] FIG53 is a schematic diagram showing the state of the gate drive circuit shown in FIG50 in the second stage in FIG51 .

[0061] FIG54 is a schematic diagram showing the state of the gate drive circuit shown in FIG50 in the third stage in FIG51 .

[0062] FIG55 is a schematic diagram showing the state of the gate drive circuit shown in FIG50 in the fourth stage in FIG51 .

[0063] FIG56 is a schematic diagram showing the state of the gate drive circuit shown in FIG50 in the fifth stage in FIG51 .

[0064] FIG57 is a schematic diagram showing the state of the gate drive circuit shown in FIG50 in the sixth stage in FIG51.

[0065] FIG58 is a schematic diagram showing the state of the gate drive circuit shown in FIG50 in the seventh stage in FIG51 .

[0066] FIG59 is a schematic diagram showing the state of the gate drive circuit shown in FIG50 in the eighth stage in FIG51.

[0067] FIG60 is a schematic diagram of the cascade structure between shift registers in the gate drive circuit shown in FIG3 or FIG20.

[0068] Figure 61 is a schematic diagram of the structure of the display panel provided in an embodiment of the present application.

[0069] Figure 62 is a structural schematic diagram of the pixel circuit provided in an embodiment of the present application.

[0070] Figure 63 is a timing diagram of the pixel circuit described in Figure 62. Modes for Carrying Out the Invention

[0071] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0072] In the gate drive circuit in the invention application with application number 202310191137.9, the N-level negative pulse gate drive signal Pout[N] has one negative pulse in one frame. The N-level positive pulse gate drive signal Nout[N] has two positive pulses in one frame, and the pulse widths of the two positive pulses must be equal and both have a width of 2H. This restricts the width of the positive pulse of the N-level positive pulse gate drive signal Nout[N] to remain consistent and cannot be changed, so that when the width of the positive pulse of the N-level positive pulse gate drive signal Nout[N] is greater than 2H, the number of negative pulses of the N-level negative pulse gate drive signal Pout[N] in one frame will increase.

[0073] Therefore, this will limit the pixel circuit shown in Figure 1 to operate according to the timing shown in Figure 2. Specifically, the pixel circuit shown in Figure 1 may include at least one of a write transistor T2P, a drive transistor T1P, a first light emission control transistor T5P, a second light emission control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light emitting device D1, a storage capacitor Cst, and a bootstrap capacitor CbOst.

[0074] The first power line is electrically connected to the first electrode of the first light-emitting control transistor T5P and one end of the storage capacitor Cst, the second electrode of the first light-emitting control transistor T5P is electrically connected to the first electrode of the driving transistor T1P and the first electrode of the writing transistor T2P, the second electrode of the driving transistor T1P is electrically connected to the first electrode of the compensation transistor T3P and the first electrode of the second light-emitting control transistor T6P, the second electrode of the second light-emitting control transistor T6P is electrically connected to the first electrode of the second initialization transistor T7P and the anode of the light-emitting device D1, and the cathode of the light-emitting device D1 is electrically connected to the second power line.

[0075] The light emission control line is electrically connected to the gate of the first light emission control transistor T5P and the gate of the second light emission control transistor T6P.

[0076] The second electrode of the write transistor T2P is electrically connected to the data line, and the gate of the write transistor T2P is electrically connected to one end of the bootstrap capacitor CbOst and receives the Nth-level negative pulse gate drive signal Pout[N]. The second electrode of the second initialization transistor T7P is electrically connected to the second initialization line, and the gate of the second initialization transistor T7P receives the gate drive signal Pscan2.

[0077] The second electrode of the compensation transistor T3P is electrically connected to the gate of the driving transistor T1P, and the gate of the compensation transistor T3P is connected to the N-th stage positive pulse gate driving signal Nout[N].

[0078] The gate of the driving transistor T1P is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor CbOst, and the first electrode of the first initialization transistor T4P.

[0079] A second electrode of the first initialization transistor T4P is electrically connected to the first initialization line, and a gate of the first initialization transistor T4P is connected to the N-1th stage positive pulse gate driving signal Nout[N-1].

[0080] A first electrode of the third initialization transistor T8P is electrically connected to the first electrode of the driving transistor T1P, a second electrode of the third initialization transistor T8P is electrically connected to the third initialization line, and a gate of the third initialization transistor T8P and a gate of the second initialization transistor T7P share a gate driving signal Pscan2.

[0081] It should be noted that the second initialization line can also be replaced by the first initialization line, which can reduce one wiring required for the pixel circuit and help increase the density of the pixel circuit in the display panel.

[0082] In this application, the first electrode can be either a source electrode or a drain electrode, and the second electrode can be the other of the source electrode and the drain electrode. For example, when the first electrode is a source electrode, the second electrode is a drain electrode; or when the first electrode is a drain electrode, the second electrode is a source electrode.

[0083] Among them, the first power line is used to transmit the positive power signal VDD, and the second power line is used to transmit the negative power signal VSS. The potential of the positive power signal VDD is higher than the potential of the negative power signal VSS. The data line is used to transmit the data signal Data. The light control line is used to transmit the light control signal EM. The first initialization line is used to transmit the first initialization signal Vi1. The second initialization line is used to transmit the second initialization signal. The third initialization line is used to transmit the third initialization signal Vi3. The first gate drive line is used to transmit the N-th level negative pulse gate drive signal Pout[N]. The second gate drive lines connected to the shift registers of different levels are used to transmit the N-1-th level positive pulse gate drive signal Nout[N-1] and the N-th level positive pulse gate drive signal Nout[N] respectively.

[0084] As can be seen from the above, in the gate drive circuit shown in the invention application No. 202310191137.9, the principle of generating a negative pulse in a frame of the N-th level negative pulse gate drive signal Pout[N] is to filter out the first pulse of the start control signal STV or the NY-th level positive pulse gate drive signal Nout[NY] by the second pulse of the reset signal RST. Therefore, the widths of the two positive pulses of the start control signal STV or the NY-th level positive pulse gate drive signal Nout[NY] must be equal.

[0085] In the pixel circuit shown in Figure 1, in order to achieve synchronous conduction of the compensation transistor T3P and the first initialization transistor T4P, the pulse of the N-1th level positive pulse gate drive signal Nout[N-1] and the pulse of the Nth level positive pulse gate drive signal Nout[N] need to partially overlap. This is why the first initialization transistor T4P in the pixel circuit shown in Figure 1 must be connected to the N-1th level positive pulse gate drive signal Nout[N-1].

[0086] In addition, in order to complete the transmission of the third initialization signal Vi3 through node A and node B to node Q in sequence to reset the potentials of node A, node B, and node Q, the third initialization transistor T8P and the compensation transistor T3P need to be turned on synchronously, which requires the pulse of the gate drive signal Pscan2 to partially overlap with the pulse of the Nth level positive pulse gate drive signal Nout[N].

[0087] In order for the pixel circuit shown in FIG1 to continue to use the gate driving signal Pscan2 whose pulse width can only be 1H, it is necessary to adjust the driving timing of the pixel circuit shown in FIG2 . Correspondingly, the gate driving circuit shown in FIG1 also needs to be improved.

[0088] In this context, in order to alleviate the technical problem that the pulse of the gate drive signal is difficult to adapt to the requirements in terms of time and width, the present embodiment provides a gate drive circuit, please refer to Figures 3 to 30. As shown in Figures 3 and 20, the gate drive circuit includes multiple shift registers, and the shift register includes a stage signal selection module 10, a pull-up control module 20, a first filter module 30, a second filter module 80 and at least one of the first output module 46.

[0089] The stage transmission signal selection module 10 is electrically connected between the first node O / O[N], the start control line, and the NYth stage positive pulse gate drive line, where Y is an integer greater than or equal to 2.

[0090] The pull-up control module 20 controls the potential of the second node K according to the potential of the first node O / O[N] and the potential of the first clock signal.

[0091] The first filter module 30 is electrically connected between the middle node and one of the second node K or the third node Q. The control end of the first filter module 30 is electrically connected to the NXth stage positive pulse gate drive line, where X is an integer greater than or equal to 2.

[0092] The second filter module 80 is electrically connected between the middle node and the other of the second node K or the third node Q. The control end of the second filter module 80 is electrically connected to the N-2th stage positive pulse gate drive line.

[0093] The first output module 46 is electrically connected to the third node Q, the fourth node P, and the N-th stage negative pulse gate driving line.

[0094] It can be understood that the gate drive circuit provided in this embodiment filters out the first part of the second pulse that appears later than the second node K in a frame through the first filtering module 30, and filters out the second part of the first pulse that appears first and the second pulse that appears later than the second node K in a frame through the second filtering module 80. The first part of the fixed width in the first pulse can be retained, and then the first output module 46 is controlled to output the gate drive signal of the pulse with the fixed width at the corresponding time. After such improvement, it can be suitable for the driving requirements of the back end.

[0095] In one embodiment, the shift register further includes a first inverting module 50 and a second output module 70, wherein the first inverting module 50 is electrically connected between the second node K and the fourth node P; the second output module 70 is electrically connected to the second node K and the Nth level positive pulse gate drive line.

[0096] It can be understood that after the improvements of Figures 3 and 20, since the first filtering module 30 can filter out the first part of the second pulse that appears later in a frame at the second node K, and the second filtering module 80 can filter out the second part of the first pulse that appears first and the second pulse that appears later in a frame at the second node K, the first part of the fixed width in the first pulse can be retained, and then the first output module 46 is controlled to output a gate drive signal with a pulse of the fixed width at a corresponding time. The pulse width of the N-level positive pulse gate drive signal Nout[N] provided by the second output module 70 does not affect the pulse width of the N-level negative pulse gate drive signal Pout[N]. Therefore, the two pulse widths of the N-level positive pulse gate drive signal Nout[N] in a frame can not only be modulated to a width greater than 2H, but also can be modulated separately without having to keep the two pulse widths equal. This provides support for the improvement of the drive timing of the pixel circuit.

[0097] In one embodiment, as shown in Figures 3 and 20, the first filtering module 30 includes a first filtering transistor T11 and a first capacitor C2, one of the source or drain of the first filtering transistor T11 is electrically connected to the second node K, the other of the source or drain of the first filtering transistor T11 is electrically connected to the intermediate node, and the gate of the first filtering transistor T11 is electrically connected to the NX-th level positive pulse gate drive line; one end of the first capacitor C2 is electrically connected to the gate of the first filtering transistor T11, and the other end of the first capacitor C2 is electrically connected to the other of the source or drain of the first filtering transistor T11.

[0098] It should be noted that, as shown in FIG30 , the first filtering module 30 is used to filter out the first part of the second pulse that appears after the second node K in one frame.

[0099] In one embodiment, as shown in Figures 3 and 20, the second filtering module 80 includes a second filtering transistor T8, one of the source or drain of the second filtering transistor T8 is electrically connected to the intermediate node, the other of the source or drain of the second filtering transistor T8 is electrically connected to the third node Q, and the gate of the first filtering transistor T11 is electrically connected to the N-2th level positive pulse gate drive line.

[0100] It should be noted that, as shown in FIG30 , the second filtering module 80 is used to filter out the latter part of the first pulse that appears first and the latter part of the second pulse that appears later at the second node K in a frame.

[0101] It can be seen from this that the first filtering module 30 and the second filtering module 80 are used to filter out the second pulse and retain the first portion of the first pulse with a fixed width.

[0102] In one embodiment, as shown in FIG20 , the shift register further includes an isolation module 75 , which is connected in series between the second node K and the input end of the second output module 70 , and a control end of the isolation module 75 is connected to the first clock signal.

[0103] It should be noted that the isolation module 75 is used to reduce the coupling of the pulse amplitude of the N-th level negative pulse gate drive signal Pout[N] to the pulse amplitude of the N-th level positive pulse gate drive signal Nout[N], thereby stabilizing the high potential of the N-th level positive pulse gate drive signal Nout[N].

[0104] In one embodiment, as shown in FIG20 , the isolation module 75 includes a sixth transistor T14, one of the source or the drain of the sixth transistor T14 is electrically connected to the second node K, the other of the source or the drain of the sixth transistor T14 is electrically connected to the input end of the second output module 70, the gate of the sixth transistor T14 is connected to the first clock signal, and the sixth transistor T14 is a P-channel thin film transistor.

[0105] It should be noted that the sixth transistor T14 can reduce the coupling of the pulse amplitude of the N-th level negative pulse gate drive signal Pout[N] to the pulse amplitude of the N-th level positive pulse gate drive signal Nout[N], thereby stabilizing the high potential of the N-th level positive pulse gate drive signal Nout[N].

[0106] In other embodiments, the isolation module 75 may further include a transistor connected in series between the gate of the sixth transistor T14 and the node N.

[0107] Among them, the input end of the level transmission signal selection module 10 is electrically connected to the starting control line or the NYth level positive pulse gate drive line, wherein N is an integer greater than or equal to 1, and Y is an integer greater than or equal to 1.

[0108] An input end of the pull-up control module 20 is electrically connected to an output end of the stage transmission signal selection module 10 , and a control end of the pull-up control module 20 is electrically connected to the first clock line.

[0109] An input terminal of the first filter module 30 is electrically connected to an output terminal of the pull-up control module 20 , and a control terminal of the first filter module 30 is electrically connected to a reset line.

[0110] The control end of the pull-up module 40 is electrically connected to the output end of the first filter module 30, the input end of the pull-up module 40 is electrically connected to the second clock line, and the output end of the pull-up module 40 is electrically connected to the N-th stage negative pulse gate drive line. The input end of the first inverting module 50 is electrically connected to the output end of the pull-up control module 20.

[0111] The control end of the pull-down module 60 is electrically connected to the output end of the first inverting module 50 , the input end of the pull-down module 60 is electrically connected to the high potential line, and the output end of the pull-down module 60 is electrically connected to the Nth stage negative pulse gate driving line.

[0112] In one embodiment, the first output module 46 includes a pull-up module 40 and a pull-down module 60 .

[0113] It should be noted that the first wiring can be a starting control line or a NY-th level positive pulse gate drive line; when NY is less than or equal to 0, the first wiring is the starting control line. The N-th level positive pulse gate drive line, i.e., the second gate control line, is used to transmit the N-th level positive pulse gate drive signal Nout[N], i.e., the second gate drive signal. The N-th level negative pulse gate drive line, i.e., the first gate control line, is used to transmit the N-th level negative pulse gate drive signal Pout[N], i.e., the first gate drive signal.

[0114] In one embodiment, the first filtering module 30 includes a first filtering transistor T11 and a first capacitor C2, one of the source or the drain of the first filtering transistor T11 is electrically connected to the second node K, the other of the source or the drain of the first filtering transistor T11 is electrically connected to the third node Q, and the gate of the first filtering transistor T11 is connected to the reset signal RST; one end of the first capacitor C2 is electrically connected to the gate of the first filtering transistor T11, and the other end of the first capacitor C2 is electrically connected to the other of the source or the drain of the first filtering transistor T11.

[0115] A ratio of a channel width of the first filter transistor T11 to a channel length of the first filter transistor T11 is greater than or equal to 0.5 and less than or equal to 1.5.

[0116] It should be noted that this embodiment is conducive to ensuring the output stability of the Nth-level negative pulse gate drive signal Pout[N], and avoids the coupling pull-down phenomenon before the negative pulse arrives.

[0117] In one embodiment, the pull-up module 40 includes a pull-up transistor T6 and a second capacitor C1, the gate of the pull-up transistor T6 is electrically connected to one of the source or drain of the first filter transistor T11, one of the source or drain of the pull-up transistor T6 is electrically connected to the second clock line, and the other of the source or drain of the pull-up transistor T6 is electrically connected to the N-level negative pulse gate drive line; one end of the second capacitor C1 is electrically connected to the gate of the pull-up transistor T6, and the other end of the second capacitor C1 is electrically connected to the other of the source or drain of the pull-up transistor T6; wherein, the ratio of the capacity of the first capacitor C2 to the second capacitor C1 is greater than or equal to 0.5.

[0118] It should be noted that the design of the capacitance ratio of the first capacitor C2 to the second capacitor C1 in this embodiment is conducive to further ensuring the output stability of the Nth level negative pulse gate drive signal Pout[N], and avoiding the coupling pull-down phenomenon before the negative pulse arrives.

[0119] Specifically, the capacity of the first capacitor C2 may be greater than or equal to 50 fF, and the capacity of the second capacitor C1 may be greater than or equal to 100 fF.

[0120] The ratio of the channel width of the pull-up transistor T6 to its channel length is greater than 30:1, which is beneficial to further ensure the output stability of the Nth stage negative pulse gate drive signal Pout[N]. The pull-up transistor T6 can be a P-channel thin film transistor.

[0121] In one embodiment, the stage transmission signal selection module 10 includes a transistor T13 and a transistor T12, one of the source or the drain of the transistor T13 is electrically connected to the low potential line, the other of the source or the drain of the transistor T13 is electrically connected to the input end of the pull-up control module 20, the first gate of the transistor T13 is electrically connected to the start control line or the NYth stage positive pulse gate drive line, the first gate of the transistor T13 is electrically connected to the second gate of the transistor T13, and the transistor T13 is an N-channel thin film transistor; one of the source or the drain of the transistor T12 is electrically connected to the high potential line, the other of the source or the drain of the transistor T12 is electrically connected to the other of the source or the drain of the transistor T13, the gate of the transistor T12 is electrically connected to the first gate of the transistor T13, and the transistor T12 is a P-channel thin film transistor.

[0122] It should be noted that, in this embodiment, the level transmission signal selection module 10 not only objectively has an inverting effect, that is, the potentials of the input signal and the output signal are opposite at the same time, but also plays the role of making the N-th level positive pulse gate drive signal Nout[N] serve as the level transmission signal between the shift registers. Otherwise, level transmission cannot be achieved between the shift registers, which will cause the gate drive circuit to be unable to normally provide the corresponding gate drive signal.

[0123] The ratio of the channel width of the transistor T13 to the channel length of the transistor T13 is greater than 2:1. The ratio of the channel width of the transistor T12 to the channel length of the transistor T12 is in the range of 0.5:1 to 3:1.

[0124] The high-potential line is used to transmit a high-potential signal VGH, which can turn on an N-channel thin-film transistor or turn off a P-channel thin-film transistor. The low-potential line is used to transmit a low-potential signal VGL, which can turn on a P-channel thin-film transistor or turn off an N-channel thin-film transistor.

[0125] In one embodiment, the pull-up control module 20 includes a pull-up control transistor T2, one of the source or drain of the pull-up control transistor T2 is electrically connected to the output end of the stage transmission signal selection module 10, the other of the source or drain of the pull-up control transistor T2 is electrically connected to the input end of the first filtering module 30, and the gate of the pull-up control transistor T2 is electrically connected to the first clock line.

[0126] It should be noted that the pull-up control transistor T2 may be a P-channel thin film transistor, and the ratio of the channel width of the pull-up control transistor T2 to the channel length of the pull-up control transistor T2 is in the range of 0.5:1 to 3:1.

[0127] In one embodiment, the first inversion module 50 includes a fourth transistor T3 and a fifth transistor T1, one of the source or the drain of the fourth transistor T3 is electrically connected to the high potential line, the other of the source or the drain of the fourth transistor T3 is electrically connected to one of the source or the drain of the fifth transistor T1 and the control end of the pull-down module 60, the other of the source or the drain of the fifth transistor T1 is electrically connected to the low potential line, and the output end of the pull-up control module 20 is electrically connected to the gate of the fourth transistor T3, the first gate of the fifth transistor T1, and the second gate of the fifth transistor T1.

[0128] It should be noted that the fourth transistor T3 is a P-channel thin film transistor, and the fifth transistor T1 is a dual-gate N-channel thin film transistor. This can improve the dynamic performance of the fourth transistor T3 and the fifth transistor T1, and thus improve the dynamic performance of the first inverter module 50.

[0129] The ratio of the channel width of the fourth transistor T3 to the channel length of the fourth transistor T3 is in the range of 0.5:1 to 3:1. The ratio of the channel width of the fifth transistor T1 to the channel length of the fifth transistor T1 is greater than or equal to 2:1.

[0130] In one embodiment, the pull-down module 60 includes a pull-down transistor T7, one of the source or drain of the pull-down transistor T7 is electrically connected to the high potential line, the other of the source or drain of the pull-down transistor T7 is electrically connected to the N-th level negative pulse gate drive line, and the gate of the pull-down transistor T7 is electrically connected to the output end of the first inverting module 50, that is, the fourth node P.

[0131] It should be noted that the pull-down transistor T7 can be a P-channel thin film transistor. Under the joint action of the pull-down module 60 and the pull-up module 40, the required Nth level negative pulse gate driving signal Pout[N] can be modulated.

[0132] The ratio of the channel width of the pull-down transistor T7 to the channel length of the pull-down transistor T7 is greater than or equal to 30:1.

[0133] The second output module 70 includes a transistor T9 and a transistor T10, one of the source or drain of the transistor T9 is electrically connected to the high potential line, the other of the source or drain of the transistor T9 is electrically connected to one of the source or drain of the transistor T10 and the N-th level positive pulse scan line, the other of the source or drain of the transistor T10 is electrically connected to the low potential line, and the output end of the pull-up control module 20 is electrically connected to the gate of the transistor T9, the first gate of the transistor T10 and the second gate of the transistor T10.

[0134] It should be noted that the transistor T9 is a P-channel thin film transistor and the transistor T10 is a dual-gate N-channel thin film transistor. This can improve the dynamic performance of the transistors T9 and T10, and thus improve the dynamic performance of the second output module 70.

[0135] The ratio of the channel width of the first transistor T9 to the channel length of the first transistor T9 is greater than or equal to 30:1. The ratio of the channel width of the second transistor T10 to the channel length of the second transistor T10 is greater than or equal to 30:1.

[0136] In one embodiment, the second filter module 80 includes a second filter transistor T8, one of the source or drain of the second filter transistor T8 is electrically connected to the output end of the first filter module 30, the other of the source or drain of the second filter transistor T8 is electrically connected to the control end of the pull-up module 40, and the gate of the second filter transistor T8 is connected to the filter control signal RST2.

[0137] It should be noted that the second filter transistor T8 can be a P-channel thin film transistor; it can also be an N-channel thin film transistor.

[0138] The ratio of the channel width of the second filter transistor T8 to the channel length of the second filter transistor T8 may be in the range of 0.5:1 to 3:1.

[0139] In one embodiment, the N-th stage shift register further includes a feedback module 90, which includes a transistor T4 and a transistor T5, wherein one of the source or the drain of the transistor T4 is electrically connected to the output end of the pull-up control module 20, the gate of the transistor T4 is electrically connected to the second clock line, the other of the source or the drain of the transistor T4 is electrically connected to one of the source or the drain of the transistor T5, the other of the source or the drain of the transistor T5 is electrically connected to the high potential line, and the gate of the transistor T5 is electrically connected to the output end of the first inversion module 50.

[0140] The ratio of the channel width of the transistor T4 to the channel length of the transistor T4 is in the range of 0.5:1 to 3:1. The ratio of the channel width of the transistor T5 to the channel length of the transistor T5 is in the range of 0.5:1 to 3:1.

[0141] It should be noted that the feedback module 90 can maintain the second node K at a high potential based on the potential of the fourth node P and the potential of the second clock line. That is, when the fourth node P is at a low potential and the second clock signal CK is at a low potential, the high potential line can control the potential of the second node K to the potential of the high potential signal VGH.

[0142] It should be noted that the N-th level positive pulse gate drive line is used to transmit the N-th level positive pulse gate drive signal Nout[N]. The N-th level negative pulse gate drive line is used to transmit the N-th level negative pulse gate drive signal Pout[N]. The first clock line is used to transmit the first clock signal XCK. The second clock line is used to transmit the second clock signal CK. The start control line is used to transmit the start control signal STV. The NY-th level positive pulse gate drive line is used to transmit the NY-th level positive pulse gate drive signal Nout[NY]. The NX-th level positive pulse gate drive line is used to transmit the NX-th level positive pulse gate drive signal Nout[NX]. The reset line is used to transmit the reset signal RST.

[0143] The operation process of the shift register shown in FIG3 in one frame may include the following stages as shown in FIG4:

[0144] Phase 1 S1: As shown in Figures 4 and 5, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the first clock signal XCK is at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0145] Second stage S2: As shown in Figures 4 and 6, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the second clock signal CK is at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0146] The third stage S3: as shown in Figures 4 and 7, the start control signal STV, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the reset signal RST and the first clock signal XCK are at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0147] The fourth stage S4: as shown in Figures 4 and 8, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the reset signal RST and the second clock signal CK are at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0148] Fifth stage S5: As shown in Figure 4 and Figure 9, the second clock signal CK is at a low potential, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the second node K, the middle node W and the third node Q are all at a high potential, the first node O / O[N] and the fourth node P are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0149] The sixth stage S6: as shown in Figures 4 and 10, the first clock signal XCK is at a low potential, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the intermediate node W, the fourth node P and the third node Q are all at a high potential, the second node K and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0150] The seventh stage S7: as shown in Figures 4 and 11, the reset signal RST and the second clock signal CK are at a low level, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high level, the fourth node P and the third node Q are both at a high level, the middle node W, the second node K, and the first node O / O[N] are at a low level, the Nth level positive pulse gate drive signal Nout[N] is at a high level, and the Nth level negative pulse gate drive signal Pout[N] is at a high level.

[0151] The eighth stage S8: as shown in Figures 4 and 12, the reset signal RST and the first clock signal XCK are at a low level, the start control signal STV, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high level, the fourth node P and the third node Q are both at a high level, the middle node W, the second node K, and the first node O / O[N] are at a low level, the Nth level positive pulse gate drive signal Nout[N] is at a high level, and the Nth level negative pulse gate drive signal Pout[N] is at a high level.

[0152] Ninth stage S9: As shown in Figures 4 and 13, the second clock signal CK and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the reset signal RST, the start control signal STV, and the first clock signal XCK are at a high potential, the intermediate node W, the first node O / O[N], the fourth node P and the third node Q are all at a high potential, the second node K is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0153] The tenth stage S10: As shown in Figures 4 and 14, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the reset signal RST and the second clock signal CK are at a high potential, the second node K, the intermediate node W, the first node O / O[N] and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0154] The eleventh stage S11: as shown in Figures 4 and 15, the reset signal RST and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the start control signal STV, the first clock signal XCK, and the second clock signal CK are at a high potential, the fourth node P and the third node Q are both at a high potential, the second node K, the middle node W, and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0155] The twelfth stage S12: as shown in Figures 4 and 16, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the first clock signal XCK is at a high potential, the fourth node P and the first node O / O[N] are both at a high potential, the third node Q, the second node K, and the middle node W are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a low potential.

[0156] Thirteenth stage S13: as shown in Figures 4 and 17, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the second clock signal CK is at a high potential, the second node K, the intermediate node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0157] Fourteenth stage S14: as shown in Figures 4 and 18, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the first clock signal XCK is at a high potential, the second node K, the intermediate node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0158] Fifteenth stage S15: As shown in Figures 4 and 19, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the second clock signal CK is at a high potential, the second node K, the intermediate node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0159] It should be noted that the "cross" in Figures 5 to 19 indicates that the transistor covered by it is in the off state, and the transistor not covered by the "cross" is in the on state. The dotted arrows in Figures 5 to 19 indicate the direction of current.

[0160] The operation process of the shift register shown in FIG20 in one frame may include the following stages as shown in FIG21:

[0161] First stage S1: As shown in Figures 21 and 22, the start control signal STV and the second clock signal CK are both at a low potential, the first clock signal XCK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0162] Second stage S2: As shown in Figures 21 and 23, the start control signal STV and the first clock signal XCK are at a low potential, the second clock signal CK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0163] The third stage S3: As shown in Figures 21 and 24, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0164] Fourth stage S4: As shown in Figures 21 and 25, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0165] Fifth stage S5: As shown in Figures 21 and 26, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0166] Sixth stage S6: As shown in Figures 21 and 27, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0167] Seventh stage S7: As shown in Figure 21 and Figure 28, the start control signal STV and the second clock signal CK are at a low potential, the first clock signal XCK is at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0168] The eighth stage S8: As shown in Figures 21 and 29, the start control signal STV and the first clock signal XCK are at a low potential, the second clock signal CK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the N-th level positive pulse gate drive signal Nout[N] is switched from a high potential to a low potential.

[0169] It should be noted that the "crosses" in Figures 22 to 29 indicate that the transistors covered by them are in the off state, and the transistors not covered by the "crosses" are in the on state. The dotted arrows in Figures 22 to 29 indicate the direction of current.

[0170] Based on the above, Figure 30 illustrates the negative pulse generation process of the Nth-level negative pulse gate drive signal Pout[N]. For clarity, the two pulses from right to left in the same signal are referred to as the first pulse and the second pulse, respectively. The second node K transmits the first pulse and the second pulse in a frame. The high voltage of the first portion of the two pulses of the N-2th-level positive pulse gate drive signal Nout[N-2] controls the second filter module 80 to filter out the latter portions of the first pulse and the second pulse output from the second node K. The high voltage of the latter portion of the first pulse of the reset signal RST controls the first filter module 30 to filter out the former portion of the second pulse output from the second node K. At this point, the width of the second pulse at the intermediate node W is also narrowed. The second pulse output from the second node K is completely filtered out, leaving only the former portion of the first pulse output from the second node K, forming a negative pulse at the third node Q. This negative pulse at the third node Q activates the pull-up module 40, forming a negative pulse of the Nth-level negative pulse gate drive signal Pout[N] with a fixed width.

[0171] Please refer to Figure 31. The second node K of the gate drive circuit shown in Figure 31 will be affected by the voltage jump of the first clock signal XCK and / or the second clock signal CK, and the potential between the second node K and the fifth node N is in a linkage relationship. Therefore, the potential of the second node K and the potential of the fifth node N will show obvious fluctuations in the high and low level stages (such as glitches or spikes as shown in Figure 31).

[0172] As shown in Figure 31, the potential of the fifth node N, in particular, will be significantly affected by the bootstrap coupling of the first gate drive signal in the low-level stage, causing the second gate drive signal, i.e., the N-th level positive pulse gate drive signal Nout[N], to show an obvious concave phenomenon in the high-level stage (as shown in the dotted box in Figure 31). This not only reduces the potential stability of the second gate drive signal, but also causes a decrease in the consistency between the second gate drive signals transmitted in the display panel, thereby affecting the uniformity of the display.

[0173] Based on this, this embodiment provides a gate drive circuit, please refer to Figures 32 to 59. As shown in Figures 32, 33, and 50, the gate drive circuit includes multiple shift registers, and the shift register includes a level signal selection module 10, a pull-up control module 20, a first filter module 30, a second filter module 80, a first inversion module 50, a first output module 46, a second output module 70 and at least one of the voltage regulation module 71.

[0174] The stage signal selection module 10 is electrically connected between the first wiring and the first node O / O[N].

[0175] The pull-up control module 20 controls the potential of the second node K according to the potential of the first node O / O[N] and the potential of the first clock signal XCK.

[0176] The first filter module 30 is electrically connected between the second node K and the third node Q. The control terminal of the first filter module 30 is connected to the reset signal RST.

[0177] The second filter module 80 is electrically connected between the first filter module 30 and the third node Q. The control terminal of the second filter module 80 is connected to the filter control signal RST2.

[0178] The first inverting module 50 is connected between the second node K and the fourth node P.

[0179] The first output module 46 outputs a first gate driving signal according to the potential of the third node Q and the potential of the fourth node P.

[0180] The second output module 70 includes a P-channel first transistor T9 and an N-channel second transistor T10. The first electrode of the first transistor T9 is electrically connected to the first high potential line, the second electrode of the first transistor T9 is electrically connected to the first electrode of the second transistor T10 to output a second gate drive signal, the second electrode of the second transistor T10 is connected to the first low potential signal, and the second node K is electrically connected to the gate of the first transistor T9 and the gate of the second transistor T10.

[0181] One end of the voltage regulating module 71 is connected to the low voltage signal, the other end of the voltage regulating module 71 is connected to the gate of the second transistor T10, and the control end of the voltage regulating module 71 is electrically connected to the fourth node P, the output end of the second output module 70, or the first node of the next stage shift register, i.e., O[n+1].

[0182] It can be understood that the gate drive circuit provided in this embodiment can stabilize or reduce the gate potential of the second transistor T10 through a low voltage signal under the control of one of the fourth node P, the output end of the second output module 70, or the first node O[n+1] of the next-stage shift register. This makes the second transistor T10 stable or better in the cut-off state to reduce leakage current, and thus can maintain the potential of the second gate drive signal at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0183] It should be noted that the filtering control signal RST2 may be the N-2th level positive pulse gate driving signal Nout[N-2], and positive pulse gate driving signals of other levels may also be selected according to filtering requirements.

[0184] It should be noted that, in one embodiment, the voltage regulating module 71 is used to stabilize or reduce the low potential of the second node K. Alternatively, in another embodiment, the voltage regulating module 71 is further used to stabilize or reduce the gate potential of the second transistor T10 during the positive pulse of the second gate driving signal.

[0185] In one embodiment, the voltage regulating module 71 includes a third transistor T15, a first electrode of the third transistor T15 is connected to a low voltage signal, a second electrode of the third transistor T15 is electrically connected to the gate of the second transistor T10, and the gate of the third transistor T15 is electrically connected to the fourth node P, the output end of the second output module 70, or the first node of the next-stage shift register, i.e., O[n+1].

[0186] It should be noted that the third transistor T15 can stabilize or reduce the gate potential of the second transistor T10 during the duration of the positive pulse of the second gate drive signal, so that the second transistor T10 is stable or better in the cut-off state to reduce leakage current, and thus can maintain the potential of the second gate drive signal at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0187] In one embodiment, as shown in FIG32 , the gate of the third transistor T15 is electrically connected to the fourth node P and one of the output terminals of the second output module 70 , the low voltage signal is a first low potential signal, and the channel type of the third transistor T15 is the same as the channel type of the second transistor T10 .

[0188] In this embodiment, the low voltage signal and the first low potential signal are both the signal NVGL.

[0189] It should be noted that since the low-voltage signal is a first low-potential signal, in this embodiment, the second transistor T10 and the third transistor T15 can share the same low-potential line, which can reduce the number of wiring required for the gate drive circuit. The channel type of the third transistor T15 is the same as that of the second transistor T10. When the second transistor T10 is in the off state, the third transistor T15 can be turned on to further reduce the gate potential of the second transistor T10.

[0190] In one embodiment, as shown in Figure 33, the gate of the third transistor T15 is electrically connected to the fourth node P and one of the output terminals of the second output module 70, the channel type of the third transistor T15 is the same as the channel type of the second transistor T10, and the potential of the low voltage signal is lower than the potential of the first low potential signal.

[0191] In this embodiment, the first low potential signal is the signal NVGL, and the low voltage signal is the signal NVGL2.

[0192] It should be noted that the channel type of the third transistor T15 is the same as that of the second transistor T10. When the second transistor T10 is in the off state, the signal NVGL2 can be transmitted to the gate of the second transistor T10 via the third transistor T15. Compared with the signal NVGL, the gate potential of the second transistor T10 can be further reduced, thereby reducing the leakage current of the second transistor T10. In this way, the stability of the low potential of the second node K and the low potential of the intermediate node W can be improved.

[0193] In one embodiment, the difference between the potentials of the signal NVGL and the signal NVGL2 is greater than or equal to 2V.

[0194] It should be noted that this embodiment can not only reduce the leakage current of the second transistor T10 , but also adjust the threshold voltage of the second transistor T10 to shift toward the positive direction, thereby increasing the threshold voltage range of the second transistor T10 .

[0195] In one embodiment, as shown in Figure 35, the first inverting module 50 includes a P-channel fourth transistor T3 and an N-channel fifth transistor T1, the first electrode of the fourth transistor T3 is electrically connected to the second high potential line, the second electrode of the fourth transistor T3 is electrically connected to the fourth node P, and the gate of the fourth transistor T3 is electrically connected to the second node K; the first electrode of the fifth transistor T1 is electrically connected to the fourth node P, the second electrode of the fifth transistor T1 is connected to the second low potential signal, and the gate of the fifth transistor T1 is electrically connected to the second node K; wherein the potential of the second low potential signal is lower than the potential of the low voltage signal.

[0196] In this embodiment, the second low potential signal is the signal PVGL, and the low voltage signal is the signal NVGL.

[0197] It should be noted that, when the fifth transistor T1 is turned on, the gate-source voltage difference of the third transistor T15 can be made less than zero, which can effectively ensure the stability of the third transistor T15 under the dual 85.

[0198] In one embodiment, the second transistor T10 is a dual-gate transistor, and the first gate of the second transistor T10 is electrically connected to the second node K and the second gate of the second transistor T10; the third transistor T15 is a dual-gate transistor, and the first gate of the third transistor T15 is electrically connected to the fourth node P and the second gate of the third transistor T15.

[0199] It should be noted that the second transistor T10 and the third transistor T15 are dual-gate transistors, which can not only reduce the drift of the threshold voltage but also improve the accuracy of control.

[0200] In one embodiment, as shown in Figure 50, the gate of the third transistor T15 is electrically connected to the first node O[n+1] of the next-stage shift register, the low voltage signal is a first low potential signal, and the channel type of the third transistor T15 is different from the channel type of the second transistor T10; the shift register also includes a sixth transistor T14, the first electrode of the sixth transistor T14 is electrically connected to the second node K, the second electrode of the sixth transistor T14 is electrically connected to the gate of the first transistor T9, the gate of the sixth transistor is connected to the first clock signal XCK, and the channel type of the sixth transistor is the same as the channel type of the first transistor T9.

[0201] In this embodiment, the low voltage signal and the first low potential signal are both signals VGL.

[0202] It should be noted that the first node O[n+1] of the next-stage shift register is used as the signal source for the gate of the third transistor T15. The potential of O[n+1] is inversely proportional to the potential of the fourth node P, while the waveform of O[n+1] is substantially identical to the waveform of the fifth node N. Therefore, by controlling the P-channel third transistor T15 using O[n+1], the potential of the fifth node N can be continuously and sufficiently pulled down, so that the voltage of the fifth node N reaches the target potential of VGL-Vth. This can also reduce the leakage current of the second transistor T10 and improve the stability of the high potential provided by the second output module 70.

[0203] Wherein, VGL is the potential of the low potential signal, and Vth is the threshold voltage of the second transistor T10.

[0204] The other structural parts, working principles, etc. of the gate driving circuits shown in Figures 32, 33, and 50 can also refer to the description of the aforementioned gate driving circuit.

[0205] FIG34 is a timing diagram of the gate drive circuit shown in FIG32 and FIG33.

[0206] The operation process of the shift register shown in Figures 32 and 33 in one frame may include the following stages as shown in Figure 34:

[0207] Phase 1 S1: As shown in Figures 34 and 35, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the first clock signal XCK is at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0208] Second stage S2: As shown in Figures 34 and 36, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the second clock signal CK is at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0209] The third stage S3: as shown in Figures 34 and 37, the start control signal STV, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the reset signal RST and the first clock signal XCK are at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0210] The fourth stage S4: as shown in Figures 34 and 38, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the reset signal RST and the second clock signal CK are at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0211] Fifth stage S5: As shown in Figures 34 and 39, the second clock signal CK is at a low potential, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the second node K, the middle node W and the third node Q are all at a high potential, the first node O / O[N] and the fourth node P are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0212] The sixth stage S6: as shown in Figures 34 and 40, the first clock signal XCK is at a low potential, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the intermediate node W, the fourth node P and the third node Q are all at a high potential, the second node K and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0213] The seventh stage S7: as shown in Figures 34 and 41, the reset signal RST and the second clock signal CK are at a low level, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high level, the fourth node P and the third node Q are both at a high level, the middle node W, the second node K, and the first node O / O[N] are at a low level, the Nth level positive pulse gate drive signal Nout[N] is at a high level, and the Nth level negative pulse gate drive signal Pout[N] is at a high level.

[0214] The eighth stage S8: as shown in Figures 34 and 42, the reset signal RST and the first clock signal XCK are at a low level, the start control signal STV, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high level, the fourth node P and the third node Q are both at a high level, the middle node W, the second node K, and the first node O / O[N] are at a low level, the Nth level positive pulse gate drive signal Nout[N] is at a high level, and the Nth level negative pulse gate drive signal Pout[N] is at a high level.

[0215] Ninth stage S9: As shown in Figures 34 and 43, the second clock signal CK and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the reset signal RST, the start control signal STV, and the first clock signal XCK are at a high potential, the intermediate node W, the first node O / O[N], the fourth node P and the third node Q are all at a high potential, the second node K is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0216] The tenth stage S10: as shown in Figures 34 and 44, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the reset signal RST and the second clock signal CK are at a high potential, the second node K, the intermediate node W, the first node O / O[N] and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0217] The eleventh stage S11: as shown in Figures 34 and 45, the reset signal RST and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the start control signal STV, the first clock signal XCK, and the second clock signal CK are at a high potential, the fourth node P and the third node Q are all at a high potential, the second node K, the middle node W, and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0218] The twelfth stage S12: as shown in Figures 34 and 46, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the first clock signal XCK is at a high potential, the fourth node P and the first node O / O[N] are both at a high potential, the third node Q, the second node K, and the middle node W are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a low potential.

[0219] Thirteenth stage S13: as shown in Figures 34 and 47, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the second clock signal CK is at a high potential, the second node K, the middle node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0220] Fourteenth stage S14: as shown in Figures 34 and 48, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the first clock signal XCK is at a high potential, the second node K, the intermediate node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0221] Fifteenth stage S15: As shown in Figures 34 and 49, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the second clock signal CK is at a high potential, the second node K, the middle node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0222] It should be noted that the "crosses" in Figures 35 to 49 indicate that the transistors covered by them are in the off state, and the transistors not covered by the "crosses" are in the on state. The dotted arrows in Figures 35 to 49 indicate the direction of current.

[0223] In a frame, the gate drive circuit includes stages S100 and S200. Stages S1 through S15 described above belong to stage S100. During stage S100, the pulses of each first gate drive signal and each second gate drive signal are fully output. However, during stage S200, the pulses of each first gate drive signal and each second gate drive signal are not required. Therefore, maintaining at least one of the first clock signal XCK and the second clock signal CK at a low voltage reduces the frequency of voltage fluctuations in at least one of the first clock signal XCK and the second clock signal CK, thereby reducing power consumption.

[0224] The operation process of the shift register shown in FIG50 in one frame may include the following stages as shown in FIG51:

[0225] First stage S1: As shown in Figures 51 and 52, the start control signal STV and the second clock signal CK are both at a low potential, the first clock signal XCK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0226] Second stage S2: As shown in Figures 51 and 53, the start control signal STV and the first clock signal XCK are at a low potential, the second clock signal CK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0227] The third stage S3: As shown in Figures 51 and 54, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0228] Fourth stage S4: As shown in Figures 51 and 55, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0229] Fifth stage S5: As shown in Figure 51 and Figure 56, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0230] Sixth stage S6: As shown in Figure 51 and Figure 57, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0231] Seventh stage S7: As shown in Figures 51 and 58, the start control signal STV and the second clock signal CK are at a low potential, the first clock signal XCK is at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0232] The eighth stage S8: As shown in Figures 51 and 59, the start control signal STV and the first clock signal XCK are at a low potential, the second clock signal CK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the N-th level positive pulse gate drive signal Nout[N] is switched from a high potential to a low potential.

[0233] It should be noted that the "crosses" in Figures 52 to 9 indicate that the transistors covered by them are in the off state, and the transistors not covered by the "crosses" are in the on state. The dotted arrows in Figures 52 to 9 indicate the direction of current.

[0234] FIG60 is a schematic diagram illustrating the cascaded structure of different shift registers in the gate drive circuit shown in FIG3 , FIG20 , FIG32 , FIG33 , or FIG50 . Arranged from top to bottom are the first-stage shift register, the second-stage shift register, the third-stage shift register, ... the Nth-stage shift register, the N+1th-stage shift register, and so on. Each shift register operates based on the first clock signal XCK and the second clock signal CK received therein.

[0235] The control terminals of the first filter module 30 and the second filter module 80 in the first-stage shift register are both connected to the low-voltage signal VGL, and the input terminal (IN) of the first-stage shift register connected to the start control line is connected to the start control signal STV. The first-stage shift register outputs the corresponding first-stage negative pulse gate drive signal Pout[1] and first-stage positive pulse gate drive signal Nout[1]. The first-stage negative pulse gate drive signal Pout[1] and first-stage positive pulse gate drive signal Nout[1] are used to drive dummy pixels (Dummy) or are left floating.

[0236] The control terminals of the first filter module 30 and the second filter module 80 in the second-stage shift register are both connected to the low-voltage signal VGL, and the starting control line connected to the second-stage shift register is connected to the cascade signal, namely the first-stage positive pulse gate drive signal Nout[1]. The second-stage shift register outputs the corresponding second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2]. The second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2] are used to drive dummy pixels (Dummy) or are left floating.

[0237] The control terminals of the first filter module 30 and the second filter module 80 in the third-stage shift register are both connected to the low-voltage signal VGL, and the starting control line connected to the third-stage shift register is connected to the cascade signal, namely the second-stage positive pulse gate drive signal Nout[2]. The third-stage shift register outputs the corresponding third-stage negative pulse gate drive signal Pout[3] and third-stage positive pulse gate drive signal Nout[3]. The third-stage negative pulse gate drive signal Pout[3] and third-stage positive pulse gate drive signal Nout[3] are used to drive dummy pixels (Dummy) or leave them floating.

[0238] The same logic can be applied to other control lines, until the control terminals of the first filter module 30 and the second filter module 80 in the N-th shift register are connected to the NX-th positive pulse gate drive signal Nout[NX] and the N-2-th positive pulse gate drive signal Nout[N-2], respectively. The starting control line connected to the N-th shift register is connected to the cascade signal, namely the N-1-th positive pulse gate drive signal Nout[N-1]. The N-th shift register outputs the corresponding N-th negative pulse gate drive signal Pout[N] and the N-th positive pulse gate drive signal Nout[N]. The N-th negative pulse gate drive signal Pout[N] and the N-th positive pulse gate drive signal Nout[N] are used to drive the first row of pixel circuits (Pixel).

[0239] The control terminals of the first filter module 30 and the second filter module 80 in the N+1-stage shift register are connected to the N-X+1-stage positive pulse gate drive signal Nout[N-X+1] and the N-1-stage positive pulse gate drive signal Nout[N-1], respectively. The starting control line connected to the N+1-stage shift register is connected to the cascade signal, namely the N-stage positive pulse gate drive signal Nout[N]. The N+1-stage shift register outputs the corresponding N+1-stage negative pulse gate drive signal Pout[N+1] and the N+1-stage positive pulse gate drive signal Nout[N+1]. The N+1-stage negative pulse gate drive signal Pout[N+1] and the N+1-stage positive pulse gate drive signal Nout[N+1] are used to drive the second row of pixel circuits (Pixel).

[0240] The same logic can be applied to the other subsequent shift registers. It should be noted that, since the output terminals of some shift registers are connected to dummy pixels or left floating, the output terminals of the Nth stage shift register are not connected to the Nth row of pixel circuits. Instead, the number of rows of connected pixel circuits needs to be determined based on the number of shift registers connected to dummy pixels or left floating. For example, if the 1st to 3rd stage shift registers are connected to dummy pixels, then the output terminals of the Nth stage shift register are connected to the N-3rd row of pixel circuits.

[0241] The same can be applied to other subsequent shift registers.

[0242] The display panel shown in Figure 61 includes pixel circuits (Pixel) distributed in an array in the display area, the display panel shown in Figure 32 includes pixel circuits (Pixel) distributed in an array in the display area, a first gate drive circuit 151 providing a light-emitting control signal EM, a fourth gate drive circuit 154 providing a gate drive signal Pscan2, a second gate drive circuit 152 providing an N-level negative pulse gate drive signal Pout[N] and a gate drive signal Nscan, and a third gate drive circuit 153 providing an N-level negative pulse gate drive signal Pout[N] and a gate drive signal Nscan.

[0243] The first gate driving circuit 151 can be located on the left side of the display area. The output end of each shift register in the first gate driving circuit 151 provides a light emitting control signal EM to two adjacent rows of pixel circuits through the corresponding light emitting control line, which is a unilateral drive.

[0244] The fourth gate driving circuit 154 can be located on the right side of the display area. The output end of each shift register in the fourth gate driving circuit 154 provides a gate driving signal Pscan2 to a row of pixel circuits through a corresponding gate driving line, which is a unilateral driving.

[0245] The second gate drive circuit 152 is located between the first gate drive circuit 151 and the display area. The third gate drive circuit 153 is located between the fourth gate drive circuit 154 and the display area. A scan line that transmits the N-th level negative pulse gate drive signal Pout[N] is electrically connected to the output of a shift register in the second gate drive circuit 152, the output of a shift register in the third gate drive circuit 153, and a row of pixel circuits. A gate drive line that transmits the gate drive signal Nscan is electrically connected to the output of a shift register in the second gate drive circuit 152, the output of a shift register in the third gate drive circuit 153, and a row of pixel circuits, demonstrating bilateral drive.

[0246] The second gate drive circuit 152 and the third gate drive circuit 153 can both adopt the gate drive circuits shown in Figures 3 and 20. The gate drive signal Nscan can include the Nth level positive pulse gate drive signal Nout[N] and the N-3th level positive pulse gate drive signal Nout[N-3].

[0247] Since it is necessary for the gate of the first initialization transistor T4P in the pixel circuit shown in Figure 1 to be connected to the N-1th level positive pulse gate drive signal Nout[N-1], after the gate of the write transistor T2P in the pixel circuit shown in Figure 33 is connected to the Nth level negative pulse gate drive signal Pout[N] and the gate of the compensation transistor T3P is connected to the Nth level positive pulse gate drive signal Nout[N], not only can the gate of the third initialization transistor T8P continue to use the existing gate drive signal Pscan2 (there is no need to improve the fourth gate drive circuit 154), the gate of the first initialization transistor T4P can also be replaced with the N-3th level positive pulse gate drive signal Nout[N-3].

[0248] After that, the pixel circuit shown in Figure 62 can not only operate in the existing stage P12 in Figure 63 in one frame, but also add an additional stage P11. In this stage P11, the first initialization transistor T4P and the compensation transistor T3P can be synchronously turned on to reset the three-terminal (Q, A, B) potentials of the driving transistor T1P, so as to reduce the drift of the threshold voltage of the driving transistor T1P and improve the flicker under different refresh frequencies.

[0249] In one embodiment, this embodiment provides a display panel, which includes the gate driving circuit and the pixel circuit in at least one of the above embodiments.

[0250] It can be understood that since the display panel provided in this embodiment includes the gate driving circuit of at least one of the above-mentioned embodiments, the voltage regulation module 71 can also stabilize or reduce the gate potential of the second transistor T10 through a low voltage signal under the control of one of the fourth node P, the output end of the second output module 70, or the first node O[n+1] of the next-stage shift register, so that the second transistor T10 is stable or better in the cut-off state to reduce leakage current, and the potential of the second gate driving signal can be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate driving signal.

[0251] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this application, and all these changes or substitutions should fall within the scope of protection of the claims attached to this application.

Claims

1. A gate drive circuit, wherein: The gate driving circuit includes a plurality of shift registers, and the shift registers include: a level transmission signal selection module, the level transmission signal selection module being electrically connected between the first wiring and the first node; A pull-up control module, wherein the pull-up control module controls the potential of the second node according to the potential of the first node and the potential of the first clock signal; A first filtering module, wherein the first filtering module is electrically connected between the second node and the third node, and a control terminal of the first filtering module is connected to a reset signal; A second filtering module, the second filtering module is electrically connected between the first filtering module and the third node, and a control end of the second filtering module is connected to a filtering control signal; A first inverting module, wherein the first inverting module is connected between the second node and a fourth node; a first output module, wherein the first output module outputs a first gate driving signal according to the potential of the third node and the potential of the fourth node; a second output module, the second output module comprising a P-channel first transistor and an N-channel second transistor, a first electrode of the first transistor being electrically connected to a first high potential line, a second electrode of the first transistor being electrically connected to a first electrode of the second transistor to output a second gate drive signal, a second electrode of the second transistor being connected to a first low potential signal, and the second node being electrically connected to a gate of the first transistor and a gate of the second transistor; and A voltage regulating module, one end of which is connected to a low voltage signal, the other end of which is connected to the gate of the second transistor, and the control end of which is electrically connected to the fourth node, the output end of the second output module, or the first node of the next-stage shift register.

2. The gate drive circuit according to claim 1, wherein: The voltage regulating module includes a third transistor, a first electrode of the third transistor is connected to the low voltage signal, a second electrode of the third transistor is electrically connected to the gate of the second transistor, and the gate of the third transistor is electrically connected to the fourth node, the output end of the second output module or one of the first nodes of the next-stage shift register.

3. The gate driving circuit according to claim 2, wherein: The gate of the third transistor is electrically connected to the fourth node and one of the output terminals of the second output module, the low voltage signal is the first low potential signal, and the channel type of the third transistor is the same as the channel type of the second transistor.

4. The gate driving circuit according to claim 2, wherein: The gate of the third transistor is electrically connected to the fourth node and one of the output terminals of the second output module, the channel type of the third transistor is the same as the channel type of the second transistor, and the potential of the low voltage signal is lower than the potential of the first low potential signal.

5. The gate driving circuit according to claim 4, wherein: A difference between a potential of the first low potential signal and a potential of the low voltage signal is greater than or equal to 2V.

6. The gate driving circuit according to claim 4, wherein: The first inversion module comprises: a fourth P-channel transistor, wherein a first electrode of the fourth transistor is electrically connected to the second high potential line, a second electrode of the fourth transistor is electrically connected to the fourth node, and a gate of the fourth transistor is electrically connected to the second node; an N-channel fifth transistor, wherein a first electrode of the fifth transistor is electrically connected to the fourth node, a second electrode of the fifth transistor is connected to a second low potential signal, and a gate of the fifth transistor is electrically connected to the second node; The potential of the second low potential signal is lower than the potential of the low voltage signal.

7. The gate driving circuit according to claim 1, wherein: The second transistor is a dual-gate transistor, and a first gate of the second transistor is electrically connected to the second node and a second gate of the second transistor; The third transistor is a double-gate transistor, and a first gate of the third transistor is electrically connected to the fourth node and a second gate of the third transistor.

8. The gate driving circuit according to claim 2, wherein: The gate of the third transistor is electrically connected to the first node of the next-stage shift register, the low voltage signal is the first low potential signal, and the channel type of the third transistor is different from the channel type of the second transistor; The shift register also includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the second node, a second electrode of the sixth transistor is electrically connected to the gate of the first transistor, the gate of the sixth transistor is connected to the first clock signal, and a channel type of the sixth transistor is the same as that of the first transistor.

9. The gate driving circuit according to claim 8, wherein: The voltage regulating module is used to stabilize or reduce the low potential of the second node.

10. The gate driving circuit according to claim 9, wherein: The voltage regulating module is further used for stabilizing or reducing the gate potential of the second transistor during the duration of the positive pulse of the second gate driving signal.

11. The gate driving circuit according to claim 1, wherein: In one frame, when the gate driving circuit completes outputting each pulse of the first gate driving signal and each pulse of the second gate driving signal, the first clock signal is maintained at a low potential.

12. The gate driving circuit according to claim 11, wherein: The first output module outputs the connected second clock signal as the first gate drive signal according to the potential of the third node; when the pulse output of each of the first gate drive signal and each of the second gate drive signal of the gate drive circuit is completed, the second clock signal is maintained at a low potential.

13. A display panel, wherein: The display panel comprises: a pixel circuit including a write transistor for controlling input of a data signal and a compensation transistor for controlling input of the data signal to a gate of a drive transistor; and According to the gate driving circuit of claim 1, the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

14. The display panel according to claim 13, wherein: The voltage regulating module includes a third transistor, a first electrode of the third transistor is connected to the low voltage signal, a second electrode of the third transistor is electrically connected to the gate of the second transistor, and the gate of the third transistor is electrically connected to the fourth node, the output end of the second output module or one of the first nodes of the next-stage shift register.

15. The display panel according to claim 14, wherein: The gate of the third transistor is electrically connected to the fourth node and one of the output terminals of the second output module, the low voltage signal is the first low potential signal, and the channel type of the third transistor is the same as the channel type of the second transistor.

16. The display panel according to claim 14, wherein: The gate of the third transistor is electrically connected to the fourth node and one of the output terminals of the second output module, the channel type of the third transistor is the same as the channel type of the second transistor, and the potential of the low voltage signal is lower than the potential of the first low potential signal.

17. The display panel according to claim 16, wherein: A difference between a potential of the first low potential signal and a potential of the low voltage signal is greater than or equal to 2V.

18. The display panel according to claim 16, wherein: The first inversion module comprises: a fourth P-channel transistor, wherein a first electrode of the fourth transistor is electrically connected to the second high potential line, a second electrode of the fourth transistor is electrically connected to the fourth node, and a gate of the fourth transistor is electrically connected to the second node; an N-channel fifth transistor, wherein a first electrode of the fifth transistor is electrically connected to the fourth node, a second electrode of the fifth transistor is connected to a second low potential signal, and a gate of the fifth transistor is electrically connected to the second node; The potential of the second low potential signal is lower than the potential of the low voltage signal.

19. The display panel according to claim 13, wherein: The second transistor is a dual-gate transistor, and a first gate of the second transistor is electrically connected to the second node and a second gate of the second transistor; The third transistor is a double-gate transistor, and a first gate of the third transistor is electrically connected to the fourth node and a second gate of the third transistor.

20. The display panel according to claim 14, wherein: The gate of the third transistor is electrically connected to the first node of the next-stage shift register, the low voltage signal is the first low potential signal, and the channel type of the third transistor is different from the channel type of the second transistor; The shift register also includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the second node, a second electrode of the sixth transistor is electrically connected to the gate of the first transistor, the gate of the sixth transistor is connected to the first clock signal, and a channel type of the sixth transistor is the same as that of the first transistor.

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