Hybrid passivated back-contact cell without doped silicon crystal layer arranged on front face thereof, and preparation method therefor

Abstract

The present application belongs to the technical field of back-contact cell preparation, and particularly relates to a hybrid passivated back-contact cell without a doped silicon crystal layer arranged on a front face thereof, and a preparation method therefor. The method comprises: S101, forming in sequence a first semiconductor layer and a mask layer on a back face of a silicon wafer, both sides of which are polished; S102, performing first etching opening in the back face, so as to form second semiconductor opening areas; S103, performing texturing and cleaning; S104, depositing a first intrinsic amorphous silicon layer on the front face, and depositing a second semiconductor layer on the back face; S105, performing second etching opening in the second semiconductor layer on the back face; and S106, depositing a second transparent conductive film layer on the back face by using a magnetron sputtering process, and directly depositing a first transparent conductive film layer on the front face. The present application can effectively avoid a power attenuation problem caused by a PID effect occurring in a cell, so that one instance of PECVD coating can be reduced, thereby effectively reducing the reflectivity and reflection loss of a front face, and the quality of film layers is high, thereby improving the efficiency of conversion.

Description

Combined passivation back contact cell without doped silicon crystal layer on the front and preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application requests the priority and rights of the Chinese patent application with patent application number 2023113531686 filed with the State Intellectual Property Office of China on October 19, 2023, and the invention name is "Combined passivated back contact battery without doped silicon crystal layer on the front and preparation method", and the full text of which is incorporated into this application by reference. Technical Field

[0003] The present application belongs to the technical field of back contact cell preparation, and specifically relates to a combined passivation back contact cell without a doped silicon crystal layer on the front side and a preparation method thereof. Background Art

[0004] At present, the front passivation layer and anti-reflection layer in the back-contact battery are generally produced by PECVD (chemical vapor deposition technology) equipment; and the front passivation layer includes a passivation film layer and a doped silicon crystal layer. The passivation film layer is used to ensure the front passivation effect, and the doped silicon crystal layer is set to increase the band gap width and enhance the passivation effect. For example, the applicant's earlier patent application CN115312633B discloses a mask-less combined passivation back contact battery and a preparation method thereof, the method comprising the following steps: S101, providing a silicon wafer substrate, and polishing and cleaning the silicon wafer substrate in sequence; S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer substrate, S103, performing a first etching on the first semiconductor layer on the back side obtained in S102 to form a first opening area W1 distributed at intervals; S104, forming a velvet surface in the first opening area W1 on the back side by velveting and cleaning; S105, then removing the mask layer; S106, then forming a second semiconductor layer on the back side obtained in S105, S107, then performing a second etching on the polished area on the back side obtained in S106 to expose the first semiconductor layer, to form a second opening area W2 arranged at intervals from the first opening area W1; S108, forming a conductive film layer to fully cover the back side obtained in S107.

[0005] However, back-contact cell fabrication uses PECVD (chemical vapor deposition) equipment to create the front passivation layer and anti-reflection layer, resulting in high costs for battery manufacturing equipment. Furthermore, the front structure is prone to the PID effect (Potential Induced Degradation). PID directly harms battery components by accumulating a large amount of charge on the cell surface, exacerbating the surface passivation effect. This leads to a decrease in the cell's fill factor, open-circuit voltage, and short-circuit current, and a power degradation of the battery component, with the degradation rate reaching up to 50%.

[0006] It should be noted that this part of the content of this application only provides background technology related to this application, and does not necessarily constitute prior art or public knowledge.

[0007] Summary of the Invention

[0008] The purpose of this application is to overcome the defects of power attenuation and high investment cost of battery preparation equipment in the back contact battery of the prior art, and to provide a combined passivated back contact battery and a preparation method without a doped silicon crystal layer on the front. The combined passivated back contact battery prepared by this method can effectively avoid the power attenuation problem caused by the PID effect of the battery, can reduce one PECVD coating, and can greatly reduce the equipment investment cost. At the same time, the front structure provided by this application effectively reduces the reflectivity of the front of the battery, effectively reduces the reflection loss of the battery, and the film layer has high quality, which improves the photoelectric conversion efficiency of the battery.

[0009] To achieve the above objectives, in a first aspect, the present application provides a method for preparing a combined passivated back contact cell without a doped silicon crystal layer on the front side, comprising the following steps:

[0010] S101, forming a first semiconductor layer and a mask layer in sequence on the back side of a double-sided polished silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer;

[0011] S102, performing a first etching opening on the back surface obtained in S101 to form second semiconductor opening regions distributed at intervals;

[0012] S103, forming a velvet surface on the front side of the silicon wafer through texturing and cleaning, and then removing all mask layers;

[0013] S104, depositing a first intrinsic amorphous silicon layer on the front surface obtained in S103, and depositing a second semiconductor layer on the back surface; the second semiconductor layer includes a second intrinsic amorphous silicon layer and a second doped silicon crystal layer;

[0014] S105, performing a second etching opening on the second semiconductor layer on the back side obtained in S104 to expose the first semiconductor layer, forming a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning the silicon wafer;

[0015] S106. Then, a second transparent conductive film layer is deposited on the back side by a magnetron sputtering process, and the sputtering target voltage of the magnetron sputtering process is controlled to be 220V-300V; and a first transparent conductive film layer is directly deposited on the surface of the first intrinsic amorphous silicon layer on the front side, and the deposition of the first transparent conductive film layer adopts a plasma enhanced chemical vapor deposition process.

[0016] In some preferred embodiments of the present application, the thickness ratio of the second transparent conductive film layer to the first transparent conductive film layer is 1:1-1.35, preferably 1:1.02-1.2.

[0017] Preferably, the thickness of the second transparent conductive film layer is 50-150 nm, preferably 90-150 nm.

[0018] Preferably, the thickness of the first transparent conductive film layer is 80-200 nm, preferably 100-200 nm.

[0019] In some preferred embodiments of the present application, the first transparent conductive film layer and the second transparent conductive film layer are each independently selected from at least one of tin-doped indium oxide, aluminum-doped zinc oxide, and tungsten-doped indium oxide.

[0020] More preferably, the second transparent conductive film layer is selected from tin-doped indium oxide and / or aluminum-doped zinc oxide, and the first transparent conductive film layer is aluminum-doped zinc oxide.

[0021] In some preferred embodiments of the present application, the thickness ratio of the first intrinsic amorphous silicon layer to the first transparent conductive film layer is 1:12.5-21.5, preferably 1:15-19.

[0022] Preferably, the thickness of the first intrinsic amorphous silicon layer is 5-10 nm, more preferably 6-10 nm.

[0023] Preferably, the conditions of the plasma enhanced chemical vapor deposition process in S106 include: controlling the gas pressure to be 200Pa-1000Pa, the temperature to be 100-200°C, and the deposition power to be 500W-3000W. In some preferred embodiments of the present application, the preparation method further includes:

[0024] S107, performing a third etching opening on the portion of the first transparent conductive film layer located between the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S106 to form an insulating trench;

[0025] S108 , forming an insulating ink layer and a main gate electrode respectively at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S107 .

[0026] In the second aspect, the present application provides a combined passivated back contact battery without a doped silicon crystal layer on the front side, which includes a silicon wafer, a first semiconductor layer and a second semiconductor layer, and a second transparent conductive film layer arranged on the back side of the silicon wafer, and a first intrinsic amorphous silicon layer arranged on the front side of the silicon wafer; it also includes: a first transparent conductive film layer arranged on the surface of the first intrinsic amorphous silicon layer and in direct contact with it, and it is prepared by the preparation method described in the first aspect.

[0027] In some preferred embodiments of the present application, in a region between the first semiconductor opening region and the second semiconductor opening region, in a direction perpendicular to the silicon wafer, the first semiconductor layer and the second semiconductor layer are in direct contact with each other. Beneficial effects:

[0028] The present application adopts the above-mentioned technical solution, especially in the post-texturing method of the combined passivation structure, in particular, a superimposed structure of a first intrinsic amorphous silicon layer and a first transparent conductive film layer is adopted on the front side without providing a doped silicon crystal layer and a conventional anti-reflection layer, and the corresponding transparent conductive film layers are prepared by different methods on the front and back sides respectively. This can effectively avoid the PID effect of the battery while ensuring the passivation effect, that is, there is no insulating layer that accumulates charge under high voltage bias conditions, and the PID phenomenon will not occur; and because the doped silicon crystal layer is not provided, one PECVD coating can be reduced, which can greatly reduce the equipment investment cost. At the same time, the front side structure provided by the present application can ensure sufficient front side passivation effect, while effectively reducing the reflectivity of the front side of the battery, effectively reducing the battery reflection loss, thereby improving the photoelectric conversion efficiency of the battery. Among them, the use of an appropriate low range of sputtering target voltage is conducive to minimizing the damage to the film layer caused by ion bombardment; under the same conditions, if the sputtering target voltage is not within the above range, if it is too large, the film damage caused by ion bombardment will be increased, and if it is too small, it will not be deposited to the required thickness.

[0029] Compared to conventional thermal evaporation methods for preparing transparent conductive film layers, the present invention uses a magnetron sputtering process to deposit a second transparent conductive film layer on the back side and a plasma-enhanced chemical vapor deposition process to form a first transparent conductive film layer on the front side. This method uses different preparation processes. Due to the single structure of the front film layer, the plasma-enhanced chemical vapor deposition process ensures that the interface adhesion of the corresponding film layers on the front and back sides is good, resulting in a high density and good uniformity of the corresponding film layer, with fewer pinholes and high overall film quality, avoiding damage to the front film layer caused by ion bombardment caused by magnetron sputtering. Moreover, the present invention uses a plasma-enhanced chemical vapor deposition process to form the first transparent conductive film layer on the front side. This method forms the film at a low temperature, has a low degree of thermal damage, reduces damage to the first intrinsic amorphous silicon layer, and maximizes the preservation of the battery body minority carrier life, thereby improving the battery's photoelectric conversion efficiency. Since the back side is a multi-layer stacked structure with a thicker film layer, a magnetron sputtering process can be used. The overall equipment cost of magnetron sputtering is lower than that of chemical vapor deposition equipment, and its performance is conducive to improving the battery's short-circuit current. The preparation method of the present application has low equipment cost and minimal film damage. However, under the same conditions, if the transparent conductive film layers are deposited using the same method on both the front and back sides, such as using magnetron sputtering, significant film damage will occur, affecting the product's passivation effect. The most direct consequence is a lower open-circuit voltage of the battery. If both sides use plasma-enhanced chemical vapor deposition, the main result is high equipment cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0031] FIG1 is a process flow chart of the preparation method of the present application.

[0032] FIG2 is a schematic structural diagram of depositing a second transparent conductive film layer in a combined passivated back contact cell according to Example 1 of the present application;

[0033] FIG3 is a schematic structural diagram of the combined passivation back contact cell prepared in Example 1 of the present application.

[0034] FIG4 is a schematic structural diagram of a conventional combined passivation back contact cell of Comparative Example 1.

[0035] Explanation of the accompanying symbols: 1. Silicon wafer, 2a. Tunneling oxide layer, 2b. N-type doped polysilicon layer, 3. Anti-reflection layer, 4. First intrinsic amorphous silicon layer, 5a. Second intrinsic amorphous silicon layer, 5b. P-type doped amorphous silicon layer, 6. Second transparent conductive film layer, 7. First transparent conductive film layer, 8. Main gate electrode, 9. N-type doped amorphous silicon. DETAILED DESCRIPTION

[0036] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0037] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0038] In a first aspect, the present application provides a method for preparing a combined passivated back contact cell without a doped silicon crystal layer on the front side, comprising the following steps:

[0039] S101, forming a first semiconductor layer and a mask layer in sequence on the back side of a double-sided polished silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer;

[0040] S102, performing a first etching opening on the back surface obtained in S101 to form second semiconductor opening regions distributed at intervals;

[0041] S103, forming a velvet surface on the front side of the silicon wafer through texturing and cleaning, and then removing all mask layers;

[0042] S104, depositing a first intrinsic amorphous silicon layer on the front surface obtained in S103, and depositing a second semiconductor layer on the back surface; the second semiconductor layer includes a second intrinsic amorphous silicon layer and a second doped silicon crystal layer;

[0043] S105, performing a second etching opening on the second semiconductor layer on the back side obtained in S104 to expose the first semiconductor layer, forming a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning the silicon wafer;

[0044] S106. Then, a second transparent conductive film layer is deposited on the back side by a magnetron sputtering process, and the sputtering target voltage of the magnetron sputtering process is controlled to be 220V-300V; and a first transparent conductive film layer is directly deposited on the surface of the first intrinsic amorphous silicon layer on the front side, and the deposition of the first transparent conductive film layer adopts a plasma enhanced chemical vapor deposition process.

[0045] In this application, the front side is not provided with a doped silicon crystal layer, and the doped silicon crystal layer refers to doped amorphous silicon or doped microcrystalline silicon. Since no doped silicon crystal layer is provided, one PECVD coating can be reduced, which can greatly reduce the equipment investment cost.

[0046] In some preferred embodiments of the present application, the thickness ratio of the second transparent conductive film layer to the first transparent conductive film layer is 1:1-1.35, preferably 1:1.02-1.2, and more preferably 1:1.02-1.10. This preferred solution, using a second transparent conductive film layer and a first transparent conductive film layer with an appropriate thickness ratio on the front and back surfaces, can effectively ensure the anti-reflection effect of the film layer, further facilitate the collection of battery carriers, and further improve the battery's conversion efficiency and short-circuit current density.

[0047] On the basis of satisfying the above thickness ratio, preferably, the thickness of the second transparent conductive film layer is 50-150 nm, preferably 90-150 nm. Preferably, the thickness of the first transparent conductive film layer is 80-200 nm, preferably 100-200 nm.

[0048] Specific types of transparent conductive film layers in the art can be used in this application. In some preferred embodiments of this application, the first transparent conductive film layer and the second transparent conductive film layer are each independently selected from at least one of tin-doped indium oxide, aluminum-doped zinc oxide, and tungsten-doped indium oxide.

[0049] More preferably, the second transparent conductive film layer is selected from tin-doped indium oxide and / or aluminum-doped zinc oxide, and the first transparent conductive film layer is aluminum-doped zinc oxide.

[0050] In some preferred embodiments of the present application, the thickness ratio of the first intrinsic amorphous silicon layer to the first transparent conductive film layer is 1:12.5-21.5, preferably 1:15-19. This preferred solution provides the appropriate thickness of the corresponding layers on the front surface, effectively ensuring the passivation and anti-reflection effects on the front surface, further improving the conversion efficiency and short-circuit current density of the battery.

[0051] When the above thickness ratio is satisfied, preferably, the thickness of the first intrinsic amorphous silicon layer is 5-10 nm.

[0052] The type and thickness of the mask layer in S101 of the present application can be selected according to the corresponding ranges in the prior art. For example, the mask layer is at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0053] The first etching opening in S102 of the present application is used to remove the first semiconductor layer and the mask layer in the second semiconductor opening region, during which part of the first semiconductor layer may remain unremoved. This remaining part can be removed during the texturing and cleaning in S103.

[0054] In S103 of the present application, it is understood that during the texturing and cleaning process, a textured surface is formed not only on the front surface of the silicon wafer, but also in the second semiconductor opening region. The textured surface in S103 is a pyramid textured surface.

[0055] The deposition of the first intrinsic amorphous silicon layer and the second semiconductor layer in S104 can both be performed using PECVD. It is understood that the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer in the second semiconductor layer can be deposited separately using the same equipment and the same method. For example, the first intrinsic amorphous silicon layer can be deposited first, and then the second semiconductor layer can be deposited.

[0056] The thickness of each layer in the first semiconductor layer and the second semiconductor layer in the present application and the corresponding doping concentration can be selected according to the corresponding range in the prior art, such as the corresponding range in the early combined passivation battery of the applicant. For example, the thickness of the tunneling oxide layer is 1.5-2.5nm, and the thickness of the first doped polycrystalline layer is 150-300nm; the thickness of the second intrinsic amorphous silicon layer is 5-15nm, and the thickness of the second doped silicon crystal layer is 10-20nm.

[0057] In S105, those skilled in the art can select the sizes of the first semiconductor opening region and the second semiconductor opening region according to needs. For example, the width W1 of the first semiconductor opening region can be 100-300 μm, the width W2 of the second semiconductor opening region can be 300-700 μm, and the spacing Wg between the first semiconductor opening region and the second semiconductor opening region can be 50-400 μm.

[0058] The sputtering time of the magnetron sputtering process in S106 can be determined according to the required thickness.

[0059] Preferably, the plasma-enhanced chemical vapor deposition process conditions in S106 include: controlling the gas pressure to 200 Pa-1000 Pa, the temperature to 100-200° C., and the deposition power to 500 W-3000 W. In this preferred embodiment, the first transparent conductive film layer can be deposited at low temperatures, with minimal thermal damage, a fast deposition rate, and good film quality.

[0060] Other conventional layers and steps may also be provided in this application. In some embodiments of this application, the preparation method further includes: S107, performing a third etching opening on the portion of the first transparent conductive film layer located between the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S106 to form an insulating trench; S108, forming an insulating ink layer and a main gate electrode in the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S107, respectively.

[0061] The insulating groove width W3 may be 30-200 μm.

[0062] It is understood that the insulating ink layer is disposed between the second transparent conductive film layer and the main gate electrode and is arranged in an intermittent manner. The main gate electrodes are disposed in both the first semiconductor opening region and the second semiconductor opening region, and the electrodes in different opening regions have different polarities. The insulating ink layer is used to isolate the second transparent conductive film layer and the main gate electrode of different polarities in the same column. The main gate electrode is used to connect the corresponding second transparent conductive film layers in the first semiconductor opening region and the second semiconductor opening region in series. Their mutual structures can be carried out according to the structures in the prior art, as long as two electrodes of different polarities can be formed to transmit current. This application is not limited to this. The insulating ink layer can be formed by printing or spraying, and the thickness of the insulating ink layer can be 5-50μm.

[0063] The first etching opening, the second etching opening and the third etching opening of the present application can all be carried out by laser or chemical etching, and those skilled in the art can freely choose according to needs.

[0064] In a second aspect, the present application provides a combined passivated back-contact cell without a doped silicon crystal layer on the front side, comprising a silicon wafer, a first semiconductor layer, a second semiconductor layer, and a second transparent conductive film layer disposed on the back side of the silicon wafer, and a first intrinsic amorphous silicon layer disposed on the front side of the silicon wafer; further comprising: a first transparent conductive film layer disposed on the surface of the first intrinsic amorphous silicon layer and in direct contact therewith, and produced by the production method described in the first aspect. The combined passivated back-contact cell produced by the production method of the present application has good interfacial adhesion between the first and second transparent conductive film layers and the adjacent film layers, resulting in high density and uniformity of the corresponding film layers, few pinholes, and high overall film quality, thereby facilitating improved cell conversion efficiency.

[0065] In some preferred embodiments of the present application, in a region between the first semiconductor opening region and the second semiconductor opening region, in a direction perpendicular to the silicon wafer, the first semiconductor layer and the second semiconductor layer are in direct contact with each other.

[0066] The other battery structures of this application are the same as those of the applicant's earlier patent CN115312633B.

[0067] The embodiments of the present application are described in detail below. These embodiments are exemplary and are only used to explain the present application. They should not be construed as limiting the present application.

[0068] Example 1

[0069] A combined passivated back contact cell without a doped silicon crystal layer on the front side is obtained by the following preparation method: as shown in FIG1 ,

[0070] S101, coating the back side of a double-sided polished silicon wafer 1 with a first semiconductor layer and a mask layer in sequence, wherein the first semiconductor layer is a tunneling oxide layer 2a and an N-type doped polysilicon layer 2b, and the mask layer is silicon nitride;

[0071] S102, performing a first etching opening on the back side of the silicon wafer 1 to remove the mask layer and a portion of the first semiconductor layer to form a second semiconductor opening region;

[0072] S103, texturing and cleaning the silicon wafer 1 to form a pyramid textured surface on the front side of the silicon wafer 1, while removing the remaining first semiconductor layer in the second semiconductor opening region on the back side of the silicon wafer 1, and then removing all mask layers to form a silicon wafer 1 with a single-side textured and single-side polished structure;

[0073] S104, depositing a first intrinsic amorphous silicon layer 4 with a thickness of 7 nm on the front side of the silicon wafer 1, and depositing a second semiconductor layer on the back side, wherein the second semiconductor layer comprises a second intrinsic amorphous silicon layer 5 a and a P-type doped amorphous silicon layer 5 b, both of which are deposited by PECVD;

[0074] S105, performing a second etching opening on the back side of the silicon wafer 1 to expose the first semiconductor layer, forming a first semiconductor opening region spaced apart from a second semiconductor opening region, wherein the first semiconductor opening region has a width W1 of 200 μm, the second semiconductor opening region has a width W2 of 400 μm, and the spacing Wg between the first semiconductor opening region and the second semiconductor opening region is 80 μm, as shown in FIG2; the silicon wafer 1 is then cleaned;

[0075] S106, depositing a second transparent conductive film layer 6 on the back side of the silicon wafer 1, wherein the second transparent conductive film layer 6 is deposited by a magnetron sputtering PVD process, wherein the second transparent conductive film layer 6 is tin-doped indium oxide (ITO), the sputtering target voltage is 250 V, and the sputtering time is such that the thickness of the second transparent conductive film layer 6 is 100 nm;

[0076] A first transparent conductive film layer 7 is deposited on the front surface using PECVD (plasma-enhanced chemical vapor deposition). As shown in Figure 2 , the PECVD process controls the gas pressure to 500 Pa, the temperature to 150°C, and the deposition power to 1000 W. The first transparent conductive film layer 7 is made of aluminum-doped zinc oxide (AZO) and has a thickness of 106 nm. The thickness ratio of the second transparent conductive film layer to the first transparent conductive film layer is 1:1.06. This deposition method forms the film at low temperatures, resulting in minimal thermal damage, minimizing damage to the intrinsic amorphous silicon layer and maximizing the minority carrier lifetime of the cell.

[0077] S107 , performing a third etching opening on the portion of the first transparent conductive film layer 7 located between the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S106 to form an insulating groove with a width W3 of 50 μm, as shown in FIG2 .

[0078] S108, forming an insulating ink layer arranged at intervals on the second transparent conductive film layer 6 on the back side of the silicon wafer 1, wherein the insulating ink is formed by printing and has a thickness of 10 μm;

[0079] As shown in FIG3 , a main gate electrode 8 is printed on the back of the silicon wafer 1 , and the first transparent conductive film layer 7 and the second transparent conductive film layer 6 on the first semiconductor opening region and the second semiconductor opening region are connected in series to form a silver paste gate line electrode.

[0080] Example 2

[0081] The method of Example 1 was followed, except that the sputtering target voltage was controlled to 240 V during the preparation of the second transparent conductive film layer, so that the thickness of the second transparent conductive film layer was 80 nm, and other conditions remained unchanged.

[0082] Example 3

[0083] The method of Example 1 is referred to, except that the thickness of the first transparent conductive film layer is changed to 100 nm. To obtain this thickness, the conditions in the plasma enhanced chemical vapor deposition process need to be adjusted: the gas pressure is 800 Pa, the temperature is 180°C, and the deposition power is 1500 W.

[0084] Example 4

[0085] The method of Example 1 is referred to, except that the thickness of the first intrinsic amorphous silicon layer is changed to 5 nm.

[0086] Comparative Example 1

[0087] The method of Example 1 was followed, except that the front side structure of the silicon wafer 1 was different. As shown in FIG4 , a first intrinsic amorphous silicon layer 4, an N-type doped amorphous silicon layer 9, and an anti-reflection layer 3 were sequentially provided on the front side. The anti-reflection layer 3 was made of silicon nitride. The thickness of the first intrinsic amorphous silicon layer 4 was the same as in Example 1, the thickness of the N-type doped amorphous silicon layer 9 was 10 nm, and the thickness of the anti-reflection layer 3 was 100 nm.

[0088] Comparative Example 2

[0089] The method of Example 1 is referred to, except that the second transparent conductive film layer in S106 is deposited by thermal evaporation, and has the same thickness as that of Example 1.

[0090] Comparative Example 3

[0091] The method of Example 1 is referred to, except that the second transparent conductive film layer in S106 is deposited by activated plasma sputtering RPD, the plasma processing power is 100W, the anode discharge voltage is 80V, and the thickness is the same as that of Example 1.

[0092] Test Case

[0093] The combined passivated back contact cells prepared in the above examples and comparative examples were respectively subjected to different preparation process parameters and tested for their related performance using the same method, with the results shown in Table 1. The PID loss rate was tested using the voltage stress method.

[0094] Table 1

[0095] Note: Equipment investment is in GW. Other examples are based on Comparative Example 1 as a reference. Comparative Example 1 is calculated as "1", that is, the corresponding equipment investment value of other examples / equipment investment value of the comparative example is the corresponding data in the above table;

[0096] The above-mentioned performance data shows that, compared to Comparative Example 1, which has a conventional front-side doped silicon crystal layer, the combined passivated back-contact cell produced using the method of the present application can effectively avoid the power attenuation problem caused by the PID effect in the cell, can reduce one PECVD coating step, and can significantly reduce equipment investment costs. At the same time, the front-side structure provided by the present application effectively reduces the reflectivity of the cell front side, effectively reduces the cell reflection loss, and has a high film quality, thereby improving the cell conversion efficiency and short-circuit current density. Comparative Example 1, which has a conventional structure, and Comparative Examples 2-3, which do not use the method of the present application, cannot achieve the excellent comprehensive effects of the present application.

[0097] Furthermore, according to Examples 1 and 2-4 of the present application, it can be seen that adopting the preferred thickness ratio scheme of the second transparent conductive film layer to the first transparent conductive film layer or the thickness ratio scheme of the first intrinsic amorphous silicon layer to the first transparent conductive film layer of the present application is more conducive to further improving the conversion efficiency and short-circuit current density of the battery at the same time.

[0098] The preferred embodiments of the present application are described in detail above, but the present application is not limited thereto. Within the technical concept of the present application, various simple modifications can be made to the technical solution of the present application, including combining the various technical features in any other appropriate manner. These simple modifications and combinations should also be regarded as the contents disclosed in the present application and fall within the scope of protection of the present application. Industrial Applicability

[0099] The present application utilizes the above-mentioned technical solutions, particularly in the post-texturing method for a combined passivation structure. Specifically, a superimposed structure of a first intrinsic amorphous silicon layer and a first transparent conductive film layer is employed on the front side, without a doped silicon crystal layer or conventional anti-reflection layer. The corresponding transparent conductive film layers are prepared using different methods on the front and back sides, effectively preventing the PID effect in the battery while ensuring passivation. Specifically, the absence of an insulating layer that accumulates charge under high-voltage bias conditions prevents PID. Furthermore, the absence of a doped silicon crystal layer reduces one PECVD coating step, significantly reducing equipment investment costs. Furthermore, the front side structure provided by the present application ensures sufficient front side passivation while effectively reducing the reflectivity of the battery front side and the reflection loss, thereby improving the battery's photoelectric conversion efficiency. Furthermore, employing a sputtering target voltage within a suitable low range helps minimize film damage caused by ion bombardment. Under the same conditions, if the sputtering target voltage is outside the above range, if it is too high, the film damage caused by ion bombardment will be increased, while if it is too low, the desired thickness cannot be deposited. Therefore, the combined passivation back contact battery designed by the present application is conducive to industrial promotion and application.

Claims

1. A method for preparing a combined passivation back contact cell without a doped silicon crystal layer on the front side, comprising the following steps: S101, forming a first semiconductor layer and a mask layer in sequence on the back side of a double-sided polished silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer; S102, performing a first etching opening on the back surface obtained in S101 to form second semiconductor opening regions distributed at intervals; S103, forming a velvet surface on the front side of the silicon wafer by velvet cleaning, and then removing all mask layers; characterized in that: S104, depositing a first intrinsic amorphous silicon layer on the front surface obtained in S103, and depositing a second semiconductor layer on the back surface; the second semiconductor layer includes a second intrinsic amorphous silicon layer and a second doped silicon crystal layer; S105, performing a second etching opening on the second semiconductor layer on the back side obtained in S104 to expose the first semiconductor layer, forming a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning the silicon wafer; S106. Then, a second transparent conductive film layer is deposited on the back side by a magnetron sputtering process, and the sputtering target voltage of the magnetron sputtering process is controlled to be 220V-300V; and a first transparent conductive film layer is directly deposited on the surface of the first intrinsic amorphous silicon layer on the front side, and the deposition of the first transparent conductive film layer adopts a plasma enhanced chemical vapor deposition process.

2. The preparation method according to claim 1, characterized in that: The thickness ratio of the second transparent conductive film layer to the first transparent conductive film layer is 1:1-1.

35.

3. The preparation method according to claim 2, characterized in that: The thickness of the second transparent conductive film layer is 50-150 nm, and the thickness of the first transparent conductive film layer is 80-200 nm.

4. The preparation method according to any one of claims 1 to 3, characterized in that: The first transparent conductive film layer and the second transparent conductive film layer are independently selected from at least one of tin-doped indium oxide, aluminum-doped zinc oxide, and tungsten-doped indium oxide.

5. The preparation method according to claim 4, characterized in that: The second transparent conductive film layer is selected from tin-doped indium oxide and / or aluminum-doped zinc oxide, and the first transparent conductive film layer is aluminum-doped zinc oxide.

6. The preparation method according to any one of claims 1 to 5, characterized in that: The thickness ratio of the first intrinsic amorphous silicon layer to the first transparent conductive film layer is 1:12.5-21.5, and the thickness of the first intrinsic amorphous silicon layer is 5-10 nm.

7. The preparation method according to any one of claims 1 to 6, characterized in that: The conditions of the plasma enhanced chemical vapor deposition process described in S106 include: controlling the gas pressure to be 200Pa-1000Pa, the temperature to be 100-200°C, and the deposition power to be 500W-3000W.

8. The preparation method according to any one of claims 1 to 7, characterized in that: The preparation method further comprises: S107, performing a third etching opening on the first transparent conductive film layer portion located between the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S106 to form an insulating groove; S108, forming an insulating ink layer and a main gate electrode respectively at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S107.

9. A combined passivation back contact cell without a doped silicon crystal layer on the front side, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer, and a second transparent conductive film layer arranged on the back side of the silicon wafer, and a first intrinsic amorphous silicon layer arranged on the front side of the silicon wafer; characterized in that: Also includes: A first transparent conductive film layer is disposed on the surface of the first intrinsic amorphous silicon layer and is in direct contact with the first intrinsic amorphous silicon layer, and is prepared by the preparation method according to any one of claims 1 to 8.

10. The combined passivation back contact cell according to claim 9, characterized in that: In a region between the first semiconductor opening region and the second semiconductor opening region, the first semiconductor layer and the second semiconductor layer are in direct contact with each other in a direction perpendicular to the silicon wafer.

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