Semiconductor device with isolation structure, and manufacturing method for isolation structure

Abstract

The present application relates to a semiconductor device with an isolation structure, and a manufacturing method for an isolation structure. The semiconductor device comprises: a substrate (110); a first doped region (112), which is located on the substrate (110), wherein the doping concentration of the first doped region (112) is below the doping concentration of the substrate (110); a junction isolation structure, which comprises a first buried region (122), and a second buried region (124) which is in direct contact with the first buried region (122), wherein the first buried region (122) is located on the first doped region (112), the second buried region (124) is located on the first buried region (122), and the doping concentration of the second buried region (124) is below the doping concentration of the first buried region (122); a second doped region (130), which is located on the second buried region (124); and a device body region (140), which is located in the second doped region (130). In the present application, a hole barrier layer is formed on surfaces of the first buried region and second buried region, such that holes can be prevented from passing through the hole barrier layer to transit to the substrate to cause substrate electric leakage, thereby improving the latch-up effect of a device. Moreover, since a first doped region is provided, the width of an effective base region can be increased by using a base widening effect, thereby effectively reducing parasitic leakage flowing into a substrate.

Description

Semiconductor device with isolation structure and method for manufacturing isolation structure

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on October 30, 2023, with application number 2023114283240, and application name “Semiconductor device with isolation structure and manufacturing method of isolation structure”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor device with an isolation structure, and also to a method for manufacturing the isolation structure. Background Art

[0003] The exemplary fully isolated structure uses an N-type buried layer to isolate the substrate from the internal structure of the device (ie, isolation is performed using junction isolation) to meet diverse circuit applications.

[0004] However, the isolation junction formed by this N-type buried layer can create a parasitic BJT (bipolar junction transistor). In an H-bridge circuit, freewheeling current through the semiconductor device's body diode during the dead time can trigger this parasitic BJT, resulting in substrate leakage. For the low-side device in a half-bridge circuit, this parasitic BJT can even cause latch-up, potentially damaging the device.

[0005] Summary of the Invention

[0006] Based on this, it is necessary to provide a semiconductor device with an isolation structure that can improve the latch-up effect.

[0007] A semiconductor device with an isolation structure comprises: a substrate having a second conductivity type; a first doped region located on the substrate and having the second conductivity type, the doping concentration of the first doped region being less than the doping concentration of the substrate; a junction isolation structure comprising a first buried region and a second buried region directly in contact with the first buried region, the first buried region being located on the first doped region and having the first conductivity type, the second buried region being located on the first buried region and having the first conductivity type, the doping concentration of the second buried region being less than the doping concentration of the first buried region; the first conductivity type and the second conductivity type being opposite conductivity types; a second doped region having the second conductivity type being located on the second buried region; wherein the junction isolation structure is used to achieve insulating isolation between the substrate and the second doped region.

[0008] The above-mentioned semiconductor device with an isolation structure comprises a first buried region and a second buried region. Due to the difference in carrier concentration between the first buried region and the second buried region, a built-in electric field is formed at the interface between the first buried region and the second buried region. Due to the existence of this electric field, a carrier blocking layer is formed at this interface. Specifically, for an embodiment in which the first conductivity type is N-type and the second conductivity type is P-type, the carrier blocking layer is a hole blocking layer, which can prevent holes in the second doped region from passing through the hole blocking layer and crossing to the substrate to form substrate leakage, thereby improving the latch-up effect of the device. For an embodiment in which the first conductivity type is P-type and the second conductivity type is N-type, the carrier blocking layer is an electron blocking layer, which can prevent electrons in the second doped region from passing through the electron blocking layer and crossing to the substrate to form substrate leakage, thereby also improving the latch-up effect of the device. Even if the parasitic transistor formed by the second doped region-junction isolation structure-first doped region and the substrate is turned on, due to the provision of the first doped region of the second conductivity type, the width of the effective base region becomes wider according to the base region expansion effect, thereby effectively reducing the parasitic leakage flowing into the substrate.

[0009] In one embodiment, the first doping region has a doping dose not exceeding 3E14 cm -2 epitaxial layer.

[0010] In one embodiment, the thickness of the first doped region is not less than 10 microns.

[0011] In one embodiment, the resistivity of the substrate is less than 0.01 Ω·cm.

[0012] In one embodiment, the semiconductor device further includes a device body region, and the device body region is located in the second doped region.

[0013] In one embodiment, the semiconductor device further includes a lateral isolation structure surrounding the device body region in a laterally direction, wherein the lateral isolation structure is located in the second doped region and on the second buried region.

[0014] In one embodiment, the lateral isolation structure includes a first conductivity type region.

[0015] In one embodiment, the lateral isolation structure comprises an insulating material.

[0016] In one embodiment, the lateral isolation structure includes an insulating layer arranged on the inner wall of the isolation trench, and a conductive structure electrically connected to the second buried area is also provided in the isolation trench. The insulating layer insulates and isolates the conductive structure in the laterally direction, and the conductive structure is used to lead the second buried area out to the upper surface of the semiconductor device.

[0017] In one embodiment, the bottom of the second buried region is in direct contact with the top of the first buried region.

[0018] In one embodiment, the doping concentration of the first buried region is not less than 1E19 cm -3 , the doping concentration of the second buried region is not higher than 1E17 cm -3 .

[0019] In one embodiment, the thickness of the second buried region is smaller than the thickness of the first buried region.

[0020] In one embodiment, the device body region includes a drift region, and the drift region is separated from the second buried region by the second doped region.

[0021] In one embodiment, the second doped region is an epitaxial layer.

[0022] In one embodiment, the drift region has a first conductivity type.

[0023] In one embodiment, the semiconductor device comprises a lateral device.

[0024] In one embodiment, the semiconductor device includes a lateral double diffused metal oxide semiconductor field effect transistor.

[0025] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0026] It is also necessary to provide a method for manufacturing an isolation structure.

[0027] A method for manufacturing an isolation structure, comprising: obtaining a substrate, on which a first doped region is formed; the substrate and the first doped region have a second conductivity type, and the doping concentration of the first doped region is less than the doping concentration of the substrate; forming a first buried region on the first doped region, the first buried region having the first conductivity type; forming a second buried region on the first buried region in direct contact with the first buried region, the second buried region having the first conductivity type and a doping concentration less than the doping concentration of the first buried region; and forming a second doped region on the second buried region.

[0028] In the above-described method for manufacturing an isolation structure, a carrier concentration difference exists between the first and second buried regions of the junction isolation structure. Consequently, a built-in electric field forms at the interface between the first and second buried regions. This electric field creates a hole blocking layer at this interface, preventing holes in the second doped region from passing through the hole blocking layer and escaping to the substrate, thereby causing substrate leakage. This improves the latch-up effect of the device. Furthermore, even if the parasitic transistor formed by the second doped region, junction isolation structure, first doped region, and substrate is turned on, the presence of the first doped region of the second conductivity type increases the effective base width due to the base extension effect, effectively reducing parasitic leakage into the substrate.

[0029] In one embodiment, the step of forming the first buried region on the first doped region includes: injecting first conductive type ions into the first doped region, and then performing a push-trap, the push-trap temperature being above 1000 degrees Celsius and the time being above 100 minutes.

[0030] In one embodiment, the doping concentration of the first buried region is at least 100 times higher than that of the second buried region.

[0031] In one embodiment, after the step of forming the second doped region on the second buried region, the method further includes the step of forming a device body region in the second doped region.

[0032] In one embodiment, the device body region includes a drift region.

[0033] In one embodiment, the drift region has a first conductivity type.

[0034] In one embodiment, the step of forming the second doped region on the second buried region is growing an epitaxial layer.

[0035] In one embodiment, the semiconductor device comprises a lateral device.

[0036] In one embodiment, the semiconductor device includes a lateral double diffused metal oxide semiconductor field effect transistor.

[0037] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0039] FIG1 is a schematic cross-sectional view of a semiconductor device having an isolation structure according to an embodiment of the present application;

[0040] 2 is a schematic diagram of the electric field direction of a junction isolation structure of a semiconductor device with an isolation structure in another embodiment of the present application;

[0041] FIG3 is an equivalent circuit diagram of the structure shown in FIG1 ;

[0042] 4a to 4c are schematic cross-sectional views of devices according to three different embodiments of the present application having a lateral isolation structure 150;

[0043] FIG5 is a flow chart of a method for manufacturing an isolation structure according to an embodiment of the present application;

[0044] 6 a to 6 c are schematic cross-sectional views of the junction isolation structure during the process of manufacturing the isolation structure using the method shown in FIG. 5 . DETAILED DESCRIPTION

[0045] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0048] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0051] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0052] The present application provides an isolation structure that can be applied to all semiconductor devices requiring junction isolation. Figure 1 is a schematic cross-sectional view of a semiconductor device with an isolation structure according to one embodiment of the present application. The semiconductor device includes a substrate 110, a first doped region 112, a junction isolation structure (including a first buried region 122 and a second buried region 124), and a second doped region 130. Substrate 110 is a semiconductor substrate, and its material can be undoped single-crystalline silicon, single-crystalline silicon doped with impurities, or at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In the embodiment shown in Figure 1, substrate 110 is a single-crystalline silicon substrate of the second conductivity type. In one embodiment of the present application, substrate 110 is a heavily doped substrate to achieve a lower resistivity. In one embodiment of the present application, the resistivity of substrate 110 is less than 0.01 Ω·cm. First doped region 112 is located on substrate 110 and has the second conductivity type. The doping concentration of first doped region 112 is lower than the doping concentration of substrate 110.

[0053] The first buried region 122 is located on the first doped region 112. The second buried region 124 is located on the first buried region 122 and is in direct contact with the first buried region 122. The first buried region 122 and the second buried region 124 have a first conductivity type, and the doping concentration of the second buried region 124 is less than the doping concentration of the first buried region 122. In the embodiment shown in Figure 1, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type may also be P-type and the second conductivity type may be N-type. The embodiment in which the first conductivity type is N-type and the second conductivity type is P-type is particularly suitable for the BCD process commonly used in medium and low voltage devices. The junction isolation structure is used to achieve insulation isolation between the substrate 110 and the second doped region 130. The insulation isolation refers to the ability to reduce or even isolate leakage, rather than having the insulation properties of a general non-conductive insulating material.

[0054] The second doped region 130 is located on the second buried region 124 .

[0055] The above-mentioned semiconductor device with an isolation structure includes a first buried region 122 and a second buried region 124. Due to the carrier concentration difference between the first buried region 122 and the second buried region 124, a built-in electric field is generated at the interface between the first buried region 122 and the second buried region 124. Due to the presence of this electric field, a carrier blocking layer is formed at this interface. In one embodiment, for an embodiment where the first conductivity type is N-type and the second conductivity type is P-type, the carrier blocking layer is a hole blocking layer, which can prevent holes in the second doped region 130 from passing through the hole blocking layer and transferring to the first doped region 112 and the substrate 110, thereby causing substrate leakage, thereby improving the latch-up effect of the device. In one embodiment, for an embodiment where the first conductivity type is P-type and the second conductivity type is N-type, the carrier blocking layer is an electron blocking layer, which can prevent electrons in the second doped region 130 from passing through the electron blocking layer and transferring to the first doped region 112 and the substrate 110, thereby causing substrate leakage, thereby also improving the latch-up effect of the device. Even if the parasitic transistor formed by the second doped region 130, the junction isolation structure, the first doped region 112, and the substrate 110 is turned on, the presence of the second conductivity type first doped region 112 increases the effective base width due to the base extension effect, thereby effectively reducing parasitic leakage into the substrate. Furthermore, the first doped region 112 ensures that the junction isolation structure has a high withstand voltage.

[0056] In the embodiment shown in FIG. 1 , the semiconductor device with the isolation structure further includes a device body region 140 located in the second doping region 130 .

[0057] It is understood that in order to achieve the desired isolation effect, the hole blocking layer should be distributed widely enough. Therefore, in the entire region where isolation is required, the bottom surface of the second buried region 124 should be in direct contact with the top surface of the first buried region 122. In one embodiment of the present application, the entire bottom surface of the second buried region 124 is in direct contact with the first buried region 122, and / or the entire top surface of the first buried region 122 is in direct contact with the second buried region 124.

[0058] Because the first buried region 122 and the second buried region 124 serve as junction isolation structures, the backside of the substrate 110 (i.e., the bottom of the substrate 110 in FIG1 ) cannot serve as an electrode of the device. The device cannot be a vertical device with an electrode disposed on the backside of the substrate 110, such as a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOSFET). In one embodiment, the semiconductor device with an isolation structure of the present application includes a lateral device, such as a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET). In one embodiment of the present application, the semiconductor device with an isolation structure of the present application is a fully isolated semiconductor device.

[0059] In the embodiment where the first conductivity type is N-type and the second conductivity type is P-type, the first buried region 122 is a high-concentration N-type buried layer BN+, and the second buried region 124 is a low-concentration N-type buried layer BN-. At the junction of the first buried region 122 and the second buried region 124, the concentration difference of carriers will cause ions to diffuse and move, thereby forming a built-in electric field with an electric field strength of where N E + is the electron concentration of BN+, N E - is the electron concentration of BN-, and the electric field direction is from BN+ to BN-, as shown in Figure 1. Due to the existence of this built-in electric field, a hole blocking layer is formed at the interface, which can prevent holes in the second doped region 130 from passing through the hole blocking layer and escaping to the substrate 110, causing substrate leakage. For the embodiment where the first conductivity type is P-type and the second conductivity type is N-type, the electric field direction is shown in Figure 2. Due to the sufficient thickness and high concentration of the first buried region 122, the resistance of the first buried region 122 is low, which suppresses the damage to the device caused by the latch-up effect.

[0060] To achieve a better blocking effect on holes, the field strength of the aforementioned built-in electric field should be large enough. In one embodiment of the present application, the doping concentration of the first buried region 122 is at least 100 times higher than that of the second buried region 124. Furthermore, for BN+, a higher doping concentration can provide better recombination ability of minority carriers, thereby further reducing hole crossing. In one embodiment of the present application, the doping concentration of the first buried region 122 is not less than 1E19 cm -3 , the doping concentration of the second buried region is not higher than 1E17 cm -3 It should be noted that a high BN+ doping concentration will affect the breakdown voltage (voltage resistance) of the device, that is, the higher the BN+ doping concentration, the lower the breakdown voltage of the device. Therefore, the BN+ doping concentration must also meet the breakdown voltage requirements of the device.

[0061] In one embodiment of the present application, the thickness of the second buried region 124 is less than that of the first buried region 122, thereby enhancing minority carrier recombination within the junction isolation structure. In the junction isolation structure, the first buried region 122 primarily performs the isolation function, while the second buried region 124 serves as a buffer layer to further enhance the isolation function of the first buried region 122. This layer is used to establish a built-in electric field on the isolation ring through a concentration gradient. This built-in electric field prevents electrons or holes from migrating to the substrate 110, thereby preventing leakage or even latch-up in the substrate 110.

[0062] Referring to FIG1 , in this embodiment, the device body region 140 includes a drift region, which is separated from the second buried region 124 by a second doped region 130. In the embodiment shown in FIG1 , the second doped region 130 is a P-type epitaxial layer, the first doped region 112 is a P-type lightly doped epitaxial layer, and the device body region 140 includes an N-type drift region. FIG3 is an equivalent circuit diagram of the structure shown in FIG1 , which includes a parasitic PNP transistor (i.e., P-type epitaxial layer-N-type buried layer-P-type first doped region and P-type substrate) and a parasitic NPN transistor (i.e., N-type drift region-P-type epitaxial layer-N-type buried layer), R P-epi is the equivalent resistance of the P-type epitaxial layer, R BN+ is the equivalent resistance of the first buried region 122 (i.e., BN+). When the body diode of the device on the junction isolation structure is freewheeling, the emitter junction of the parasitic PNP transistor and the emitter junction of the parasitic NPN transistor in the equivalent circuit in FIG3 are forward biased. However, due to the presence of the aforementioned hole blocking layer, only a very small current will enter the first buried region 122. Since the first buried region 122 has a higher doping concentration, R BN+ The resistance value is very small, R BN+ The voltage drop is also very small, and it is difficult for the parasitic PNP transistor and the parasitic NPN transistor to be turned on at the same time, thereby effectively avoiding the latch effect. In addition, since the doping concentration of the first doping region 112 is very low, a base region extension region (i.e., the area above the doped line of the first doping region 112 in Figure 1) will be formed in the first doping region 112. Even if the parasitic PNP is turned on, based on the base region extension effect, the width of the effective base region will become wider, thereby effectively reducing the parasitic leakage flowing into the substrate 110. In one embodiment of the present application, the doping dose of the first doping region 112 does not exceed 3E14cm -2 In one embodiment of the present application, the thickness of the first doping region 112 is not less than 10 micrometers to obtain a sufficient width of the effective base region.

[0063] In one embodiment of the present application, the semiconductor device with an isolation structure is a lateral device, such as an LDMOSFET. In one embodiment of the present application, the semiconductor device with an isolation structure can be applied to circuit structures such as a half-bridge circuit and an H-bridge circuit, for example, as a low-side device of a half-bridge circuit.

[0064] Because the upper and lower transistors in a half-bridge circuit share a common substrate, a parasitic NPN transistor is created between the upper and lower transistors. However, due to the provision of the first doped region 112 in this application, a heavily doped substrate material (e.g., a substrate 110 with a resistivity of less than 0.01 Ω·cm) can be used for Psub of the substrate 110. This reduces the base resistance of the parasitic N-type buried layer-P-type substrate-N-type buried layer transistor between the upper and lower transistors in both half-bridge and H-bridge circuits, further mitigating potential latch-up between the upper and lower transistors.

[0065] In one embodiment of the present application, the semiconductor device with an isolation structure further includes a lateral isolation structure 150 that laterally surrounds the device main region 140. The lateral isolation structure 150 is located in the second doped region 130 and on the second buried region 124, thereby, together with the junction isolation structure, serving as an isolation cover that surrounds the device main region 140, surrounding and electrically isolating the device main region 140 laterally and at the bottom, thereby reducing leakage current. For embodiments in which the lateral isolation structure 150 is provided, the junction isolation structure only needs to be formed in the area defined by the lateral isolation structure 150, and does not need to occupy the entire first doped region 112 in the horizontal plane. In the embodiment shown in Figure 4a, the lateral isolation structure 150 includes a first conductive type region. In an embodiment in which the first conductive type is N-type and the second conductive type is P-type, the first conductive type region is an N-well.

[0066] In one embodiment of the present application, the lateral isolation structure 150 is formed by digging a trench and then filling the trench with an isolation material. In the embodiment shown in FIG4 b , the junction isolation structure (first buried region 122 and second buried region 124) is extended to the top surface of the semiconductor device via a conductive structure 160 (which may be made of a metal and / or alloy) filled in an extraction trench. The bottom of the extraction trench extends to the second buried region 124.

[0067] In the embodiment shown in FIG. 4 c , lateral isolation structure 150 includes an insulating layer 154 disposed on the inner wall of an isolation trench. A conductive structure 152 electrically connected to second buried region 124 is also disposed within the isolation trench. Insulating layer 154 laterally isolates conductive structure 152. Conductive structure 152 is used to lead second buried region 124 to the top surface of the semiconductor device. Conductive structure 152 can be made of metal and / or alloy.

[0068] The present application accordingly provides a method for manufacturing an isolation structure. FIG5 is a flow chart of the method for manufacturing an isolation structure in one embodiment of the present application, comprising the following steps:

[0069] S510 , obtaining a substrate, on which a first doped region is formed.

[0070] The substrate 110 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, etc., or at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In the embodiment shown in Figure 6a, the substrate 110 is a single crystal silicon substrate of the second conductivity type. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type. In one embodiment of the present application, the substrate 110 is a heavily doped substrate to obtain a lower resistivity. In one embodiment of the present application, the resistivity of the substrate 110 is less than 0.01Ω·cm. The first doped region 112 is located on the substrate 110 and has the second conductivity type. The doping concentration of the first doped region 112 is lower than the doping concentration of the substrate 110.

[0071] In one embodiment of the present application, the first doping region 112 is formed by epitaxy. In one embodiment of the present application, the doping dose of the first doping region 112 does not exceed 3E14 cm -2 In one embodiment of the present application, the thickness of the first doping region 112 is not less than 10 micrometers.

[0072] S520 , forming a first buried region on the first doped region.

[0073] In one embodiment of the present application, ions of the first conductive type are implanted into the first doping region 112 by an ion implantation process to form a first buried region 122, with reference to FIG6b. In one embodiment of the present application, the first buried region 122 is a heavily doped N-type buried layer (BN+), and the concentration of the N-type impurities should be as heavily doped as possible while ensuring the breakdown voltage of the device, because a higher concentration of N-type impurities can provide a stronger minority carrier recombination ability and reduce hole crossing. After the implantation, a thermal process is used to push the well so that the junction depth of the first buried region 122 is deeper and the width is larger. In one embodiment of the present application, the temperature of the thermal process is above 1000 degrees Celsius and the time is above 100 minutes.

[0074] S530 , forming a second buried region on the first buried region and in direct contact with the first buried region.

[0075] The second buried region 124 has the first conductivity type and has a doping concentration lower than that of the first buried region 122. In one embodiment of the present application, an additional ion implantation step may be performed after forming the first buried region 122 (i.e., after the well push-in step S520) to form the second buried region 124, as shown in FIG6c. In one embodiment of the present application, the second buried region 124 is formed using an N-type implantation with a lower impurity concentration and a shallow implantation depth (low implantation energy), resulting in a second buried region 124 (a lightly doped N-type buried layer BN-) with its bottom directly contacting the top of the first buried region 122. The concentration difference at the interface between the first buried region 122 and the second buried region 124 causes ion diffusion, thereby forming a built-in electric field directed from BN+ to BN-. This electric field forms a hole blocking layer at the interface between BN+ and BN-, preventing holes in the semiconductor device body from entering the buried layer and then traveling to the substrate 110, causing substrate leakage. At the same time, due to the high concentration of BN+, the resistance is low, and the aforementioned push-well makes the buried layer deep enough (that is, the depth from the top to the bottom of the buried layer is large), thereby suppressing the damage to the device caused by the latch-up effect.

[0076] In one embodiment of the present application, the doping concentration of the first buried region 122 is at least 100 times higher than that of the second buried region 124 .

[0077] S540 , forming a second doped region on the second buried region.

[0078] In one embodiment of the present application, epitaxy is grown on the structure formed in step S530 to form a second doped region 130 located on the second buried region 124, as shown in Figure 1. In one embodiment of the present application, the second doped region 130 is a P-type epitaxial layer.

[0079] The internal manufacturing processes of the device can then be carried out on the epitaxial layer.

[0080] The above-described method for manufacturing the isolation structure, by providing a first buried region 122 and a second buried region 124 as a junction isolation structure, forms a hole blocking layer at the interface between the first buried region 122 and the second buried region 124, which has a concentration difference. This utilizes the contact potential difference to prevent holes from passing through the buried layer and entering the substrate 110, thereby causing substrate leakage. This improves the junction isolation effect of the semiconductor device and alleviates the latch-up problem of fully isolated devices. Furthermore, due to the provision of the second conductivity type first doped region 112, even if the parasitic transistor formed by the second doped region 130 - junction isolation structure - first doped region 112 and substrate 110 is turned on, the base region extension effect can be utilized to increase the effective base width, thereby effectively reducing parasitic leakage into the substrate.

[0081] In one embodiment of the present application, the doping concentration of the first buried region 122 is at least 100 times higher than that of the second buried region 124 .

[0082] In one embodiment of the present application, the doping concentration of the first buried region 122 is not less than 1E19 cm -3 , the doping concentration of the second buried region 124 is not higher than 1E17 cm -3 .

[0083] In one embodiment of the present application, step S540 further includes forming a device body region 140 in the second doping region.

[0084] In one embodiment of the present application, step S540 is followed by a step of forming a lateral isolation structure 150. The lateral isolation structure 150 is located in the second doped region 130 and on the second buried region 124, and surrounds the device body region 140 in a lateral direction.

[0085] 4a, the lateral isolation structure 150 includes a first conductivity type region. In an embodiment where the first conductivity type is N-type and the second conductivity type is P-type, the first conductivity type region is an N-well formed by ion implantation.

[0086] In one embodiment of the present application, the lateral isolation structure 150 is formed by photolithography on the second doping region 130 , etching the second doping region 130 to form an isolation trench, and then filling the trench with isolation material, as shown in FIG. 4 b .

[0087] In the embodiment shown in FIG. 4 b , step S540 is followed by photolithography on the second doped region 130, etching the second doped region 130 to form an extraction trench, and then filling the extraction trench with a conductive structure. The junction isolation structure (the first buried region 122 and the second buried region 124 ) is led to the top surface of the semiconductor device via a conductive structure 160 (which may be made of a metal and / or alloy), and the bottom of the extraction trench extends to the second buried region 124 .

[0088] In the embodiment shown in FIG. 4 c , lateral isolation structure 150 includes an insulating layer 154 disposed on the inner wall of an isolation trench. A conductive structure 152 electrically connected to second buried region 124 is also disposed within the isolation trench. Insulating layer 154 laterally isolates conductive structure 152. Conductive structure 152 is used to lead second buried region 124 to the top surface of the semiconductor device. Conductive structure 152 can be made of metal and / or alloy.

[0089] In one embodiment of the present application, the device body region includes a drift region.

[0090] In one embodiment of the present application, the drift region has a first conductivity type.

[0091] In one embodiment of the present application, the semiconductor device includes a lateral device.

[0092] In one embodiment of the present application, the semiconductor device includes an LDMOSFET (Lateral Double-Diffused Metal Oxide Semiconductor Field Effect Transistor).

[0093] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0094] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0095] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor device with an isolation structure, comprising: a substrate having a second conductivity type; A first doping region, located on the substrate and having a second conductivity type, wherein a doping concentration of the first doping region is less than a doping concentration of the substrate; A junction isolation structure, comprising a first buried region and a second buried region directly contacting the first buried region, wherein the first buried region is located on the first doped region and has a first conductivity type, the second buried region is located on the first buried region and has the first conductivity type, and the doping concentration of the second buried region is less than the doping concentration of the first buried region; the first conductivity type and the second conductivity type are opposite conductivity types; a second doped region, having a second conductivity type, located on the second buried region; Wherein, the junction isolation structure is used to achieve insulation isolation between the substrate and the second doping region.

2. The semiconductor device with an isolation structure according to claim 1, wherein: The first doping region has a doping dose not exceeding 3E14cm -2 and / or The thickness of the first doping region is not less than 10 micrometers.

3. The semiconductor device with an isolation structure according to claim 1, wherein: The resistivity of the substrate is less than 0.01Ω·cm.

4. The semiconductor device with an isolation structure according to claim 1, wherein: The doping concentration of the first buried region is not less than 1E19 cm -3 , the doping concentration of the second buried region is not higher than 1E17 cm -3 .

5. The semiconductor device with an isolation structure according to claim 1, further comprising: A device body region, located in the second doped region; A lateral isolation structure surrounds the device main region in a lateral direction, and the lateral isolation structure is located in the second doped region and on the second buried region.

6. The semiconductor device with an isolation structure according to claim 5, wherein: The lateral isolation structure includes a first conductivity type region; or The lateral isolation structure comprises an insulating material; or The lateral isolation structure includes an insulating layer arranged on the inner wall of the isolation groove, and a conductive structure electrically connected to the second buried area is also provided in the isolation groove. The insulating layer insulates and isolates the conductive structure in the lateral direction, and the conductive structure is used to lead the second buried area to the upper surface of the semiconductor device.

7. The semiconductor device with an isolation structure according to claim 1, wherein: The thickness of the second buried region is smaller than the thickness of the first buried region.

8. The semiconductor device with an isolation structure according to claim 1, wherein: The first conductivity type is N type, and the second conductivity type is P type; or the first conductivity type is P type, and the second conductivity type is N type.

9. The semiconductor device with an isolation structure according to claim 1, wherein: The bottom of the second buried region is in direct contact with the top of the first buried region, and / or the entire top surface of the first buried region is in direct contact with the bottom of the second buried region.

10. The semiconductor device with an isolation structure according to claim 5, wherein: The device body region includes a drift region, and the drift region is separated from the second buried region by the second doped region.

11. The semiconductor device with an isolation structure according to claim 1, wherein: The second doped region is an epitaxial layer.

12. A method for manufacturing an isolation structure, comprising: Obtaining a substrate, on which a first doping region is formed; The substrate and the first doping region have a second conductivity type, and the doping concentration of the first doping region is less than the doping concentration of the substrate; forming a first buried region on the first doped region, wherein the first buried region has a first conductivity type; forming a second buried region on the first buried region and in direct contact with the first buried region, the second buried region having a first conductivity type and a doping concentration lower than that of the first buried region; A second doped region is formed on the second buried region.

13. The method for manufacturing an isolation structure according to claim 12, wherein: The step of forming the first buried region on the first doped region includes: injecting first conductive type ions into the first doped region, and then performing well-driving, the well-driving temperature is above 1000 degrees Celsius, and the time is above 100 minutes.

14. The method for manufacturing an isolation structure according to claim 12, further comprising: After forming the second doped region on the second buried region, a device body region is formed in the second doped region.

15. The method for manufacturing an isolation structure according to claim 12, wherein: The forming of the second doped region on the second buried region is to grow an epitaxial layer on the second buried region.

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