Multi-input low-dropout linear voltage stabilizing circuit and control method therefor

Abstract

A multi-input low-dropout (LDO) linear voltage stabilizing circuit and a control method therefor. The multi-input LDO linear voltage stabilizing circuit comprises a LDO unit, comprising a first LDO linear regulator (LDO1) and a second LDO linear regulator (LDO2) connected to a same output node, wherein the first LDO linear regulator (LDO1) comprises a first operational amplifier (AMP1) and a first power device (201), the input voltage of the first LDO linear regulator (LDO1) is a first input voltage (VIN), the second LDO linear regulator (LDO2) comprises a second operational amplifier (AMP2) and a second power device (202), and the input voltage of the second LDO linear regulator (LDO2) is a second input voltage (BIAS); and a reference voltage selection unit (10), used for selecting, when the first LDO linear regulator (LDO1) is switched to the second LDO linear regulator (LDO2), the reference voltage of the first operational amplifier (AMP1) as a second reference voltage (VREFb), and the reference voltage of the second operational amplifier (AMP2) as a first reference voltage (VREFa), wherein the first reference voltage (VREFa) is higher than the second reference voltage (VREFb). By optimizing the structure and the working time sequence of a multi-input LDO circuit, stable switching among different LDOs can be achieved, the power supply fluctuation amplitude of an internal analog circuit is greatly reduced, the output voltage of the LDOs during different switching does not trigger UVLO by mistake, and the normal working state and good performance of the circuit are guaranteed.

Description

Multi-input low voltage difference linear voltage regulator circuit and control method thereof

[0001] This invention claims priority to Chinese patent application number 202311850268X, filed with the Patent Office of China on December 28, 2023, entitled “Multi-input low voltage difference linear voltage regulator circuit and its control method”. The entire contents of this application are incorporated herein by reference. Technical Field

[0002] The present invention belongs to the technical field of low voltage difference linear regulators, and in particular relates to a multi-input low voltage difference linear regulator circuit and a control method thereof. Background Art

[0003] In DC-DC power conversion chips, one approach is to switch the power supply from a low-dropout linear regulator (LDO) to another power supply to reduce the chip's static power consumption from the power supply and improve the transmission efficiency from the power supply to the output. This requires the LDO to have the ability to detect and switch power supplies from multiple power inputs.

[0004] There are two main problems in the existing technology: First, considering the voltage difference between multiple input power supplies, it is necessary to add an anti-backflow circuit to the power supply path. In the existing technology, diodes are generally used as anti-backflow devices, and their unidirectional conductivity is used to achieve the anti-backflow function. However, since there is a voltage drop of about 0.7V when the diode is turned on, the power consumption is further increased and the voltage margin of the LDO internal circuit is limited. Secondly, if the traditional detection hard switching timing is used, during the input power switching process, the output voltage of the LDO is at risk of being pulled down, resulting in the undervoltage lockout (UVLO) voltage being falsely triggered.

[0005] Therefore, in order to solve the above technical problems, it is necessary to provide a multi-input low voltage difference linear voltage regulator circuit and a control method thereof. Summary of the Invention

[0006] In view of this, an object of the present invention is to provide a multi-input low voltage dropout linear voltage regulator circuit and a control method thereof, so as to prevent the output voltage from falsely triggering UVLO during the input power switching process.

[0007] In order to achieve the above object, the present invention provides a multi-input low voltage dropout linear voltage regulator circuit, wherein the low voltage dropout linear regulator comprises:

[0008] The LDO unit includes a first low-dropout linear regulator and a second low-dropout linear regulator connected to the same output node, the first low-dropout linear regulator includes a first operational amplifier and a first power device, the first power device receives a first input voltage, and the second low-dropout linear regulator includes a second operational amplifier and a second power device, and its input voltage is the second input voltage;

[0009] The reference voltage selection unit is used to select the reference voltage of the first operational amplifier as the second reference voltage and the reference voltage of the second operational amplifier as the first reference voltage when the first low-voltage-dropout linear regulator is switched to the second low-voltage-dropout linear regulator, wherein the first reference voltage is greater than the second reference voltage.

[0010] By optimizing the structure and working sequence of the multi-input LDO circuit, the present invention can achieve smooth switching between different LDOs, greatly reducing the power supply fluctuation amplitude of the internal analog circuit. The LDO output voltage will not falsely trigger the UVLO during different switching processes, ensuring the normal working state and good performance of the circuit.

[0011] In addition, MOS tubes are used as anti-backflow devices. They have unidirectional conductivity when turned off and reduce voltage drop when turned on, which has the advantages of reducing power consumption and increasing voltage margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] FIG1 is a circuit diagram of a multi-input low voltage difference linear voltage regulator circuit in the prior art;

[0014] FIG2 is a working timing diagram of a multi-input low voltage difference linear voltage regulator circuit in the prior art;

[0015] FIG3 a is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to an embodiment of the present invention;

[0016] FIG3 b is a circuit diagram of a signal generating circuit according to an embodiment of the present invention;

[0017] FIG4 is a working timing diagram of the multi-input low voltage difference linear voltage regulator circuit in the embodiment of FIG3a;

[0018] FIG5 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to another embodiment of the present invention;

[0019] FIG6 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to another embodiment of the present invention;

[0020] FIG7 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to another embodiment of the present invention;

[0021] FIG8 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to another embodiment of the present invention.

[0022] FIG9 is a flow chart of a control method for a multi-input low voltage dropout linear voltage regulator circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0023] To help those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. It should be understood that the described embodiments are only some of the embodiments of the present invention, and not all of the embodiments. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort should fall within the scope of protection of the present invention. The embodiments described herein are for illustrative purposes only and are not intended to limit the present invention. Throughout this specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that the specific features, structures, or characteristics described in connection with that embodiment or example are included in at least one embodiment of the present invention. The phrases "in an embodiment," "in one embodiment," "an example," or "an example" appearing in various places throughout this specification do not necessarily refer to the same embodiment or example; specific features, structures, or characteristics may be combined in any appropriate combination and / or subcombination in one or more embodiments or examples.

[0024] In the description herein, unless otherwise specified or limited, the terms "connected" and "connected" should be understood in a broad sense. For example, it can be a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meanings of the above terms can be understood according to the specific circumstances. In addition, it should be understood by those skilled in the art that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0025] It should be understood that while the terms "first," "second," and "third" may be used herein to describe various devices, elements, components, or parts, this description should not be limited to these terms. These terms are used to distinguish one from another. For example, a first device could also be referred to as a second device without departing from the essential technical solutions of the embodiments of this application.

[0026] FIG1 is a circuit diagram of a multi-input low voltage difference linear voltage regulator circuit in the prior art, which includes:

[0027] A feedback unit comprising a first resistor R1 connected between the output node and the feedback node, and a second resistor R2 connected between the feedback node and a reference potential;

[0028] A first operational amplifier AMP1, a first power device MP1, and a first diode D1. The first input terminal of the first operational amplifier AMP1 is connected to the reference voltage VREF, and the second input terminal is connected to the feedback node in the voltage divider unit. The enable terminal of the first operational amplifier AMP1 receives the first enable signal VIN_LDO_EN. The first power device MP1 is a PMOS tube, the source of which is connected to the first input voltage VIN, the drain of which is connected to the anode of the first diode D1, the gate of which is connected to the output terminal of the first operational amplifier AMP1, and the cathode of the first diode D1 is connected to the output node;

[0029] A second operational amplifier AMP2, a second power device MP2, and a second diode D2, wherein a first input terminal of the second operational amplifier AMP2 is connected to a reference voltage VREF, a second input terminal is connected to a feedback node in the feedback unit, an enable terminal of the second operational amplifier AMP2 receives a second enable signal VBIAS_LDO_EN, the second power device MP2 is a PMOS tube, a source terminal is connected to the second input voltage BIAS, a drain terminal is connected to the anode of the second diode D2, a gate terminal is connected to the output terminal of the second operational amplifier AMP2, and a cathode terminal of the second diode D2 is connected to the output node;

[0030] The first low-dropout linear regulator LDO1 includes a first operational amplifier AMP1, a first power device MP1, a first diode D1 and a feedback unit. The second low-dropout linear regulator LDO2 includes a second operational amplifier AMP2, a second power device MP2, a second diode D2 and a feedback unit. The voltage output by the output node is the output voltage VCC.

[0031] FIG2 is a timing diagram showing the operation of the multi-input low voltage difference linear voltage regulator circuit in the prior art shown in FIG1 . The specific working principle is as follows:

[0032] When it is detected that the second input voltage BIAS exceeds the first threshold voltage VTH1, BIAS_UV_BUF becomes a low level, the first enable signal VIN_LDO_EN received by LDO1 becomes a low level, LDO1 is turned off, and VCC is pulled low; the second enable signal VBIAS_LDO_EN received by LDO2 becomes a high level, LDO2 is turned on, and the LDO2 operating point begins to be established, and its rate is related to the bias current and parasitic capacitance.

[0033] Before LDO2 fully stabilizes, VCC will continue to lose power. This rapidly reduces the voltage margin of analog circuits operating in the VCC domain, potentially causing circuit performance issues. In the worst case, the voltage drops below the UVLO voltage (VCC_UV), triggering UVLO protection. This is an incorrect state for properly functioning circuits. Similarly, when the BIAS voltage drops below the second threshold voltage (VTH2), causing the multi-input low-dropout linear regulator to switch back to LDO1, excessive VCC power loss can occur. When the BIAS voltage is higher than VIN, current will not flow from BIAS to VIN due to D1's reverse bias, and vice versa. BIAS_UV_BUF indicates whether BIAS is greater than the first threshold or less than the second threshold.

[0034] FIG3 a is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to an embodiment of the present invention. The multi-input low voltage dropout linear voltage regulator circuit includes:

[0035] The LDO unit includes a first low-dropout linear regulator LDO1 and a second low-dropout linear regulator LDO2 connected to the same output node; the first low-dropout linear regulator LDO1 includes a first operational amplifier AMP1 and a first power device 201, and the input voltage of the first low-dropout linear regulator LDO1 is a first input voltage VIN; the second low-dropout linear regulator LDO2 includes a second operational amplifier AMP2 and a second power device 202, and the input voltage of the second low-dropout linear regulator LDO2 is a second input voltage BIAS.

[0036] The reference voltage selection unit 10 is configured to select the second reference voltage VREFb as the reference voltage of the first operational amplifier AMP1 and the first reference voltage VREFa as the reference voltage of the second operational amplifier AMP2 when the first low-dropout linear regulator LDO1 switches to the second low-dropout linear regulator LDO2. The first reference voltage VREFa is greater than the second reference voltage VREFb. The first input terminal of the first operational amplifier AMP1 and the first input terminal of the second operational amplifier AMP2 serve as input terminals for the reference voltages.

[0037] In one embodiment of the present invention, the first power device 201 and / or the second power device 202 include a P-type MOS transistor, but those skilled in the art should appreciate that the first power device 201 and / or the second power device 202 may also include an N-type MOS transistor, or other types of power devices, such as a BJT (bipolar junction transistor), an IGBT (insulated gate bipolar transistor), etc.

[0038] In one embodiment of the present invention, the reference voltage selection unit 10 selects the reference voltage of the first operational amplifier AMP1 based on the first reference voltage selection signal VREF1_SEL, and selects the reference voltage of the second operational amplifier AMP2 based on the second reference voltage selection signal VREF2_SEL.

[0039] The LDO unit also includes:

[0040] The feedback unit 30 is connected between the output node and the reference potential; the feedback unit 30 is configured to provide a feedback signal to the second input terminal of the first operational amplifier AMP1 and / or the second input terminal of the second operational amplifier AMP2.

[0041] The first input terminal of the first operational amplifier AMP1 is connected to the reference voltage selection unit 10, the second input terminal is connected to the feedback node in the feedback unit 30, the first terminal of the first power device 201 is connected to the first input voltage VIN, the second terminal is connected to the output node, and the control terminal is connected to the output terminal of the first operational amplifier AMP1;

[0042] The first input terminal of the second operational amplifier AMP2 is connected to the reference voltage selection unit 10, the second input terminal is connected to the feedback node in the feedback unit, the first terminal of the second power device 202 is connected to the second input voltage BIAS, the second terminal is connected to the output node, and the control terminal is connected to the output terminal of the second operational amplifier AMP2.

[0043] The first low dropout linear regulator LDO1 includes a first operational amplifier AMP1 , a first power device 201 and a feedback unit 30 . The second low dropout linear regulator LDO2 includes a second operational amplifier AMP2 , a second power device 202 and a feedback unit 30 .

[0044] In one embodiment of the present invention, the feedback unit includes a first resistor R1 connected between the output node and the feedback node, and a second resistor R2 connected between the feedback node and a reference potential.

[0045] In one embodiment of the present invention, the reference voltage selection unit 10 may select a voltage selector, and output corresponding reference voltages by respectively inputting the first reference voltage selection signal VREF1_SEL and / or the second reference voltage selection signal VREF2_SEL. The output reference voltages include a first reference voltage VREFa and a second reference voltage VREFb, satisfying VREFa>VREFb.

[0046] In one embodiment of the present invention, the reference voltage selection unit 10 includes a first reference voltage selector 101 and a second reference voltage selector 102. The first reference voltage selector 101 is used to select the first reference voltage VREFa or the second reference voltage VREFb for the first operational amplifier AMP1. The second reference voltage selector 102 is used to select the first reference voltage VREFa or the second reference voltage VREFb for the second operational amplifier.

[0047] The first reference voltage selector 101 has a first input connected to the first reference voltage VREFa, a second input connected to the second reference voltage VREFb, an output connected to the first input of the first operational amplifier AMP1, and a control connected to the first reference voltage selection signal VREF1_SEL. The second reference voltage selector 102 has a first input connected to the first reference voltage VREFa, a second input connected to the second reference voltage VREFb, an output connected to the first input of the second operational amplifier AM2, and a control connected to the second reference voltage selection signal VREF2_SEL.

[0048] In one embodiment of the present invention, when the first reference selection signal VREF1_SEL / the second reference voltage selection signal VREF2_SEL is at a low level, the first reference voltage VREFa is selected; and when it is at a high level, the second reference voltage VREFb is selected. However, those skilled in the art will appreciate that in other implementations, when the first reference selection signal VREF1_SEL / the second reference voltage selection signal VREF2_SEL is at a high level, the first reference voltage VREFa is selected; and when it is at a low level, the second reference voltage VREFb is selected.

[0049] In one embodiment of the present invention, the first op amp AMP1 and the second op amp AMP2 are enabled and controlled by a first op amp enable signal VIN_LDO_EN and a second op amp enable signal VBIAS_LDO_EN, respectively. For example, when the first op amp enable signal VIN_LDO_EN and / or the second op amp enable signal VBIAS_LDO_EN are at an active level, the first op amp AMP1 and / or the second op amp AMP2 are enabled and operated; when the first op amp enable signal VIN_LDO_EN and / or the second op amp enable signal VBIAS_LDO_EN are at an inactive level, the first op amp AMP1 and / or the second op amp AMP2 are disabled. The active level can be either high or low; the inactive level can be either low or high.

[0050] In one embodiment of the present invention, a first backflow prevention device is provided between the second end of the first power device 201 and the output node, and a second backflow prevention device is provided between the second end of the second power device 202 and the output node.

[0051] In one embodiment of the present invention, the first anti-backflow device is a first switching tube 203, which can be a PMOS tube, whose source is connected to the output node, whose drain is connected to the drain of the first power device 201, and whose gate is connected to the first op amp enable signal VIN_LDO_EN of the first op amp AMP1; the second anti-backflow device is a second switching tube 204, which can be a PMOS tube, whose source is connected to the output node, whose drain is connected to the drain of the second power device 202, and whose gate is connected to the second op amp enable signal VBIAS_LDO_EN of the second op amp AMP2.

[0052] In one embodiment of the present invention, the first op amp enable signal VIN_LDO_EN is inverted by an inverter and then output to the gate of the first switch 203 to drive the first switch 203. The second op amp enable signal VBIAS_LDO_EN is inverted by another inverter and then output to the gate of the second switch 204 to drive the second switch 204.

[0053] Figure 3b shows a signal generation circuit 40 according to an embodiment of the present invention. The signal generation circuit 40 is configured to generate control signals to control the reference voltage selection unit and the LDO unit. The signal generation circuit 40 includes a detection circuit 401, an op amp enable signal generation circuit 402, and a reference voltage selection signal generation circuit 403.

[0054] The detection circuit 401 is configured to compare the second input voltage BIAS with the first threshold voltage VTH1 / the second threshold voltage VTH2 and output a detection signal BIAS_UV_BUF based on the comparison result. The signal generation circuit 40 generates a first reference voltage selection signal VREF1_SEL, a second reference voltage selection signal VREF2_SEL, a first op amp enable signal VIN_LDO_EN, and a second op amp enable signal VBIAS_LDO_EN based on the detection signal BIAS_UV_BUF.

[0055] In one embodiment of the present invention, reference voltage selection signal generation circuit 403 generates a first reference voltage selection signal VREF1_SEL and a second reference voltage selection signal VREF2_SEL based on a detection signal BIAS_UV_BUF. Reference voltage selection signal generation circuit 403 includes an inverter and a follower. The detection signal BIAS_UV_BUF passes through a plurality of inverters and followers to generate the first reference voltage selection signal VREF1_SEL and the second reference voltage selection signal VREF2_SEL. The number of inverters and followers can be set based on the actual requirements for the effective voltage levels of the first reference voltage selection signal VREF1_SEL and the second reference voltage selection signal VREF2_SEL. FIG. 3b illustrates an example in which the second reference voltage selection signal VREF2_SEL is generated by passing through two serially connected inverters, and the first reference voltage selection signal VREF1_SEL is generated by passing through one inverter and one follower.

[0056] In one embodiment of the present invention, the op amp enable signal generating circuit 402 generates a first op amp enable signal VIN_LDO_EN and a second op amp enable signal VBIAS_LDO_EN based on the detection signal BIAS_UV_BUF.

[0057] In one embodiment of the present invention, the detection signal BIAS_UV_BUF generates the second op amp enable signal VBIAS_LDO_EN after passing through a NAND gate 4022 and a follower 4023. A first input of NAND gate 4022 is connected to the detection signal BIAS_UV_BUF, and a second input is connected to the output of a hysteresis inverting unit 4020. The detection signal BIAS_UV_BUF generates the first op amp enable signal VIN_LDO_EN after passing through the hysteresis inverting unit 4020 and a follower 4024. The hysteresis inverting unit 4020 includes a Schmitt trigger 4021.

[0058] FIG4 is a timing diagram showing the operation of the multi-input low voltage difference linear voltage regulator circuit in the embodiment of FIG3a. The operating principle is as follows:

[0059] 1. In the first time period (the time period before TD1), the second input voltage BIAS is less than the first threshold voltage VTH1, the first op amp enable signal VIN_LDO_EN of the first op amp AMP1 is high, the second op amp enable signal VBIAS_LDO_EN of the second op amp AMP2 is low, the first reference voltage selection signal VREF1_SEL is low, the second reference voltage selection signal VREF2_SEL is high, the first reference voltage selector 101 outputs the first reference voltage VREFa, and the first low dropout linear regulator LDO1 modulates the output voltage VCC of the output node based on the first reference voltage VREFa.

[0060] 2. During the second time period, or TD1, which is the first delay period, the second input voltage BIAS is greater than the first threshold voltage VTH1. The first op amp enable signal VIN_LDO_EN of the first op amp AMP1 remains high, the second op amp enable signal VBIAS_LDO_EN of the second op amp AMP2 transitions and remains high, the first reference voltage select signal VREF1_SEL transitions high, and the first reference voltage selector 101 outputs the second reference voltage VREFb. The second reference voltage select signal VREF2_SEL transitions low, and the second reference voltage selector 102 outputs the first reference voltage VREFa. The second low-dropout linear regulator LDO2 modulates the output voltage VCC based on the first reference voltage VREFa, and the first low-dropout linear regulator LDO1 modulates the output voltage VCC based on the second reference voltage VREFb. ΔV2 represents the VCC power loss during this time period.

[0061] 3. In the third time period (the period between TD1 and TD2), the first op amp enable signal VIN_LDO_EN of the first op amp AMP1 jumps and remains at a low level, the second op amp enable signal VBIAS_LDO_EN of the second op amp AMP2 remains at a high level, and the second low-dropout linear regulator LDO2 modulates the output voltage VCC based on the first reference voltage VREFa.

[0062] 4. In the fourth time period, i.e., the TD2 time period, TD2 is the second delay time period, the second input voltage BIAS decreases to less than the second threshold voltage VTH2, the first op amp enable signal VIN_LDO_EN of the first op amp AMP1 jumps and remains at a high level, the second op amp enable signal VBIAS_LDO_EN of the second op amp AMP2 remains at a high level, the first reference voltage selection signal VREF1_SEL jumps to a low level, the first reference voltage selector 101 outputs the first reference voltage VREFa, the second reference voltage selection signal VREF2_SEL jumps to a high level, the second reference voltage selector 102 outputs the second reference voltage VREFb, the first low dropout linear regulator LDO1 modulates the output voltage VCC based on the first reference voltage VREFa, and the second low dropout linear regulator LDO2 modulates the output voltage VCC based on the second reference voltage VREFb.

[0063] The first threshold voltage VTH1 and the second threshold voltage VTH2 may be the same threshold voltage or different threshold voltages, and the duration of the second period may be equal to or different from the duration of the fourth period, and may be set according to the LDO loop settling time. Preferably, in this embodiment, the first threshold voltage VTH1 is greater than the second threshold voltage VTH2, and the duration of the TD1 period is equal to the duration of the TD2 period.

[0064] By optimizing the circuit structure and working sequence, this embodiment ensures that there is always a loop modulating VCC when LDO1 and LDO2 switch, thereby achieving a small power loss of VCC and ensuring normal circuit operation and good performance.

[0065] Furthermore, in one embodiment of the present invention, PMOS switches with backflow protection are used as the first and second switches 203 and 204. Diodes D1 and D2 are replaced with PMOS switches controlled by inverted signals from VIN_LDO_EN and VBIAS_LDO_EN. Specifically, the source potential of the PMOS switches is lower than the drain potential in the connection method, thereby achieving backflow protection. Furthermore, since a diode has a voltage drop of approximately 0.7V when it is turned on, the reduced on-state voltage drop of the PMOS switches can achieve lower power consumption and higher voltage margin compared to using diodes as backflow protection devices.

[0066] As shown in Figures 3a and 4, when the BIAS voltage rises above VTH1, the second op amp enable signal VBIAS_LDO_EN transitions high, immediately turning on the second switch 102 to minimize its voltage drop and simultaneously enabling the second op amp AMP2. The first op amp enable signal VIN_LDO_EN remains high, enabling the first op amp AMP1. Simultaneously, the first reference voltage select signal VREF1_SEL transitions high, selecting VREFb as the reference voltage for LDO1. The second reference voltage select signal VREF2_SEL transitions low, selecting VREFa as the reference voltage for LDO2, with VREFa being greater than VREFb. Compared to the prior art, when LDO1 is turned off, LDO2 has not yet fully reset, resulting in a significant VCC drop (see ΔV1 in Figure 1), which can lead to the risk of false UVLO triggering. The technical solution of the present invention ensures that during the TD1 period, one of the LDO1 and LDO2 loops is always modulating VCC, thereby ensuring that VCC does not drop too much. Specifically, when the BIAS voltage rises above VTH1, LDO2 begins to establish. If the establishment is too slow at this time, the presence of the LDO1 loop ensures that VCC will not fall below VREFb / R2×(R1+R2). If the LDO2 loop is fully established before VCC drops to VREFb / R2×(R1+R2), the LDO2 loop will pull down the gate of the second power device 202, and the LDO2 loop will independently modulate VCC. In this case, the LDO1 loop operates in an open-loop state, and the first power device 201 is shut off by the loop, reducing the risk of two loops controlling the same voltage simultaneously.

[0067] For example, if VREFa = 3V, VREFb = 2.7V, and R2 / (R1+R2) = 3 / 5, the VCC voltage of LDO1 / LDO2 is 5V in steady-state at a 3V reference voltage, and 4.5V in steady-state at a 2.7V reference voltage. When the BIAS voltage exceeds VTH1, the reference voltage of LDO1 is immediately switched from 3V to 2.7V, and LDO2 is immediately turned on, with the reference voltage of LDO2 switched from 2.7V to 3V. The steady-state VCC modulated by LDO1 changes from 5V to 4.5V, and the steady-state VCC modulated by LDO2 changes from 4.5V to 5V. During the establishment time of LDO2, the current of the second power device 202 is small, and VCC starts to drop from 5V under the power withdrawal of the load current. Before dropping to 4.5V, the current of the first power device 201 gradually decreases, and the current of the second power device 202 gradually increases. VCC is slowly increased under the current of the second power device 202, causing the first power device 201 to be completely shut down and LDO1 to enter the open-loop state. At this time, the loop is completely taken over by LDO2.

[0068] After working together for a period of time TD1, VIN_LDO_EN jumps to a low level, the first switch tube 203 is turned off and LDO1 is completely turned off. When BIAS drops below the second threshold voltage VTH2, the power switching is similar.

[0069] It can be seen that with the optimized working timing, the VCC power-off is significantly less than that of the existing technology, and VCC will not drop below the UVLO voltage (VCC_UV), ensuring the correct working state and good performance of the circuit.

[0070] FIG5 is a circuit diagram of a multi-input low-dropout linear voltage regulator circuit according to an embodiment of the present invention. Unlike the embodiment shown in FIG3a , this embodiment includes N+1 low-dropout linear regulators LDO1, LDO2, ..., LDON+1, and the n-th low-dropout linear regulator LDOn (n=1, 2, ..., N+1) includes an n-th operational amplifier AMPn and an n-th power device.

[0071] In one embodiment of the present invention, the n-th low dropout linear regulator LDOn (n=1, 2, . . . , N+1) further includes an n-th switch tube.

[0072] The operating principle of this embodiment is similar to that of the embodiment shown in Figure 3a. When a switching condition is detected requiring switching from LDO1 to LDOX (where X is between 2 and N+1), LDO1's reference voltage is immediately adjusted to VREFb, and LDOX's reference voltage is adjusted to VREFa. The Xth switch, which serves as a backflow prevention device connected between the Xth power device of LDOX and VCC, is immediately turned on. This reduces the voltage drop across the Xth switch. After both LDO1 and LDOX operate simultaneously for a period of TD1, the gate voltage of the first switch is lowered, completely shutting down LDO1. The logic for switching from LDOX to LDO1 and vice versa is similar and will not be further elaborated here.

[0073] FIG6 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to an embodiment of the present invention. Unlike the embodiment shown in FIG3a , the first power device 201 and the second power device 202 in this embodiment are both NMOS transistors, wherein:

[0074] The drain of the first power device 201 is connected to the first input voltage VIN, the source is connected to the drain of the first switch tube 203, and the gate is connected to the output terminal of the first operational amplifier AMP1;

[0075] The drain of the second power device 202 is connected to the second input voltage BIAS, the source is connected to the drain of the second switch tube 204 , and the gate is connected to the output terminal of the second operational amplifier AMP2 .

[0076] FIG7 shows a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to an embodiment of the present invention. Unlike the embodiment shown in FIG3a , the first switch transistor 203 and the second switch transistor 204 in this embodiment are both NMOS transistors, wherein:

[0077] The source of the first switch tube 203 is connected to the drain of the first power device 201 , the drain is connected to the output node, and the gate is connected to the first operational amplifier enable signal VIN_LDO_EN;

[0078] The source of the second switch tube 204 is connected to the drain of the second power device 202 , the drain is connected to the output node, and the gate is connected to the second operational amplifier enable signal VBIAS_LDO_EN.

[0079] FIG8 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to an embodiment of the present invention. Unlike the embodiment shown in FIG3a , the first power device 201 and the second power device 202, the first switch tube 203 and the second switch tube 204 in this embodiment are all NMOS tubes, wherein:

[0080] The drain of the first power device 201 is connected to the first input voltage VIN, the gate is connected to the output terminal of the first operational amplifier AMP1, the source is connected to the source of the first switch tube 203, the drain of the first switch tube 203 is connected to the output node, and the gate is connected to the first operational amplifier enable signal VIN_LDO_EN;

[0081] The drain of the second power device 202 is connected to the second input voltage BIAS, the gate is connected to the output end of the second operational amplifier AMP1, the source is connected to the source of the second switch tube 204, the drain of the second switch tube 204 is connected to the output node, and the gate is directly connected to the second operational amplifier enable signal VBIAS_LDO_EN.

[0082] FIG9 is a flow chart of a control method for a multi-input low-dropout linear voltage regulator circuit according to another embodiment of the present invention, specifically comprising: when it is detected that the second input voltage is greater than the first threshold voltage, the second operational amplifier enable signal is flipped and maintained at an effective level, and the first operational amplifier enable signal is maintained at an effective level; the first input terminal of the second operational amplifier is input with a first reference voltage, and the first input terminal of the first operational amplifier is input with a second reference voltage;

[0083] After the first delay period TD1, the first operational amplifier enable signal is flipped and maintained at an invalid level, the second operational amplifier enable signal is maintained at a valid level, the first input terminal of the first operational amplifier is maintained at the second reference voltage, and the first input terminal of the second operational amplifier is maintained at the second reference voltage;

[0084] When it is detected that the second input voltage is less than the second threshold, the first operational amplifier enable signal is flipped and maintained at a valid level, the second operational amplifier enable signal is maintained at a valid level, the first input terminal of the first operational amplifier inputs the first reference voltage, and the first input terminal of the second operational amplifier inputs the second reference signal;

[0085] After the second delay period TD2, the first op amp enable signal remains at a valid level, the second op amp enable signal is flipped and remains at an invalid level, the first input terminal of the first op amp remains at the first reference voltage, and the first input terminal of the second op amp remains at the second reference voltage.

[0086] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0087] By optimizing the structure and operating timing of the multi-input LDO circuit, the present invention can achieve smooth switching between different LDOs, greatly reducing the power supply fluctuation amplitude of the internal analog circuit. The LDO output voltage will not falsely trigger the UVLO during different switching processes, ensuring the normal operation and good performance of the circuit.

[0088] In addition, MOS tubes are used as anti-backflow devices. They have unidirectional conductivity when turned off and reduce voltage drop when turned on, which has the advantages of reducing power consumption and increasing voltage margin.

[0089] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0090] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A multi-input low voltage drop linear voltage regulator circuit, characterized in that: The multi-input low voltage drop linear voltage regulator circuit comprises: The LDO unit includes a first low-voltage dropout linear regulator and a second low-voltage dropout linear regulator connected to the same output node, the first low-voltage dropout linear regulator includes a first operational amplifier and a first power device, the first power device receives a first input voltage, the second low-voltage dropout linear regulator includes a second operational amplifier and a second power device, and the input voltage of the first power device is a second input voltage; The reference voltage selection unit is used to select the reference voltage of the first operational amplifier as the second reference voltage and the reference voltage of the second operational amplifier as the first reference voltage when the first low-voltage difference linear regulator is switched to the second low-voltage difference linear regulator, wherein the first reference voltage is greater than the second reference voltage.

2. The multi-input low voltage dropout linear voltage regulator circuit according to claim 1, characterized in that: The LDO unit further includes a feedback unit connected between the output node and a reference potential; the feedback unit is configured to provide a feedback signal to the second input terminal of the first operational amplifier and the second input terminal of the second operational amplifier through the feedback node.

3. The multi-input low voltage dropout linear voltage regulator circuit according to claim 2, characterized in that: The first input terminal of the first operational amplifier is connected to the reference voltage selection unit, the second input terminal is connected to the feedback node, the first terminal of the first power device is connected to the first input voltage, the second terminal is connected to the output node, and the control terminal is connected to the output terminal of the first operational amplifier; The first input terminal of the second operational amplifier is connected to the reference voltage selection unit, the second input terminal is connected to the feedback node, the first terminal of the second power device is connected to the second input voltage, the second terminal is connected to the output node, and the control terminal is connected to the output terminal of the second operational amplifier.

4. The multi-input low voltage dropout linear voltage regulator circuit according to claim 2, characterized in that: The feedback unit includes: a first resistor connected between the output node and the feedback node; and a second resistor connected between the feedback node and a reference potential.

5. The multi-input low voltage dropout linear voltage regulator circuit according to any one of claims 1 to 3, characterized in that: The reference voltage selection unit includes a first reference voltage selector and a second reference voltage selector; The output end of the first reference voltage selector is connected to the first input end of the first operational amplifier; the first end is connected to the first reference voltage, the second end is connected to the second reference voltage, and the control end is connected to the first reference voltage selection signal; the first reference voltage selector outputs the first reference voltage or the second reference voltage under the control of the first reference voltage selection signal; The output end of the second reference voltage selector is connected to the first input end of the second operational amplifier; the first end is connected to the first reference voltage, the second end is connected to the second reference voltage, and the control end is connected to the second reference voltage selection signal; the second reference voltage selector outputs the first reference voltage or the second reference voltage under the control of the second reference voltage selection signal.

6. The multi-input low voltage dropout linear voltage regulator circuit according to any one of claims 1 to 3, characterized in that: The first power device and the second power device are both PMOS tubes, the first end is the source, the second end is the drain, and the control end is the gate; or, The first power device and the second power device are both NMOS tubes, with a first end being a drain, a second end being a source, and a control end being a gate.

7. The multi-input low voltage dropout linear voltage regulator circuit according to claim 1, characterized in that: The LDO unit also includes: A first switch tube, a first end of which is connected to the output node, a second end of which is connected to the second end of the first power device, and a control end of which is connected to the first operational amplifier enable signal; A second switch tube, a first end of which is connected to the output node, a second end of which is connected to the second end of the second power device, and a control end of which is connected to the second operational amplifier enable signal; The first operational amplifier is enabled when the first operational amplifier enable signal is at a valid level, and the second operational amplifier is enabled when the second operational amplifier enable signal is at a valid level.

8. The multi-input low voltage dropout linear voltage regulator circuit according to claim 7, characterized in that: The first operational amplifier enable signal is connected to the control end of the first switch tube via an inverter; The second operational amplifier enable signal is connected to the control end of the second switch tube via an inverter.

9. The multi-input low voltage dropout linear voltage regulator circuit according to claim 1, characterized in that: The detection unit detects and compares the second input voltage with the first threshold voltage, the second input voltage with the second threshold voltage, and outputs a detection signal based on the comparison result; the first threshold voltage and the second threshold voltage are the same threshold voltage or different threshold voltages.

10. The multi-input low voltage dropout linear voltage regulator circuit according to claim 9, characterized in that: The reference voltage selection signal generating circuit generates a first reference voltage selection signal and / or a second reference voltage selection signal based on the detection signal; The first reference voltage selection signal is input to the reference voltage selection unit to select the first reference voltage or the second reference voltage for the first operational amplifier; The second reference voltage selection signal is input to the reference voltage selection unit to select the first reference voltage or the second reference voltage for the second operational amplifier.

11. The multi-input low voltage dropout linear voltage regulator circuit according to claim 9, characterized in that: The operational amplifier enable signal generating circuit generates a first operational amplifier enable signal and / or a second operational amplifier enable signal based on the detection signal; The first operational amplifier is enabled when the first operational amplifier enable signal is at a valid level, and the second operational amplifier is enabled when the second operational amplifier enable signal is at a valid level.

12. A control method for a multi-input low voltage dropout linear voltage regulator circuit, characterized in that: The multi-input low voltage difference linear voltage regulator circuit comprises: a first low voltage difference linear voltage regulator and a second low voltage difference linear voltage regulator connected to the same output node, the first low voltage difference linear voltage regulator comprises a first operational amplifier and a first power device, the first power device receives a first input voltage, the second low voltage difference linear voltage regulator comprises a second operational amplifier and a second power device, the second power device receives a second input voltage; the output end of the first operational amplifier is connected to the control end of the first power device; the output end of the second operational amplifier is connected to the control end of the second power device; The control method comprises: When it is detected that the second input voltage is greater than the first threshold voltage, the second operational amplifier enable signal is flipped and maintained at a valid level, and the first operational amplifier enable signal is maintained at a valid level; the first input terminal of the second operational amplifier inputs the first reference voltage, and the first input terminal of the first operational amplifier inputs the second reference voltage; After the first delay period TD1, the first operational amplifier enable signal is flipped and maintained at an invalid level, the second operational amplifier enable signal is maintained at a valid level, the first input terminal of the first operational amplifier is maintained at the second reference voltage, and the first input terminal of the second operational amplifier is maintained at the second reference voltage; When it is detected that the second input voltage is less than the second threshold, the first operational amplifier enable signal is flipped and maintained at a valid level, the second operational amplifier enable signal is maintained at a valid level, the first input terminal of the first operational amplifier inputs the first reference voltage, and the first input terminal of the second operational amplifier inputs the second reference signal; After the second delay period TD2, the first operational amplifier enable signal remains at a valid level, the second operational amplifier enable signal is flipped and remains at an invalid level, the first input terminal of the first operational amplifier remains at the first reference voltage, and the first input terminal of the second operational amplifier remains at the second reference voltage; The first reference voltage is greater than the second reference voltage; When the first operational amplifier enable signal is at a valid level, the first operational amplifier is enabled; when the second operational amplifier enable signal is at a valid level, the second operational amplifier is enabled.

13. The control method of the multi-input low voltage dropout linear voltage regulator circuit according to claim 12, characterized in that: The first threshold voltage and the second threshold voltage are the same threshold voltage or different threshold voltages; and / or, The first delay period is equal to or different from the second delay period.

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