Transceiver device for a subscriber station of a serial bus system and method for receiving differential signals in a serial bus system

Abstract

The invention relates to a transceiver device (12; 120; 1200) for a subscriber station (10; 30) of a serial bus system (1) and to a method for transmitting differential signals (CAN_H, CAN_L; VDIFF) in a serial bus system (1). The transceiver device (12; 120; 1200) has: a first comparator (151) for evaluating differential signals (CAN_H, CAN_L; VDIFF) received from a bus (40) of the bus system (1), with a first reception threshold (T1), in order to generate a first digital comparator output signal (CA1); a second comparator (152) for evaluating the differential signals (CAN H, CAN L; VDIFF) received from the bus (40), with a second reception threshold (T2) different from the first reception threshold (T1), in order to generate a second digital comparator output signal (CA2); a logic circuit (1222) for combining the first and second digital comparator output signals (CA1, CA2) in order to output a reception signal (RxD; RxD1; RxD2) to a communication control device (11) of the subscriber station (10; 30); and a filter block (154; 154A; 154B) for evaluating the reception signal (RxD) and the second comparator output signal (CA2) in order to decide whether or not the second digital comparator output signal (CA2) should, with a delay, be output to the logic circuit (1222), and for outputting the second digital comparator output signal (CA2) to the logic circuit (1222) on the basis of the evaluation by the filter block (154; 154A; 154B).

Description

[0001] Description

[0002] Sending, Device for a subscriber station of a serial of differential in a serial

[0003] The present invention relates to a transmitting / receiving device for a subscriber station of a serial bus system and a method for receiving differential signals in a serial bus system.

[0004] State of the art

[0005] Serial bus systems are used for serial message or data transmission in technical systems. Serial bus systems have a bus to which subscriber stations (nodes) are connected via a transmitting / receiving device to communicate with each other over the bus. The transmitting / receiving device is also called a transceiver. During communication, data is exchanged between the subscriber stations, which can be, for example, sensors, control units in a vehicle or a technical production system, etc.

[0006] There are various standards or data transmission protocols for data transmission with differential signals in serial bus systems over a bus with two bus lines. The most well-known are a CAN bus system, an LVDS bus system (LVDS = Low Voltage Differential Signaling), an MSC bus system (MSC = Micro Second Channel), and 10BASE-T1 S-Ethernet.

[0007] In a CAN bus system, messages are transmitted using methods such as CAN FD or CAN XL, which are standardized in the international standard ISO / DIS 11898-1:2023. In every CAN bus system, transmission on the bus switches back and forth between a slow operating mode in a first communication phase (arbitration phase) and a fast operating mode in a second communication phase (data phase). In the arbitration phase, the subscriber stations on the bus negotiate (arbitration) which of the subscriber stations is allowed to send its message on the bus in the subsequent data phase and has exclusive access to the bus.

[0008] In an initial phase, most users will deploy CAN FD in vehicles with a data bit rate of 2 Mbit / s and an arbitration bit rate of 500 kbit / s. New CAN SIC transceivers enable the use of CAN FD at up to 8 Mbit / s. The standards for CAN SIC are defined by the CAN in Automation (CiA) organization in CiA601-4.

[0009] CAN XL is now available for even higher data bit rates than CAN FD. CAN XL supports up to 20 Mbps and payload lengths of 2048 bytes in the data phase. CAN XL is currently being deployed in real-world products.

[0010] In all of the CAN-based bus systems mentioned above, a CAN_H bus signal and, ideally, a CAN_L bus signal are driven separately onto a bus for a TxD transmission signal. At least in the first communication phase, one bus state is actively driven in the CAN_H and CAN_L bus signals. The other bus state is not driven and is determined by a terminating resistor for the bus lines or bus wires. In the first communication phase (arbitration phase), the dominant and recessive transmission levels are used. For the dominant state, a differential voltage VDIFF of approximately 2V should be achieved. For the recessive state, a differential voltage VDIFF of approximately 0V should be achieved.

[0011] In CAN XL, in contrast to CAN FD, a new communication phase called FAST has been introduced as the second communication phase, in which the two states L0 (Level0) and L1 (Level1) are used for data transmission on the bus. For the L0 state, a differential voltage VDIFF of approximately -1 V should be established. For the L1 state, a differential voltage VDIFF of approximately +1 V should be established. The L0 and L1 states are generated by a physical layer, which is currently defined in the CiA610-3 standard and differs from the physical layer of the first communication phase (arbitration phase). The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection Model).

[0012] After the first communication phase, the CAN XL transmit / receive device can be switched to FAST TX mode to transmit a signal to the bus itself. The associated subscriber station is also called the transmitting node. Alternatively, the transmit / receive device can be switched to FAST RX mode for the FAST communication phase to only receive signals from the bus. The associated subscriber station is also called the receiving node. In contrast, the transmit / receive device is always switched to SIC mode during the first communication phase (arbitration phase).

[0013] In this way, CAN XL data can be sent to the bus at a significantly higher data rate in the second communication phase (FAST) than in the first communication phase. Furthermore, the bus levels of the CAN_H and CAN_L bus signals for the first communication phase can differ from the bus levels of the second communication phase.

[0014] To ensure a low error rate in CAN XL and thus maximize the possible transmission rate in the bus system, it is important that a subscriber station that is newly added to the communication on the bus recognizes in which communication phase the bus is currently communicating.

[0015] Currently, a comparator with a comparatively low threshold of -1 V and high bandwidth requirements is used to detect the FAST communication phase. The reason for this is that such a comparator of a first transceiver device only detects L1 levels or L1 bus states on the bus with very high bandwidth if the first transceiver device itself is in SIC mode, but the L1 levels or L1 bus states were sent to the bus by a second transceiver device that is in FAST-TX mode. The typical bit time for the LO, L1 bus states at 20 Mbit / s is 50 ns. Upon detection of an L1 symbol with a duration of 50 ns, the comparator must acknowledge this at the output with a pulse of at least 15 ns, as specified in CiA610-3. The pulse is then made visible in the receive signal for the CAN-XL protocol controller.

[0016] The problem is that the comparator, which is designed to detect the FAST communication phase in CAN XL, also incorrectly detects low, unwanted voltage difference levels that occur during bus system operation. Such unwanted voltage difference levels can arise from non-idealities in the bus system. Such non-idealities in the system include, for example, reflections in the network and / or a so-called common-to-differential mode conversion and / or asymmetrically coupled interference signals.

[0017] Reflections in the network arise because, despite the use of an SLC transceiver, oscillations can occur on the bus during the transition from the low-impedance dominant state to the contrasting high-impedance recessive state. These oscillations appear as dominant glitches, i.e., temporary errors, in the received signal RxD. Depending on the topology and oscillation duration, these unwanted glitches in the received signal RxD can occur up to the sampling point for one bit. This can lead to disruption of communication on the bus.

[0018] A so-called "common-to-differential mode conversion" occurs because potentially high common-mode or common-mode voltage fluctuations occur on the bus when interference signals are radiated. This is especially true when the bus is in a high-impedance recessive state. These voltage fluctuations on the bus can be converted into differential signals at the input of the comparator, which can arise due to asymmetries in the external circuitry (common-mode chokes, circuit board design (circuit board layout), etc.) or in the transmit / receive device due to its production tolerances and / or layout effects, etc. Such differential signals are then falsely detected by the comparator as L1 level. This leads to a low (LOW) state in the receive signal RxD and disrupts communication on the bus.Asymmetrical interference occurs when external signals, for example, capacitively, couple more strongly onto one bus line than the other. In this case, small differential voltages arise between the bus lines, which in turn are reflected in the received signal (RxD) and disrupt communication on the bus.

[0019] For all operating phases of communication on the bus, even in the event of faults on the bus, it must be ensured that a receiving subscriber station of the bus system can correctly detect and evaluate the levels of the bus signals CAN_H, CAN_L.

[0020] Disclosure of the invention

[0021] Therefore, it is an object of the present invention to provide a transmitting / receiving device for a subscriber station of a serial bus system and a method for receiving differential signals in a serial bus system, which solve the aforementioned problems. In particular, the transmitting / receiving device for a subscriber station of a serial bus system and the method for receiving differential signals in a serial bus system are intended to ensure reliable and inexpensive detection of bus signals even in the event of bus faults and / or to ensure that no communication takes place on the bus, even if the subscriber station is newly connected to the bus communication and the physical layer is switched between two communication phases during bus communication.

[0022] The object is achieved by a transmitting / receiving device for receiving differential signals in a serial bus system with the features of claim 1. The transmitting / receiving device has a first comparator for evaluating differential signals received from a bus of the bus system with a first reception threshold for generating a first digital comparator output signal, a second comparator for evaluating the differential signals received from the bus with a second reception threshold that differs from the first reception threshold for generating a second digital comparator output signal, a logic circuit for combining the first and second digital comparator output signals to output a reception signal to a communication control device of the subscriber station, and a filter block for evaluating the reception signal and the second comparator output signal to decidewhether the second digital comparator output signal should be output to the logic circuit with a delay or not, and to output the second digital comparator output signal to the logic circuit based on the evaluation of the filter block.

[0023] With the described transmitting / receiving device, it is possible to correctly generate the receive signal for at least one differential signal transmitted on the bus, even if interference occurs on the bus and the transmitting / receiving device uses a comparator with a comparatively low threshold of -1 V and high bandwidth or high bandwidth requirements.

[0024] The described transmit / receive device is designed to ensure reliable and uncomplicated detection of bus signals during bus system operation. This applies particularly to communication in which the physical layer can be switched between two communication phases for bus communication and bus disturbances occur. The receive module can reliably distinguish between the respective bus states of the individual communication phases and thus the individual communication phases during bus communication for all operating scenarios.

[0025] The described transmitting / receiving device enables the specifications for communication to be met in accordance with the requirements of CAN XL, which are laid down in particular in the standards CIA610-3, CiA601 -4 and / or in the international standard ISO / DIS 11898-1:2023.

[0026] The described transceiver device solves the problem of suppressing bus interference at a relatively low cost. Compared to a conventional transceiver device, especially for CAN XL, this significantly improves interference immunity and, in particular, the received signal quality.

[0027] In addition, the described transceiver device can ensure that a subscriber station that is added and attempts to integrate into the bus communication does not disrupt the bus communication. This is because the subscriber station can reliably detect whether the bus is free of data traffic using the transceiver device. Since the transceiver device reliably assigns the current bus states, the newly added subscriber station will only send data to the bus when the bus is free. Thus, adding a subscriber station that is, for example, initially starting up or attempting to reintegrate into the bus communication after a bus communication error does not disrupt the bus communication.

[0028] As a result, the transceiver device enables the functionality to use different receive thresholds for the arbitration phase and the data phase, while still ensuring improved robustness against bus disturbances. This not only enables communication within the bus system at higher bit rates, but also prevents the transmittable bit rate from being reduced due to communication errors.

[0029] Advantageous further embodiments of the receiving module are described in the dependent claims.

[0030] The filter block can be designed to output the second digital comparator output signal with a temporarily changed value to the logic circuit on the basis of its evaluation.

[0031] The filter block may be configured to partially withhold output of the second digital comparator output signal to the logic circuit based on its evaluation. According to one configuration, the filter block is configured to evaluate whether the second comparator has detected an undershoot of the second reception threshold in a first predetermined period of time in which the reception signal has a predetermined value. The filter block is configured to output the second digital comparator output signal to the logic circuit if an undershoot of the second reception threshold was not detected in the first predetermined period of time. The filter block is configured to drive a predetermined value for the second digital comparator output signal to the logic circuit for a predetermined period of time if an undershoot of the second reception threshold was detected in the first predetermined period of time.

[0032] According to one embodiment, the filter block is designed not to output the second digital comparator output signal to the logic circuit if, in a second predetermined period of time, the values ​​of the received signal indicate that the first received threshold was exceeded at least once, and the values ​​of the second digital comparator output signal indicate that the second received threshold was undershot at least once.

[0033] It is conceivable that the filter block is designed as a time recording unit for recording the first and / or the second predetermined time period, and wherein the time recording unit is designed as a counter.

[0034] The filter block may be configured, in an operating mode in which the transmitting / receiving device is only a receiver of the signals from the bus, to evaluate whether a transmitted signal, which the communication control device sends to the transmitting / receiving device, contains a predetermined bit indicating error-free reception of a frame on the basis of which the transmitted signal was generated. The filter block may be configured not to output the second digital comparator output signal to the logic circuit after the predetermined bit until the filter block detects a start bit for the next frame in the received signal. Optionally, the received signal has bits with a first bit time in a first communication phase on the bus and bits with a second bit time that is shorter than the first bit time in a second communication phase.

[0035] The first predetermined time period may be greater than 5 bits with the first bit time and less than 11 bits with the first bit time

[0036] The transmitting / receiving device may be configured to set the first bit time in the transmitting / receiving device, after a restart of the transmitting / receiving device, to a bit time for a fastest possible data rate that may be set in the first communication phase, wherein the transmitting / receiving device is configured to subsequently adapt the first bit time to the bit time of a predetermined bit that was received after successful reception of a frame at an input of the transmitting / receiving device for the transmission signal.

[0037] It is conceivable that the second predetermined time period is less than 11 bits with the second bit time.

[0038] The transmitting / receiving device can be designed to receive differential signals for communication in a bus system in which, in the first communication phase, it is negotiated between the subscriber stations on the bus which of the subscriber stations has exclusive, collision-free access to the bus of the bus system in the subsequent second communication phase.

[0039] The transmitting / receiving device can be designed to generate the differential signals for the bus in the first communication phase with a first physical layer and to generate them in the second communication phase with a second physical layer that differs from the first physical layer.

[0040] According to a special embodiment, the transmitting / receiving device also has a receiving stage which is connected upstream of the first comparator and is designed to set either the first receiving threshold or a third receiving threshold for the first comparator, which is different from the first and second receiving thresholds, so that the first comparator evaluates the differential signals with either the first receiving threshold or the third receiving threshold to generate the first digital comparator output signal. Additionally or alternatively, the receiving stage can be a resistive voltage divider.Additionally or alternatively, the first comparator can be designed to be switchable between the first reception threshold and a third reception threshold in order to evaluate the differential signals received from a bus of the bus system to generate the first digital comparator output signal either with the first reception threshold or with the third reception threshold. The previously described transmitting / receiving device can be part of a subscriber station for a serial bus system. The subscriber station can also have a communication control device for controlling communication in the bus system and for generating a digital transmission signal for the transmitting / receiving device. The transmitting / receiving device can also have a driver for driving the digital reception signal to the communication control device and / or a transmission module for transmitting signals to a bus of the bus system.

[0041] The aforementioned object is also achieved by a method for receiving differential signals in a serial bus system with the features of claim 16. The method comprises the steps of evaluating, with a first comparator, differential signals received from a bus of the bus system with a first reception threshold and generating a first digital comparator output signal, evaluating, with a second comparator, the differential signals received from the bus with a second reception threshold that differs from the first reception threshold and generating a second digital comparator output signal, combining, with a logic circuit, the first and second digital comparator output signals to output a reception signal to a communication control device of the subscriber station, evaluating, with a filter block, the reception signal and the second comparator output signal to decide,whether or not the second digital comparator output signal should be output to the logic circuit with a delay, and outputting the second digital comparator output signal to the logic circuit based on the evaluation of the filter block.

[0042] The method offers the same advantages as previously mentioned with regard to the receiving module.

[0043] Further possible implementations of the invention also include combinations of features or embodiments described above or below with respect to the exemplary embodiments that are not explicitly mentioned. In this case, the person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention.

[0044] Drawings

[0045] The invention is described in more detail below with reference to the accompanying drawings and exemplary embodiments. They show:

[0046] Fig. 1 is a simplified block diagram of a bus system according to a first embodiment;

[0047] Fig. 2 is a diagram illustrating the structure of a message that can be sent by a subscriber station of the bus system according to the first embodiment;

[0048] Fig. 3 shows the format of CAN XL frames according to the standard ISO / DIS 11898-2:2023 for a message that can be sent to the bus by a transceiver for a subscriber station of the bus system according to the first embodiment;

[0049] Fig. 4 shows an example of the ideal time course of bus signals CAN_H, CAN_L in the bus system of Fig. 1;

[0050] Fig. 5 shows the time profile of a differential voltage VDIFF that develops on the bus of the bus system as a result of the bus signals of Fig. 4; Fig. 6 shows an example of a time profile of a digital transmission signal that is to be converted into bus signals CAN_H, CAN_L for a bus of the bus system of Fig. 1 during the arbitration phase in a SIC operating mode of the transmitting / receiving device.

[0051] Fig. 7 shows the time course of the bus signals CAN_H, CAN_L when changing between a recessive bus state to a dominant bus state and back to the recessive bus state, which are sent to the bus in the arbitration phase of CAN XL and in the SIC operating mode of the transceiver device due to the transmission signal of Fig. 6;

[0052] Fig. 8 is a simplified block diagram of a transceiver device for a subscriber station of the bus system according to the first embodiment;

[0053] Fig. 9 shows an example of the time course of a differential voltage VDIFF which forms on the bus of the bus system as a result of signals generated by sending a frame on the bus and by external disturbances on the bus;

[0054] Fig. 10 to Fig. 15 each show the time course of signals which were generated as a result of the differential voltage VDIFF of Fig. 9 by the transceiver device according to the first embodiment;

[0055] Fig. 16 is a simplified block diagram of a transceiver device for a subscriber station of the bus system according to a second embodiment;

[0056] Fig. 17 is a simplified block diagram of a transceiver device for a subscriber station of the bus system according to a third embodiment;

[0057] Fig. 18 shows an example of the time course of a differential voltage VDIFF, which develops on the bus of the bus system as a result of signals generated by the transmission of two consecutive frames on the bus and by external disturbances on the bus; and

[0058] Fig. 19 to Fig. 26 each show the time course of signals which are generated as a result of the differential voltage VDIFF of Fig. 18 by the transceiver device according to the third embodiment.

[0059] In the figures, identical or functionally equivalent elements are provided with the same reference numerals unless otherwise indicated.

[0060] Description of the embodiments

[0061] Fig. 1 shows a bus system 1, which can, for example, at least in sections, be a CAN bus system, a CAN-FD bus system, etc. The bus system 1 can be used in a vehicle, in particular a motor vehicle, an aircraft, etc., or in a hospital, etc. The bus system 1 is not limited to the CAN bus system, even if the bus system 1 is described below with reference to the CAN bus system.

[0062] In Fig. 1, the bus system 1 has a plurality of subscriber stations 10, 20, 30, each connected to a bus 40 configured as a bus line with a first bus wire 41 and a second bus wire 42. The bus wires 41, 42 can also be referred to as CAN_H and CAN_L for the signals on the bus 40. Messages 45, 46 in the form of signals can be transmitted between the individual subscriber stations 10, 20, 30 via the bus 40. The signals can be differential signals, as described in more detail below. The subscriber stations 10, 20, 30 can be, for example, control units or display devices of a motor vehicle.

[0063] As shown in Fig. 1, the subscriber stations 10, 30 each have a communication control device 11 and a transmitting / receiving device 12. The transmitting / receiving device 12 has a transmitting module 121 and a receiving module 122. The subscriber station 20 has a communication control device 21 and a transmitting / receiving device 22. The transmitting / receiving device 22 has a transmitting module 221 and a receiving module 222.

[0064] The transmitting / receiving devices 12 of the subscriber stations 10, 30 and the transmitting / receiving device 22 of the subscriber station 20 are each directly connected to the bus 40, even if this is not shown in Fig. 1.

[0065] The communication control devices 11, 21 each serve to control communication of the respective subscriber station 10, 20, 30 via the bus 40 with at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to the bus 40.

[0066] The communication control devices 11 create and read first messages 45, which are, for example, Classical CAN or CAN FD messages, or second messages 46, which are, for example, CAN XL messages. The transmitting / receiving device 12 is used to transmit the messages 45, 46 to the bus 40 and receive the messages 45, 46 from the bus 40. The transmitting module 121 serially receives a digital transmit signal TxD created by the communication control device 11 for one of the messages 45, 46 and converts this into signals on the bus 40. The receiving module 121 receives signals corresponding to the messages 45, 46 transmitted serially on the bus 40 and generates a digital receive signal RxD therefrom. The receiving module 122 transmits the receive signal RxD serially to the communication control device 11.

[0067] The communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1:2015, i.e. like a CAN FD-tolerant Classical CAN controller or a CAN FD controller. The communication control device 21 creates and reads first messages 45, for example CAN FD messages 45. The transceiver device 22 serves to send the messages 45 to the bus 40 and to receive the messages 45, and some of the messages 46, from the bus 40. The transmit module 221 receives a digital transmit signal TxD created by the communication control device 21 and converts it into signals for a message 45 on the bus 40. The receive module 221 receives signals transmitted on the bus 40 corresponding to the messages 45, 46 and generates a digital receive signal RxD therefrom.Otherwise, the transmitting / receiving device 22 can be designed like a conventional CAN transceiver that receives and / or transmits signals serially and processes them accordingly, as previously described.

[0068] To send messages 46 with CAN SIC or CAN XL, proven properties are adopted that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular the frame structure with identifier and arbitration according to the well-known CSMA / CR method.

[0069] With the two subscriber stations 10, 30, the formation and then transmission of messages 45, 46 with various CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format, as well as the reception of such messages 45, 46 is possible, as described in more detail below.

[0070] Fig. 2 shows a frame 450 for message 45, which is in particular a CAN FD frame, as provided by each of the communication control devices 11, 21 for the associated transmitting / receiving device 12, 22 for transmission on the bus 40. In this embodiment, the communication control device 11, 21 creates the frame 450 as compatible with CAN XL.

[0071] According to Fig. 2, frame 450 for CAN communication on bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). After a start bit SOF, frame 450 has an arbitration field 453, a control field 454, a data field 455, a checksum field 456, and a frame termination field 457. This is followed by an end-of-frame field EOF (EOF).

[0072] In the arbitration phase 451, using an identifier (ID) with, for example, bits ID28 to IDO in the arbitration field 453, the subscriber stations 10, 20, 30 negotiate bit by bit which subscriber station 10, 20, 30 wishes to send the message 45, 46 with the highest priority and therefore receives exclusive access to the bus 40 of the bus system 1 for the next transmission time in the subsequent data phase 452. In the arbitration phase 451, a physical layer 451_P (Fig. 4) is used, as in CAN and CAN-FD. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection Model).

[0073] An important point during phase 451 is the use of the well-known CSMA / CR method, which allows simultaneous access of the subscriber stations 10, 20, 30 to the bus 40 without destroying the higher-priority message 45, 46. This allows additional bus subscriber stations 10, 20, 30 to be added to the bus system 1 relatively easily, which is very advantageous.

[0074] The CSMA / CR method requires so-called recessive states on bus 40, which can be overwritten by other subscriber stations 10, 20, or 30 with dominant levels or dominant states on bus 40. In the recessive state, high-impedance conditions prevail at the individual subscriber stations 10, 20, or 30, which, in combination with the parasitics of the bus circuitry, results in longer time constants. This limits the maximum bit rate of today's CAN FD physical layer to approximately 2 megabits per second in real-world vehicle use.

[0075] In the data phase 452, in addition to part of the control field 454, the payload of the CAN FD frame 450 or the message 45 from the data field 455 and the checksum field 456 are sent. The checksum field 456 can contain a checksum of the data of the data phase 452, including the stuff bits, which are inserted by the sender of the message 45 as an inverse bit after a predetermined number of identical bits, in particular 10 identical bits (“stuff bit rule”). At the end of the data phase 452, the system switches back to the arbitration phase 451. The frame termination field 457 can contain at least one acknowledge bit, which is also called an ACK bit. The at least one acknowledge bit can be used to indicate whether or not a receiver has detected an error in the received CAN FD frame 450 or the message 45.

[0076] The end field EOF may contain a sequence of 11 identical bits indicating the end of the CAN FD frame 450.

[0077] After the end-of-frame field (EOF), the frame 450 is followed by an interframe space (IFS). The interframe space has at least 11 bits of the arbitration phase 451, as explained in more detail below.

[0078] During the end-of-frame (EOF) and the interframe (IFS) interval, no communication occurs on bus 40. During the end-of-frame (EOF) and the interframe (IFS) interval, bus 40 is free of traffic. Bus 40 is in the idle state, which can also be referred to as the idle or standby state.

[0079] A sender of the message 45 begins sending bits of the data phase 452 to the bus 40 only when the subscriber station 10 as the sender has won the arbitration and the subscriber station 10 as the sender thus has exclusive access to the bus 40 of the bus system 1 for sending.

[0080] Thus, in the arbitration phase 451 as the first communication phase, the subscriber stations 10, 30 partially use, in particular up to the FDF bit (inclusive), a format known from CAN / CAN-FD in accordance with ISO11898-1:2015. However, compared to CAN, in the data phase 452 as the second communication phase, an increase in the net data transmission rate to 2 megabits per second is possible, in particular to over 8 megabits per second when generating the signal with CAN SIC. Furthermore, an increase in the size of the payload data per frame, in particular to approximately 64 bytes, is possible. Fig. 3 shows a frame 460 for the message 46, which is in particular a CAN XL frame, as provided by the communication control device 11 for the transmitting / receiving device 12 for transmission on the bus 40. In this case, the communication control device 11 creates the frame 460 in the present embodiment as compatible with CAN FD.

[0081] Thus, the CAN XL frame 460 for the CAN communication on the bus 40 is also divided into different communication phases 451, 452, namely the arbitration phase 451 and the data phase 452.

[0082] As shown in Fig. 3, in the arbitration phase 451 as the first communication phase, subscriber station 10, as well as subscriber station 30, partially uses the format known from CAN FD according to ISO / DIS 11898-1:2023, in particular up to and including the FDF bit. In contrast, subscriber station 10, as well as subscriber station 30, uses a CAN XL format starting with the FDF bit in the first communication phase 451 and in the data phase 452 as the second communication phase, as follows. In the CAN XL data phase 452, symmetrical '1' and '0' levels are used for transmission on bus 40, instead of recessive and dominant levels as in CAN FD.

[0083] After a start bit (SOF), frame 460 has an arbitration field 463, a control field 464 with an ADS field for switching between the communication phases 451, 452, a data field 465, a checksum field 466 and a frame termination field 467. This is followed by an end of frame field EOF, as in frame 450. The CAN-XL format is defined in ISO / DIS 11898-2:2023.

[0084] In the arbitration phase 451, the arbitration is also performed for frame 460 of Fig. 3 using the identifier (ID), as previously described with reference to Fig. 2 for the various bus configurations. In the arbitration phase 451, an arbitration bit rate of less than or equal to 1 Mbit / s is used in the present embodiment.

[0085] According to Fig. 3, in the data phase 452, in addition to a part of the control field

[0086] 464 of frame 460, the payload data of CAN-XL frame 460 or message 46 from data field 465 as well as the checksum field 466 are sent. In the data phase 452, the present embodiment uses a data bit rate that can have values ​​of up to 20 Mbps, in particular.

[0087] After the data phase 452, in CAN XL, according to Fig. 3, the DAS field follows, which is used to switch from the data phase 452 back to the arbitration phase 451.

[0088] In the CAN XL data phase 452, when using appropriate transmit / receive devices for CAN XL, symmetrical '1' and '0' levels can be used for transmission on the bus 40, instead of recessive and dominant levels as in CAN FD.

[0089] In general, two different stuffing rules are applied when generating frame 460. Up to the FDF bit in the arbitration field 453, the dynamic bit stuffing rule of CAN FD, or for a frame 450 of Fig. 2, applies, so that after every five identical bits in a row, an inverse stuff bit is inserted. In the data phase 452 up to the FCP field in Fig. 3, a fixed stuffing rule applies, so that after a fixed number of bits, a fixed stuff bit is inserted that is the inverse of the previous bit. Alternatively, instead of just one stuff bit, two or more bits can be inserted as fixed stuff bits.

[0090] In the present exemplary embodiment, the res bit known from CAN FD, which is designated as the XLF bit in frame 460, is used to switch from the CAN FD format to the CAN XL format. Therefore, the frame formats of CAN FD and CAN XL are identical up to the res bit or XLF bit. A receiver only recognizes the format in which frame 460 is being sent when it receives this bit. If the bit is sent as 1, i.e. recessively, it is the XLF bit and thus identifies frame 460 as a CAN XL frame. For a CAN FD frame of Fig. 2, the communication control device 11, 31 sets the bit as 0, i.e. as the dominant res bit.

[0091] After the XLF bit, frame 460 is followed by a resXL bit, which is a dominant bit for future use. The resXL must be transmitted as 0, i.e., dominant, for frame 460. After the resXL bit, frame 460 is followed by an ADS (Arbitration Data Switch) sequence, in which a predetermined bit sequence is encoded. This bit sequence allows for simple and reliable switching from the bit rate of arbitration phase 451 (arbitration bit rate) to the bit rate of data phase 452 (data bit rate). Optionally, within the ADH bit, the operating mode of the transmitting / receiving device 12, 32 is switched from operating mode B_451 (SIC) of arbitration phase 451 to one of two operating modes: B_452_TX, B_452_RX of data phase 452.The two operating modes of data phase 452 are a B_452_TX (FAST_TX) operating mode for a transmitting node that is permitted to transmit its signal to bus 40 during data phase 452, and a B_452_RX (FAST_RX) operating mode for a receiving node that is only a receiver of the signal from bus 40. To achieve data bit rates of up to 20 Mbps, the physical layer, i.e., the operating mode of the transceiver device 12, is switched from SLOW or SIC to FAST_TX or FAST_RX within the ADH bit. Switching the physical layer is necessary when data bit rates of over 8 Mbps are required or when a complex CAN bus topology is used, which is the case, for example, with long spur lines.

[0092] The following fields up to the beginning of data field 465 are not described in detail here. Data field 465 can have up to 2048 bytes. The length of data field 465 is encoded in bits 0 through 10 of the DLC field.

[0093] Following the data field 465 in frame 460 is the checksum field 466, which contains a frame checksum (FCRC) and an FCP field. FCP = Frame Check Pattern. The FCP field consists of 4 bits, specifically the bit sequence 1100. A receiving node uses the FCP field to check whether the receiving node is bit-synchronized with the transmit data stream. Furthermore, a receiving node synchronizes itself to the falling edge in the FCP field.

[0094] The FCP field is followed by the frame termination field 467. The frame termination field 467 consists of two fields, namely the DAS field and the acknowledgment field or ACK field with at least one ACK bit and the ACK-Dlm bit. The DAS field contains the DAS (Data Arbitration Switch) sequence, in which a predetermined bit sequence is encoded. The bit sequence DAH, AH1, AL1 allows for a simple and secure switchover from the data bit rate of the data phase 452 to the arbitration bit rate of the arbitration phase 451. Furthermore, during the DAS field, more precisely in the DAH bit, the operating mode of the transmitting / receiving device 12, 32 is switched, optionally from an operating mode B_452_TX (FAST_TX) or B_452_RX (FAST_RX) to the operating mode B_451 (SLOW or SIC). If the physical layer was previously switched, the physical layer is switched within the DAH bit. Bit AH1 is followed by bit AL1 (logical 0) and bit AH2 (logical 1).The two bits DAH and AH1 ensure that sufficient time is available for the operating mode switching of the transmit / receive device 11, and that all subscriber stations 10, 30 see a recessive level significantly more than one arbitration bit time before the edge at the beginning of the AL2 bit (logical 0). This ensures reliable synchronization for the subscriber stations of the bus system.

[0095] In the frame termination field 467, the acknowledgment field (ACK) follows the DAS field sequence. The acknowledgment field contains bits for confirming or denying correct reception of frame 460.

[0096] After the frame termination field 467, the frame end field EOF follows in the frame 460, as in CAN FD according to Fig. 2.

[0097] For subscriber stations whose error signaling is not enabled and that transmit a CAN XL frame, the end-of-frame field (EOF) has a length that varies depending on whether a dominant bit or a recessive bit was seen in the ACK bit. If the transmitting subscriber station received the ACK bit as dominant, the end-of-frame field (EOF) has 7 recessive bits. Otherwise, the end-of-frame field (EOF) is only 5 recessive bits long. Following the end-of-frame field (EOF) in frame 460 is the interframe space (IFS), as previously explained with reference to frame 450 in Fig. 2.

[0098] The following applies to CAN XL.

[0099] - In contrast to CAN FD, the identifier ID of frame 460 in CAN XL is called “Priority ID”.

[0100] - Unlike CAN FD, CAN XL can send the RRS bit as (logical) 0 or as (logical) 1. In CAN FD, the RRS bit is always sent as logical 0.

[0101] Fig. 4 shows on the left that during the arbitration phase 451, subscriber stations 10, 20, and 30 send signals CAN_H and CAN_L to bus 40, which alternately have at least one dominant state 401 or at least one recessive state 402. States 401 and 402 each have a bit time of T_bt1. After the arbitration in the arbitration phase 451, one of the subscriber stations 10, 20, and 30 is declared the winner. Assume that subscriber station 10 has won the arbitration. Then, at the end of the arbitration phase 451, the transmitting / receiving device 12 of the subscriber station 10 switches its physical layer 451_P from a first operating mode (SLOW or SIC) to a second operating mode (FAST_TX), since the subscriber station 10 is the sender of the message 45 in the data phase 452. The transmitting module 121 then generates in the data phase 452 orIn the second operating mode (FAST_TX), depending on a transmit signal TxD, the states L0 or L1 are sequentially and thus serially transferred to a physical layer 452_P for the CAN_H and CAN_L signals on bus 40. In the example shown in Fig. 4, the states L0 and L1 each have a bit time of T_bt2. The bit time T_bt2 is shorter than the bit time T_bt1.

[0102] As a result, the frequency of the CAN_H, CAN_L signals can be increased in the data phase 452, as shown on the right-hand side of Fig. 4. Thus, the net data transmission rate in the data phase 452 is increased compared to the arbitration phase 451. In contrast, at the end of the arbitration phase 451, the transmitting / receiving device 12 of the subscriber station 30 switches its physical layer 451_P from the first operating mode (SLOW or SIC) to a third operating mode (FAST_RX), in which the physical layer 452_P is also used, since the subscriber station 30 is only a receiver, i.e., not a transmitter, of the frame 450 in the data phase 452. After the end of the arbitration phase 451, all transmitting / receiving devices 12 of the subscriber stations 10, 30 switch their operating mode to the first operating mode (SLOW or SIC). Thus, all transmitting / receiving devices 12 also switch their physical layer.

[0103] According to Fig. 5, in the arbitration phase 451, in the ideal case, a differential signal VDIFF = CAN_H - CAN_L with values ​​of VDIFF = 2V for dominant states 401 and VDIFF = 0V for recessive states 402, each with a bit time T_bt1, is generated on bus 40. This is shown on the left side of Fig. 5.

[0104] In contrast, in the data phase 452, a differential signal VDIFF = CAN_H - CAN_L with states L0, L1 with bit time T_bt2 is formed on bus 40, as shown on the right side of Fig. 5. State L0 has a value VDIFF = 1 V. State L1 has a value VDIFF = -1 V.

[0105] The receiving module 122 of Fig. 1 can distinguish the states 401, 402 each with two of the receiving thresholds T1, T2, T3, which lie in the ranges TH_T1, TH_T2, TH_T3, as shown in Fig. 5. To evaluate the signals from the bus 40, the receiving module 122 uses the receiving threshold T1 of, for example, 0.7 V in the arbitration phase 451 to generate the receiving signal RxD, and optionally the receiving threshold T2 of, for example, -0.35 V. In contrast, the receiving module 122 uses the receiving threshold T3 in the data phase 452 to evaluate the signals from the bus 40 to generate the receiving signal RxD. When switching between the first to third operating modes (SLOW or SIC, FAST_TX, FAST_RX) previously described with reference to Fig. 4, the receiving module 122 switches the receiving thresholds T1, T3, respectively, as described below.

[0106] The reception thresholds T1 and T2 are used to detect whether the bus 40 is free when the subscriber station 12 is newly connected to the communication on bus 40 and attempts to integrate itself into the communication on bus 40. The reception threshold T2 is referred to in the CAN standard as OOB (= Out-of-Boundary). The conditions for a traffic-free CAN-XL bus 40 are that no dominant state 401 occurs, which typically has the differential voltage VDIFF = 2V. Thus, the reception threshold T1 of, for example, 0.7V must not be exceeded. Furthermore, no levels corresponding to state L1 may occur, which typically has the differential voltage VDIFF = 2V -1V. Thus, the reception threshold T2 of, for example, -0.35V must not be undercut.

[0107] Each subscriber station 10, 30 switches the operating mode of the transmitting / receiving device 12 to the operating mode of the arbitration phase 451 when the subscriber station 10, 30 is newly added to the communication on the bus 40.

[0108] The connection of, for example, subscriber station 10 may be necessary, on the one hand, when subscriber station 10 is initially started and is to be integrated into the communication on bus 40. On the other hand, the connection of subscriber station 10 may be necessary if subscriber station 10 attempts to reintegrate into the communication on bus 40 after an error in the bus communication. Only when it is detected that the bus is free, i.e., free of traffic or communication, may subscriber station 10 itself send data, in particular messages 46, to bus 40 in the aforementioned cases.

[0109] The following Table 1 shows the values ​​that can be set by the subscriber station 10, in particular its receive module 122, for the individual receive thresholds for receiving signals from the bus 40. VDIFF_min specifies the lower limit in volts (V) that can be set for the corresponding receive threshold T1, T2, T3 for the individual ranges TH_T1, TH_T2, TH_T3. VDIFF_typ specifies the value that is typically or usually set for the corresponding receive threshold T1, T2, T3 in volts (V). VDIFF_max specifies the upper limit in volts (V) that can be set for the corresponding receive threshold T1, T2, T3 for the individual ranges TH_T1, TH_T2, TH_T3.

[0110] Table 1 : Tolerance ranges of the reception thresholds T1 , T2, T3

[0111] The following Table 2 shows the permitted minimum and maximum levels of the differential voltage VDIFF in volts (V) that a transmitting subscriber station (transmitting node) may generate on the bus 40 for the individual bus states 401 (DOM), 402 (REC), 403 (SIC), LVO, LV1.

[0112] Table 2: According to the specification, permitted voltage levels on the bus according to bus state

[0113] If subscriber station 10 is now connected, as previously mentioned as an example, subscriber station 10, as a receiving node, cannot reliably detect the LVO state on bus 40 with the reception threshold T1. The reason for this is that, according to Table 1 and Table 2, V_DIFF_L0_send_min = 0.5V < V_DIFF_receive_max = 0.9V. Therefore, the transmitting / receiving device 12 of subscriber station 10 is designed to simultaneously check not only the reception threshold T1, but also the reception threshold T2, as described in more detail below, so that false detection of the idle state on bus 40 (false IDLE detection) is prevented.

[0114] Fig. 6 shows an example of a portion of the digital transmission signal TxD, which the transmission module 121 receives from the communication control device 11 in the arbitration phase 451, and from which it generates the signals CAN_H, CAN_L of Fig. 7 for the bus 40 when the transmission module 121 is switched to the SIC operating mode. In Fig. 6, the transmission signal TxD changes from a state LW (Low) to a state Hl (High) and back to the state LW (Low).

[0115] Ideally, the receive signal RxD is identical to the transmit signal TxD. In such an ideal case, there is no transmission delay / propagation time, especially via bus 40, and no possible receive errors. Therefore, the receive signal RxD is not shown separately.

[0116] As shown in more detail in Fig. 7, the transmit module 121 for the transmit signal TxD of Fig. 6 in the CAN SIC operating mode can receive the signals CAN_H, CAN_L of Fig.

[0117] 7 for the bus wires 41, 42. To generate signals according to Fig. 7, the transmitter module 121 in CAN XL is switched to an SIC operating mode (SIC mode) instead of the SLOW operating mode.

[0118] In contrast to Fig. 4, the signals in Fig. 7 also include a state 403 (sic). State 403 (sic) can vary in length, as shown with state 403_0 (sic) during the transition from state 402 (rec) to state 401 (dorn) and with state 403_1 (sic) during the transition from state 401 (dorn) to state 402 (rec). State 403_0 (sic) is shorter in time than state 403_1 (sic).

[0119] Passing through the short sic state 403_0 is not required by ISO / FDIS11898-2:2023, and the state depends on the implementation type. The duration of the "long" state 403_1 (sic) is specified for the first operating mode (SLOW or SIC) as t_sic < 530 ns, starting with the rising edge of the transmit signal TxD in Fig. 6.

[0120] In the "long" state 403_1 (sic) according to Fig. 7, the transmit module 121 should match the impedance between the bus wires 41 (CANH) and 42 (CANL) as closely as possible to the characteristic wave impedance Zw of the bus line used. Here, Zw=1000 hm or 1200 hm. This matching prevents reflections and thus allows operation at higher bit rates. For simplicity, the following will always refer to state 403 (sic) or sic state 403. Fig. 8 shows the basic structure of the transmit / receive device 12 of the subscriber station 10. The transmit module 121 is shown only in a very simplified manner. The transmit module 121 is connected directly to the bus 40 in order to be able to transmit the transmit signal TxD of the communication control device 11 to the bus 40. For this purpose, the transmitting module 121 generates signals according to Fig. 4 or Fig. 7 on the bus 40, as previously described.

[0121] During operation of the bus system 1, the transmitting / receiving device 12 receives, for example, a differential voltage VDIFF according to Fig. 9 from the bus 40. The receiving module 122 generates the signals from Fig. 10 to Fig. 15 therefrom, as described below. In the example of Fig. 9, disturbances G1 in the form of glitches, i.e. temporary errors, occur on the bus 40. In the example of Fig. 9, the disturbances G1 occur at the sampling point t_A, at which the receiving module 122 evaluates the differential voltage VDIFF from Fig. 9, as described above. However, the receiving module 122 is configured as follows in order to compensate for the disturbances G1, which simulate a dominant state 401, in such a way that the disturbances G1 are not present in a compensated received signal RxD2 from Fig. 15.

[0122] According to Fig. 8, the receiving module 122 has a driver 1221 for the digital received signal RxD, a logic circuit 1222 and a receiving circuit 15. The receiving circuit 15 has a first receiving comparator 151, a second receiving comparator 152, a receiving stage 153 and a filter block 154. The filter block 154 has a receiving threshold evaluation unit 1541, a time detection unit 1542 and a signal processing unit 1543. A predetermined time period T_P is stored in the signal processing unit 1543.

[0123] The receiving comparators 151, 152 are each low-voltage comparators. The filter block 154 can be configured as a digital component.

[0124] The receiving circuit 15 is connected between the bus 40 and the logic circuit 1222. The driver 1221 is connected to the output of the logic circuit 1222. Depending on the operating mode of the transmitting / receiving device 12, the logic circuit 1222 is configured to output a signal CA1 and a signal CA2, which are described in more detail below, to the driver 1221 or to output only the signal CA2 to the driver 1221. For this purpose, the logic circuit 1222 can have at least one AND gate. Alternatively, the logic circuit 1222 has other logic components to fulfill the function of the receiving module 122 described below.

[0125] The driver 1221 drives or transmits the digital receive signal RxD at the output RXD of the transceiver 12 to the communication controller 11. The digital receive signal RxD is either the receive signal RxD1 of Fig. 14 or the compensated receive signal RxD2 of Fig. 15, as described below.

[0126] In the receiving circuit 15, the receiving stage 153 is connected to the bus 40. The receiving stage 153 can be configured as a voltage divider having separate receiving branches for the differential signals CAN_H, CAN_L. Optionally, the receiving stage 153 is configured to set either the first receiving threshold T1 of Fig. 5 or the third receiving threshold T3 of Fig. 5 for the first comparator 151, as required. Furthermore, the receiving stage 153 sets the second receiving threshold T2 of Fig. 5 for the second comparator 152. The receiving stage 153 is configured, in particular, as a resistive voltage divider or resistance voltage divider. In such a voltage divider, the receiving thresholds T1, T2, T3 are set using electrical resistors. The voltage divider divides the bus voltages generated by the signals CAN_H, CAN_L into values ​​that can be processed by the comparators 151, 152.Optionally, the receiving stage 153, with the comparators 151, 152, checks two different reception thresholds of the reception thresholds T1, T2, T3 of Fig. 4 independently of one another and thus also simultaneously or simultaneously. In addition, switching can be performed between two reception thresholds of the reception thresholds T1, T2, T3. As a result, with respect to the at least one signal VDIFF, CAN_H, CAN_L received from the bus 40, the receiving circuit 15 can either check the reception thresholds T1, T2 according to Fig. 4 independently of one another and simultaneously, or the reception thresholds T3, T2 according to Fig. 4 independently of one another and simultaneously.

[0127] During operation of bus system 1, the receiving stage 153 generates differential signals S_1, S_2 from the signals CAN_H, CAN_L, or the voltage VDIFF at its input. The receiving stage 153 forwards the differential signals S_1, S_2 to the first receiving comparator 151 at its output.

[0128] The first receiving comparator 151 generates a comparator output signal CA1 from the signals S_1, S_2, as shown as an example in Fig. 10. Fig. 10 shows the time profile of the comparator output signal CA1, which the first comparator 151 of the receiving module 122 of Fig. 8 generates based on the differential voltage VDIFF of Fig. 9.

[0129] The comparator output signal CA1 of Fig. 10 indicates in the arbitration phase 451 of a frame 450, 460 whether the first reception threshold T1 of Fig. 9 has been exceeded or not. According to the example of Fig. 10, the comparator output signal CA1 in the arbitration phase 451 of a frame 450, 460 has the value Hl = high (HIGH) if the first reception threshold T1 of Fig. 9 has not been exceeded. Furthermore, the comparator output signal CA1 of Fig. 10 in the arbitration phase 451 of a frame 450, 460 has the value LW = low (LW) if the first reception threshold T1 of Fig. 9 has been exceeded. In the data phase 452 of a frame 450, 460, which is not shown in Fig. 10, the comparator output signal CA1 indicates whether the third reception threshold T3 of Fig. 5 is exceeded or not.

[0130] In addition, during operation of the bus system 1, the receiving stage 153 of Fig. 8 additionally generates differential signals S_3, S_4 from the signals CAN_H, CAN_L or the voltage VDIFF at its input. The receiving stage 153 forwards the differential signals S_3, S_4 at its output to the second receiving comparator 152. The receiving stage 153 uses the second receiving threshold T2 of Fig. 5 or Fig. 9 to generate the signals S_3, S_4, at least in the arbitration phase 451. However, in the data phase 452, the receiving stage 153 and / or the filter block 154 inhibits or blocks the forwarding of the signal CA2 to the logic circuit 1222 and thus to the driver 1221. In other words, the second receive comparator 152 has no access to the logic circuit 1222 and thus the driver 1221 in the data phase 452. This applies regardless of whether the receive stage 153 and / or the second comparator 152 checks the receive threshold T2 or not.

[0131] The second receive comparator 152 generates a comparator output signal CA2 from the signals S_3, S_4, as shown as an example in Fig. 11. According to the example of Fig. 11, the comparator output signal CA2 has the value Hl = high (HIGH) in the arbitration phase 451 of a frame 450, 460 if the second receive threshold T2 of Fig. 9 is not undershot, in other words, if it is exceeded. Furthermore, the comparator output signal CA2 of Fig. 11 has the value LW = low (LW) in the arbitration phase 451 of a frame 450, 460 if the second receive threshold T2 of Fig. 9 is undershot, in other words, if it is not exceeded.

[0132] The comparator output signal CA2 is input to the filter block 154. As shown in Fig. 8, the digital receive signal RxD output by the driver 1221 is input to the filter block 154 in addition to the comparator output signal CA2.

[0133] The filter block 154 generates signals CA2_E and cnt_rxd_h according to Fig. 12 and Fig. 13 and evaluates them, as explained in more detail below. Depending on the evaluation of the signals CA2_E and cnt_rxd_h, the signal processing unit 1543 drives the output RXD of the transceiver 12 of Fig. 8 to the value LW = low (LOW) for the predetermined time period T_P (Fig. 8) in order to achieve a received signal RxD2, which is shown in Fig. 15. The predetermined time period T_P (Fig. 8) is to be set to a value greater than 15 ns. For example, the predetermined time period T_P (Fig. 8) is set to a fixed value, in particular 50 ns or any other value greater than 15 ns.

[0134] If the filter block 154 is inactive, the receiving module 122 outputs the received signal

[0135] RxD1 according to Fig. 14, in which the interference G1 is visible. However, if the filter block 154 is active, the receive module 122 outputs the receive signal RxD2 according to Fig. 15. The interference G1 is not visible in the receive signal RxD2 according to Fig. 15. To this end, the filter block 154 proceeds as follows.

[0136] The reception threshold evaluation unit 1541 detects in the comparator output signal CA2 whether the second reception comparator 152 has detected a fall below the second reception threshold T2 or not. If the reception threshold evaluation unit 1541 detects that the second reception comparator 152 has detected a fall below the second reception threshold, the reception threshold evaluation unit 1541 changes the value for the signal CA2_E to the value Hl = high (HIGH). Furthermore, the reception threshold evaluation unit 1541 and / or the signal processing unit 1543 stores the previous value LW = low (LOW) as the value for the comparator output signal CA2.

[0137] Fig. 12 shows the signal CA2_E, which results from the comparator output signal CA2 of Fig. 11 resulting from VDIFF in the example of the differential voltage VDIFF of Fig. 9.

[0138] Thus, the CA2_E signal, with its change from a value of LW = low (LOW) to a value of Hl = high (HIGH), indicates that and when the second receive comparator 152 has detected a fall below the second receive threshold T2. The CA2_E signal indicates the event of the second receive comparator 152 detecting a fall below the second receive threshold T2. The CA2_E signal can also be called oob_event or event_at_second_comparator.

[0139] The time acquisition unit 1542 of Fig. 8 is designed to acquire how long the digital receive signal RxD at the output of the driver 1221 is at the value High = Hl (High). In particular, the time acquisition unit 1542 is or has at least one counter which outputs the signal cnt_rxd_h of Fig. 13. Fig. 13 indicates, over time t, the progression of a counter reading of a counter of the time acquisition unit 1542 of Fig. 8, which results from the differential voltage VDIFF of Fig. 9. In other words, in the signal cnt_rxd_h, the count for the receive signal RxD up to a maximum value |T_rxd_h_m| indicates for how many bits or for how long, i.e., for what period of time, the digital receive signal RxD at the output of the driver 1221 of Fig. 8 has the value High = Hl (High). The maximum value T_rxd_h_m corresponds to a predetermined number of bits or a predetermined number of magazines or a predetermined time period T_H.Thus, it can also be said that in the signal cnt_rxd_h, the time period T_H for the received signal RxD is counted, i.e., how long the digital received signal RxD at the output of the driver 1221 has the value High = Hl (High).

[0140] The time acquisition unit 1542 outputs the signal cnt_rxd_h to the signal processing unit 1543.

[0141] If the signal processing unit 1543 detects by evaluating the signals CA2_E and cnt_rxd_h that the second comparator 152 detects that the second reception threshold T2 = -0.35V has been undershot during the detection with the time detection unit 1542, the signal processing unit 1543 drives the output RXD of the transceiver 12 of Fig. 8 to the value LW = low (LOW) for the predetermined time period T_P, so that the signal RxD2 of Fig. 15 results.

[0142] At the times t_R shown in Fig. 15, the output RXD of the receiving module 122 of Fig. 8 is driven to the value LW = low (LOW), since the signal CA1 of Fig. 10 indicates that the receiving threshold T1 has been exceeded by the first comparator 151. Therefore, at the times t_R of Fig. 15, the time acquisition unit 1542 is reset, and the stored event (Event) of the second comparator 152 (00 B comparator) is discarded.

[0143] The predetermined time period T_H of Fig. 13 can be determined in a CAN bus system 1, for example, based on a time period TJdle, which is not shown in the figures. According to the CAN standard, the time period TJdle is the time period during which an idle or standby state of the CAN bus 40 exists. The time period TJdle can lie at least partially in the end field EOF of a frame 450, 460 and / or at least partially in the interframe interval I FS between two frames 450, 460. During this time period TJdle, the aforementioned traffic-free CAN-XL bus exists.

[0144] During the time period TJdle, the communication control device 11 waits to receive a message 45, 46. In this state, no communication takes place on the bus 40. In other words, no signal is passed to the communication control device 11 of Fig. 1 at the RXD terminal of the transceiver device 12, or the value logical 1 or HI is present, since the recessive level on the bus 40 corresponds to a bit value = 1 or a logical 1 in the received signal RxD or RxD1 or RxD2.

[0145] To reliably prevent false idle detection on a CAN bus 40, the time period T_H of Fig. 13 is selected as T_H < 11 * T_bt1 for the receiving module 122, in particular the filter block 154, of Fig. 8. The value 11 * T_bt1 corresponds to the time period T_dle. The time period T_dle has 11 bits of the arbitration phase 451, each of which has the bit time T_bt1 shown in Fig. 4 and Fig. 5.

[0146] Secondly, for the receiving module 122, in particular the filter block 154, of Fig. 8, the predetermined time period T_H of Fig. 13 is selected as T_H > 5 * T_bt1. This takes into account that according to the CAN standard, according to the "stuff bit rule" mentioned above with reference to Fig. 2, a dominant bit is inserted after at most 5 recessive bits. The predetermined time period T_H can also be stored in at least one of the units 1541, 1542, 1543.

[0147] For example, for the receiving module 122, in particular the filter block 154, of Fig. 8, the time period T_H is set between 5 * T_bt1 and 11 * T_bt1, in particular as T_H = 8 * T_bt1.

[0148] With such a selection or configuration of T_H, detection of interference G1 in the received signal RxD is reliably prevented, since erroneous detections of the second comparator 152 (OOB comparator) in the form of interference G1 are not passed on to the output RXD of Fig. 8 for the communication control device 11.

[0149] In this way, the filter block 154 ensures that the output of the second comparator 152 (OOB comparator) is not passed directly to the output RXD of the transceiver 12 of Fig. 8, but is delayed and passed only when necessary to reliably prevent false idle detection, as previously described.

[0150] If it is not certain to which bit time T_bt1 the transmitting / receiving devices 12, 22 on the bus 40 are set, the transmitting / receiving device 12, for example the receiving module 122, in particular the filter block 154, can proceed as follows.

[0151] In the CAN standard, the bit time T_bt1 can be between 10 ps and 1 ps, which corresponds to an arbitration bit rate of 100 kbit / s to 1 Mbit / s. The transceiver 12 can therefore be configured such that, after a restart, in particular a reset of the transceiver 12, the bit time T_bt1 is initialized to the bit time for the fastest possible data rate of the arbitration phase 451, i.e., to T_bt1 = 1 ps. This reliably prevents false IDLE detection of the traffic-free bus 40 even after the restart.

[0152] After successfully receiving at least one bit of the arbitration phase 451 of a frame 450 or 460 after the restart, in particular a reset, the transmitting / receiving device 12, for example the receiving module 122, in particular the filter block 154, measures the bit time T_bt1 based on the length of the bit of the arbitration phase 451 at the TXD input. Subsequently, the transmitting / receiving device 12, for example the receiving module 122, in particular the filter block 154, adjusts the bit time T_bt1 set for the transmitting / receiving device 12 to the bit time measured for the individual bit of the arbitration phase 451. The transmitting / receiving device 12 is then set to the adjusted bit time T_bt1. In particular, the single bit is the ACK bit or the SOF bit or another single bit of the arbitration phase 451 of a frame 450 or 460.The ACK bit is well suited for measuring the bit time T_bt1 because bit times T_bt1, T_bt2 on bus 40 could potentially be distorted and the ACK bit is guaranteed to be a single dominant bit.

[0153] As a result, even if the arbitration bit rate and associated bit time T_t1 on the bus 40 are initially unknown, a transmitting / receiving device 12 newly connected to the bus 40 can reliably prevent false detection of the traffic-free bus 40 (false IDLE detection) in any case.

[0154] Fig. 16 shows a transmitting / receiving device 120 according to a second embodiment. The transmitting / receiving device 120 can be used instead of a transmitting / receiving device 12 in the bus system 1 of Fig. 1.

[0155] The transmitting / receiving device 120 has a transmitting module 121 and a receiving module 122A, which includes a receiving circuit 15A. The receiving module 122A is constructed in many parts in the same way as the receiving module 122 according to the first embodiment. Therefore, only the differences from the first embodiment are described below.

[0156] In contrast to the first embodiment, the receiving module 122A, in particular its receiving circuit 15A and / or its filter block 154A, is designed to additionally or alternatively carry out the following test.

[0157] The filter block 154A has a signal processing unit 1543A which stores a time period T_C that is less than the time period 11 * T_bt2. The unit 1543A checks whether, within the time period T_C, neither the first reception threshold T1 is exceeded nor the second reception threshold T2 is undershot. The time period T_C can also be called t_check_stuff_fast. If the check by the signal processing unit 1543A shows that, within the time period T_C < 11 * T_bt2, neither the first reception threshold T1 is exceeded nor the second reception threshold T2 is undershot, the signal processing unit 1543A does not forward the signal CA2 to the logic circuit 1222.

[0158] In this way, CAN XL can also reliably detect that there is actually no communication on bus 40 or that bus 40 is not falsely assumed to be free, i.e., that the idle state exists. The reason for this is that according to the CAN-XL protocol, the bit time T_bt2 (Fig. 4) of the data phase 452 is less than or equal to half the bit time T_bt1 (Fig. 4) of the arbitration phase 451. This means that T_bt2 <= 1 Z> * T_bt1 . If neither the first reception threshold T1 is exceeded nor the second reception threshold T2 is undershot within the time period T_C < 11 * T_bt2, it can be safely assumed that no communication is taking place on bus 40 (IDLE).

[0159] Fig. 17 shows a transmitting / receiving device 1200 according to a third embodiment. The transmitting / receiving device 1200 can be used instead of one of the transmitting / receiving devices 12, 120 in the bus system 1 of Fig. 1.

[0160] The transmitting / receiving device 1200 has a transmitting module 121 and a receiving module 122B, which includes a receiving circuit 15B. The receiving module 122B is constructed in many parts in the same way as the receiving module 122 according to the first embodiment. Therefore, only the differences from the first embodiment are described below.

[0161] In contrast to the first embodiment, the receiving module 122B, in particular its receiving circuit 15B, also evaluates the transmit signal TxD. Therefore, the transmit signal TxD is also input to the input of the filter block 154B. The transmit signal TxD, which the transmit module 121 of Fig. 17 generates, encodes a CAN XL frame 460 shown in Fig. 3, as provided by each of the subscriber stations 10, 30, more precisely their communication control device 11 (Fig. 1), for the associated transmitting / receiving device 12, 120, 1200 for transmission on the bus 40.

[0162] Fig. 18 shows a portion of the differential voltage VDIFF signal on bus 40 plotted against time t, which develops on bus 40 for two consecutive frames 460_1, 460_2. Fig. 18 shows the differential voltage VDIFF on bus 40 at the end of the data phase 452 of the first frame 460_1, the following arbitration phase 451 with the end of the first frame 460_1 and the beginning of the second frame 460_2, and then the beginning of the subsequent data phase 452 of the second frame 460_2. In the arbitration phase 451, at least the interframe spacing IFS is present between the frames 460_1, 460_2.

[0163] To explain the operation of the receiving module 122B, the ACK bit of the first frame 460_1 in its frame end phase 467 is shown in more detail in Fig. 18 in the arbitration phase 451. In addition, the following start bit SOF and some of the following bits of the second frame 460_2 are shown in more detail for the arbitration phase 451.

[0164] As a result of the differential voltage VDIFF of Fig. 18, the receiving module 122B generates the signals of Fig. 19 to Fig. 26 over time t.

[0165] Fig. 19 shows the time profile of the signal cnt_rxd_h, which corresponds, for example, to a counter reading of a counter of the receiving module 122B of Fig. 17, which results from the differential voltage VDIFF of Fig. 18. The counter of the receiving module 122B is, in particular, part of the time recording unit 1542. The signal cnt_rxd_h is generated in the same way as previously described with reference to Fig. 13.

[0166] Fig. 20 shows the comparator output signal CA1 of the first comparator 151, which is generated in the same manner as previously described with reference to Fig. 10. Fig. 21 shows the comparator output signal CA2 of the second comparator 152, which is generated in the same manner as previously described with reference to Fig. 11.

[0167] Fig. 22 shows a signal S_F that indicates, over time t, whether the transmitting / receiving device 12, in particular the receiving module 122, is switched to the operating mode of the data phase 452 or not. In the example of Fig. 22, the signal S_F has a value Hl = high (HIGH) when the second comparator 152 is switched off or has no access to the logic circuit 1222 and thus the output RXD. Thus, in the example of Fig. 22, the signal S_F has a value LW = low (LOW) when the second comparator 152 is switched on or has access to the logic circuit 1222 and thus the output RXD.

[0168] Fig. 23 shows a signal S_T2 which indicates, over time t, whether the second comparator 152 is switched off or not. The signal S_T2 can be generated by the filter block 154B, in particular the reception threshold evaluation unit 154I. In the example of Fig. 23, the signal S_T2 has a value Hl = high (HIGH) when the second comparator 152 is switched off or has no access to the logic circuit 1222 and thus the output RXD. Thus, in the example of Fig. 23, the signal S_T2 has a value LW = low (LOW) when the second comparator 152 is switched on or has access to the logic circuit 1222 and thus the output RXD.

[0169] Fig. 24 shows the temporal progression of the signal CA2_E, which is as follows. If the reception threshold evaluation unit 1541 detects that the second reception comparator 152 has detected that the second reception threshold T2 has been undershot, the reception threshold evaluation unit 1541 changes the value for the signal CA2_E to the value Hl = high (HIGH). This is the case, for example, at the transition from the data phase 452 to the arbitration phase 451, as can be seen in the synopsis of Fig. 18 and Fig. 24. Furthermore, in this case, the reception threshold evaluation unit 1541 and / or the signal processing unit 1543 stores the previous value LW = low (LOW) as the value for the comparator output signal CA2. The receive threshold evaluation unit 1541 changes the value for the CA2_E signal to LW = low (LOW) when the first receive threshold T1 is exceeded again, as occurs with the ACK bit. This can be seen in conjunction with Fig. 18.

[0170] Fig. 25 shows the time course of the receive signal RxD1, which the receive module 122B generates from the time course of the differential voltage VDIFF of Fig. 18 when the filter module 154B is switched off. And Fig. 26 shows the time course of the receive signal RxD2, which the receive module 122B generates from the time course of the differential voltage VDIFF of Fig. 18 when the filter module 154B is switched on.

[0171] Thus, when the filter block 154B is deactivated, the received frames 460_1, 460_2 are forwarded to the communication control device 11 via the RXD output by means of the received signal RxD1 of Fig. 25. However, when the filter block 154B is activated, the received frames 460_1, 460_2 are forwarded to the communication control device 11 via the RXD output by means of the received signal RxD2 of Fig. 26.

[0172] If the first frame 460_1 has been understood by the communication control device 11, the communication control device 11 will send the ACK bit (“Acknowledge” bit) to the listening transceiver 1200 at the TXD terminal. If, after a time period T_ACK or evaluation, the transmitting / receiving device 1200, in particular the receiving module 122B and / or the receiving circuit 15B and / or the filter block 154 and / or the receiving threshold evaluation unit 1541, sees a dominant bit at the terminal TXD or in the transmit signal TxD at the time t_A, which appears as state 401 in the difference signal VDIFF of Fig. 18, the receiving module 122B and / or the receiving circuit 15B and / or the filter block 154 and / or the receiving threshold evaluation unit 1541 sets the signal S_T2 such that the second comparator 152 is switched off or has no access to the logic circuit 1222 and thus the output RXD. In the example of Fig.23, the signal S_T2 is at the value HI = HIGH from the beginning of the ACK bit (Fig. 18). Furthermore, the receiving module 122B and / or the receiving circuit 15B and / or the filter block 154 and / or the reception threshold evaluation unit 1541 sets the signal S_T2 such that the signal S_T2 changes to the value LW = LOW from the beginning of the SOF bit (Fig. 18) of the second frame 460_2. Thus, the second comparator 152 is switched on again from the beginning of the SOF bit (Fig. 18) of the second frame 460_2, or has a pass-through to the logic circuit 1222 and thus the RXD output.

[0173] The transmitting / receiving device 1200 and / or the receiving module 122B and / or the receiving circuit 15B and / or the filter block 154 and / or the receiving threshold evaluation unit 1541 therefore assume that the bus 40 is free again after the ACK bit (Fig. 18), since the first frame 460_1 has ended and the next data phase 452 (FAST phase) will be preceded by an arbitration phase 451, as shown in Fig. 18.

[0174] Thus, the transmitting / receiving device 1200 and / or the receiving module 122B is configured to ignore (oob_disable) the output of the second comparator 152 (OOB comparator) until the next dominant bit, which is usually the SOF bit (“Start-of-Frame” bit) of the next frame 460_2, since it cannot be FAST communication and thus there is no risk of erroneous detection of the idle state (false IDLE detection).

[0175] This solves the problem that theoretically undefined long recessive times can occur between CAN frames 450, 460, 460_1, 460_2, whereby potential false detections of the second comparator 152 (OOB comparator) are passed on to the RXD output after t_rxd_high_max, since no dominant states 401 occur to reset the timer of the time acquisition unit 1542.

[0176] The described procedure of the transmitting / receiving device 1200 and / or the receiving module 122B also has the advantage that the transmitting / receiving device 1200 and / or the receiving module 122B, when switched from the FAST-RX operating mode to the SIC operating mode by the signaling at its TXD input, does not have to recognize whether this happened because the communication control device 11 has detected an error and thus the frame 460 on the bus 40 potentially continues to run and thus there is a risk of erroneous detection of the idle state (false IDLE detection), or the frame 460 is over and has been fully understood. In this way, the transmitting / receiving device 1200 and / or the receiving module 122B are / is designed to prevent erroneous detections of the second comparator 152 (OOB comparator) from disrupting the communication on the bus 40, provided that the disruption G1 was preceded by successful communication.

[0177] All previously described configurations of the transmitting module 121, the receiving module 122, 122A, 122B, the transmitting / receiving devices 12, 22, 120, 1200, the subscriber stations 10, 20, 30, the bus system 1, and the method implemented therein according to the first to third exemplary embodiments, and their modifications, can be used individually or in all possible combinations. In addition, the following modifications are particularly conceivable.

[0178] The previously described bus system 1 according to the first to third exemplary embodiments is described with reference to a bus system based on the CAN protocol. However, the bus system 1 according to the first and / or second and / or third exemplary embodiments can alternatively be a different type of communications network in which the signals are transmitted as differential signals. It is advantageous, but not a mandatory requirement, that in the bus system 1, exclusive, collision-free access of a subscriber station 10, 20, 30 to the bus 40 is guaranteed, at least for certain time periods.

[0179] The bus system 1 according to the first and / or second and / or third embodiments and their modifications is, in particular, a CAN bus system, a CAN-HS bus system, a CAN FD bus system, a CAN SIC bus system, or a CAN XL bus system. However, the bus system 1 can be another communication network in which the signals are transmitted as differential signals and serially via the bus 40.

[0180] Thus, the functionality of the previously described embodiments can be used, for example, in transmitting / receiving devices 12, 22, 120, 1200 that can be operated in a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system.

[0181] The number and arrangement of the subscriber stations 10, 20, 30 in the bus system 1 according to the first to third embodiments and their

[0182] Modifications are possible. In particular, only subscriber stations 10 or only subscriber stations 30 are present in the bus systems 1 of the first, second, or third embodiment. In each of the embodiments, the receiving circuit 15 can have more than two comparators 151, 152. In particular, the receiving circuit 15 has at least one comparator for checking one of the reception thresholds T1, T2, T3.

Claims

Claims 1) Transmitting / receiving device (12; 120; 1200) for a subscriber station (10; 30) of a serial bus system (1), comprising a first comparator (151) for evaluating differential signals (CAN_H, CAN_L; VDIFF) received from a bus (40) of the bus system (1) with a first reception threshold (T1) for generating a first digital comparator output signal (CA1), a second comparator (152) for evaluating the differential signals (CAN_H, CAN_L; VDIFF) received from the bus (40) with a second reception threshold (T2), which is different from the first reception threshold (T1), for generating a second digital comparator output signal (CA2), a logic circuit (1222) for combining the first and second digital comparator output signals (CA1, CA2) to output a reception signal (RxD; RxD1; RxD2) to a communication control device (11) of the subscriber station (10; 30), and a filter block (154; 154A;154B) for evaluating the received signal (RxD) and the second comparator output signal (CA2) to decide whether or not the second digital comparator output signal (CA2) should be output to the logic circuit (1222) with a delay, and for outputting the second digital comparator output signal (CA2) to the logic circuit (1222) on the basis of the evaluation of the filter block (154; 154A; 154B). 2) Transmitting / receiving device (120) according to claim 1, wherein the filter block (154; 154A; 154B) is designed, on the basis of its evaluation, to compare the second digital comparator output signal (CA2) with a temporarily changed value to the logic circuit (1222). 3) Transmitting / receiving device (120) according to claim 1 or 2, wherein the filter block (154; 154A; 154B) is designed not to output the second digital comparator output signal (CA2) to the logic circuit (1222) in part on the basis of its evaluation. 4) Transmitting / receiving device (120) according to one of the preceding claims, wherein the filter block (154; 154A; 154B) is designed to evaluate whether the second comparator (152) has detected an undershoot of the second reception threshold (T2) in a first predetermined time period (T_H) in which the reception signal (RxD) has a predetermined value (H1). wherein the filter block (154; 154A; 154B) is designed to output the second digital comparator output signal (CA2) to the logic circuit (1222) if no undershoot of the second reception threshold (T2) was detected in the first predetermined time period (T_H), and wherein the filter block (154; 154A; 154B) is designed to drive a predetermined value (LW) for the second digital comparator output signal (CA2) to the logic circuit (1222) for a predetermined time period (T_P) if an undershoot of the second reception threshold (T2) was detected in the first predetermined time period (T_H). 5) Transmitting / receiving device (1200) according to one of the preceding claims, wherein the filter block (154; 154A; 154B) is designed not to output the second digital comparator output signal (CA2) to the logic circuit (1222) if, in a second predetermined time period (T_C), the values of the received signal (RxD) indicate that the first received threshold (T1) was exceeded at least once, and the values of the second digital comparator output signal (CA2) indicate that the second received threshold (T2) was undershot at least once. 6) Transmitting / receiving device (12; 120; 1200) according to claim 5, wherein the filter block (154) is designed as a time recording unit (1542) for recording the first and / or the second predetermined time period (T_H; T_C), and wherein the time recording unit (1542) is designed as a counter. 7) Transmitting / receiving device (1200) according to one of the preceding claims, wherein the filter block (154; 154A; 154B) is designed, in an operating mode in which the transmitting / receiving device (1200) is only a receiver of the signals (CANH; CANL; VDIFF) from the bus (40), to evaluate whether a transmission signal (TxD) which the communication control device (11) sends to the transmitting / receiving device (12; 120; 1200) contains a predetermined bit (ACK) which indicates the error-free reception of a frame (450; 460) on the basis of which the transmission signal (TxD) was generated, and wherein the filter block (154; 154A; 154B) is designed to filter the second digital comparator output signal (CA2) after the predetermined bit (ACK) not to be output to the logic circuit (1222) until the filter block (154B) detects a start bit (SOF) for the next frame (450; 460) in the received signal (RxD; RxD2). 8) Transceiver device (12; 120; 1200) according to one of the preceding claims, wherein the received signal (RxD; RxD2) in a first communication phase (451) on the bus (40) has bits with a first bit time (T_bt1) and in a second communication phase (452) has bits with a second bit time (T_bt2) which is shorter than the first bit time (T_bt1). 9) Transceiver (12; 120; 1200) according to claim 8, wherein the first predetermined time period (T_H) is greater than 5 bits with the first bit time (T_bt1) and less than 11 bits with the first bit time (T_bt1). 10) Transmitting / receiving device (120) according to claim 8 or 9, wherein the transmitting / receiving device (12; 120; 1200) is designed to reset the first bit time (T_bt1) in the transmitting / receiving device (12; 120; 1200) after a restart of the transmitting / receiving device (12; 120; 1200) to a bit time for the fastest possible data rate that may be set in the first communication phase (451), and wherein the transmitting / receiving device (12; 120; 1200) is designed to subsequently adapt the first bit time (T_bt1) to the bit time of a predetermined bit (ACK) that was received after successful reception of a frame (450; 460) at an input (TXD) of the transmitting / receiving device (12; 120; 1200) for the transmission signal (TxD). 11) Transceiver (120) according to claim 8 or 9, wherein the second predetermined time period (T_C) is less than 11 bits with the second bit time (T_bt2). 12) Transmitting / receiving device (12; 120; 1200) according to one of the claims 8 to 10, wherein the transmitting / receiving device (12; 120; 1200) is designed to receive differential signals (CAN_H, CAN_L; VDIFF) for communication in a bus system (1), in which in the first communication phase (451) it is negotiated between the subscriber stations (10; 20; 30) on the bus (40) which of the subscriber stations (10; 20; 30) has exclusive, collision-free access to the bus (40) of the bus system (1) in the subsequent second communication phase (452). 13) Transmitting / receiving device (12; 120; 1200) according to one of the claims 9 to 12, wherein the transmitting / receiving device (12; 120; 1200) is designed to generate the differential signals (CAN_H, CAN_L; VDIFF) for the bus (40) in the first communication phase (451) with a first physical layer (451_P) and in the second communication phase (452) with a second physical layer (452_P) which is different from the first physical layer (451 _P). 14) Transmitting / receiving device (12; 120; 1200) according to one of the preceding claims, further comprising a receiving stage (153) which is connected upstream of the first comparator (151) and is designed to set either the first receiving threshold (T1) or a third receiving threshold (T3) for the first comparator (151), which is different from the first and second receiving thresholds (T1; T2), so that the first comparator (151) evaluates the differential signals (CAN_H, CAN_L; VDIFF) either with the first receiving threshold (T1) or the third receiving threshold (T3) to generate the first digital comparator output signal (CA1), and / or wherein the receiving stage (153) is a resistive voltage divider, and / or wherein the first comparator (151) is connected between the first receiving threshold (T1) and a third reception threshold (T3) is designed to be switchable in order to receive the differential signals (CAN_H, CAN_L;VDIFF) to generate the first digital comparator output signal (CA1) either with the first reception threshold (T1) or with the third reception threshold (T3); 15) Subscriber station (10; 30) for a serial bus system (1), with a transmitting / receiving device (12; 120; 1200) according to one of the preceding claims, and a communication control device (11) for controlling the communication in the bus system (1) and for generating a digital transmit signal (TxD) for the transmitting / receiving device (12; 120; 1200), and wherein the transmitting / receiving device (12; 120; 1200) further comprises a driver (1222) for driving the digital receive signal (RxD) to the communication control device (11), and / or a transmission module (121; 1210) for transmitting signals to a bus (40) of the bus system (1). 16) Method for receiving differential signals (CAN_H, CAN_L; VDIFF) in a serial bus system (1), the method comprising the steps of Evaluating, with a first comparator (151), differential signals (CAN_H, CAN_L; VDIFF) received from a bus (40) of the bus system (1) with a first reception threshold (T1) and generating a first digital comparator output signal (CA1), Evaluating, with a second comparator (152), the differential signals (CAN_H, CAN_L; VDIFF) received from the bus (40) with a second reception threshold (T2) which differs from the first reception threshold (T1), and generating a second digital comparator output signal (CA2), Combining, with a logic circuit (1222), the first and second digital comparator output signals (CA1, CA2) to output a received signal (RxD; RxD1; RxD2) to a communication control device (11) of the subscriber station (10; 30), Evaluating, with a filter block (154; 154A; 154B), the received signal (RxD; RxD1; RxD2) and the second comparator output signal (CA2) to decide whether the second digital comparator output signal (CA2) should be output to the logic circuit (1222) with a delay or not, and Outputting the second digital comparator output signal (CA2) to the logic circuit (1222) based on the evaluation of the filter block (154; 154A; 154B).

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