Stacked die structure

Inorganic dielectric materials and metal damascene processes enhance thermal and mechanical performance, and connection density in IC packages by forming metallization structures with fine pitch connections, overcoming limitations of conventional IC packaging technologies.

WO2025170780A1 Publication Date: 2025-08-14QUALCOMM INC
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Patent Information

Application Number
PCT/US2025/013209
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-02-10
Filing Date
2025-01-27
Publication Date
2025-08-14

AI Technical Summary

Technical Problem

Conventional IC packaging technologies face limitations in thermal performance and warpage due to polymer/Cu redistribution layer (RDL) based fan-out packages, and connection bottlenecks due to pitch and routing limitations in organic interposer technology, particularly in high-density connections like AP to DDR6.

Method used

The use of inorganic dielectric materials, such as silicon, and a metal damascene process to build metallization structures with fine pitch connections, including through-substrate vias (TSVs) for improved thermal and mechanical performance, and the formation of metallization structures with inorganic dielectric layers for stacked die configurations.

Benefits of technology

The solution provides enhanced thermal conductivity, mechanical stability, and higher connection density in IC packages, addressing the limitations of conventional polymer/Cu RDL and organic interposer technologies.

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Abstract

In an aspect, an IC device may include a structure wafer and a first die bonded to the structure wafer by a bonding layer. A first metallization structure is disposed below and electrically coupled to the first die opposite the structure wafer. A fill material is disposed between the structure wafer and the first metallization structure. A second metallization structure is disposed on top of the structure wafer. The second metallization structure includes a second plurality of inorganic dielectric layers. A second die is disposed on top of the second metallization structure and electrically coupled to the second metallization structure by a plurality of die connectors. A plurality of throughsubstrate vias electrically couple the first metallization structure to the second metallization structure.
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