Data recording method and apparatus, and electronic device and nonvolatile readable storage medium

Abstract

The present application relates to the technical field of computers. Provided are a data recording method and apparatus, and an electronic device and a nonvolatile readable storage medium. The method comprises: separately configuring a basic input output system and a baseboard management controller as a shared memory under a shared central processing unit, wherein the shared memory is a preset region of a memory mounted on the central processing unit; agreeing on a shared-memory usage rule for the basic input output system and the baseboard management controller; and when a server is started, performing shared-channel inspection on the shared memory to determine whether the shared memory has been successfully initialized; and when the shared memory has been successfully initialized, on the basis of the shared-memory usage rule, transmitting, to the baseboard management controller by means of the shared memory, data collected by the basic input output system and related to an RAS function. The solution of the present application enables the recording of data related to an RAS function no longer to be affected by a server chip architecture and constrained by the architecture, and has the characteristics of high universality and high applicability.

Description

Data recording method, device, electronic device and non-volatile readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on March 13, 2024, with application number 202410282789.8, and application name “Data Recording Method, Device, Electronic Device and Medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular, to a data recording method, device, electronic device, and non-volatile readable storage medium. Background Art

[0004] The full name of RAS is Reliability, Availability and Serviceability. RAS function is an important part of the stable operation of the server system. Since the server system needs to run stably for a long time, the role of RAS as a whole is to ensure that the entire system runs reliably for as long as possible without going offline, and has a sufficiently powerful fault tolerance mechanism.

[0005] Currently, mainstream and traditional server products on the market are required to support RAS. The core management and identification of RAS functions are actively managed and recorded by the Basic Input Output System (BIOS), which then proactively identifies and reports errors. A common approach in the industry is to remotely view errors through the Baseboard Management Controller (BMC) management interface, rather than collecting BIOS registers or error logs. In this case, the BIOS must report actively identified RAS error information to the BMC through some means. Due to the different communication protocols supported by CPUs (Central Processing Units) of different architectures, the methods used vary. Some use the LPC bus (Low Pin Count Bus) and KCS interface (Keyboard Controller Style Interface) to exchange RAS error information between the BIOS and BMC, while others use the IPMI (Intelligent Platform Management Interface) protocol, a two-wire serial bus (I2C), for RAS information reporting and transmission. Regardless of the method, corresponding physical links are required to enable upper-layer software applications. However, KCS transmission is limited by the number of system management interrupts (SMIs), which can only support a maximum of 255. However, SMIs are widely used, leading to insufficient SMIs for RAS functions or system performance degradation due to frequent SMI use. Therefore, improvements to existing RAS data recording methods are urgently needed. Summary of the Invention

[0006] The present application provides a data recording method, device, electronic device and non-volatile readable storage medium to address the defects of existing RAS-type data recording being affected by server architecture and reducing server performance.

[0007] According to a first aspect of the present application, the present application provides a data recording method, the method comprising:

[0008] Configuring the basic input / output system and the baseboard management controller as shared memory under the shared central processing unit, wherein the shared memory is a preset area of ​​memory mounted by the central processing unit;

[0009] Define shared memory usage rules for the BIOS and BMC;

[0010] When the server is started, a shared channel check is performed on the shared memory to determine whether the shared memory is initialized successfully;

[0011] When the shared memory is initialized successfully, the data related to the RAS function collected by the basic input and output system is transmitted to the baseboard management controller through the shared memory based on the shared memory usage rule.

[0012] In some embodiments, configuring the basic input / output system and the baseboard management controller as shared memories under a shared central processing unit includes:

[0013] Mount at least one memory stick to the CPU on the motherboard via the I2C bus;

[0014] Connecting the basic input and output system and the baseboard management controller to the central processing unit through a preset bus respectively;

[0015] The storage space of the central processing unit is divided into at least one memory bank for common use by the basic input and output system and the baseboard management controller.

[0016] In some embodiments, the preset bus is an ESPI bus or an LPC bus.

[0017] In some embodiments, agreeing on a shared memory usage rule between a basic input / output system and a baseboard management controller includes:

[0018] It is agreed that after the basic input and output system collects the RAS function related data, it will encapsulate the RAS function related data and the baseboard management controller interrupt related data into a preset structure data packet according to the preset data combination rule and write it into the shared memory;

[0019] It is agreed that the baseboard management controller parses the preset structure data packet according to the preset data parsing rules when reading the shared memory to obtain RAS function related data and displays it through the management interface.

[0020] In some embodiments, when the server is started, a shared channel check is performed on the shared memory to determine whether the shared memory is successfully initialized, including:

[0021] Instructing the basic input and output system to read the first preset address during the startup phase to obtain a startup signal, a reset signal, and an initialization state of the baseboard management controller;

[0022] If the start signal, reset signal and BMC initialization state of the baseboard management controller are all equal to their corresponding preset values, it is determined that the shared memory initialization is successful;

[0023] If any one of the start signal, the reset signal, and the BMC initialization state of the baseboard management controller is not equal to a corresponding preset value, it is determined that the shared memory initialization fails.

[0024] In some embodiments, when the server is started, a shared channel check is performed on the shared memory to determine whether the shared memory is successfully initialized, including:

[0025] Instructing the baseboard management controller to read the second preset address during the startup phase to obtain a startup signal, a reset signal, and an initialization state of the basic input and output system;

[0026] If the startup signal, reset signal and initialization state of the basic input and output system are all equal to their corresponding preset values, it is determined that the shared memory initialization is successful;

[0027] If any one of the start signal, the reset signal and the initialization state of the basic input / output system is not equal to the corresponding preset value, it is determined that the shared memory initialization fails.

[0028] In some embodiments, the shared channel is a data communication channel from the basic input / output system and the baseboard management controller to the shared memory, respectively.

[0029] In some embodiments, when the server is started, a shared channel check is performed on the shared memory to determine whether the shared memory is successfully initialized, including:

[0030] Check whether the shared channel exists;

[0031] When a shared channel is detected, it is determined that the shared memory initialization is successful;

[0032] If no shared channel is detected, it is determined that the shared memory initialization has failed.

[0033] In some embodiments, checking whether a shared channel exists includes:

[0034] Check whether the data communication channel from the basic input and output system to the shared memory exists, and check whether the data communication channel from the baseboard management controller to the shared memory exists;

[0035] When it is detected that both the data communication channel from the basic input / output system to the shared memory and the data communication channel from the baseboard management controller to the shared memory exist, it is determined that the shared channel exists.

[0036] In some embodiments, transmitting RAS function-related data collected by the basic input / output system to the baseboard management controller through the shared memory based on the shared memory usage rule includes:

[0037] Instructing the basic input and output system to obtain a data packet containing data related to the baseboard management controller interrupt from a cache in the shared memory, and determining whether the data packet is empty;

[0038] In response to the data packet being not empty, the baseboard management controller is instructed to obtain, through the shared memory, a preset structure data packet transmitted by the basic input and output system according to the agreement, and parse the preset structure data packet according to the agreement to obtain RAS function-related data and then display it through the management interface;

[0039] In response to the data packet being empty, the basic input and output system is made to wait for an interrupt-related data packet.

[0040] In some embodiments, the shared memory cache includes: a first cache and a second cache, the first cache is configured to cache data sent by the baseboard management controller, and the second cache is configured to cache data received by the baseboard management controller.

[0041] In some embodiments, the method further comprises:

[0042] The waiting time of the basic input and output system for the data packets related to the interrupt is counted to obtain the waiting time;

[0043] When the waiting time exceeds the preset time, the server is caused to skip the process of exchanging RAS function related data between the basic input and output system and the baseboard management controller and continue to execute the startup process.

[0044] In some embodiments, the method further comprises:

[0045] In the case where the shared memory initialization fails, the server is caused to skip the process of exchanging RAS function-related data between the basic input and output system and the baseboard management controller and continue to execute the startup process.

[0046] In some embodiments, the RAS function-related data includes RAS type error information and location information.

[0047] In some embodiments, the preset structure data packet includes at least the following information: definition flag, definition version, number of interactions, next data address, data address of the first cache, data address of the second cache, data length of the first cache, data length of the second cache, cache type, cache type target, basic input and output system read data, basic input and output system write data, message protocol type, basic input and output system interrupt type, global system input data, baseboard management controller interrupt type, baseboard management controller interrupt address, baseboard management controller interrupt value, and data check value.

[0048] In some embodiments, the shared memory usage rule indicates how the basic input / output system and the baseboard management controller exchange data via data packets in a preset format.

[0049] In some embodiments, the preset area is a storage area consisting of a continuous segment of addresses, or the preset area is a storage area consisting of multiple segments of spaced addresses.

[0050] According to a second aspect of the present application, the present application further provides a data recording device, the device comprising:

[0051] A configuration module is configured to configure the basic input and output system and the baseboard management controller to respectively share a shared memory under the central processing unit, wherein the shared memory is a preset area of ​​memory mounted by the central processing unit;

[0052] The agreement module is configured to agree on a shared memory usage rule between the basic input and output system and the baseboard management controller;

[0053] The checking module is configured to perform a shared channel check on the shared memory when the server is started to determine whether the shared memory is successfully initialized;

[0054] The transfer module is configured to transfer the RAS function-related data collected by the basic input and output system to the baseboard management controller through the shared memory based on the shared memory usage rules when the shared memory is successfully initialized.

[0055] According to the third aspect of the present application, the present application also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any of the above-mentioned data recording methods is implemented.

[0056] According to a fourth aspect of the present application, the present application further provides a non-volatile readable storage medium on which a computer program is stored. When the computer program is executed by a processor, any of the above-mentioned data recording methods is implemented.

[0057] The present application provides a data recording method that first configures a basic input / output system and a baseboard management controller to share the memory mounted under a central processing unit, then agrees on shared memory usage rules for the two to use the shared memory, and when the server starts, checks whether the shared memory is successfully initialized through a shared channel. Finally, when the shared memory is successfully initialized, the RAS function-related data collected by the basic input / output system is transmitted to the baseboard management controller with the help of the agreed shared memory usage rules. This not only enriches the recording method of RAS data, but also makes the recording of RAS function-related data no longer affected by the server chip architecture and architectural restrictions, and has the characteristics of strong versatility and high applicability.

[0058] In addition, a data recording device, an electronic device and a non-volatile readable storage medium provided in this application can also achieve the above technical effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in this application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0060] FIG1 is a flow chart of a data recording method provided by the present application;

[0061] FIG2 is a schematic diagram of the overall physical topology of the server motherboard provided in this application;

[0062] FIG3 is a second flow chart of the data recording method provided by the present application;

[0063] FIG4 is a lane diagram corresponding to the data recording process of FIG3 provided by the present invention;

[0064] FIG5 is a schematic diagram of MMBI shared memory interaction data provided by this application;

[0065] FIG6 is a schematic diagram of the MMBI shared memory data interaction process provided by this application;

[0066] FIG7 is a schematic structural diagram of a data recording device provided by the present application;

[0067] FIG8 is a schematic structural diagram of the electronic device provided in this application. DETAILED DESCRIPTION

[0068] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0069] For ease of understanding, the following description is given of the professional terms used in the embodiments of this application:

[0070] BIOS: Basic Input Output System; stores the computer's most important basic input and output programs, system settings, self-test programs after powering on, and system startup programs;

[0071] BMC: Baseboard Management Controller, which is the core component of server out-of-band management;

[0072] I2C: Inter-Integrated Circuit, two-wire serial bus;

[0073] CPU: Central Processing Unit, referred to as CPU;

[0074] GPIO: General-purpose input / output, general-purpose input / output;

[0075] IPMI: Intelligent Platform Management Interface, intelligent platform management interface;

[0076] LPC: Low pin count, low-speed bus protocol, is based on the Intel standard 33MHz 4-bit parallel bus protocol;

[0077] KCS: Keyboard Controller Style (KCS) Interface, keyboard controller style interface, referred to as KCS interface;

[0078] MMBI: Memory-Mapped BMC Interface, a shared memory area for data packet exchange between BIOS and BMC;

[0079] H2B: Host to BMC, host to baseboard management controller, that is, data communication is sent from Host to BMC;

[0080] B2H: BMC to Host, baseboard management controller to host, that is, data communication is sent from BMC to Host;

[0081] RAS: Reliability, Availability, and Serviceability.

[0082] ESPI: Enhanced Serial Peripheral Interface. The ESPI bus is a high-performance, high-reliability bus standard used to connect various devices and sensors in computer systems. It uses a point-to-point communication model, supports high-speed data transmission and DMA data transmission, and has a complete communication protocol.

[0083] A data recording method, a data recording device, an electronic device, and a non-volatile readable storage medium of the present application are described below with reference to FIG. 1 to FIG. 8 .

[0084] FIG1 is a flow chart of a data recording method provided by the present application. Referring to FIG1 , this embodiment provides a data recording method, which can be implemented through steps S101 to S104. Each step will be described in detail below:

[0085] In step S101 , a basic input / output system and a baseboard management controller are respectively configured to share a shared memory under a central processing unit, wherein the shared memory is a preset area of ​​memory mounted on the central processing unit.

[0086] In this embodiment, memory is mounted to the CPU via any existing bus. To configure shared memory, the BIOS and baseboard management controller are first connected to the CPU on the motherboard, and then the CPU can access the memory, thereby achieving memory sharing. A preset area refers to a storage area of ​​a specified size in memory. This preset area can be a storage area consisting of a continuous address range or a storage area consisting of multiple intervals of addresses.

[0087] Step S102 : agreeing on a shared memory usage rule between the basic input / output system and the baseboard management controller.

[0088] In this embodiment, the shared memory usage rules are that the basic input / output system and the baseboard management controller exchange data through data packets in a specific format. According to the agreed memory usage rules, the basic input / output system and the baseboard management controller can transfer data to each other according to certain rules, and the baseboard management controller can also parse the transferred data according to certain rules.

[0089] Step S103: When the server is started, a shared channel check is performed on the shared memory to determine whether the shared memory is successfully initialized.

[0090] In this embodiment, the shared channel refers to the data communication channel from the basic input / output system and the baseboard management controller to the shared memory, respectively. The corresponding shared channel check includes checking the data channel from the basic input / output system to the shared memory, and checking the data communication channel from the baseboard management controller to the shared memory. Since the shared channel should exist after the shared memory is initialized after the shared memory is configured, the shared memory initialization status can be indicated based on the shared channel check result. If the shared channel is found to exist, the shared memory initialization is considered successful. If the shared channel is found to not exist, the shared memory initialization is considered unsuccessful.

[0091] Step S104: If the shared memory is successfully initialized, the RAS function-related data collected by the BIOS is transmitted to the baseboard management controller via the shared memory based on the shared memory usage rules. In some embodiments, the RAS function-related data includes RAS error information and location information.

[0092] For example, in the case where the shared memory is initialized successfully, the memory usage rules pre-agreed upon by the basic input / output system and the baseboard management controller are used to interact by setting the data packet and the parameter meanings corresponding to each offset address in the data packet through the baseboard management controller and the basic input / output system. The basic input / output system combines the relevant data of the RAS class according to the agreed rules and passes it to the baseboard management controller. The baseboard management controller parses the received data according to the agreed rules and displays it on the management interface of the baseboard management controller.

[0093] A data recording method of this embodiment first configures a basic input / output system and a baseboard management controller to share the memory mounted under the central processing unit, then agrees on shared memory usage rules for the two to use the shared memory, and when the server starts, checks whether the shared memory is successfully initialized through a shared channel. Finally, when the shared memory is successfully initialized, the agreed shared memory usage rules are used to transmit the RAS function-related data collected by the basic input / output system to the baseboard management controller. This not only enriches the recording method of RAS data, but also makes the recording of RAS function-related data no longer affected by the server chip architecture and architectural restrictions, and has the characteristics of strong versatility and high applicability.

[0094] In some embodiments, referring to FIG. 2 , the aforementioned step S104 of configuring the basic input / output system and the baseboard management controller as shared memory under the shared central processing unit includes the following steps:

[0095] Mount at least one memory stick to the CPU on the motherboard via the I2C bus;

[0096] Connecting the basic input and output system and the baseboard management controller to the central processing unit through a preset bus respectively;

[0097] The storage space of the central processing unit is divided into at least one memory bank for common use by the basic input and output system and the baseboard management controller.

[0098] In some embodiments, the preset bus is an ESPI bus or an LPC bus.

[0099] The data recording method of this embodiment is based on the physical link connection design of the motherboard server hardware. It adopts the basic input and output system and the baseboard management controller to share the memory channel through the ESPI bus or LPC bus. It is applicable to most server architectures. The constructed shared memory channel can enable the basic input and output system and the baseboard management controller to transmit their respective data, preparing for the subsequent data interaction between the two.

[0100] In some embodiments, the aforementioned step S102 of agreeing on a shared memory usage rule between the basic input / output system and the baseboard management controller includes:

[0101] It is agreed that after the basic input and output system collects the RAS function related data, it will encapsulate the RAS function related data and the baseboard management controller interrupt related data into a preset structure data packet according to the preset data combination rule and write it into the shared memory;

[0102] It is agreed that the baseboard management controller parses the preset structure data packet according to the preset data parsing rules when reading the shared memory to obtain RAS function related data and displays it through the management interface.

[0103] The data recording method of this embodiment is to respectively agree on the usage rules of the shared memory between the basic input and output system and the baseboard management controller. After the agreement, the basic input and output system and the baseboard management controller can cooperate with each other to complete the recording and transmission of data related to the RAS function with the help of preset structured data packets.

[0104] In some embodiments, referring to FIG. 3 , in step S103 , when the server is started, a shared channel check is performed on the shared memory to determine whether the shared memory is successfully initialized, including:

[0105] Instructing the basic input and output system to read the first preset address during the startup phase to obtain a startup signal, a reset signal, and an initialization state of the baseboard management controller;

[0106] If the start signal, reset signal and BMC initialization state of the baseboard management controller are all equal to their corresponding preset values, it is determined that the shared memory initialization is successful;

[0107] If any one of the start signal, the reset signal, and the BMC initialization state of the baseboard management controller is not equal to a corresponding preset value, it is determined that the shared memory initialization fails.

[0108] The data recording method of this embodiment uses the basic input and output system to check whether the baseboard management controller's startup signal, BMC initialization signal, and reset signal meet the conditions, thereby automatically determining whether the shared memory MMBI area is available. The entire process does not require manual assistance and has good stability and accuracy.

[0109] In some embodiments, referring again to FIG. 3 , in step S103 , when the server is started, a shared channel check is performed on the shared memory to determine whether the shared memory is successfully initialized, including:

[0110] Instructing the baseboard management controller to read the second preset address during the startup phase to obtain a startup signal, a reset signal, and an initialization state of the basic input and output system;

[0111] If the startup signal, reset signal and initialization state of the basic input and output system are all equal to their corresponding preset values, it is determined that the shared memory initialization is successful;

[0112] If any one of the start signal, the reset signal and the initialization state of the basic input / output system is not equal to the corresponding preset value, it is determined that the shared memory initialization fails.

[0113] The data recording method of this embodiment uses the baseboard management controller to check whether the basic input and output system startup signal, BMC initialization signal, and reset signal meet the conditions, thereby automatically determining whether the shared memory MMBI area is available. The entire process does not require manual assistance and has good stability and accuracy.

[0114] In some embodiments, as shown in FIG. 4 , the aforementioned step S104 of transmitting the RAS function-related data collected by the basic input / output system to the baseboard management controller via the shared memory based on the shared memory usage rule includes:

[0115] Instructing the basic input and output system to obtain a data packet containing data related to the baseboard management controller interrupt from a cache in the shared memory, and determining whether the data packet is empty;

[0116] In response to the data packet being not empty, the baseboard management controller is instructed to obtain, through the shared memory, a preset structure data packet transmitted by the basic input and output system according to the agreement, and parse the preset structure data packet according to the agreement to obtain RAS function-related data and then display it through the management interface;

[0117] In response to the data packet being empty, the basic input and output system is made to wait for an interrupt-related data packet.

[0118] In some embodiments, please refer to Figures 5 and 6, the shared memory cache includes: a first cache and a second cache, the first cache is set to cache data sent by the baseboard management controller (i.e., B2H), and the second cache is set to cache data received by the baseboard management controller (i.e., H2B).

[0119] The data recording method of this embodiment collects and combines data related to the server RAS function according to the data format of the basic input and output system end and the baseboard management controller end, and performs data interaction through H2B and B2H methods, so that the interaction data between the baseboard management controller and the basic input and output system can be processed in an orderly manner through a specific cache, which helps to improve data recording efficiency.

[0120] In some embodiments, the method further comprises:

[0121] The waiting time of the basic input and output system for the data packets related to the interrupt is counted to obtain the waiting time;

[0122] When the waiting time exceeds the preset time, the server is caused to skip the process of exchanging RAS function related data between the basic input and output system and the baseboard management controller and continue to execute the startup process.

[0123] The data recording method of this embodiment sets a waiting time to prevent the basic input and output system from entering an infinite waiting state when data interaction between the basic input and output system and the baseboard management controller is abnormal, thereby avoiding affecting the startup of the server.

[0124] In some embodiments, the method further comprises:

[0125] In the case where the shared memory initialization fails, the server is caused to skip the process of exchanging RAS function-related data between the basic input and output system and the baseboard management controller and continue to execute the startup process.

[0126] The data recording method of this embodiment can improve the operation stability of the server by skipping the process of exchanging RAS function-related data between the basic input and output system and the baseboard management controller and continuing the startup process in the case of shared memory initialization failure.

[0127] In some embodiments, the preset structure data packet includes at least the following information: definition flag, definition version, interaction number, next data address, first cache data address, second cache data address, first cache data length, second cache data length, cache type, cache type target, BIOS read data, BIOS write data, message protocol type, BIOS interrupt type, global system input data, baseboard management controller interrupt type, baseboard management controller interrupt address, baseboard management controller interrupt value, and data checksum. For example, the data information included in the preset structure data packet can be referred to in Table 1.

[0128] Table 1 Shared memory MMBI parameter definition

[0129] In another embodiment, to facilitate understanding of the solution of the present application, please refer again to Figures 3 and 4. This embodiment provides another data recording method. The implementation principle of this method is: ignoring the influence and architectural limitations of the server chip architecture, using the EPSI bus supported by the BIOS and BMC through the physical hardware of the motherboard. When the server starts, the BIOS and BMC share a fixed memory area through the ESPI bus, and interact by setting the data packet and the parameter meaning corresponding to each offset address in the data packet through the BMC and BIOS ends. The BIOS combines the relevant data of the RAS class according to the agreed rules and passes it to the BMC. The BMC parses the received data according to the agreed rules and displays it on the BMC interface.

[0130] The interaction data packet between BIOS and BMC is a data packet structure defined by multiple parameters such as definition flag, definition version, interaction quantity, next data address, B2H data address, H2B data address, B2H data length, H2B data length, cache type, cache type target, BIOS read data, BIOS write data, message protocol type, BIOS interrupt type, global system input data, BMC interrupt type, BMC interrupt address, BMC interrupt value, and data check value.

[0131] The implementation process is as follows:

[0132] First, the server motherboard is connected to the BIOS chip through the ESPI bus and to the BMC chip through the ESPI bus;

[0133] Next, when the server starts, the BIOS obtains the start signal in the MMBI capability description address through the MMBI target address during the startup phase. The start signal is 1, the reset signal is 0, and BMC initialization is completed. When the above conditions are met, the MMBI area channel exists. If the BIOS obtains the start signal in the MMBI capability description address through the MMBI target address during the startup phase. The reset signal is 1, and the BMC initialization is completed, any one of which is not true, the MMBI area channel does not exist and an error state is returned.

[0134] Next, obtain the data packet in the cache register in the MMBI memory area channel and determine whether the data packet is empty;

[0135] Then, when the data packet is empty, set the request signal to 1 and wait for data to be obtained from the BMC. When the data is transferred from the BMC to the BIOS, set the request signal to 0.

[0136] Finally, when the acquired data packet is not empty, it means that there is data. The data packet is filled in according to the format agreed with the BMC. The data includes but is not limited to RAS error information and location information. After the data packet is written, the BIOS RAS information is transmitted to the BMC through the MMBI area. The BMC parses the data according to the agreed format and displays the relevant data on the BMC interface, so that users can view the RAS error information records in real time.

[0137] The data recording method of this embodiment combines the motherboard hardware design to physically link the BIOS and BMC firmware via the ESPI bus. Data is exchanged through a shared area mapped by the MMBI memory. The BIOS's RAS error information is combined according to the data format agreed upon by both the BIOS and the BMC. When the MMBI shared memory channel exists and meets the communication requirements, the RAS error information recorded by the BIOS is transmitted to the BMC for parsing and display on the BMC interface. Simultaneously, the MMBI shared memory channel can be used to transmit system data collected by the BMC back to the BIOS via the MMBI shared memory channel. The BIOS also parses the transmitted data in the agreed format and records it in the BIOS function. This solution allows the information required for exchange between the BIOS and BMC to be effectively transmitted and updated via the MMBI, ensuring information synchronization between the BIOS and BMC. Furthermore, this application can meet the actual business needs of customer data centers and only requires considering any architecture server that supports the ESPI bus. It has strong versatility and high applicability.

[0138] The data recording device provided by the present application is described below. The data recording device described below and the data recording method described above can be referenced to each other.

[0139] As shown in FIG. 7 , this embodiment provides a data recording device, which includes a configuration module 710 , a contract module 720 , a check module 730 , and a transfer module 740 . The following describes each of the modules in detail:

[0140] Configuration module 710, configuration module 710 is configured to configure the basic input and output system and the baseboard management controller to share the shared memory under the central processing unit, wherein the shared memory is a preset area of ​​memory mounted by the central processing unit;

[0141] The agreement module 720 is configured to agree on a shared memory usage rule between the basic input and output system and the baseboard management controller;

[0142] The checking module 730 is configured to perform a shared channel check on the shared memory to determine whether the shared memory is successfully initialized when the server is started;

[0143] The transmission module 740 is configured to transmit the RAS function-related data collected by the basic input and output system to the baseboard management controller through the shared memory based on the shared memory usage rules when the shared memory is successfully initialized.

[0144] The data recording device of this embodiment first configures the basic input and output system and the baseboard management controller to share the memory mounted under the central processing unit, then stipulates shared memory usage rules for the two to use the shared memory, and determines whether the shared memory is successfully initialized through a shared channel check when the server is started. Finally, when the shared memory is successfully initialized, the data related to the RAS function collected by the basic input and output system is transmitted to the baseboard management controller with the help of the stipulated shared memory usage rules. This not only enriches the recording method of RAS data, but also makes the recording of RAS function-related data no longer affected by the server chip architecture and architectural restrictions, and has the characteristics of strong versatility and high applicability.

[0145] In some embodiments, the configuration module 710 is further configured to:

[0146] Mount at least one memory stick to the CPU on the motherboard via the I2C bus;

[0147] Connecting the basic input and output system and the baseboard management controller to the central processing unit through a preset bus respectively;

[0148] The storage space of the central processing unit is divided into at least one memory bank for common use by the basic input and output system and the baseboard management controller.

[0149] In some embodiments, the preset bus is an ESPI bus or an LPC bus.

[0150] In some embodiments, the appointment module 720 is further configured to:

[0151] It is agreed that after the basic input and output system collects the RAS function related data, it will encapsulate the RAS function related data and the baseboard management controller interrupt related data into a preset structure data packet according to the preset data combination rule and write it into the shared memory;

[0152] It is agreed that the baseboard management controller parses the preset structure data packet according to the preset data parsing rules when reading the shared memory to obtain RAS function related data and displays it through the management interface.

[0153] In some embodiments, the inspection module 730 is further configured to:

[0154] Instructing the basic input and output system to read the first preset address during the startup phase to obtain a startup signal, a reset signal, and an initialization state of the baseboard management controller;

[0155] If the start signal, reset signal and BMC initialization state of the baseboard management controller are all equal to their corresponding preset values, it is determined that the shared memory initialization is successful;

[0156] If any one of the start signal, the reset signal, and the BMC initialization state of the baseboard management controller is not equal to a corresponding preset value, it is determined that the shared memory initialization fails.

[0157] In some embodiments, the inspection module 730 is further configured to:

[0158] Instructing the baseboard management controller to read the second preset address during the startup phase to obtain a startup signal, a reset signal, and an initialization state of the basic input and output system;

[0159] If the startup signal, reset signal and initialization state of the basic input and output system are all equal to their corresponding preset values, it is determined that the shared memory initialization is successful;

[0160] If any one of the start signal, the reset signal and the initialization state of the basic input / output system is not equal to the corresponding preset value, it is determined that the shared memory initialization fails.

[0161] In some embodiments, the delivery module 740 is further configured to:

[0162] Instructing the basic input and output system to obtain a data packet containing data related to the baseboard management controller interrupt from a cache in the shared memory, and determining whether the data packet is empty;

[0163] In response to the data packet being not empty, the baseboard management controller is instructed to obtain, through the shared memory, a preset structure data packet transmitted by the basic input and output system according to the agreement, and parse the preset structure data packet according to the agreement to obtain RAS function-related data and then display it through the management interface;

[0164] In response to the data packet being empty, the basic input and output system is made to wait for an interrupt-related data packet.

[0165] In some embodiments, the shared memory cache includes: a first cache and a second cache, the first cache is configured to cache data sent by the baseboard management controller, and the second cache is configured to cache data received by the baseboard management controller.

[0166] In some embodiments, the apparatus further includes a first startup recovery module, and the first startup recovery module is configured to:

[0167] The waiting time of the basic input and output system for the data packets related to the interrupt is counted to obtain the waiting time;

[0168] When the waiting time exceeds the preset time, the server is caused to skip the process of exchanging RAS function related data between the basic input and output system and the baseboard management controller and continue to execute the startup process.

[0169] In some embodiments, the apparatus further includes a first startup recovery module, and the second startup recovery module is configured to:

[0170] In the case where the shared memory initialization fails, the server is caused to skip the process of exchanging RAS function-related data between the basic input and output system and the baseboard management controller and continue to execute the startup process.

[0171] In some embodiments, the RAS function-related data includes RAS type error information and location information.

[0172] In some embodiments, the preset structure data packet includes at least the following information: definition flag, definition version, number of interactions, next data address, data address of the first cache, data address of the second cache, data length of the first cache, data length of the second cache, cache type, cache type target, basic input and output system read data, basic input and output system write data, message protocol type, basic input and output system interrupt type, global system input data, baseboard management controller interrupt type, baseboard management controller interrupt address, baseboard management controller interrupt value, and data check value.

[0173] It should be noted that each module in the above-mentioned data recording device can be implemented in whole or in part through software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor of the electronic device in hardware form, or can be stored in the memory of the electronic device in software form, so that the processor can call and execute the corresponding operations of each of the above modules.

[0174] FIG8 illustrates a schematic diagram of the physical structure of an electronic device. As shown in FIG8 , the electronic device may include: a processor 810, a communication interface 820, a memory 830, and a communication bus 840, wherein the processor 810, the communication interface 820, and the memory 830 communicate with each other via the communication bus 840. The processor 810 may call logic instructions in the memory 830 to execute a data recording method, which includes: configuring a basic input / output system and a baseboard management controller to share a shared memory under a central processing unit, wherein the shared memory is a preset area of ​​memory mounted by the central processing unit; agreeing on a shared memory usage rule for the basic input / output system and the baseboard management controller; when the server is started, performing a shared channel check on the shared memory to determine whether the shared memory is successfully initialized; if the shared memory is successfully initialized, transmitting the RAS function-related data collected by the basic input / output system to the baseboard management controller via the shared memory based on the shared memory usage rule.

[0175] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer non-volatile readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the relevant technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a non-volatile readable storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned non-volatile readable storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various non-volatile readable storage media that can store program code.

[0176] On the other hand, the present application also provides a computer program product, which includes a computer program, which can be stored on a non-volatile readable storage medium. When the computer program is executed by a processor, the computer can execute the data recording method provided by the above methods, which includes: configuring the basic input and output system and the baseboard management controller as shared memories under a shared central processing unit, respectively, wherein the shared memory is a preset area of ​​the memory mounted by the central processing unit; agreeing on shared memory usage rules for the basic input and output system and the baseboard management controller; when the server is started, performing a shared channel check on the shared memory to determine whether the shared memory is successfully initialized; if the shared memory is successfully initialized, the data related to the RAS function collected by the basic input and output system is passed to the baseboard management controller through the shared memory based on the shared memory usage rules.

[0177] On the other hand, the present application also provides a non-volatile readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data recording method provided by the above-mentioned methods, the method comprising: configuring a basic input / output system and a baseboard management controller as shared memories under a shared central processing unit, respectively, wherein the shared memory is a preset area of ​​memory mounted by the central processing unit; agreeing on shared memory usage rules for the basic input / output system and the baseboard management controller; when the server is started, performing a shared channel check on the shared memory to determine whether the shared memory is successfully initialized; if the shared memory is successfully initialized, passing the RAS function-related data collected by the basic input / output system to the baseboard management controller through the shared memory based on the shared memory usage rules.

[0178] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. That is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0179] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus the necessary general hardware platform, or of course, by hardware. Based on this understanding, the above technical solution, in essence, or the part that contributes to the relevant technology, can be embodied in the form of a software product. The computer software product can be stored in a non-volatile computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiment.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data recording method, characterized in that: The method comprises: Configuring the basic input / output system and the baseboard management controller as shared memory under the shared central processing unit, wherein the shared memory is a preset area of ​​memory mounted by the central processing unit; agreeing on a shared memory usage rule between the basic input / output system and the baseboard management controller; When the server is started, performing a shared channel check on the shared memory to determine whether the shared memory is successfully initialized; When the shared memory is successfully initialized, the data related to the reliability, availability, and serviceability (RAS) function collected by the basic input and output system is transmitted to the baseboard management controller through the shared memory based on the shared memory usage rule.

2. The data recording method according to claim 1, wherein: The step of configuring the basic input / output system and the baseboard management controller as shared memories under a shared central processing unit includes: Mount at least one memory stick to the CPU on the motherboard via a two-wire serial I2C bus; Connecting the basic input and output system and the baseboard management controller to the central processing unit via a preset bus respectively; The storage space of the central processing unit mapped to the at least one memory bank is divided and shared by the basic input and output system and the baseboard management controller.

3. The data recording method according to claim 2, wherein: The preset bus adopts ESPI bus or LPC bus.

4. The data recording method according to claim 1, wherein: The step of agreeing on a shared memory usage rule between the basic input / output system and the baseboard management controller includes: It is agreed that after the basic input and output system collects the RAS function-related data, it will encapsulate the RAS function-related data and the baseboard management controller interrupt-related data into a preset structure data packet according to a preset data combination rule and then write the data packet into the shared memory; It is agreed that the baseboard management controller parses a preset structure data packet according to a preset data parsing rule when reading the shared memory to obtain RAS function related data, and displays the data through a management interface.

5. The data recording method according to claim 1, wherein: When the server is started, performing a shared channel check on the shared memory to determine whether the shared memory is successfully initialized includes: Instructing the basic input and output system to read a first preset address during a startup phase to obtain a startup signal, a reset signal, and an initialization state of the baseboard management controller; If the start signal, reset signal and BMC initialization state of the baseboard management controller are all equal to their corresponding preset values, it is determined that the shared memory initialization is successful; If any one of the start signal, the reset signal and the BMC initialization state of the baseboard management controller is not equal to the corresponding preset value, it is determined that the shared memory initialization fails.

6. The data recording method according to claim 1, wherein: When the server is started, performing a shared channel check on the shared memory to determine whether the shared memory is successfully initialized includes: Instructing the baseboard management controller to read a second preset address during a startup phase to obtain a startup signal, a reset signal, and an initialization state of the basic input and output system; If the startup signal, reset signal and initialization state of the basic input and output system are all equal to their corresponding preset values, it is determined that the shared memory is initialized successfully; If any one of the start signal, the reset signal and the initialization state of the basic input / output system is not equal to the corresponding preset value, it is determined that the shared memory initialization fails.

7. The data recording method according to claim 1, wherein: The shared channel is a data communication channel from the basic input / output system and the baseboard management controller to the shared memory respectively.

8. The data recording method according to claim 1, wherein: When the server is started, performing a shared channel check on the shared memory to determine whether the shared memory is successfully initialized includes: Checking whether the shared channel exists; In the case where the shared channel is detected, determining that the shared memory initialization is successful; If the shared channel is not detected, it is determined that the shared memory initialization fails.

9. The data recording method according to claim 8, wherein: The checking whether the shared channel exists includes: Checking whether a data communication channel from the basic input and output system to the shared memory exists, and checking whether a data communication channel from the baseboard management controller to the shared memory exists; In a case where it is detected that both the data communication channel from the basic input / output system to the shared memory and the data communication channel from the baseboard management controller to the shared memory exist, it is determined that the shared channel exists.

10. The data recording method according to claim 4, wherein: The method of transmitting the RAS function-related data collected by the basic input and output system to the baseboard management controller through the shared memory based on the shared memory usage rule includes: Instructing the basic input and output system to obtain a data packet containing data related to the baseboard management controller interrupt from the cache of the shared memory, and determining whether the data packet is empty; In response to the data packet being not empty, the baseboard management controller is instructed to obtain, through the shared memory, a preset structure data packet transmitted by the basic input and output system according to the agreement, and parse the preset structure data packet according to the agreement to obtain RAS function-related data and then display it through the management interface; In response to the data packet being empty, the basic input and output system is made to wait for an interrupt-related data packet.

11. The data recording method according to claim 10, wherein: The shared memory cache includes: a first cache and a second cache, the first cache is configured to cache data sent by a baseboard management controller, and the second cache is configured to cache data received by the baseboard management controller.

12. The data recording method according to claim 10, wherein: The method further comprises: Collecting statistics on the time the basic input / output system waits for interruption-related data packets to obtain a waiting time; In the case that the waiting time exceeds the preset time, the server is caused to skip the process of exchanging RAS function related data between the basic input and output system and the baseboard management controller and continue to execute the startup process.

13. The data recording method according to claim 1, wherein: The method further comprises: In the case where the shared memory initialization fails, the server is instructed to skip the process of exchanging RAS function-related data between the basic input and output system and the baseboard management controller and continue to execute the startup process.

14. The data recording method according to claim 1, wherein: The RAS function related data includes RAS error information and location information.

15. The data recording method according to claim 4, wherein: The preset structure data packet includes at least the following information: definition flag, definition version, interaction quantity, next data address, data address of the first cache, data address of the second cache, data length of the first cache, data length of the second cache, cache type, cache type target, basic input and output system read data, basic input and output system write data, message protocol type, basic input and output system interrupt type, global system input data, baseboard management controller interrupt type, baseboard management controller interrupt address, baseboard management controller interrupt value, and data check value.

16. The data recording method according to claim 1, wherein: The shared memory usage rule indicates a manner in which the basic input / output system and the baseboard management controller perform data interaction via data packets in a preset format.

17. The data recording method according to claim 1, wherein: The preset area is a storage area composed of a continuous address segment, or the preset area is a storage area composed of multiple interval addresses.

18. A data recording device, characterized in that: The device comprises: A configuration module configured to configure the basic input and output system and the baseboard management controller to respectively share a shared memory under the central processing unit, wherein the shared memory is a preset area of ​​memory mounted by the central processing unit; a contract module configured to contract a shared memory usage rule between the basic input / output system and the baseboard management controller; a checking module, wherein the checking module is configured to perform a shared channel check on the shared memory to determine whether the shared memory is successfully initialized when the server is started; A transfer module is configured to transfer the RAS function-related data collected by the basic input and output system to the baseboard management controller through the shared memory based on the shared memory usage rule when the shared memory is successfully initialized.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the data recording method according to any one of claims 1 to 17 is implemented.

20. A non-volatile readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data recording method according to any one of claims 1 to 17 is implemented.

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