All optical coherent ising machines

Abstract

A computing system may be provided. The computing system may include an optical memory cavity configured to store signal pulses representing a current combination for a combinatorial optimization computation. The computing system may further include an optical processing cavity. The optical processing cavity may be configured to receive the signal pulses from the optical memory cavity, perform an all-optical 1-bit delay computation on the signal pulses to generate a feedback pulse for at least one signal pulse, and provide the feedback pulse to be coupled back to the optical memory cavity.

Description

[0001] ALL OPTICAL COHERENT ISING MACHINES

[0002] CROSS REFERENCE TO RELATED APPLICATIONS

[0003] [1] This application claims priority to U.S. Provisional Application No. 63 / 564,205, filed March 12, 2024, which is hereby incorporated by reference in its entirety.

[0004] FIELD

[0005] [2] This disclosure relates to all optical coherent Ising machines configured to perform computations associated with combinatorial optimizations.

[0006] BACKGROUND

[0007] [3] Combinatorial optimization is a form of computation where a computing device searches a combination of states that maximizes and minimizes a particular objective function. The search generally includes the computing device cycling through the different combination of states, calculating the value of the objective function for each state, and comparing the value against the values generated by previous combinations to determine whether the objective function is moving toward a maximum point or a minimum point.

[0008] [4] For computations associated with combinatorial optimization, classical digital computing devices (e.g., CPUs, GPUs) and digital electronics (e.g., FPGAs) are both time and energy inefficient. Classical digital computing devices are inherently built for a sequential processing, and evaluating each combination includes a number of sequential operations. For example, evaluating one combination includes a matrix-vector multiplication, which in turn includes a plurality of multiplication instances (e.g., based on the matrix size) and a classical computing device performs these multiplications sequentially.

[0009] [5] A coherent Ising machine (CIM) improves upon classical computing devices and digital electronics because it allows for parallel operations. For example, the underlying optics of the CIM allows for a plurality of pulses of light performing the multiplications in parallel. In addition to the time savings, these parallel computations are energy efficient as well. However, conventional CIMs still use digital electronics components to perform a portion of computations, and these digital electronics components cause a significant speed bottleneck in the computations. The digital electronics components additionally consume a significant amount of power.

[0010] SUMMARY

[0011] [6] In some embodiments, a computing system may be provided. The computing system may include an optical memory cavity configured to store signal pulses representing a current combination for a combinatorial optimization computation. The computing system may further include an optical processing cavity. The optical processing cavity may be configured to receive the signal pulses from the optical memory cavity, perform an all-optical 1 -bit delay computation on the signal pulses to generate a feedback pulse for at least one signal pulse, and provide the feedback pulse to be coupled back to the optical memory cavity.

[0012] [7] In some embodiments, a computing system may be provided. The computing system may include an optical memory cavity configured to store signal pulses representing a current combination for a combinatorial optimization computation. The computing system may also include a plurality of optical processing cavities. Each of the of the plurality of optical processing cavities configured to, in parallel with other optical processing cavities: receive the signal pulses from the optical memory cavity, perform an all-optical 1-bit delay computation on the signal pulses to generate a feedback pulse for at least one signal pulse, and provide the feedback pulse to be coupled back to the optical memory cavity.

[0013] [8] In some embodiments, a computing system may be provided. The computing system may include a plurality of optical memory cavities, each configured to store signal pulses representing a current combination for a combinatorial optimization computation. The computing system may also include a plurality of optical processing cavities. Each of the plurality of optical processing cavities configured to, in parallel with other optical processing cavities: receive the signal pulses from a corresponding optical memory cavity, perform an all-optical 1-bit delay computation on the signal pulses to generate a feedback pulse for at least one signal pulse, and provide the feedback pulse to be coupled back to the corresponding optical memory cavity.

[0014] BRIEF DESCRIPTION OF DRAWINGS

[0015] [9] FIG. 1 shows an illustrative computing system implementing an all optical CIM, according to example embodiments of this disclosure.

[0016]

[0010] FIG. 2A shows an illustrative computing system implementing an all optical CIM, according to example embodiments of this disclosure.

[0017]

[0011] FIG. 2B shows an illustrative computing performed by the computing system to generate a feedback pulse for a cavity pulse, according to example embodiments of this disclosure.

[0018]

[0012] FIG. 2C shows an illustrative computing performed by the computing system to generate a feedback pulse for a cavity pulse, according to example embodiments of this disclosure.

[0019]

[0013] FIG. 2D shows an illustrative computing performed by the computing system to generate a feedback pulse for a cavity pulse, according to example embodiments of this disclosure.

[0020]

[0014] FIG. 2E shows an illustrative computing performed by the computing system to generate a feedback pulse for a cavity pulse, according to example embodiments of this disclosure.

[0015] FIG. 3 shows an example computing system implementing an all optical CIM, according to example embodiments of this disclosure.

[0021]

[0016] FIG. 4 shows a flow diagram of an example method of performing a combinatorial optimization, according to example embodiments of this disclosure.

[0022]

[0017] FIG. 5 shows a flow diagram of an example method of performing a combinatorial optimization, according to example embodiments of this disclosure.

[0023]

[0018] FIG. 6 shows a flow diagram of an example method of performing a combinatorial optimization, according to example embodiments of this disclosure.

[0024]

[0019] The figures are for purposes of illustrating example embodiments, but it is understood that the present disclosure is not limited to the arrangements and instrumentality shown in the drawings. In the figures, identical reference numbers identify at least generally similar elements.

[0025] DESCRIPTION

[0026]

[0020] Embodiments disclosed herein solve the speed and energy efficiency problems associated with classical digital computers and digital electronics by providing all optical CIMs. The embodiments implement each of the processing and memory components as optical cavities. The optical processing cavities perform a 1 -bit delay calculation to calculate a feedback term for a signal within a plurality of signal pulses from the optical memory cavity. Embodiments disclosed herein allow for a significant amount of parallelism by providing multiple 1 -bit delay optical processing cavities such that feedback terms for multiple signal pulses may be calculated in parallel. Another type of parallelism is provided by multiple optical memory cavities in parallel, each with its own 1 -bit delay optical processing cavity to calculate multiple feedback terms in parallel.

[0027]

[0021] FIG. 1 shows an illustrative computing system 100 implementing an all optical CIM, according to example embodiments of this disclosure. The computing system 100 may include an optical processing cavity 102 (also referred to as “processing cavity”) and an optical memory cavity 104 (also referred to as “memory cavity”). The memory cavity 104 may provide signal pulses 106 at an angular frequency, CD, to the processing cavity. A degenerate optical parametric amplifier (DOPA) (not shown) in the memory cavity 104 may amplify the signals within the memory cavity 104. The processing cavity 102 may incur a 1 -bit delay on an input signal pulse 106 from a memory cavity 104. This 1 -bit delay may allow the processing cavity 102 to process signal pulse 1 (also referred to as x-^) through signal pulse N (also referred to as xN) in the time window from when signal pulse 1 reaches beam splitter 108 to when signal pulse 1 reaches beam splitter 118. At the time the signal pulse 1 reaches the beam splitter 118, the processing cavity 102 may have calculated a feedback term (also referred to as fi) for signal pulse 1, as described in detailed below. An optical homodyne detector 117 may be used to detect a pulse for the feedback term from the beam splitter 118.

[0022] As shown, the beam splitter 108 may split the signal pulses 106 and may send a first split portion of the signal pulses 106 toward the processing cavity 102. The first split portion of the signal pulses 106 toward the processing cavity 102 may be amplified by a degenerate optical parametric amplifier (DOPA) 110. An input-coupling electro-optical (EO) switch 112 may couple the signal pulses 106 to the processing cavity 102. The signal pulses 106 within the processing cavity may be pumped with pump pulses 116 ( i, P2, ••• N) of angular frequency 2CD. Particularly, a pulse from a master laser (not shown) may be modified by an electro-optical modulator (EOM) 152 and passed on to a second harmonic generation (SHG) oscillator 154 to double the laser’s frequency and then pumped to the processing cavity 102 via a dichroic mirror (DM) 156.

[0028]

[0023] At the beginning of a processing cycle, the input-coupling EO switch 112 may couple signal pulse 1 (%i) (e.g., through an in-phase amplitude coupling) into the processing cavity 102. Let gain of the processing cavity 102 be Gi and let the loss be Z. Each of the Gi and L may be provided by a DOPA within the processing cavity 102. The in-phase amplitude of the signal pulse 1 before it is extracted by an output-coupling EO switch 114 may be:

[0029]

[0024] An assumption may be made that the propagation loss for each of the input-coupling EO switch 112 and the output-coupling EO switch 114 is negligible. When the input-coupling EO switch 112 couples in a signal pulse 2 (x2), the combined signal pulse 1 and signal pulse 2 may observe G2 and loss L. Therefore, the in-phase amplitude of the combined signal pulse 1 and signal pulse 2 in the processing cavity 102 before the output-coupling EO switch 114 may be:

[0030]

[0025] After the input-coupling EO switch 112 couples in the signal pulse N (xw) and the signal pulses 1 through N observe a gain G ,- and loss Z, the in-phase amplitude of the combined pulses within the processing cavity 102 may be:

[0031] >

[0032] +V GNGN-••• G1LNx1

[0033]

[0026] This expression may be mapped to a coupling matrix (or Hamiltonian) Jij of an Ising problem.

[0034] The mapping may be represented as:

[0027] The specific coefficients of the coupling matrix Jij may be generated by controlling the gains Gi, G2 ■■ ■■ GN of the processing cavity 102 (e.g., the gain of the DOPA). The coefficient Ji,i is a 1-bit delay self-coupling constant, which may serve as a “momentum term.”

[0035]

[0028] If a specific coefficient Jij is 0, signal pulse xj may be blocked by the input-coupling EO switch

[0036] 112 such that xj is not coupled into the processing cavity 102. For these 0-coefficient cases, GjL may be set as 1 to realize balanced gain and loss. After all of signal pulse 1 through signal pulse N are input into the processing cavity 102, the in-phase amplitude ( v) of the pulse in the processing cavity 102 is a desired result of a matrix vector multiplication as shown below:

[0037]

[0029] In some embodiments, the 0-coefficient cases may be handled by fictitious Jij. For a first round, a fictitious / 1;= +a (a « 1) may be implemented. In a second round, the polarity of / 1;, may be switched from / 1;- = +a to / 1;- = — a. After multiple rounds of implementing / 1;- = +a and / 1;- = —a. the effect of hjXj may be canceled out by destructive interference.

[0038]

[0030] The output-coupling EO switch 114 may extract the pulse XNfrom the processing cavity 102. The extracted pulse XNmay be sent back to the memory cavity 104 when signal pulse 1 is incident on the beam splitter 118 after a 1-bit delay. In the way, one vector-vector multiplication, may be implemented. The 1stsignal pulse in the next round trip may then be rejected by the input-coupling EO switch 112. The processing cavity 102 may return back to a vacuum state, using a vacuum input 119, and ready to capture the signal pulses x2, x3, ••• xN, x to complete the feedback pulse preparation to the signal pulse 2 (x2).

[0039]

[0031] FIG. 2A shows an illustrative computing system 200 implementing an all optical CIM, according to example embodiments of this disclosure. Compared to the computing system 100 implementing a single 1-bit delay processing cavity 102, the computing system 200 may implement 1-bit delay with multiple optical processing cavities 202 (also referred to as “processing cavities”), where some example processing cavities 202a, 202b,... , 2021,... are shown. As with FIG. 1, the computing system 200 may include a memory cavity 204 storing signal pulses 206, a beam splitter 208 to divert a portion of the signal pulses 206 toward the 1-but delay processing cavities 202, a DOPA 210 to boost the diverted portion of the signal pulses 206, and a beam splitter 218 that directs the received feedback pulses from the processing cavities 202 toward an optical homodyne detector 217. Each of the processing cavities 202 may include a corresponding input-coupling EO switch 212, an output-coupling EO switch 214, and a pump pulse 216 being pumped to the corresponding processing cavity via a dichroic mirror 256. The computing system 200 may calculate the different feedback terms f in parallel by controlling the input-coupling EO switches 212, as detailed below. A DOPA (not shown) in the memory cavity 204 may amplify the signals within the memory cavity. A vacuum input 219 may clear the signal within one or more processing cavities 202. An optical homodyne detector may be used to detect a feedback pulse from one or more of the processing cavities 202.

[0040]

[0032] FIG. 2B shows an illustrative computing performed by the computing system 200 to generate a feedback pulse for a cavity pulse, according to example embodiments of this disclosure. As shown, the computing system 200 may generate a feedback pulse i for a memory cavity pulse x1in the processing cavity 202a. Extracted pulses 220a may be incoming pulses from the memory cavity 204, where a portion of the extracted pulses 220a may be blocked by input-coupling EO switch 212a. Particularly, the input-coupling EO switch may block a previous round trip of the signal pulses and start coupling the extracted pulses beginning from the memory cavity pulse x1. Based on the principles described above, processing cavity 202a (e.g., by controlling gains and losses within the processing cavity 202a) may calculate a momentum term 224a and an Ising term 226a and generate the feedback pulse i. The feedback pulse i may be extracted from the processing cavity 202a and injected into the memory cavity 204 by an output-coupling EO switch 214a.

[0041]

[0033] FIG. 2C shows an illustrative computing performed by the computing system 200 to generate a feedback pulse for a cavity pulse, according to example embodiments of this disclosure. This computing may be performed in parallel with the computing shown in FIG. 2B. As shown, the computing system 200 may generate a feedback pulse fy for a memory cavity pulse x2in the processing cavity 202b. Extracted pulses 220b may be incoming pulses from the memory cavity 204, where a portion of the extracted pulses 220b may be blocked by input-coupling EO switch 212b. Particularly, the inputcoupling EO switch 212b may block previous round trips and memory cavity pulse x1from the current round trip. The input-coupling EO switch 212b may start coupling the extracted pulses 220b beginning from the memory cavity pulse x2up until the memory cavity pulse xrof the next round trip. Based on the principles described above, processing cavity 202b (e.g., by controlling gains and losses within the processing cavity 202b) may calculate a momentum term 224b and an Ising term 226b and generate the feedback pulse >. The feedback pulse fy may be extracted from the processing cavity 202b and injected into the memory cavity 204 by an output-coupling EO switch 214b.

[0042]

[0034] FIG. 2D shows an illustrative computing performed by the computing system 200 to generate a feedback pulse for a cavity pulse, according to example embodiments of this disclosure. This computing may be performed in parallel with the computing shown in each of FIG. 2B and FIG. 2C. As shown, the computing system 200 may generate a feedback pulse / i for a memory cavity pulse xtin the processing cavity 2021. Extracted pulses 2201 may be incoming pulses from the memory cavity 204, where a portion of the extracted pulses 2201 may be blocked by input-coupling EO switch 2121. Particularly, the inputcoupling EO switch 2121 may block memory cavity pulses from previous round trips and memory cavity pulses until xL-from the current round trip. The input-coupling EO switch 212b may start coupling the extracted pulses 2201 beginning from the memory cavity pulse xLup until the memory cavity pulse xL-1of the next round trip. Based on the principles described above, processing cavity 2021 (e.g., by controlling gains and losses within the processing cavity 2021) may calculate a momentum term 2241 and an Ising term 2261 and generate the feedback pulse Ji. The feedback pulse / [' may be extracted from the processing cavity 2021 and injected into the memory cavity 204 by an output-coupling EO switch 2141.

[0043]

[0035] FIG. 2E shows an illustrative computing performed by the computing system 200 to generate a feedback pulse for a cavity pulse, according to example embodiments of this disclosure. This computing may be performed in parallel with the computing shown in each of FIG. 2B, FIG. 2C, and FIG. 2D. As shown, the computing system 200 may generate a feedback pulse / i i for a memory cavity pulse xt+1in the processing cavity 202a. Extracted pulses 220m may be incoming pulses from the memory cavity 204, where a portion of the extracted pulses 220m may be blocked by input-coupling EO switch 212m. Particularly, the input-coupling EO switch 212m may block memory cavity pulses from previous round trips and memory cavity pulses until xLfrom the current round trip. The input-coupling EO switch 212m may start coupling the extracted pulses 220m beginning from the memory cavity pulse xL+1up until the memory cavity pulse xLof the next round trip. Based on the principles described above, processing cavity 202a (e.g., by controlling gains and losses within the processing cavity 202a) may calculate a momentum term 224m and an Ising term 226m and generate the feedback pulse L+i. The feedback pulseL+I may be extracted from the processing cavity 202a and injected into the memory cavity 204 by an output-coupling EO switch 214m.

[0044]

[0036] To compare the computing systems implementing an all optical CIM with conventional computing systems, an example computing system implementing an all optical CIM may be designed as follows. In the below design, L designates the number of parallel 1-but processing cavities. clock frequency for pulse repetition: 100 GHz pulse duration: 100 fsec memory cavity round trip time: 3 X 10-7sec (60 m fiber) number of pulses N: 3 x 104time lor matrix- vector multiplication (all-to-all coupling):

[0045] = 9.00 msec (L=l)

[0046] 3.00 msec (L=3) 0.90 msec (L= 10) 0.30 msec (L=30) 0.09 msec (L=100)

[0047] Power budget: master laser: 100 (mW) x 1 EO modulator and switch: 20 (mW) x (L + 2L) processing cavity DOPA: 1 (mW) x L memory cavity DOPA: 1 (mW) x 1

[0048]

[0037] The performance of the above computing system may be compared against a conventional silicon based graphics processing unit (GPU) with the following results: All-o tical CIM

[0049] Time per MVM 1 [msec] 9 [msec] 3 [msec] 0.9 0.3 [msec] 0.09

[0050] [msec] [msec]

[0051] Energy per MVM 100 [mJ] 1.5 [mJ] 0.85 [mJ] 0.64 [mJ] 0.58 [mJ] 0.56 [mJ]

[0052] * Master laser for pumping (1), EO Modulator for each 1-bit delay processing cavity (L), EO switch (2L), DOPA (L+l)

[0053]

[0038] As shown, there is a significant improvement in both time and energy consumption in the all optical CIM compared to the GPU. For example, in case of L=100 in an all optical CIM, the speed gain is more than an order of magnitude while having a concomitant energy consumption of less than 1% compared to a traditional GPU.

[0054]

[0039] FIG. 3 shows an example computing system 300 implementing an all optical CIM, according to example embodiments of this disclosure. The computing system 300 may include a memory cavity 304 may include a multi-core fiber with M cores (core #1 to core #M), where each of the M cores may support N pulses. Each of the M cores be associated with a corresponding processing cavities 302a, 302b,... , 302m. The operations of the processing cavities 302a, 302b,... , 302m has been described in detail above. A DOPA 330 may amplify the signals in each of the M cores. The computing system 300 may perform computations for combinatorial optimizations simultaneously using M independent CIM. Another advantage of using such M-CIMs is that the same pump pulses (Pi, P2, "• PN) may be used for all M-CIMS, so that the single master laser, single EO modulator, and single SHG can be shared by M independent CIMs. Additionally, because M independent CIMs are embedded in a single fiber, the phase stabilization of M independent CIMs can be realized readily.

[0055]

[0040] The below comparative charts illustrate the significant improvements provided by the multi-core fibers based CIM (M-CIM) compared to conventional GPU.

[0056] ■ System design clock frequency for pulse repetition: 100 GHz (10 psec pulse-to-pulse interval) pulse duration: 100 fsec (20 pm width in fiber, 15 pm width in TFLN) main cavity round trip time: 3 X 10-7sec (corresponding to 60 m fiber length) number of pulses N: 3 x 104time for MVM (all-to-all coupling): 9 msec (3 x 10-7(s) x 3xl04(pulses)) for L = 1

[0057] 0.9 msec for L = 10

[0058] 0.09 msec for L = 100

[0059] ■ Performance comparison against GPU

[0060] GPU CIM (L=l)

[0061] M=1 M=3 M=10 M=100

[0062] Clock frequency 2 GHz 100 GHz 300 GHz 1 THz 10 THz

[0063] Number of active 7.6 X 10107 11 43 403 elements 9 (transistors)

[0064] 1) Master laser (1), EOM (1), SHG (1), DOPA (2M), EO switch (2M)

[0065] 2) Master laser power: 100 (mW) x l

[0066] EO modulator and switch: 20 (mW) x (1 + 2M)

[0067] Processing cavity DOPA: 1 (mW) x M

[0068] Memory cavity DOPA: 1 (mW) x M

[0069] GPU CIM (L=10)

[0070] M=1 M=3 M=10 M=100

[0071] Clock frequency 2 GHz 100 GHz 300 GHz 1 THz 10 THz

[0072] Number of active 7.6 X 101042 104 321 3111 elements (transistors)

[0073] Power1’ 100 |W | 6.2 |W | 14.4 | W| 43. 1 |W | 410 |W |

[0074] Time per MVM 1 [msec] 0.09 0.03n r, 0.9

[0075] [msec] [msec]9 [tlsec][Msec]

[0076] Energy per MVM 100 [mJ] 0.56 0.43 0.39 0.37

[0077] [mJ] [mJ] [mJ] [mJ] 3) Master laser (1), EOM (L), EO switch (2LM), DOPA (M + ML)

[0078] 4) Master laser: 100 (mW) x l

[0079] EO modulator and switch:20 (mW) x L (1 + 2M) Processing cavity DOPA: 1 (mW) x LM

[0080] Memory cavity DOPA: 1 (mW) x M

[0081]

[0041] FIG. 4 shows a flow diagram of an example method 400 of performing a combinatorial optimization, according to example embodiments of this disclosure. The steps of the method 400 may be performed by the computing system 100 that may include an optical processing cavity 102 and an optical memory cavity 104.

[0082]

[0042] At step 402, the optical processing cavity 102 may receive signal pulses from the optical memory cavity 104. The signal pulses may represent the current state of the combinatorial optimization.

[0083]

[0043] At step 404, the optical processing cavity 102 may perform an all-optical 1 -bit delay computation on the signal pulses. The computation may generate a feedback pulse for at least one signal pulse.

[0084]

[0044] At step 406, the optical processing cavity 102 may provide the feedback pulse to be coupled back to the optical memory cavity 104. The feedback pulse may be used to update the current state of the combinatorial optimization to a next state.

[0085]

[0045] FIG. 5 shows a flow diagram of an example method 500 of performing a combinatorial optimization, according to example embodiments of this disclosure. The steps of the method 500 may be performed by the computing system 200 that may include multiple optical processing cavities 202 and an optical memory cavity 204.

[0086]

[0046] At step 502, each optical processing cavity of the multiple optical processing cavities 202 may receive signal pulses from the optical memory cavity 204. The signal pulses may represent the current state of the combinatorial optimization. The optical processing cavities 202 may receive parallelly receive the signal pulses.

[0087]

[0047] At step 504, each optical processing cavity may perform an all-optical 1 -bit delay computation on the signal pulses. The computation may generate a feedback pulse for at least one signal pulse.

[0088]

[0048] At step 506, each optical processing cavity may provide the feedback pulse to be coupled back to the optical memory cavity 204. The feedback pulse may be used to update the current state of the combinatorial optimization to a next state.

[0089]

[0049] FIG. 6 shows a flow diagram of an example method 600 of performing a combinatorial optimization, according to example embodiments of this disclosure. The steps of the method 600 may be performed by the computing system 300 that may include multiple optical processing cavities 302 and an optical memory cavity 304 comprising multiple cores (each core may also be referred as an optical memory cavity, therefore the optical memory cavity 304 may include multiple optical memory cavities).

[0050] At step 602, each optical processing cavity of the multiple optical processing cavities 302 may receive signal pulses from corresponding core of the optical memory cavity 304. The signal pulses may represent the current state of the combinatorial optimization. The optical processing cavities 302 may receive parallelly receive the signal pulses from their corresponding cores.

[0090]

[0051] At step 604, each optical processing cavity may perform an all-optical 1 -bit delay computation on the signal pulses. The computation may generate a feedback pulse for at least one signal pulse.

[0091]

[0052] At step 606, each optical processing cavity may provide the feedback pulse to be coupled back to the corresponding core of optical memory cavity 304. The feedback pulse may be used to update the current state of the combinatorial optimization to a next state.

[0092]

[0053] Additional examples of the presently described method and device embodiments are suggested according to the structures and techniques described herein. Other non-limiting examples may be configured to operate separately or can be combined in any permutation or combination with any one or more of the other examples provided above or throughout the present disclosure.

[0093]

[0054] The steps of the methods described herein are just exemplary and should not be considered limiting. That is, methods with additional, alternate, or fewer number of steps should be considered within the scope of this disclosure.

[0094]

[0055] It will be appreciated by those skilled in the art that the present disclosure can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restricted. The scope of the disclosure is indicated by the appended claims rather than the foregoing description and all changes that come within the meaning and range and equivalence thereof are intended to be embraced therein.

[0095]

[0056] It should be noted that the terms “including” and “comprising” should be interpreted as meaning “including, but not limited to”. If not already set forth explicitly in the claims, the term “a” should be interpreted as “at least one” and “the”, “said”, etc. should be interpreted as “the at least one”, “said at least one”, etc. Furthermore, it is the Applicant's intent that only claims that include the express language "means for" or "step for" be interpreted under 35 U.S.C. 112(f). Claims that do not expressly include the phrase "means for" or "step for" are not to be interpreted under 35 U.S.C. 112(f).

Claims

CLAIMSWhat is claimed is:

1. A computing system comprising: an optical memory cavity configured to store signal pulses representing a current combination for a combinatorial optimization computation; and an optical processing cavity configured to: receive the signal pulses from the optical memory cavity; perform an all-optical 1 -bit delay computation on the signal pulses to generate a feedback pulse for at least one signal pulse; and provide the feedback pulse to be coupled back to the optical memory cavity.

2. The computing system of claim 1, wherein the optical processing cavity is configured to implement an Ising Hamiltonian using a gain of the optical processing cavity.

3. The computing system of claim 1, wherein the optical processing cavity is configured to implement an Ising Hamiltonian using a loss of the optical processing cavity.

4. The computing system of claim 1, wherein the optical processing cavity includes a degenerate optical parametric amplifier configured to provide a gain.

5. The computing system of claim 1, further comprising: an electro-optical switch configured to couple the signal pulses from the optical memory cavity to the optical processing cavity.

6. The computing system of claim 1, further comprising: an electro-optical switch configured to couple the feedback pulse from the optical processing cavity to the optical memory cavity.

7. The computing system of claim 1, further comprising: a pumping laser configured to pump the optical processing cavity.

8. A computing system comprising: an optical memory cavity configured to store signal pulses representing a current combination for a combinatorial optimization computation; anda plurality of optical processing cavities, each of the plurality of optical processing cavities configured to, in parallel with other optical processing cavities: receive the signal pulses from the optical memory cavity; perform an all-optical 1 -bit delay computation on the signal pulses to generate a feedback pulse for at least one signal pulse; and provide the feedback pulse to be coupled back to the optical memory cavity.

9. The computing system of claim 8, wherein each optical processing cavity is configured to implement an Ising Hamiltonian using a gain of the optical processing cavity.

10. The computing system of claim 8, wherein each optical processing cavity is configured to implement an Ising Hamiltonian using a loss of the optical processing cavity.

11. The computing system of claim 8, wherein each processing cavity includes a degenerate optical parametric amplifier configured to provide a gain.

12. The computing system of claim 8, further comprising: a plurality of an electro-optical switches corresponding to the plurality of optical processing cavities, each electro-optical switch configured to couple a portion of the signal pulses from the optical memory cavity to a corresponding optical processing cavity.

13. The computing system of claim 8, comprising: a plurality of electro-optical switches, each configured to couple the feedback pulse from a corresponding optical processing cavity to the optical memory cavity.

14. The computing system of claim 8, comprising: a plurality of pumping lasers, each configured to pump a corresponding optical processing cavity.

15. A computing system comprising: a plurality of optical memory cavities, each configured to store signal pulses representing a current combination for a combinatorial optimization computation; and a plurality of optical processing cavities, each of the plurality of optical processing cavities configured to, in parallel with other optical processing cavities: receive the signal pulses from a corresponding optical memory cavity;perform an all-optical 1 -bit delay computation on the signal pulses to generate a feedback pulse for at least one signal pulse; and provide the feedback pulse to be coupled back to the corresponding optical memory cavity.

16. The computing system of claim 15, wherein each optical processing cavity is configured to implement an Ising Hamiltonian using a gain of the optical processing cavity.

17. The computing system of claim 15, wherein each optical processing cavity is configured to implement an Ising Hamiltonian using a loss of the optical processing cavity.

18. The computing system of claim 15, wherein each processing cavity includes a degenerate optical parametric amplifier configured to provide a gain.

19. The computing system of claim 15, further comprising: a plurality of an electro-optical switches corresponding to the plurality of optical processing cavities, each electro-optical switch configured to couple a portion of the signal pulses from a corresponding optical memory cavity to a corresponding optical processing cavity.

20. The computing system of claim 15, further comprising: a plurality of electro-optical switches, each configured to couple the feedback pulse from a corresponding optical processing cavity to a corresponding optical memory cavity.

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