Differential ring oscillator

Abstract

In the present invention, cross-coupled latches 15, 25, 35 are each formed by counter connection between multiple outputs A1-A3 of first inverters 11, 21, 31 and multiple outputs B1-B3 of second inverters 12, 22, 32. When controlled by a control circuit 50, a first output A1 of the first inverter 11 in a first loop L1 is pulled down to an L level, and a second output B2 of the second inverter 22 in a second loop L2 is also pulled down to the L level, thus achieving an initial reset state.

Description

Differential Ring Oscillator CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2024-77256, filed on May 10, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a differential ring oscillator.

[0003] A ring oscillator is a self-oscillating circuit made by cascading CMOS inverters in a ring shape. The oscillation frequency of a ring oscillator can be variably controlled by inputting and varying the supply current, allowing it to function as a CCO (Current-Controlled Oscillator). Furthermore, if a voltage-input, current-output amplifier is placed in front of the ring oscillator and the input current is varied according to the input voltage to control the oscillation frequency, it can function as a VCO (Voltage-Controlled Oscillator). The oscillation frequency can be converted to a digital value by measuring the oscillation output over a certain period of time with a digital counter. If the input is a voltage and the oscillation frequency is a digital output, it will function as a simple A / D converter, known as a VCO-based quantizer.

[0004] As an independent A / D converter, it has a narrow linear conversion range and low resolution, but it is characterized by its small size, high speed, and low power consumption. For this reason, it is often used in combination with other circuit methods, for example, as an internal component circuit of successive approximation A / D converters or delta-sigma A / D converters. An initial reset function is sometimes required to accurately measure the oscillation frequency of a ring oscillator. During initial reset, the H / L state of each component is set to a predetermined state before the ring oscillator starts operating, stopping oscillation, and after the reset is released, it resumes stable oscillation.

[0005] Conventionally, a method for initially resetting a ring oscillator involves inserting a logic circuit such as a NAND gate or a NOR gate into the loop to determine the output and then resetting (see, for example, Japanese Patent Laid-Open No. 2003-222998).

[0006] Japanese Patent Application Laid-Open No. 2006-217455

[0007] As described in the Background Art section, when a logic circuit is used to determine the output H / L level of a ring oscillator and then the oscillator is reset, the static current of the ring oscillator becomes zero. For example, if the available power supply current is limited, the static current of the ring oscillator becomes zero upon reset, causing the operating point of the power supply voltage Vdd to exceed the upper limit of the supply current Idd. This has the disadvantage that the ring oscillator becomes unstable immediately after starting oscillation after reset release until the operating point of the power supply voltage Vdd minus the supply current Idd stabilizes.

[0008] An object of the present disclosure is to provide a differential ring oscillator that can suppress Vdd fluctuations before and after resetting after resetting is released, and can immediately start stable oscillation after resetting is released.

[0009] According to one aspect of the present disclosure, a loop is configured with a plurality of n first inverters and n second inverters forming differential pairs and configured with positive feedback. Opposing connection circuits are connected between the multiple outputs of the n first inverters and the multiple outputs of the n second inverters, respectively. When controlled by a control circuit, the opposing connection circuits pull down the first output of a certain first inverter in the first loop to an L level, and pull down the second output of a second inverter in a second loop that forms a differential pair with the first output of the first inverter at a stage subsequent to the first inverter to an L level, thereby setting the loop to an initial reset state.

[0010] According to one aspect of the present disclosure, even in an initial reset state, the operating points of the supply current and power supply voltage do not fluctuate significantly after the reset is released, thereby improving the stability of operation.

[0011] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Fig. 1 is an electrical configuration diagram of a differential ring oscillator according to a first embodiment, Fig. 2 is a first example of a configuration of a differential inverter cell circuit according to the first embodiment, Fig. 3 is a second example of a configuration of a differential inverter cell circuit according to the first embodiment, Fig. 4 is a third example of a configuration of a differential inverter cell circuit according to the first embodiment, Fig. 5 is a diagram showing the H / L levels of each node at the time of resetting in the first embodiment, Fig. 6 is an electrical configuration diagram of a differential ring oscillator according to a second embodiment, Fig. 7 is a fourth example of a configuration of a differential inverter cell circuit according to the second embodiment, and Fig. 8 is a diagram showing the H / L levels of each node at the time of resetting in the second embodiment.

[0012] Hereinafter, several embodiments will be described with reference to the drawings. In each embodiment described below, components that perform the same or similar operations are denoted by the same or similar reference numerals, and descriptions thereof will be omitted as necessary.

[0013] (First Embodiment) A first embodiment will be described with reference to Figures 1 to 5. As shown in Figure 1, a differential ring oscillator 1 of this embodiment has two loops L1 and L2, and these loops are configured as a differential circuit that operates in pairs. This circuit configuration is called a differential ring oscillator or a pseudo-differential oscillator.

[0014] The differential ring oscillator 1 is configured by connecting n (n is an odd number) differential inverter cell circuits 10, 20, and 30 in a ring shape. A power supply voltage Vdd is supplied to each of the differential inverter cell circuits 10, 20, and 30. The power supply voltage Vdd supplies a constant voltage to each of the differential inverter cell circuits 10, 20, and 30, but there is a predetermined upper limit on the overall supply current Idd when voltage is supplied. The English term for differential inverter cell is "Differential Inverter Cell."

[0015] The differential inverter cell circuit 10 is configured with a cross-coupled latch 15 consisting of a pair of first and second inverters 11 and 12, and latches 13 and 14 connected in opposite directions between their outputs. The differential inverter cell circuit 10 operates as a differential pair in which the pair of inverters 11 and 12 inverts high and low levels relative to each other. To maintain differential pair operation even if there is a mismatch in characteristics between the two inverters 11 and 12, a cross-coupled latch 15 is provided as an opposite-connection circuit, with latches 13 and 14 connected in opposite directions between the outputs. Note that a circuit element having the same function as the cross-coupled latch 15 and equivalent to the cross-coupled latch 15 may also be installed as the opposite-connection circuit.

[0016] Similarly, the differential inverter cell circuit 20 is configured by a pair of a first inverter 21 and a second inverter 22, and a cross-coupled latch 25 made up of latches 23 and 24 connected in opposite directions between the outputs of the first inverter 21 and the second inverter 22. The differential inverter cell circuit 20 is configured as a differential pair in which the pair of inverters 21 and 22 inverts H / L with respect to each other.

[0017] At this time, in order to maintain differential pair operation even if there is a mismatch in characteristics between the two inverters 21 and 22 that make up the pair, a cross-coupled latch 25 is provided as an opposing connection circuit, in which latches 23 and 24 are arranged opposite each other in both directions between the outputs. Note that a circuit element that has the same function as the cross-coupled latch 25 and is equivalent to the cross-coupled latch 25 may also be provided as the opposing connection circuit.

[0018] Furthermore, the differential inverter cell circuit 30 is configured with a pair of a first inverter 31 and a second inverter 32, and a cross-coupled latch 35 made up of latches 33 and 34 as a paired connection circuit connected in opposite directions between the outputs of the first inverter 31 and the second inverter 32. The differential inverter cell circuit 30 is configured as a differential pair in which the pair of inverters 31 and 32 inverts H / L with respect to each other.

[0019] In this case, in order to maintain differential pair operation even if there is a mismatch in characteristics between the two inverters 31 and 32 that make up the pair, a cross-coupled latch 35 is provided as an opposing connection circuit, in which latches 33 and 34 are arranged opposite each other in both directions between the outputs. Note that a circuit element that has the same function as the cross-coupled latch 35 and is equivalent to the cross-coupled latch 25 may also be provided as the opposing connection circuit.

[0020] The differential ring oscillator 1 includes a first loop L1 and a second loop L2 that are cyclically connected. The first loop L1 is formed by straight-connecting and cyclically connecting an odd number of first inverters (here, three inverters 11, 21, and 31). The second loop L2 is formed by straight-connecting and cyclically connecting an odd number of second inverters (here, three inverters 12, 22, and 32) that are cyclically connected to the first inverters 11, 21, and 31 to form differential pairs.

[0021] The cross-coupled latches 15, 25, and 35 are connected in opposing relation between the multiple outputs A1, A2, and A3 of the odd number of first inverters 11, 21, and 31 and the multiple outputs B1, B2, and B3 of the odd number of second inverters 12, 22, and 32, respectively. A control circuit 50 is also connected to the differential ring oscillator 1. The control circuit 50 is configured, for example, by a hardware control logic circuit, and is capable of outputting a reset signal at a digital level (H level or L level) to forcibly place the differential ring oscillator 1 in an initial reset state. This provides an initial reset function that determines the outputs of the differential inverter cell circuits 10, 20, and 30.

[0022] A specific example of the first-stage differential inverter cell circuit 10 is shown in Figure 2. As shown in Figure 2, the inverter 11 has a p-channel MOSFET_M1p and an n-channel MOSFET_M1n connected as a CMOS inverter between a power supply Vdd and ground GND. When an input signal in+ is input to the inverter 11, the inverter 11 inverts the input signal in+ and outputs an output signal out-. The inverter 12 has a p-channel MOSFET_M2p and an n-channel MOSFET_M2n connected as a CMOS inverter between a power supply Vdd and ground GND. When an input signal in- is input to the inverter 12, the inverter 12 inverts the input signal in- and outputs an output signal out+.

[0023] The latch 13 connects the source-drain of a p-channel MOSFET_M3p and the drain-source of an n-channel MOSFET_M3n in series between a power supply Vdd and ground GND, and inputs an output signal out+ to the gate of MOSFET_M3p. The common connection node of MOSFET_M3p and MOSFET_M3n is referred to as a first intermediate node N3. A control circuit 50 is connected to the gate of MOSFET_M3n, making it possible to apply a reset signal to the gate of MOSFET_M3n.

[0024] MOSFET_M3n is provided for initial reset. Since the differential inverter cell circuit 10 has MOSFET_M3n of the latch 13, it is advisable to connect MOSFET_M4n of the latch 14 to MOSFET_M3n so that they form a differential pair. By adopting this configuration, it is possible to maintain a good balance between the differential circuit and its semiconductor layout structure, and to improve operational stability against power supply voltage fluctuations and common noise. Note that MOSFET_M3n corresponds to the first switch, and MOSFET_M4n corresponds to the second switch.

[0025] The latch 14 connects the source-drain of a p-channel MOSFET_M4p and the drain-source of an n-channel MOSFET_M4n in series between a power supply Vdd and ground GND, and inputs an output signal out- to the gate of MOSFET_M4p. The common connection node of MOSFET_M4p and MOSFET_M4n is referred to as a second intermediate node N4. In this embodiment, a control circuit 50 is connected to the gate of MOSFET_M4n, making it possible to apply a reset signal to the gate of MOSFET_M4n.

[0026] The MOSFETs M1p to M4p and MOSFETs M1n to M4n that configure the inverters 11 and 12 and the latches 13 and 14 have a gate-source voltage V ＧＳ V ＧＳ (M1p to M4p)>V ＧＳ (M1n to M4n).

[0027] The first reason is that the drain current Id is supplied from the source side of the p-channel MOSFETs M1p to M4p to the differential inverter cell circuits 10, 20, and 30. Generally, the source and body of the n-channel MOSFETs M1n to M4n are shorted to the same potential, whereas the body and source of the p-channel MOSFETs M1p to M4p are not at the same potential, and therefore the threshold voltage Vt of the p-channel MOSFETs M1p to M4p is likely to become high due to the substrate bias effect (body effect).

[0028] The second reason is that n-channel MOSFETs M1n to M4n generally have a higher drain current Id driving capability than p-channel MOSFETs M1p to M4p. When the same drain current Id flows through the same element size, the gate-source voltage V ＧＳ (M1p to M4p) is the gate-source voltage V of the n-channel MOSFETs M1n to M4n ＧＳ (M1n to M4n). For these two reasons, V ＧＳ (M1p to M4p)>V ＧＳ(M1n to M4n).

[0029] 3 and 4 show the configurations of differential inverter cell circuits 20 and 30, which are the next and subsequent stages of differential inverter cell circuit 10. Corresponding elements in the internal configuration of differential inverter cell circuits 20 and 30 are shown with the same reference numerals as the corresponding elements in the internal configuration of differential inverter cell circuit 10, and elements having different functions are given the suffix a. In describing the configuration of differential inverter cell circuits 20 and 30, only elements that differ from differential inverter cell circuit 10 will be described, and descriptions of other parts will be omitted.

[0030] 3 differs from the differential inverter cell circuit 10 in the latch 23. The differential inverter cell circuit 20 includes a first inverter 21, a second inverter 22, and latches 23 and 24. The configuration of the latch 23 corresponds to the configuration of the latch 13, and includes a p-channel MOSFET_M3p and an n-channel MOSFET_M3na. The gate of MOSFET_M3p is connected to the second intermediate node N4, the source is connected to the supply node of the power supply voltage Vdd, and the drain is connected to the first intermediate node N3.

[0031] MOSFET_M3na has a gate connected to the control circuit 50, a drain connected to the supply node of the power supply voltage Vdd, and a source connected to the first intermediate node N3. As a result, when MOSFET_M3na is turned on by the control circuit 50, the first intermediate node N3 can be pulled up to the H level. The configurations of the other components, the first inverter 21, the second inverter 22, and the latch 24, are similar to those of the first inverter 11, the second inverter 12, and the latch 14 of the differential inverter cell circuit 10, respectively, and therefore will not be described here.

[0032] 4 differs from the differential inverter cell circuit 10 in the latch 34. The differential inverter cell circuit 30 includes a first inverter 31, a second inverter 32, and latches 33 and 34. The configuration of the latch 34 corresponds to the configuration of the latch 14, and includes a p-channel MOSFET_M4p and an n-channel MOSFET_M4na. The gate of the MOSFET_M4p is connected to the first intermediate node N3, the source is connected to the supply node of the power supply voltage Vdd, and the drain is connected to the second intermediate node N4.

[0033] MOSFET_M4na has a gate connected to the control circuit 50, a drain connected to the supply node of the power supply voltage Vdd, and a source connected to the second intermediate node N4. As a result, the control circuit 50 turns on MOSFET_M4na, thereby making it possible to pull up the second intermediate node N4 to the H level. The configurations of the other components, the first inverter 31, the second inverter 32, and the latch 33, are similar to those of the first inverter 11, the second inverter 12, and the latch 13 of the differential inverter cell circuit 10, and therefore description thereof will be omitted.

[0034] <Explanation of Normal Operation> Normal operation of the differential inverter cell circuit 10 will be described with reference to FIG. 2. During normal operation, the output signals out+ and out- of the inverters 11 and 12 change complementarily, so that when the output signal out+ goes to an H level, the output signal out- goes to an L level. In this case, MOSFET_M3p is turned off by inputting the H level of the output signal out+ to its gate, but the first intermediate node N3 goes to the L level, the same as the output signal out-. MOSFET_M4p is turned on by inputting the L level of the output signal out- to its gate, but the second intermediate node N4 goes to the H level, the same as the output signal out+.

[0035] Conversely, when the output signal out+ goes to the L level, the output signal out- goes to the H level. In this case, MOSFET_M3p is turned on by inputting the L level of the output signal out+ to its gate, but the first intermediate node N3 goes to the H level, the same as the output signal out-. MOSFET_M4p is turned off by inputting the H level of the output signal out- to its gate, but the second intermediate node N4 goes to the L level, the same as the output signal out+.

[0036] Therefore, even if the output signals out+ and out− change to either H or L level, the drain-source states of the MOSFETs M3n and M4n remain open, and the oscillation operation of the differential ring oscillator 1 is not affected.

[0037] When the differential inverter cell circuit 10 receives the signals in+ and in-, it inverts these signals and outputs the signals out- and out+ as first outputs A1 and B1, respectively. The differential inverter cell circuits 20 and 30 similarly invert and output signals. The differential inverter cell circuit 10 then receives the inverted levels of the previous input signals in+ and in-, inverts the input signals in+ and in-, and outputs the output signals out- and out+. These operations are repeated. Therefore, the differential ring oscillator 1 oscillates by positively feeding back the signals.

[0038] <Explanation of Reset Operation> When performing an initial reset, the control circuit 50 applies a reset signal to the gates of MOSFET_M3n of latch 13 and MOSFET_M4n of latch 24 of the outputs of predetermined inverters (11 and 22 in this example), thereby fixing the first output A1 to the third output A3 and the first output B1 to the third output B3 to the L level or the H level.

[0039] The control circuit 50 pulls down the first output A1 of a certain first inverter (here, for example, 11) in the first loop L1 to the L level. At the same time, the control circuit 50 may pull down the second output B2 of the second inverter 22 in the second loop L2, which forms a differential pair with the first inverter 21, to the L level, thereby setting the circuit in an initial reset state.

[0040] Specifically, the control circuit 50 forcibly turns on the MOSFET_M3n and fixes the output signal out− to the L level by outputting an H level reset signal to the gate of the MOSFET_M3n constituting the latch 13 in the next stage of the first inverter 11 shown in Fig. 2. This allows the first output A1 of the first inverter 11 to be pulled down to the L level.

[0041] At the same time, the control circuit 50 outputs a high-level reset signal to the gate of the MOSFET M4n that constitutes the latch 24 in the next stage of the second inverter 22, which is a differential pair with the first inverter 21 shown in FIG. 3, thereby forcibly turning on the MOSFET M4n and fixing the output signal out+ to a low level. This fixes the digital levels of portions of each of the loops L1 and L2. In this embodiment, the control circuit 50 turns on only the two MOSFETs M3n and M4n, leaving the other MOSFETs unchanged. The first inverters 11, 21, and 31 and the second inverters 12, 22, and 32 sequentially invert the output signals out+ and out- of the subsequent stages to a high or low level, completing a circuit of the loops L1 and L2. This confirms the high or low level states of all outputs, stopping oscillation and achieving the initial reset state.

[0042] At this time, the H / L states of all output signals out+ and out- can be determined and oscillation can be stopped without causing an HH collision in which both the inputs and outputs of the first inverters 11, 21, and 31 and the second inverters 12, 22, and 32 are H. Note that Fig. 5 shows the steady state of the final H / L levels of the first output A1 to the third output A3 and the first output B1 to the third output B3 in the initial reset state.

[0043] It should be noted here that in loop L1, oscillation stops when the third output A3 of the third stage and the first output A1 of the first stage both go to L level, and in loop L2, oscillation stops when the first output B1 of the first stage and the second output B2 of the second stage both go to L level.

[0044] In the loop L1, both the input and output of the first inverter 11 that contribute to the first output A1 of the differential inverter cell circuit 10 are stopped in the L level state.

[0045] On the other hand, MOSFET_M3n is designed with an element size that allows it to be pulled down to the L level sufficiently even when a supply current Idd having an upper limit is used. That is, at a Vdd-Idd operating point that satisfies the condition that the overall supply current Idd is at its upper limit, the current drive capability of MOSFET_M3n that constitutes the latch 13 is set higher than the current drive capability of MOSFET_M1p of the first inverter 11. For this reason, while maintaining a state in which a shunt current of the supply current Idd continues to flow as a static current through MOSFET_M1p of the first inverter 11 and the pull-down MOSFET_M4na, it is possible to fix the input of the first inverter 11 to the L level and the first output A1 to the L level.

[0046] In the loop L2, both the input and output of the second inverter 22 that contribute to the second output B2 of the differential inverter cell circuit 20 are stopped at the L level.

[0047] On the other hand, MOSFET_M4n is designed with an element size that allows it to be pulled down to the L level even using a supply current Idd that has an upper limit. That is, at the operating point of Vdd-Idd, which satisfies the condition that the supply current Idd of the entire circuit is at its upper limit, the current drive capability of MOSFET_M4n constituting the latch 24 is set higher than the current drive capability of MOSFET_M2p. Therefore, while maintaining a state in which the shunt current of the supply current Idd continues to flow as a static current through MOSFET_M2p of the second inverter 22 and the pull-down MOSFET_M4n, the input of the second inverter 22 can be fixed at the L level and the second output B2 can be fixed at the L level. As a result, the H / L levels of all output signals out+ and out- in the loops L1 and L2 can be determined while stopping oscillation and entering an initial reset state.

[0048] The differential ring oscillator 1 stops oscillating in a state in which a shunt current of the upper limit supply current Idd continues to flow as a static current through the MOSFET_M1p of the first inverter 11 and the MOSFET_M3n of the latch 13 shown in Fig. 2. The differential ring oscillator 1 also stops oscillating in a state in which a shunt current of the upper limit supply current Idd continues to flow as a static current through the MOSFET_M2p of the second inverter 22 and the MOSFET_M4n of the latch 24 shown in Fig. 3. Therefore, even in the oscillation-stopped state, the MOSFETs_M1p and M2p are on-biased, and the differential ring oscillator 1 is in a standby state in which it can immediately start oscillating.

[0049] When the initial reset state is released and the oscillation operation is resumed, the control circuit 50 resets the gate-source voltage V applied to the MOSFET_M3n of the latch 13 and the MOSFET_M4n of the latch 24. ＧＳ At this time, the control circuit 50 stops outputting the reset signal and fixes the gates of the MOSFETs M3n and M4n to the L level.

[0050] When the control circuit 50 releases the reset state, the differential ring oscillator 1 starts oscillating. At this time, the power supply voltage Vdd is secured to be high enough to operate the CMOS inverter, so that oscillation can start immediately without causing a large fluctuation in the power supply voltage Vdd even after the reset state is released.

[0051] The H / L level fixed by using MOSFETs M3n and M4n during reset may fluctuate greatly due to leakage of the gate drive signal including charge injection when the reset is released. However, because the differential ring oscillator 1 has a differential configuration, fluctuations due to leakage of the gate drive signal can be minimized.

[0052] Since some of the internal outputs of the differential ring oscillator 1 are fixed to the L level and initially reset while maintaining the operating point of the supply current Idd-power supply voltage Vdd, fluctuations in the power supply voltage Vdd before and after the reset can be kept small, and the oscillator can start up immediately even when the reset is released and oscillation operation begins. Since the fluctuations in the power supply voltage VDD are small, it can be turned on quickly.

[0053] When the control circuit 50 stops outputting the reset signal, after the reset is released, the first output A1 is charged from the MOSFET_M3n of the first inverter 11 in the loop L1, and the first output A1 rises from the L level to the H level. In the loop L2, the second output B2 is charged from the MOSFET_M4n of the second inverter 22, and the second output B2 rises from the L level to the H level.

[0054] The speed at which the first output A1 rises to the H level is relatively fast. This is because in the initial reset state, the third output A3 is at the L level, the first output B1 of the loop L2 is also at the L level, and furthermore, after the reset is released, the cross-coupled latch 15 drives the first output A1 to the H level side. Therefore, by combining these driving capabilities, the first output A1 can be raised to the H level, and the speed at which the first output A1 rises to the H level is relatively fast.

[0055] On the other hand, the speed at which the second output B2 rises to the H level is relatively slow. This is because, in the initial reset state, the first output B1 is at the L level but the second output A2 is at the H level. After the reset is released, the cross-coupled latch 25 operates to maintain the second output B2 at the L level. Therefore, the speed at which the second output B2 rises to the H level after the reset is released is relatively slow. As a result, after the reset is released, the speed at which the first output A1 of the loop L1 rises to the H level is faster than the speed at which the second output B2 of the loop L2 rises to the H level, and the first output A1 rises the fastest.

[0056] At the time of initial reset, the first output A1 of the first inverter 11 and the first output B1 of the second inverter 12 are both at L level, and only these outputs are not in an H / L inverted output pair state. However, after reset is released, the first output A1 rises from L level to H level first, and as a result, the first output A1 and the first output B1 become differential pair outputs in which the first output A1 and the first output B1 are inverted to H / L level. Thereafter, the output pairs of all the first inverters 11, 21, 31 and the second inverters 12, 22, 32 are in an H / L inverted state.

[0057] At the initial start, the first output A1 inverts from L to H level, while the second output B2 inverts from L to H level. Subsequently, in response to the inversion of the first output A1, the second output A2 inverts from H to L level. After that, the differential outputs of the third output A3 and the third output B3 are sequentially inverted to H / L level, thereby starting the ring oscillation operation of the differential pair. In this way, after reset is released, the differential ring oscillator 1 starts oscillating in a uniquely predetermined order. The differential ring oscillator 1 can improve robustness against power supply fluctuations and common-mode noise.

[0058] <Modifications> In the differential inverter cell circuits 10, 20, and 30 shown in FIG. 1, cross-coupled latches 15, 25, and 35 are generally provided between the differential outputs of a pair of first inverter 11 and second inverter 12, but they do not necessarily have to be provided in all stages and may be omitted in some stages.

[0059] In the above description, other pull-down or pull-up MOSFETs that do not contribute to the reset operation are left open as dummy MOSFETs, but these dummy MOSFETs are not necessarily required.

[0060] For example, the MOSFET_M4n constituting the latch 14 shown in Fig. 2 may be omitted. The MOSFET_M3na constituting the latch 23 shown in Fig. 3 may be omitted. The MOSFET_M3n and M4na constituting the latches 33 and 34 shown in Fig. 4 may be omitted.

[0061] When a pull-down or pull-up MOSFET (symbol omitted) is added to the latch (symbol omitted) of one output of the differential first inverters 11, 21, 31 and second inverters 12, 22, 32, it is advisable to balance the circuit and semiconductor layout structure by adding a pull-down or pull-up MOSFET (symbol omitted) to the other inverter as well, which makes it possible to achieve circuit matching taking into account parasitic capacitance, etc.

[0062] However, it is desirable to complete the reset operation in a shorter time in order to increase the circuit operating speed even with the limited supply current Idd and quickly determine the H / L levels of the overall output signals out+ and out- of the loops L1 and L2. For this reason, it is advisable to forcibly set the digital level of each node to a fixed level using at least one of the aforementioned target MOSFETs M4n, M3n, M4na, and M3na.

[0063] For example, in order to pull up the second output A2 of the first inverter 21 in the output stage next to the first output A1 to the H level, it is advisable to add a MOSFET_M3na to the latch 23. Also, it is advisable to add a MOSFET_M3n to the latch 33 for pulling down to the L level and a MOSFET_M4na to the latch 34 for pulling up to the H level to the subsequent output stages in sequence. By fixing all the nodes inside the loops L1 and L2 to the initial reset value simultaneously, the entire circuit can be immediately put into the initial reset state.

[0064] 2, when the control circuit 50 pulls down the first output A1 of the first inverter 11 by the MOSFET_M3n of the latch 13, it is preferable that the control circuit 50 pulls down the first output B1 of the second inverter 12 by the MOSFET_M4n (corresponding to the second switch) of the latch 14. This makes it possible to increase the number of nodes that are controlled to a fixed level at one time during initial reset, thereby improving the stability and immediacy of oscillation stop.

[0065] Furthermore, the control circuit 50 may pull up the second output A2 of the first inverter 21 to the H level in the first loop L1 by the MOSFET_M3na (corresponding to the third switch) of the latch 23, and may also pull up the third output B3 of the second inverter 32 to the H level in the second loop L2 by the MOSFET_M4na (corresponding to the fourth switch) of the latch 34. Furthermore, it is possible to increase the number of nodes that are controlled to a fixed level at one time during reset, thereby improving the stability and immediacy of oscillation stop.

[0066] The control circuit 50 may be configured such that, when the second output A2 of the first inverter 21 in the first loop L1 is pulled up to the H level by the MOSFET_M3na (corresponding to the fifth switch) of the latch 23, the third output A3 of the first inverter 31 is pulled down to the L level by the MOSFET_M3n (corresponding to the sixth switch) of the latch 33. Furthermore, it is possible to increase the number of nodes that are controlled to a fixed level at one time during reset, thereby improving the stability and immediacy of oscillation halt.

[0067] By implementing all of these individual specific examples, the initial reset can be speeded up and the balance of the differential circuit can be improved.

[0068] <Comparative Example> As described in the Background Art section, various methods have been proposed for determining the outputs of each part of the differential ring oscillator 1. However, when adding an initial reset function to the differential ring oscillator 1, there was a problem when attempting to perform initial reset in a differential pair state in which all differential output pairs are inverted between H and L.

[0069] For example, consider the case where the output of the first inverter constituting the ring oscillator is pulled up to H level and reset to initial state. After the first inverter transitions to H level, the inverters in the following stages successively invert their outputs H / L to complete one loop, and the input of the first inverter goes H level, resulting in an "HH collision" where both the input and output of the first inverter are H level. In this case, the supply current Idd is concentrated on the switch that pulls up to H level and the output transistor of the inverter, and the power supply voltage Vdd is reduced by the gate-source voltage V of the output transistor of the inverter. ＧＳ As the supply current Idd decreases, the power supply voltage Vdd decreases to the element threshold voltage V ｔｎ As a result, the static current of the ring oscillator becomes zero at reset, causing a delay in restarting oscillation.

[0070] When the parasitic capacitance is charged using the supply current Idd after reset is released, the power supply voltage Vdd rises and the circuit starts operating, but operation is not stable until the power supply voltage Vdd rises, resulting in slow startup. Furthermore, if the power supply voltage Vdd changes during startup, the H / L state established at the time of initial reset may fluctuate depending on element variations and parasitic capacitance, making startup operation prone to instability. Therefore, immediately after oscillation begins after reset is released, operation becomes unstable until the operating point of power supply voltage Vdd - supply current Idd stabilizes.

[0071] <Summary of this embodiment> According to this embodiment, the differential ring oscillator 1 is set to an initial reset state by pulling down the first output A1 of a first inverter 11 in the first loop L1 to L level and pulling down the second output B2 of the second inverter 22 in the second loop L2, which forms a differential pair with the first inverter 21 in the next stage, to L level.

[0072] According to this embodiment, even in the initial reset state, a static current flows through the first inverter 11 and the second inverter 22, so that oscillation can be started quickly after the reset is released, and the operating point of the supply current Idd-power supply voltage Vdd can be determined quickly, thereby improving the stability of operation. Although the embodiment has been described in which the first inverters 11, 21, 31 and the second inverters 12, 22, 32 are configured in three stages, similar effects can be achieved by configuring them in an odd number of stages, five or more.

[0073] The differential inverter cell circuit 10 includes a MOSFET_M3n of a latch 13 for pulling down the first output A1 of the first inverter 11, and also includes a MOSFET_M4na connected to the MOSFET_M3n in a differential pair. This makes it possible to maintain a good balance between the differential circuit and its semiconductor layout structure, even if the MOSFET_M3n is not provided for initial resetting, and improves operational stability against power supply voltage fluctuations and common-mode noise.

[0074] Second Embodiment A second embodiment will be described with reference to Figures 6 to 8. The second embodiment differs from the first embodiment in that the differential inverter cell circuits 10, 20, 30, and 40 are configured in an even number of stages. Therefore, the same parts are denoted by the same reference numerals and their description will be omitted, and the description will focus on the different parts.

[0075] 6, a differential ring oscillator 201, which replaces the differential ring oscillator 1, is configured by connecting n (n is an even number) differential inverter cell circuits 10, 20, 30, and 40 in a ring shape. The configuration of the differential inverter cell circuits 10, 20, and 30 is the same as that of the above-described embodiment, and therefore a description thereof will be omitted.

[0076] 6 and 7, the differential inverter cell circuit 40 is configured with a pair of a first inverter 41 and a second inverter 42, and a cross-coupled latch 45 made up of latches 43 and 44 connected in opposite directions between the outputs of the first inverter 41 and the second inverter 42 as an opposite connection circuit. The differential inverter cell circuit 40 is configured as a differential pair in which the pair of inverters 41 and 42 inverts H / L with respect to each other.

[0077] In this case, in order to maintain differential pair operation even if there is a mismatch in characteristics between the two inverters 41 and 42 that make up the pair, a cross-coupled latch 45 is provided as an opposing connection circuit, in which latches 43 and 44 are arranged opposite each other in both directions between the outputs. Note that a circuit element that has the same function as the cross-coupled latch 45 and is equivalent to the cross-coupled latch 25 may also be provided as the opposing connection circuit.

[0078] 6, the differential ring oscillator 201 includes circuits in a first loop L1a and a second loop L2a. The first loop L1a includes an even number (four in this example) of first inverters 11, 21, 31, and 41 cascade-connected with their outputs cross-connected to the input of the second loop L2a. The second loop L2a includes second inverters 12, 22, 32, and 42 cascade-connected to form differential pairs with the first inverters 11, 21, 31, and 41 and their outputs cross-connected to the input of the first loop L1a.

[0079] The cross-coupled latches 15, 25, 35, and 45 are connected in opposing relation between the multiple outputs A1, A2, A3, and A4 of the first inverters 11, 21, 31, and 41 and the multiple outputs B1, B2, B3, and B4 of the second inverters 12, 22, 32, and 42, respectively. A control circuit 50 is also connected to the differential ring oscillator 201. The control circuit 50 is configured, for example, by a hardware control logic circuit, and is capable of outputting a reset signal at an H level or an L level to forcibly place the differential ring oscillator 1 in an initial reset state. This provides an initial reset function that determines the outputs of the differential inverter cell circuits 10, 20, 30, and 40.

[0080] The differential inverter cell circuits 10, 20, and 30 have the same configuration as that shown in the first embodiment. The differential inverter cell circuit 40 shown in FIG. 7 differs from the differential inverter cell circuit 10 in the latch 43. The even-numbered differential inverter cell circuits 40 have the same configuration as the differential inverter cell circuit 20.

[0081] The differential inverter cell circuit 40 includes a first inverter 41, a second inverter 42, and latches 43 and 44. The configuration of the latch 43 corresponds to the configuration of the latch 13, and includes a p-channel MOSFET_M3p and an n-channel MOSFET_M3na. The gate of the MOSFET_M3p is connected to the second intermediate node N4, the source is connected to the supply node of the power supply voltage Vdd, and the drain is connected to the first intermediate node N3.

[0082] MOSFET_M3na has a gate connected to the control circuit 50, a drain connected to the supply node of the power supply voltage Vdd, and a source connected to the first intermediate node N3. As a result, when MOSFET_M3na is turned on by the control circuit 50, the first intermediate node N3 can be pulled up to the H level. The configurations of the other components, the first inverter 41, the second inverter 42, and the latch 44, are similar to those of the first inverter 11, the second inverter 12, and the latch 14 of the differential inverter cell circuit 10, respectively, and therefore will not be described here.

[0083] The operation of the initial reset is generally similar to that of the first embodiment. First, the control circuit 50 pulls down the first output A1 of a certain first inverter (here, for example, 11) in the first loop L1a to the L level. At the same time, the control circuit 50 pulls down the second output B2 of the second inverter 22 in the second loop L2, which forms a differential pair with the first inverter 21 in the next stage of the first inverter 11, to the L level, thereby achieving the initial reset state. This allows the initial reset state to be achieved in the same manner as in the operation of the first embodiment.

[0084] When the differential inverter cell circuits 10, 20, 30, and 40 are cross-connected in four stages, the H / L levels of the first output A1 to the fourth output A4 and the first output B1 to the fourth output B4 can be determined and oscillation can be stopped, as shown in Fig. 8. As shown in Fig. 8, the digital levels of the first output A1 to the third output A3 and the first output B1 to the third output B3 are fixed to the same levels as those shown in Fig. 5 of the first embodiment. Also, as shown in Fig. 8, the fourth output A4 is fixed to the H level, and the fourth output B4 is fixed to the L level.

[0085] 7 may be omitted or provided as a dummy. However, in order to maintain a good balance in the differential circuit, to increase the circuit operating speed even with a limited supply current Idd, and to quickly determine the H / L levels of the overall output signals out+, out- of the loops L1, L2, it is preferable to provide MOSFET_M3na of the latch 43 to pull it up to the H level, or to provide MOSFET_M4n of the latch 44 to pull it down to the L level.

[0086] To explain a specific example, when the control circuit 50 pulls up the third output B3 of the second inverter 32 in the second loop L2a to the H level, it is preferable that the control circuit 50 pulls down the fourth output B4 of the second inverter 42 to the L level using the MOSFET_M4n (corresponding to the seventh switch) of the latch 44. Furthermore, when the control circuit 50 pulls down the third output A3 of the first inverter 31 in the first loop L1a to the L level, it is preferable that the control circuit 50 pulls up the fourth output A4 of the first inverter 41 to the H level using the MOSFET_M3na of the latch 43. This makes it possible to increase the number of nodes that are controlled to a fixed level at one time during initial reset, thereby improving the stability and immediacy of oscillation stop.

[0087] According to this embodiment, the first output A1 of the first inverter 11 is pulled down to the L level, and the second output B2 of the second inverter 22, which forms a differential pair with the first inverter 21, is pulled down to the L level, thereby causing a static current to flow through the first inverter 11 and the second inverter 22, thereby setting them to an initial reset state. This provides the same effects as the first embodiment.

[0088] As shown in this embodiment, the polarity can be inverted from the output to the input of the loops L1a and L2a, making the connection applicable to a four-stage inverter configuration. The same applies to an even number of inverter stages, such as six or more stages. Alternatively, the polarity can be inverted midway through the loops L1a and L2a.

[0089] (Other Embodiments) The present disclosure is not limited to the above-described embodiments and can be modified or expanded, for example, as follows. Although the embodiments have been described in which three- and four-stage differential inverter cell circuits 10, 20, 30, and 40 are provided, the present disclosure may be applied to a configuration in which five or more stages of differential inverter cell circuits are provided as long as loops L1, L2, L1a, and L2a are formed. For example, when four or more even-numbered or odd-numbered stages of differential inverter cell circuits are provided, the third or higher odd-numbered stage differential inverter cell circuits may have the same configuration as the differential inverter cell circuit 30. Furthermore, the even-numbered stage differential inverter cell circuits may have the same configuration as the differential inverter cell circuits 20 and 40. The present disclosure may also be applied to a two-stage ring oscillator. When MOSFETs M3n, M3na, M4, and M4na are not used for pull-up or pull-down, the gates of MOSFETs M3n, M3na, M4, and M4na may be connected to ground GND.

[0090] In the above-described embodiment, various types of MOSFETs are used as switches. For example, MOSFETs M3n, M3na, M4, and M4na are used as switches that pull down to an L level and switches that pull up to an H level. However, the present invention is not limited to this, and other types of switches, such as semiconductor switches such as bipolar junction transistors, may also be used.

[0091] The present disclosure includes the following in addition to the contents of the claims: [1] A differential ring oscillator comprising: a loop (L1, L2; L1a, L2a) in which a plurality of n first inverters and the n second inverters are configured to form differential pairs and configured with positive feedback; and opposing connection circuits (15, 25, 35; 15, 25, 35, 45) respectively connected in opposing relation between a plurality of outputs of the n first inverters and a plurality of outputs of the n second inverters, wherein, when controlled by a control circuit (50), a first output (A1) of one of the first inverters in the loop is pulled down to an L level, and a second output (B2) of the second inverter that forms a differential pair with the first inverter in a stage subsequent to the first output (A1) of the first inverter is pulled down to an L level, thereby setting the oscillator to an initial reset state.

[0092] [2] The differential ring oscillator of [1], wherein the opposing connection circuit includes a first switch (M3n of 13) that pulls down the first output (A1) of the first inverter, and a second switch (M4n of 14) that is differentially paired with the first switch.

[0093] [3] The differential ring oscillator of [2], wherein, when controlled by the control circuit, the first output (A1) of the first inverter is pulled down by the first switch (M3n of 13), the first output (B1) of the second inverter that is differentially paired with the first inverter is pulled down by the second switch (M4n of 14).

[0094] [4] The differential ring oscillator according to any one of [1] to [3], comprising a third switch (M3na of 23) and a fourth switch (M4n of 34), wherein, when controlled by the control circuit, the second output (A2) of the first inverter in the next stage of the first output (A1) of the first inverter is pulled up to H level by the third switch, and the third output (B3) of the second inverter in the next stage of the second output (B2) of the second inverter is pulled up to H level by the fourth switch.

[0095] [5] The differential ring oscillator according to any one of [1] to [4], comprising a fifth switch (M3na of 23) and a sixth switch (M3n of 33), wherein, when controlled by the control circuit, the second output (A2) of the first inverter in the next stage of the first output (A1) of the first inverter is pulled up to an H level by the fifth switch, and the third output (A3) of the first inverter in the next stage of the second output (A1) of the first inverter is pulled down to an L level by the sixth switch.

[0096] [6] A differential ring oscillator according to any one of [1] to [5], further comprising a seventh switch (M4n of 44), wherein, when controlled by the control circuit, the fourth output (B4) of the second inverter in the next stage to the third output of the second inverter is pulled down to the L level by the seventh switch when the third output (B3) of the second inverter is pulled up to the H level.

[0097] Although the present disclosure has been described based on the above-described embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including one, more, or less than one element, are also within the scope and spirit of the present disclosure.

Claims

1. A differential ring oscillator comprising: a loop (L1, L2; L1a, L2a) in which a plurality of n first inverters and the n second inverters are configured to form differential pairs and configured with positive feedback; and opposing connection circuits (15, 25, 35; 15, 25, 35, 45) respectively connected in opposing relation between the multiple outputs of the n first inverters and the multiple outputs of the n second inverters, wherein, when controlled by a control circuit (50), the first output (A1) of one of the first inverters in the loop is pulled down to L level, and the second output (B2) of the second inverter that forms a differential pair with the first inverter in the next stage of the first output (A1) of the first inverter is pulled down to L level, thereby setting the oscillator to an initial reset state.

2. A differential ring oscillator according to claim 1, wherein the opposing connection circuit comprises a first switch (M3n of 13) that pulls down the first output (A1) of the first inverter, and a second switch (M4n of 14) that is differentially paired with the first switch.

3. A differential ring oscillator as claimed in claim 2, wherein, when controlled by the control circuit, the first output (A1) of the first inverter is pulled down by the first switch (M3n of 13), the first output (B1) of the second inverter that forms a differential pair with the first inverter is pulled down by the second switch (M4n of 14).

4. A differential ring oscillator according to claim 1, comprising a third switch (M3na of 23) and a fourth switch (M4n of 34), wherein, when controlled by the control circuit, the second output (A2) of the first inverter in the next stage to the first output (A1) of the first inverter is pulled up to the H level by the third switch, and the third output (B3) of the second inverter in the next stage to the second output (B2) of the second inverter is pulled up to the H level by the fourth switch.

5. A differential ring oscillator according to claim 4, comprising a fifth switch (M3na of 23) and a sixth switch (M3n of 33), wherein, when controlled by the control circuit, the third output (A3) of the first inverter in the next stage to the second output (A1) of the first inverter is pulled up to the L level by the sixth switch when the second output (A2) of the first inverter in the next stage to the first output (A1) of the first inverter is pulled up to the H level by the fifth switch.

6. A differential ring oscillator according to claim 4, further comprising a seventh switch (M4n of 44), wherein, when controlled by the control circuit, the fourth output (B4) of the second inverter in the stage following the third output of the second inverter is pulled down to the L level by the seventh switch when the third output (B3) of the second inverter is pulled up to the H level.

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