Preparation method for stacked transistor, stacked transistor, and semiconductor device

Abstract

The present disclosure provides a preparation method for a stacked transistor, a stacked transistor, and a semiconductor device. The preparation method comprises: on a semiconductor substrate, forming a first sacrificial layer, and active structures located on the first sacrificial layer, the active structures comprising a first active structure and a second active structure; depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure, the shallow trench isolation structure wrapping around the second active structure and the first sacrificial layer, and the first active structure being exposed out of the shallow trench isolation structure; forming a first transistor on the basis of the first active structure; inverting the entire structure and removing the semiconductor substrate, to expose the shallow trench isolation structure and the first sacrificial layer; removing the first sacrificial layer, and forming a hard mask structure at the position of the removed first sacrificial layer; using the hard mask structure as a hard mask, thinning the shallow trench isolation structure, so that the second active structure is exposed out of the shallow trench isolation structure; and, after removing the hard mask structure, forming a second transistor on the basis of the second active structure.

Description

Method for manufacturing stacked transistors, stacked transistors and semiconductor device

[0001] Cross-reference to Related Applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202410609235.4, filed on May 16, 2024, the entire contents of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of semiconductor technology, and particularly relates to a method for manufacturing stacked transistors, stacked transistors and semiconductor devices. BACKGROUND

[0004] At present, it is a hot issue in the industry to continue to promote the miniaturization of transistors in the context of Moore's Law. Stacked transistors, which integrate two or more layers of transistors in the vertical space, can further improve the integration density of transistors and become one of the important technologies to continue the miniaturization of integrated circuits.

[0005] In some schemes for manufacturing stacked transistors, the active regions of two layers of homologous transistors are formed by etching, and the stacked transistors are manufactured on the front and back surfaces of the wafer by peeling. This can also be referred to as a "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, the exposure of the upper active region needs to be completed by etching a shallow trench isolation structure after peeling. In the etching process, the upper active region is often damaged, causing differences in device performance, so the process scheme needs to be optimized to ensure device performance.

[0006] SUMMARY

[0007] The present disclosure provides a method for manufacturing stacked transistors, stacked transistors and semiconductor devices.

[0008] The first aspect of the present disclosure provides a method for manufacturing a stacked transistor. The method comprises: forming a first sacrificial layer and an active structure on a semiconductor substrate; wherein the active structure comprises: a first active structure and a second active structure; the first active structure and the second active structure are stacked along a first direction, and the first active structure is farther away from the first sacrificial layer than the second active structure; depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the second active structure and the first sacrificial layer, and the first active structure is exposed outside the shallow trench isolation structure; forming a first transistor based on the first active structure; developing and removing the semiconductor substrate to expose the shallow trench isolation structure and the first sacrificial layer; removing the first sacrificial layer and forming a hard mask structure at the position of the removed first sacrificial layer; thinning the shallow trench isolation structure with the hard mask structure as a hard mask to expose the second active structure outside the shallow trench isolation structure; and forming a second transistor based on the second active structure after removing the hard mask structure.

[0009] The second aspect of the present disclosure provides a stacked transistor. The stacked transistor is manufactured by the method of the first aspect or any possible implementation of the first aspect. The stacked transistor comprises: a first transistor; a second transistor stacked along a first direction with the first transistor; an active structure comprising a first active structure of the first transistor and a second active structure of the second transistor; and a first gate structure of the first transistor and a second gate structure of the second transistor arranged oppositely.

[0010] The third aspect of the present disclosure provides a semiconductor device comprising the stacked transistor of the second aspect.

[0011] Compared with the prior art, the present disclosure has the following beneficial effects:

[0012] In the present disclosure, by forming a first sacrificial layer and an active structure with a certain depth on a semiconductor substrate, the active regions of the upper and lower transistors are self-aligned. Then, a first transistor is manufactured based on a first active structure in the active structure, and after developing, the semiconductor substrate is etched to expose the first sacrificial layer, so that the first sacrificial layer is conveniently removed and a hard mask structure is formed by filling a hard mask material; then, in the process of thinning the shallow trench isolation structure, the hard mask structure is used to protect the lower half of the active region, so that an undamaged second active structure is obtained. Finally, a second transistor is manufactured based on the undamaged second active structure, so that the performance of the second transistor is improved.

[0013] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, but not limiting the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the embodiments of the present disclosure together with the description given hereinafter.

[0015] FIG. 1 is a top view of a stacked transistor according to embodiments of the present disclosure.

[0016] FIGS. 2-3 are schematic diagrams of a fabrication process of a stacked transistor according to embodiments of the present disclosure.

[0017] FIG. 4 is an implementation flowchart of a fabrication method of a stacked transistor according to embodiments of the present disclosure.

[0018] FIGS. 5-18 are schematic diagrams of a fabrication process of a stacked transistor according to embodiments of the present disclosure.

[0019] FIGS. 19-28 are schematic diagrams of a fabrication process of a stacked transistor according to embodiments of the present disclosure.

[0020] FIGS. 29-30 are schematic diagrams of a fabrication process of a stacked transistor according to embodiments of the present disclosure.

[0021] FIG. 31 is a schematic diagram of a stacked transistor according to embodiments of the present disclosure.

[0022] FIG. 32 is a schematic diagram of a stacked transistor according to embodiments of the present disclosure.

[0023] BRIEF DESCRIPTION OF DRAWINGS stacked transistor 10; first transistor 11; second transistor 12; first dummy gate sidewall 111; first source-drain structure 112; first interlayer dielectric layer 113; first gate structure 114; first source-drain metal 115; first metal interconnection layer 116; second dummy gate sidewall 121; second source-drain structure 122; second interlayer dielectric layer 123; second gate structure 124; second source-drain metal 125; second metal interconnection layer 126; semiconductor substrate 20; first sacrificial layer 21; active structure 22; first active structure 221; second active structure 222; first material layer 23; second material layer 24; initial shallow trench isolation structure 25; shallow trench isolation structure 26; hard mask structure 27; insulating layer 28; carrier wafer 29; recess 30; first hard mask 31; third hard mask 32; buried oxide layer 33; intermediate dielectric isolation layer 34. DETAILED DESCRIPTION

[0024] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The following description is made with reference to the accompanying drawings in which like reference numerals refer to like elements, and the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." The following description is not intended to limit the scope of the present disclosure, but is merely intended to describe the ways in which the exemplary embodiments can be put into practice. Examples of apparatuses and methods consistent with the present disclosure are described below.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0026] In the context of Moore's Law, the continued scaling of transistor size is a hot topic in the industry. Stacked transistors, which integrate two or more layers of transistors in the vertical space through three-dimensional transistor stacking, can help further improve transistor integration density and circuit performance, and is considered one of the important technologies for continuing the scaling of integrated circuits.

[0027] In an embodiment, there are two schemes for the preparation process of stacked transistors, the first being monolithic and the second being sequential.

[0028] The sequential scheme is based on wafer bonding and is processed layer by layer, but thanks to wafer bonding, the device structures, channel crystal orientations, and even channel materials used by the upper and lower transistors can be optimized accordingly to achieve better and more matched device performance. The sequential stacked transistor process faces major challenges, including: (1) the preparation of high-quality upper transistor active layers; (2) the thinning and defect control of the upper bonded wafer; and (3) the alignment error between the upper and lower transistors, which requires extremely high photolithography precision.

[0029] In monolithic stacked transistor technology, wafer bonding technology is not used, but N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) are fabricated on the same substrate, which also determines that the same layer transistors must be of the same type, i.e. NFET or PFET. Moreover, the upper and lower layer transistors are strictly in the same plane space, and there is no alignment deviation. It is obvious that the advantage of monolithic stacked transistors is higher integration density. But its disadvantages are also obvious: (1) complex process, a large amount of process technology development and optimization are needed; (2) the polarity of each layer transistor is fixed, and the basic CMOS circuit must rely on two layers of transistors, and the design flexibility is poor.

[0030] In order to solve the technical problems existing in the above two schemes, a "self-aligned flip transistor" scheme is proposed. The "self-aligned flip transistor" scheme forms the active area of the upper and lower layer homologous transistors by etching, and realizes the fabrication of stacked transistors on the front and back surfaces of the wafer by flipping, so as to overcome the disadvantages of the above two schemes. However, the preparation process of the self-aligned flip transistor still has optimization space to further improve the performance of the stacked transistor.

[0031] In some embodiments, the present disclosure provides a stacked transistor. FIG. 1 is a top view of a stacked transistor according to an embodiment of the present disclosure. Referring to FIG. 1, only the fin structure, gate structure and source-drain structure of the stacked transistor 10 are shown in the top view. It can be understood that the fin structure can also be a columnar structure or a block structure based on the type of the stacked transistor, which is not limited in the embodiments of the present disclosure.

[0032] In some embodiments, FIG. 2 to FIG. 3 are schematic diagrams of a preparation process of a stacked transistor according to an embodiment of the present disclosure. For ease of understanding, (a) in FIG. 2 to FIG. 3 shows a cross-sectional view along the direction of the dashed line A-A' in FIG. 1, (b) in FIG. 2 to FIG. 3 shows a cross-sectional view along the direction of the dashed line B-B' in FIG. 1, and (c) in FIG. 2 to FIG. 3 shows a cross-sectional view along the direction of the dashed line C-C' in FIG. 1. Referring to FIG. 2 to FIG. 3, after the self-aligned flip transistor is flipped, the substrate structure can be removed to expose the second active structure 222 and the shallow trench isolation structure 26. The height of the second active structure 222 is h1. Then, the exposure of the second active structure 222 needs to be completed by etching the shallow trench isolation structure. In the etching process, the second active structure 222 is often damaged by etching, so that the height of the second active structure 222 changes to h2. In an example, h2 is less than h1. It can be seen that the current process damages the second active structure 222, causing a difference between the actual performance of the device and the designed performance of the device, and thus the process scheme needs to be optimized to ensure the performance of the device.

[0033] To solve the above technical problems, an embodiment of the present disclosure provides a preparation method of a stacked transistor to optimize the process of exposing the upper active region of the stacked transistor and improve the performance of the upper transistor.

[0034] In some embodiments, an embodiment of the present disclosure provides a preparation method of a stacked transistor. FIG. 4 is an implementation flowchart of a preparation method of a stacked transistor according to an embodiment of the present disclosure. Referring to FIG. 4, the preparation method of the stacked transistor can include steps S401 to S407.

[0035] Step S401: forming a first sacrificial layer and an active structure above the first sacrificial layer on a semiconductor substrate; wherein the active structure includes: a first active structure and a second active structure; the first active structure and the second active structure are stacked along a first direction, and the first active structure is farther away from the first sacrificial layer than the second active structure;

[0036] Step S402: depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the second active structure and the first sacrificial layer, and the first active structure is exposed outside the shallow trench isolation structure;

[0037] Step S403: forming a first transistor based on the first active structure;

[0038] Step S404: flipping and removing the semiconductor substrate to expose the shallow trench isolation structure and the first sacrificial layer;

[0039] Step S405: removing the first sacrificial layer, and forming a hard mask structure at the position of the removed first sacrificial layer;

[0040] Step S406: thinning the shallow trench isolation structure with the hard mask structure as a hard mask, so as to expose the second active structure outside the shallow trench isolation structure.

[0041] Step S407: after removing the hard mask structure, forming a second transistor based on the second active structure.

[0042] It should be noted that the steps shown in FIG. 4 are not exclusive, and other steps can be performed before, after or between any of the steps shown; the order of the steps shown in FIG. 4 can be adjusted according to actual needs.

[0043] It can be understood that by forming the hard mask structure on top of the second active structure after the film is reversed, protection of the second active structure can be provided. In this way, when the process of thinning the shallow trench isolation structure is started, the second active structure will not be damaged, thereby ensuring the performance of the second transistor.

[0044] In some embodiments, FIGS. 5-18 are schematic diagrams of a preparation process of a stacked transistor according to embodiments of the present disclosure, for ease of understanding, (a) in FIGS. 5-18 shows a cross-sectional view along the direction of dashed line A-A' in FIG. 1, (b) in FIGS. 5-18 shows a cross-sectional view along the direction of dashed line B-B' in FIG. 1, and (c) in FIGS. 5-18 shows a cross-sectional view along the direction of dashed line C-C' in FIG. 1; the preparation method of a stacked transistor and the stacked transistor prepared according to embodiments of the present disclosure will be exemplarily described below with reference to FIGS. 1-18.

[0045] In step S401, a first sacrificial layer 21 and an active structure 22 located above the first sacrificial layer 21 are formed on a semiconductor substrate 20.

[0046] It can be understood that the processes of material layer deposition, epitaxial growth, photolithography, etc. can be performed on the semiconductor substrate 20 to form the first sacrificial layer 21 and the active structure 22 located above the first sacrificial layer 21 on the semiconductor substrate 20.

[0047] In an embodiment, the active structure 22 includes a first active structure 221 and a second active structure 222. The first active structure 221 and the second active structure 222 are stacked along a first direction (a direction perpendicular to the semiconductor substrate 20), and the first active structure 221 is farther away from the first sacrificial layer 21 than the second active structure 222.

[0048] It can be understood that the first active structure 221 is used to form an active region of the first transistor 11 (located at the lower layer) of the stacked transistor 10; and the second active structure 222 stacked with the first active structure 221 along the first direction is used to form an active region of the second transistor 12 (located at the upper layer) of the stacked transistor 10.

[0049] It should be noted that the first sacrificial layer 21 is located at the bottom of the active structure 22, and after the development, the first sacrificial layer 21 can be located at the top of the active structure 22.

[0050] In an embodiment, the step of forming the first sacrificial layer 21 and the active structure 22 located above the first sacrificial layer 21 on the semiconductor substrate 20 in step S401 comprises: forming a first material layer 23 and a second material layer 24 on the semiconductor substrate 20; the first material layer 23 is away from the semiconductor substrate 20 relative to the second material layer 24. Then, using the same etching process, the first material layer 23 is etched to form an initial active structure, and the second material layer 24 is etched to form an initial first sacrificial layer. Then, using a fin cutting process, the initial active structure located in the two side regions of the stacked transistor 10 is removed to form the active structure 22, and the initial first sacrificial layer located in the two side regions of the stacked transistor 10 is removed to form the first sacrificial layer 21.

[0051] In an embodiment, the two side regions of the stacked transistor 10 refer to the regions located at the two sides of the stacked transistor along the second direction (the extension direction or the length direction of the fin structure).

[0052] It can be understood that, by forming the material layers required for the active structure 22 and the first sacrificial layer 21 on the semiconductor substrate 20, and etching the material layers using the standard process of semiconductor preparation, an initial active structure (which can be a fin structure, a column structure or a block structure) and an initial first sacrificial layer can be formed. Then, a fin cutting process is performed to cut off the active structure located between two adjacent transistors, so as to isolate the active regions of the adjacent transistor units. And, the active structure 22 and the first sacrificial layer 21 required for subsequent preparation processes are obtained.

[0053] It can be understood that, when the active structure 22 (including the first active structure 221 and the second active structure 222) and the first sacrificial layer 21 are formed by photolithography, a larger etching depth can be used. For example, the height of the active structure 22 obtained by etching can be greater than 100 nm. It should be noted that the height of the active structure 22 can be set according to actual conditions, and the embodiments of the present disclosure do not limit this.

[0054] In an embodiment, the steps of the photolithography process can include: depositing a photoresist material, exposing and developing the photoresist material, removing a part of the photoresist material, etching to remove the material layer corresponding to the part of the photoresist material, etc.

[0055] In an embodiment, the shape of the active structure 22 can be different when the type of the stacked transistor 10 is different.

[0056] In some possible implementation manners, the first material layer 23 away from the semiconductor substrate 20 is used to form the active structure 22. Based on the structural composition of different types of active structures 22, it can be known that the first material layer 23 is a single-layer structure formed by deposition of a first material; or the first material layer 23 is a stacked structure formed by stacking of at least two material layers.

[0057] In an embodiment, the stacking direction of the stacked structure is the first direction.

[0058] It can be understood that when the type of the stacked transistor 10 is different, the structural composition of the active structure 22 in the transistor is different, so that the structure of the first material layer 23 used to form the active structure 22 can also be different.

[0059] In an embodiment, when the stacked transistor 10 is a fin field effect transistor, the active structure 22 can constitute a fin structure. When the stacked transistor 10 is a planar transistor, the active structure 22 can constitute a bulk structure. In an embodiment, the fin structure and the bulk structure can be a single-layer structure formed by deposition of a first material, or a stacked structure formed by stacking of at least two material layers.

[0060] In an embodiment, when the stacked transistor 10 is a gate-all-around nanosheet (GAA Nanosheet) transistor, the active structure 22 can constitute a columnar structure. In an embodiment, the columnar structure can be a stacked structure formed by stacking of at least two material layers. For example, the first active structure 221 and the second active structure 222 can be formed by alternately deposited silicon layers and silicon germanium layers.

[0061] It should be noted that the structure of the first material layer 23 is designed according to the structure of the first active structure 221 and the second active structure 222, and the structure of the first active structure 221 and the second active structure 222 can be set according to actual requirements of the stacked transistor 10, which is not limited in the embodiments of the present disclosure.

[0062] In some embodiments, the first transistor 11 and the second transistor 12 can be transistors of the same type. For example, the first transistor 11 and the second transistor 12 can both be fin field effect transistors.

[0063] In some embodiments, the first transistor 11 and the second transistor 12 can be different types of transistors. For example, one is a fin field effect transistor and the other is a gate-all-around transistor; or, one is a fin field effect transistor and the other is a planar transistor; or, one is a gate-all-around transistor and the other is a planar transistor.

[0064] In some embodiments, when the first material layer 23 is a single layer structure formed by deposition of the first material, the first active structure 221 and the second active structure 222 are formed of the same material. For example, the first active structure 221 and the second active structure 222 are formed of silicon. In this case, in order to prevent a conductive current path from being formed between the active regions of the first transistor 11 and the second transistor 12, the first active structure 221 and the second active structure 222 need to be electrically isolated.

[0065] In an embodiment, the process of isolating the first active structure 221 and the second active structure 222 can be set according to actual needs, and the present disclosure does not limit this.

[0066] In an embodiment, the first active structure 221 and the second active structure 222 can be electrically isolated by ion implantation at the junction of the first active structure 221 and the second active structure 222. The ions for ion implantation include P-type ions, N-type ions, or oxygen ions. The P-type ions include one or more of boron ions, gallium ions, and indium ions; and the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

[0067] In some possible implementations, the second material layer 24 close to the semiconductor substrate 20 is used to form the first sacrificial layer 21. The second material layer 24 can be a single layer structure formed by deposition of the second material.

[0068] It can be understood that the first sacrificial layer 21 can be a single layer structure formed by deposition of the second material. Then, only the etching process of one type of material (i.e., the second material) needs to be considered to remove the first sacrificial layer 21, thereby reducing the process difficulty.

[0069] For example, the second material layer 24 can be a single layer structure formed of silicon material; or, the second material layer 24 can be a single layer structure formed of silicon germanium material.

[0070] In some possible embodiments, when the first material layer 23 and the second material layer 24 are both single-layer structures, the first material layer 23 is formed by deposition of a first material, and the second material layer 24 is formed by deposition of a second material. In an embodiment, the first material can be different from the second material, for example, the first material can be silicon, and the second material can be silicon germanium, so that the first sacrificial layer 21 formed by the silicon germanium is removed in a subsequent process by using the etching selectivity difference between silicon and silicon germanium. Alternatively, the first material can be the same as the second material, for example, the first material can be silicon, and the second material can also be silicon, so that the first sacrificial layer 21 formed by the silicon is removed in a subsequent process by controlling the etching time.

[0071] It can be understood that, when the first material and the second material are different, the second material layer 24 can be formed by depositing or epitaxially growing the second material on the semiconductor substrate 20, and then depositing or epitaxially growing the first material on the second material layer 24 to form the first material layer 23. Then, the second material layer 24 is etched to form the first sacrificial layer 21, and the first material layer 23 is etched to form the active structure 22 on the first sacrificial layer 21.

[0072] It can be understood that, when the first material and the second material are the same, the first material layer 23 and the second material layer 24 can be formed by depositing or epitaxially growing the first material on the semiconductor substrate 20 at the same time. Then, the first material layer 23 and the second material layer 24 are etched to form the first sacrificial layer 21 and the active structure 22 on the first sacrificial layer 21.

[0073] It should be noted that, in the embodiments of the present disclosure, a relatively deep etching depth can be directly used to etch the silicon wafer to form the first sacrificial layer 21 and the active structure 22 at one time. At this time, the first sacrificial layer 21 and the active structure 22 are both formed by silicon.

[0074] In an embodiment, as shown in FIGS. 5 to 6, the silicon wafer can be etched to obtain the first sacrificial layer 21 and the active structure 22. Meanwhile, the hard mask structure 27 disposed on the top of the active structure 22 is also shown in FIG. 6. The hard mask structure 27 is used to protect the first active structure 221 from being damaged in a subsequent process of exposing the first active structure 221.

[0075] In some possible embodiments, the first material layer 23 can be formed by stacking at least two material layers. The at least two material layers include a first semiconductor layer, an oxide layer, and a second semiconductor layer. The oxide layer is located between the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer is away from the second material layer relative to the second semiconductor layer. That is, the second semiconductor layer is located on the second material layer, the oxide layer is located on the second semiconductor layer, and the first semiconductor layer is located on the oxide layer.

[0076] In an embodiment, etching the first material layer 23 to form the initial active structure includes: etching the first semiconductor layer, the oxide layer and the second semiconductor layer to form an initial first active structure, an initial insulating structure and an initial second active structure, respectively; and then, removing the initial first active structure, the initial insulating structure and the initial second active structure in the regions on both sides of the stacked transistor 10 by using a finning process to form the first active structure 221, the insulating structure and the second active structure 222, respectively.

[0077] It can be understood that the first semiconductor layer away from the second material layer 24 can be used to form the first active structure 221, and the second semiconductor layer close to the second sacrificial layer can be used to form the second active structure 222. The oxide layer between the first semiconductor layer and the second semiconductor layer can be used to form the insulating structure. Through the insulating structure, the first active structure 221 and the second active structure 222 can be electrically isolated.

[0078] It can be understood that the first active structure 221, the insulating structure and the second active structure 222 can be formed by etching, so that no other process steps are needed to form the isolation structure between the first active structure 221 and the second active structure 222, greatly reducing the complexity of the preparation process.

[0079] In an embodiment, the material forming the oxide layer can be selected according to actual needs, and the embodiments of the present disclosure are not limited thereto. For example, the material forming the oxide layer can be an oxide material.

[0080] It should be noted that in the embodiments of the present disclosure, a silicon-on-insulator (SOI) substrate can also be directly obtained, and then a deep etching depth is used to etch the SOI substrate to form the first active structure 221, the insulating structure and the second active structure 222. At this time, the buried oxide layer in the SOI substrate is equivalent to the oxide layer for forming the insulating structure; the material layer above the buried oxide layer is equivalent to the first semiconductor layer for forming the first active structure 221; and the material layer below the buried oxide layer is equivalent to the second semiconductor layer and the second material layer for forming the second active structure 222 and the first sacrificial layer 21.

[0081] In some possible implementations, the oxide layer in the above-mentioned embodiments can be replaced by a second sacrificial layer. That is, at least two material layers include: a first semiconductor layer, a second sacrificial layer and a second semiconductor layer. The second sacrificial layer is located between the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer is away from the second material layer relative to the second semiconductor layer. That is, the second semiconductor layer is located above the second material layer, the second sacrificial layer is located above the second semiconductor layer, and the first semiconductor layer is located above the second sacrificial layer.

[0082] In an embodiment, etching the first material layer 23 to form the initial active structure comprises: etching the first semiconductor layer, the second sacrificial layer and the second semiconductor layer to form an initial first active structure, an initial third sacrificial layer and an initial second active structure, respectively; and then, removing the initial first active structure, the initial third sacrificial layer and the initial second active structure in the regions on both sides of the stacked transistor 10 by a fin cutting process to form the first active structure 221, the third sacrificial layer and the second active structure 222, respectively.

[0083] It can be understood that the first semiconductor layer away from the second material layer 24 can be used to form the first active structure 221, and the second semiconductor layer close to the second sacrificial layer can be used to form the second active structure 222. The second sacrificial layer between the first semiconductor layer and the second semiconductor layer can be used to form the third sacrificial layer. The third sacrificial layer is used to form a dielectric structure in a subsequent step. Through the dielectric structure, the first active structure 221 and the second active structure 222 can be electrically isolated.

[0084] It can be understood that the first active structure 221, the third sacrificial layer and the second active structure 222 can be formed by etching, thereby providing a new scheme for forming an isolation structure between the first active structure 221 and the second active structure 222 to meet the preparation requirements under different process conditions.

[0085] In an embodiment, the material forming the third sacrificial layer can be selected according to actual requirements, and the embodiments do not limit the material forming the third sacrificial layer. For example, the material forming the third sacrificial layer can be different from the material forming the active structure 22, so as to facilitate the removal of the third sacrificial layer in a subsequent process.

[0086] In some embodiments, the first semiconductor layer and the second semiconductor layer are single-layer structures or multi-layer structures according to the structures of the first active structure 221 and the second active structure 222.

[0087] In an embodiment, if the first active structure is a fin structure, the first semiconductor layer can be a single-layer structure; and if the second active structure is a columnar structure, the second semiconductor layer can be a multi-layer structure.

[0088] In an embodiment, the multi-layer structure refers to a structure formed by stacking at least two material layers. For example, a multi-layer structure formed by alternately stacking silicon and silicon germanium.

[0089] In some embodiments, the material forming the first semiconductor layer is the same as the material forming the second semiconductor layer; or the material forming the first semiconductor layer is different from the material forming the second semiconductor layer.

[0090] It can be understood that, based on the performance setting of the stacked transistor 10, the materials of the first semiconductor layer and the second semiconductor layer can be set according to actual needs, and the embodiments of the present disclosure do not make any limitation in this regard.

[0091] In some embodiments, the second material forming the second material layer can be a first silicon germanium material. The second semiconductor layer is a multi-layer structure. The multi-layer structure at least includes a bottom material layer adjacent to the second material layer. The bottom material layer can be formed by depositing a second silicon germanium material.

[0092] In an embodiment, the germanium content in the first silicon germanium material and the germanium content in the second silicon germanium material are different.

[0093] It can be understood that, when the second transistor 12 in the stacked transistor 10 is a full-surrounding gate transistor, the second active structure 222 of the second transistor 12 can be formed by alternately stacking silicon and silicon germanium. When the bottom material layer of the second active structure 22, i.e., the layer of material adjacent to the second material layer of the second semiconductor layer, is a second silicon germanium material, the second material should be a first silicon germanium material. The germanium content in the first silicon germanium material and the germanium content in the second silicon germanium material are different, so that the first sacrificial layer 21 and the second semiconductor layer can be distinguished.

[0094] In step S402, an oxide material is deposited on the semiconductor substrate 20 in which the active structure 22 is formed, to form a shallow trench isolation structure 26.

[0095] In an embodiment, the shallow trench isolation structure 26 wraps the second active structure 222 and the first sacrificial layer 21, and the first active structure 221 is exposed outside the shallow trench isolation structure 26.

[0096] It can be understood that, an initial shallow trench isolation (STI) structure 25 can be formed on the semiconductor substrate 20 by depositing an oxide material. The height of the initial shallow trench isolation structure 25 can be equal to the height of the active structure 22, as shown in FIG. 7; or can be greater than the height of the active structure 22, as shown in FIG. 8. Then, the initial shallow trench isolation structure 25 is etched to expose the first active structure 221, to form the shallow trench isolation structure 26 wrapping the second active structure 222 and the first sacrificial layer 21, and to obtain the structure as shown in FIG. 9.

[0097] In an embodiment, the oxide forming the shallow trench isolation structure 26 can be a silicon-based oxide (SiOx, x is the number of oxygen atoms), such as silicon dioxide (SiO2) and the like.

[0098] It should be noted that the height in the embodiments of the present disclosure refers to the distance between the highest point and the lowest point of the stacked transistor 10 in the first direction.

[0099] The etching process mentioned in the embodiments of the present disclosure can include dry etching, wet etching, reactive ion etching, chemical oxide removal process, etc., and the embodiments of the present disclosure do not limit this.

[0100] In step S403, the first transistor 11 is formed based on the first active structure 221.

[0101] It can be understood that the first transistor 11 in the stacked transistor 10 can be formed based on the exposed first active structure 221 by using a semiconductor manufacturing process. The first transistor 11 includes a first dummy gate side wall 111, a first source-drain structure 112, a first interlayer dielectric layer 113, a first gate structure 114, and a first source-drain metal 115.

[0102] In some embodiments, referring to FIG. 10, the first transistor 11 is formed based on the first active structure 221, including: forming a plurality of first dummy gate structures arranged at intervals along a second direction on the first active structure 221; forming a first dummy gate side wall 111 covering the side walls of the plurality of second dummy gate structures based on the plurality of first dummy gate structures. Etching the first active structure 221 in the source-drain region of the stacked transistor 10 by using the first dummy gate side wall 111 as a hard mask to form a first source-drain recess; and epitaxially growing a first source-drain structure 112 in the first source-drain recess. After the first source-drain structure 112 is formed, an insulating material can be deposited on the first source-drain structure 112 to form a first interlayer dielectric layer 113. Subsequently, the first dummy gate structure can be removed to form a first gate structure 114, and a first source-drain metal 115 can be formed on the first source-drain structure 112.

[0103] It can be understood that the source-drain region of the stacked transistor 10 can be a region for forming a source-drain structure, and the gate region can be a region for forming a gate structure.

[0104] In an embodiment, the material for forming the first dummy gate structure can be polysilicon, amorphous silicon, etc., and the material for forming the first dummy gate side wall 111 can be silicon oxide, silicon nitride, etc. In an example, the first dummy gate side wall 111 can have a single-layer structure and be made of the same material (e.g., porous silicon carbide oxide hydride (SiCOH)).

[0105] In an embodiment, when a third sacrificial layer is formed between the active structure 22 and the semiconductor substrate 20, the third sacrificial layer can be removed after the first dummy gate structure is formed, and a dielectric material can be deposited at the position of the removed third sacrificial layer to form a dielectric structure.

[0106] In an embodiment, the dielectric material can be selected according to actual needs, and the embodiments of the present disclosure do not limit this.

[0107] In an embodiment, the first source / drain recess can be formed on the first active structure 221 by using a fin recess process.

[0108] In an embodiment, a strained material such as silicon germanium or silicon carbide can be formed in the first source / drain recess by selective epitaxy growth to fill the first source / drain recess, and then a first source / drain structure 112 can be formed on the strained material by a heavy doping process.

[0109] In an embodiment, after the plurality of first dummy gate structures are removed, a metal material can be deposited at the positions of the removed first dummy gate structures, and the deposited metal material is used to form a first gate structure 114.

[0110] In an embodiment, the first gate structure 114 at least includes a first gate dielectric layer and a first gate electrode layer. The materials of the gate dielectric layer and the gate electrode layer can be set according to actual needs, and the embodiments of the present disclosure do not limit them.

[0111] In an embodiment, the first gate dielectric layer can be composed of a silicon oxide layer and a high-K hafnium oxide layer, and the thicknesses of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the first transistor 11. The first gate electrode layer can be composed of multiple layers of electrode materials, and each layer of electrode material includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0112] In an example, the first gate dielectric layer can include a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0113] In an embodiment, the first interlayer dielectric layer 113 can be etched to expose the first source / drain structure 112, and a metal material can be deposited on the first source / drain structure 112 to form a first source / drain metal 115.

[0114] In an embodiment, after the first gate structure 114 and the first source / drain metal 115 are formed, a first metal interconnection layer 116 can be formed on the first source / drain metal 115 and the first gate structure 114 by using standard post-processes of semiconductor preparation (such as interconnection line dielectric deposition, metal line formation, and lead pad formation).

[0115] It should be noted that, for the convenience of description, the first source / drain structure mentioned in the embodiments of the present disclosure is a simple term, which can refer to a first source structure and / or a first drain structure. In addition, the second source / drain structure, the first source / drain metal, the second source / drain metal, and the like are similar to the first source / drain recess, and the "source / drain" is a simple term of "source electrode and / or drain electrode".

[0116] It should be noted that the above one or more embodiments only show the preparation process of the transistor type of fin field effect transistor. Those skilled in the art should know that when the transistor types of the first transistor 11 and the second transistor 12 are other types, the embodiments of the present disclosure also include the corresponding standard preparation process of other types of transistors.

[0117] In step S404, the semiconductor substrate 20 is stripped and removed to expose the shallow trench isolation structure 26 and the first sacrificial layer 21.

[0118] It can be understood that an insulating material (such as silicon oxide) can be deposited on the prepared first transistor 11 to form an insulating layer 28, and the insulating layer 28 is bonded with the carrier wafer 29. Then, the first transistor 11 can be stripped to make the prepared first transistor 11 at the bottom and the semiconductor substrate 20 and the first sacrificial layer 21 connected to the semiconductor substrate 20 at the upper part, which is convenient for subsequent formation of the hard mask structure 27 using the first sacrificial layer 21, as shown in FIG. 11.

[0119] It should be noted that the carrier wafer 29 bonded with the first transistor 11 can provide physical support for the flipped first transistor 11 after stripping, effectively preventing the first transistor 11 from being broken by external force during the preparation of the second transistor 12.

[0120] Referring to FIG. 12, the semiconductor substrate 20 can be removed by polishing or chemical mechanical planarization after stripping to expose the shallow trench isolation structure 26 and the first sacrificial layer 21.

[0121] In step S405, as shown in FIG. 15, the first sacrificial layer 21 is removed, and the hard mask structure 27 is formed at the position of the removed first sacrificial layer 21.

[0122] It can be understood that the etching process can be used to remove part or all of the first sacrificial layer 21, and the hard mask structure 27 is formed at the position of the removed first sacrificial layer 21, so that the hard mask structure 27 can be arranged above the second active structure 222, and the hard mask structure 27 protects the second active structure 222 from being damaged.

[0123] In an embodiment, the removing the first sacrificial layer 21 and forming the hard mask structure 27 at the position of the removed first sacrificial layer 21 in step S405 includes: removing the first sacrificial layer 21 to form a groove 30. Wherein, the groove bottom of the groove 30 is formed by the second active structure 222, and the groove wall of the groove 30 is formed by the shallow trench isolation structure 26; then, a hard mask material is deposited in the groove 30 to form the hard mask structure 27.

[0124] It can be understood that the first sacrificial layer 21 can be removed by an etching process to expose the second active structure 222, and the second active structure 222 and the shallow trench isolation structure 26 are enclosed to form the recess 30, as shown in FIG. 13. Subsequently, a hard mask material can be deposited in the recess 30 to form the hard mask structure 27.

[0125] In some embodiments, the deposition of the hard mask material in the recess 30 to form the hard mask structure 27 includes: depositing the hard mask material on the surface of the shallow trench isolation structure 26 and the bottom of the recess 30 to form a first hard mask 31, as shown in FIG. 14; and then thinning the first hard mask 31 by a chemical mechanical planarization process until the shallow trench isolation structure 26 is exposed to form the hard mask structure 27, as shown in FIG. 15.

[0126] It can be understood that the deposition of the hard mask material on the surface of the shallow trench isolation structure 26 and the bottom of the recess 30 is easier to implement and reduces the difficulty of preparation. At the same time, the hard mask structure 27 can be obtained only by thinning the first hard mask 31 by the chemical mechanical planarization process, effectively reducing the complexity of the process.

[0127] In some embodiments, the deposition of the hard mask material in the recess 30 to form the hard mask structure 27 includes: depositing the hard mask material on the surface of the shallow trench isolation structure and the bottom of the recess to form a second hard mask (not shown, which can be referred to the first hard mask in FIG. 14); and then thinning the second hard mask by a chemical mechanical planarization process until the top surface of the second hard mask is at the same height to form a third hard mask 32, as shown in FIG. 16; and etching the third hard mask 32 by a dry etching process until the shallow trench isolation structure 26 is exposed to form the hard mask structure 27 to obtain the structure shown in FIG. 15.

[0128] It can be understood that the hard mask structure 27 can be formed by first controlling the surface of the hard mask to be at the same height and then etching by the dry etching process, which can improve the consistency of the etching depth and thus control the consistency of the plurality of hard mask structures, which is beneficial to the preparation of the stacked transistors 10.

[0129] In step S406, the shallow trench isolation structure 26 is thinned with the hard mask structure 27 as a hard mask to expose the second active structure 222 outside the shallow trench isolation structure 26, as shown in FIG. 17.

[0130] It can be understood that the hard mask structure 27 can protect the second active structure 222 when the shallow trench isolation structure 26 is thinned, effectively avoiding damage to the second active structure 222.

[0131] In step S407, after removing the hard mask structure 27, the second transistor 12 can be formed based on the second active structure 22 in step S203.

[0132] It can be understood that, after removing the hard mask structure 27, the top of the second active structure 222 can be exposed; then, based on the exposed second active structure 222, the second transistor 12 in the stacked transistor 10 can be formed by using a semiconductor manufacturing process, as shown in FIG. 18. The second transistor 12 includes a second dummy gate sidewall 121, a second source-drain structure 122, a second interlayer dielectric layer 123, a second gate structure 124, and a second source-drain metal 125. The second transistor 12 further includes a second metal interconnection layer 126.

[0133] It can be understood that the manufacturing process of the second transistor 12 in step S407 can refer to the manufacturing process of the first transistor 11 in step S403.

[0134] So far, the manufacturing of the stacked transistor 10 is completed.

[0135] It should be noted that the above one or more embodiments take the first sacrificial layer and the active structure as the same material as an example to illustrate a manufacturing method of the stacked transistor 10. In the method, when the active structure is etched, the etching depth is slightly deeper than the etching depth of only etching the active structure, and the extra part forms the first sacrificial layer. The method does not need to deposit or epitaxially grow other material layers, and the manufacturing process is simpler.

[0136] In the embodiments of the present disclosure, by etching the first sacrificial layer and the active structure with a certain depth, the active regions of the upper and lower transistors can be self-aligned. Then, the first transistor can be manufactured based on the first active structure in the active structure, and after developing, the first sacrificial layer is exposed by etching the substrate structure, so that the first sacrificial layer is removed and the hard mask material is filled to form the hard mask structure; then, in the process of thinning the shallow trench isolation structure, the hard mask structure is used to protect the lower half of the active region, and the second active structure is obtained without damage. Finally, the second transistor is manufactured based on the undamaged second active structure, and the performance of the second transistor is improved.

[0137] In some embodiments, FIGS. 19-28 are schematic diagrams of a preparation process of a stacked transistor according to embodiments of the present disclosure. For ease of understanding, (a) in FIGS. 19-28 shows a cross-sectional view along the direction of the dashed line A-A' in FIG. 1, (b) in FIGS. 19-28 shows a cross-sectional view along the direction of the dashed line B-B' in FIG. 1, and (c) in FIGS. 19-28 shows a cross-sectional view along the direction of the dashed line C-C' in FIG. 1. The preparation method of the stacked transistor and the stacked transistor prepared according to embodiments of the present disclosure will be described below in conjunction with FIGS. 1-28.

[0138] Different from the preparation process of the stacked transistor described above, different materials can be used to form the active structure and the first sacrificial layer in the preparation process of the stacked transistor.

[0139] In an embodiment, step S401 further includes epitaxially growing a second material layer on the semiconductor substrate 20, and then epitaxially growing a first material layer on the second material layer. Then, the first material layer and the second material layer are etched to form the first sacrificial layer 21 and the active structure 22 on the semiconductor substrate 20.

[0140] It can be understood that the material forming the first sacrificial layer 21 and the material forming the active structure 22 can be different. For example, the material forming the first sacrificial layer 21 can be silicon germanium, and the material forming the active structure 22 can be silicon, as shown in FIG. 19. Then, the first material layer and the second material layer are etched to obtain the structure shown in FIG. 20.

[0141] In an embodiment, after the first sacrificial layer 21 and the active structure 22 are formed, step S402 can be performed. An oxide material can be deposited on the semiconductor substrate 20 to obtain an initial shallow trench isolation structure 25, as shown in FIG. 21 or FIG. 22; then, the initial shallow trench isolation structure 25 is etched back to expose the first active structure 221 to obtain a shallow trench isolation structure 26, as shown in FIG. 23.

[0142] In an embodiment, after the first active structure 221 is exposed, step S403 can be performed. Based on the first active structure 221, a first transistor 11 is formed to obtain the structure shown in FIG. 24. Then, step S404 can be performed to develop the first transistor 11 to obtain the structure shown in FIG. 25. Then, the semiconductor substrate 20 can be removed to expose the shallow trench isolation structure 26 and the first sacrificial layer 21 to obtain the structure shown in FIG. 26.

[0143] In an embodiment, the first sacrificial layer 21 formed of silicon germanium is removed to obtain the structure shown in FIG. 27. It can be understood that by selectively etching silicon germanium, better process control can be achieved and the loss of the second active structure 222 is smaller.

[0144] In an embodiment, on the structure shown in FIG. 27, steps S405 to S407 are continuously performed, and a structure shown in FIG. 28 can be obtained.

[0145] In the embodiments of the present disclosure, the material forming the first sacrificial layer is different from the material forming the active structure, so that the first sacrificial layer can be removed by a selective etching process, not only improving the control performance of the process, but also reducing damage to the second active structure.

[0146] In some embodiments, FIGS. 29 to 30 are schematic diagrams of a preparation process of a stacked transistor provided in the embodiments of the present disclosure, for the convenience of understanding, (a) in FIGS. 29 to 30 shows a cross-sectional view along the direction of the dashed line A-A' in FIG. 1, (b) in FIGS. 29 to 30 shows a cross-sectional view along the direction of the dashed line B-B' in FIG. 1, and (c) in FIGS. 29 to 30 shows a cross-sectional view along the direction of the dashed line C-C' in FIG. 1; the preparation method of the stacked transistor provided in the embodiments of the present disclosure and the stacked transistor prepared will be exemplarily described below in combination with FIGS. 1 to 30.

[0147] Referring to FIGS. 29 to 30, the scheme of forming the first sacrificial layer 21 and removing the first sacrificial layer 21 after developing to form a hard mask structure is suitable for a full-wrapped gate transistor. By thinning the shallow trench isolation structure with the hard mask structure as a hard mask, the second active region can be protected from damage during exposure, effectively improving the performance of the transistor.

[0148] It should be noted that the scheme in the embodiments of the present disclosure is also suitable for a flip-chip stacking scheme of a planar transistor.

[0149] In the embodiments of the present disclosure, a stacked transistor 10 is provided, which can be prepared by the method in one or more embodiments corresponding to FIGS. 3 to 30. Referring to FIGS. 18, 28 and 30, the stacked transistor 10 comprises a first transistor 11 and a second transistor 12 stacked along a first direction with the first transistor 11.

[0150] The first active structure 221 of the first transistor 11 and the second active structure 222 of the second transistor 12 constitute an active structure 22; the first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12 are arranged opposite to each other.

[0151] It can be understood that the first transistor 11 and the second transistor 12 form a self-aligned flip-chip transistor.

[0152] In some embodiments, the disclosure provides a stacked transistor. FIG. 31 is a schematic diagram of a stacked transistor according to an embodiment of the disclosure. FIG. 32 is a schematic diagram of a stacked transistor according to an embodiment of the disclosure. Referring to FIGS. 31 and 32, it can be seen that the preparation method in the embodiments of the disclosure is also applicable to a flip stacked transistor formed based on an SOI substrate and a flip stacked transistor with an intermediate dielectric isolation layer.

[0153] It can be understood that the buried oxide layer 33 shown in FIG. 31 corresponds to an oxide layer in the first material layer; and the intermediate dielectric isolation layer 34 shown in FIG. 32 corresponds to a dielectric structure formed by the second sacrificial layer in the first material layer.

[0154] In some embodiments, the first transistor 11 or the second transistor 12 is of any one of the following types: a planar transistor, a fin field effect transistor, and a fully-enclosed gate transistor.

[0155] It can be understood that the stacked transistor in the embodiments of the disclosure can be prepared by using the preparation method in one or more embodiments corresponding to FIGS. 3 to 32. The embodiments of the disclosure achieve the protection of the second active structure from damage by forming a hard mask structure to protect the second active structure before thinning the shallow trench isolation structure of the second transistor, which is conducive to improving the performance of the stacked transistor.

[0156] It should be noted that the scheme of the upper and lower transistors realized by the flip in the embodiments of the disclosure is an organic integration of the current sequential and monolithic stacked transistor schemes, and takes into account the consistency, defect density, alignment, and thermal budget of the active regions of the upper and lower transistors. The scheme solves the long-term problems such as process complexity, polarity fixation (monolithic scheme), and alignment difficulty, high defect density of the upper semiconductor material (sequential scheme) existing in the current mainstream technical schemes of the stacked transistor, thereby promoting the industrialization of the transistor stacking technology.

[0157] The flip stacked transistor scheme has high maturity of technology reuse, can avoid a large amount of costly process development to save costs, and has high feasibility. At the same time, the flip transistor adopts a self-aligned “back-to-back” active region design, and the front and back transistors have independent signal and power supply networks and are connected through local interconnection, which greatly releases the metal wiring resources (more than 60% improvement compared with the current scheme), and has a huge space for process design and collaborative optimization.

[0158] Finally, the flip transistor scheme is compatible with mainstream device architectures, and can realize front-back stacking of planar transistors, fin transistors, all-surrounding gate transistors, and even vertical transistors (VTFETs), without the need for special process development for specific device architectures, and has strong flexibility and strong extendibility in terms of semiconductor process node iteration. The flip transistor is very advanced in concept, has important industrial value, and is practical, and has a wide development prospect.

[0159] In some embodiments, the semiconductor device includes a stacked transistor as in any of the above embodiments. The structure of the stacked transistor can refer to at least the structures shown in FIGS. 18, 28, 30-32.

[0160] In some embodiments, the electronic device includes a circuit board and a semiconductor device as in any of the above embodiments, and the semiconductor device is disposed on the circuit board. The semiconductor device includes a stacked transistor as described above. The structure of the stacked transistor can refer to at least the structures shown in FIGS. 18, 28, 30-32.

[0161] In the above embodiments, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can refer to the relevant description of other embodiments.

[0162] The above description is merely exemplary specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of fabricating a stack of transistors, wherein, The method comprises: forming a first sacrificial layer and an active structure above the first sacrificial layer on a semiconductor substrate; wherein the active structure comprises: a first active structure and a second active structure; the first active structure and the second active structure are stacked along a first direction, and the first active structure is farther away from the first sacrificial layer than the second active structure; depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the second active structure and the first sacrificial layer, and the first active structure is exposed outside the shallow trench isolation structure; forming a first transistor based on the first active structure; developing and removing the semiconductor substrate to expose the shallow trench isolation structure and the first sacrificial layer; removing the first sacrificial layer and forming a hard mask structure at the position of the removed first sacrificial layer; thinning the shallow trench isolation structure with the hard mask structure as a hard mask to expose the second active structure outside the shallow trench isolation structure; after removing the hard mask structure, forming a second transistor based on the second active structure.

2. The production method according to claim 1, wherein, The removing the first sacrificial layer and forming a hard mask structure at the position of the removed first sacrificial layer comprises: removing the first sacrificial layer to form a groove; the groove bottom is formed by the second active structure; depositing a hard mask material in the groove to form the hard mask structure.

3. The production method according to claim 2, wherein, The depositing a hard mask material in the groove to form the hard mask structure comprises: depositing a hard mask material above the surface of the shallow trench isolation structure and the groove bottom to form a first hard mask; thinning the first hard mask by a chemical mechanical polishing process until the shallow trench isolation structure is exposed to form the hard mask structure.

4. The production method according to claim 2, wherein The depositing a hard mask material in the groove to form the hard mask structure comprises: depositing a hard mask material above the surface of the shallow trench isolation structure and the groove bottom to form a second hard mask; thinning the second hard mask by a chemical mechanical polishing process until the top surface of the second hard mask is at the same height to form a third hard mask; etching the third hard mask by a dry etching process until the shallow trench isolation structure is exposed to form the hard mask structure.

5. The production method according to claim 1, wherein The forming a first sacrificial layer and an active structure above the first sacrificial layer on a semiconductor substrate comprises: forming a first material layer and a second material layer on a semiconductor substrate; the first material layer is farther away from the semiconductor substrate than the second material layer; etching the first material layer to form an initial active structure and etching the second material layer to form an initial first sacrificial layer by a same etching process; removing the initial active structure in the region on both sides of the stacked transistor to form the active structure by a fin cutting process, and removing the initial first sacrificial layer in the region on both sides of the stacked transistor to form the first sacrificial layer by a fin cutting process.

6. The production method according to claim 5, wherein The first material layer is a single layer structure formed by depositing a first material; Alternatively, the first material layer is a stack structure formed by stacking at least two material layers; a stacking direction of the stack structure is the first direction; The second material layer is a single-layer structure formed by depositing a second material.

7. The production method according to claim 6, wherein The first material and the second material are different; or, the first material and the second material are the same.

8. The production method according to claim 6, wherein The at least two material layers include a first semiconductor layer, an oxide layer and a second semiconductor layer; the oxide layer is located between the first semiconductor layer and the second semiconductor layer; the first semiconductor layer is away from the second material layer relative to the second semiconductor layer; a material forming the oxide layer is different from a material forming the first semiconductor layer or the second semiconductor layer; The etching the first material layer to form an initial active structure includes: Etching the first semiconductor layer, the oxide layer and the second semiconductor layer to form an initial first active structure, an initial insulating structure and an initial second active structure, respectively; The removing the initial active structure located in the two-side regions of the stacked transistor to form the active structure by using a fin cut process includes: The removing the initial first active structure, the initial insulating structure and the initial second active structure located in the two-side regions of the stacked transistor to form a first active structure, an insulating structure and a second active structure, respectively, by using a fin cut process; the insulating structure is used to electrically isolate the first active structure and the second active structure.

9. The production method according to claim 6, wherein The at least two material layers include a first semiconductor layer, a second sacrificial layer and a second semiconductor layer; the second sacrificial layer is located between the first semiconductor layer and the second semiconductor layer; the first semiconductor layer is away from the second material layer relative to the second semiconductor layer; a material forming the second sacrificial layer is different from a material forming the first semiconductor layer or the second semiconductor layer; The etching the first material layer to form an initial active structure includes: Etching the first semiconductor layer, the second sacrificial layer and the second semiconductor layer to form an initial first active structure, an initial third sacrificial layer and an initial second active structure, respectively; The removing the initial active structure located in the two-side regions of the stacked transistor to form the active structure by using a fin cut process includes: The removing the initial first active structure, the initial third sacrificial layer and the initial second active structure located in the two-side regions of the stacked transistor to form a first active structure, a third sacrificial layer and a second active structure, respectively, by using a fin cut process; The forming a first transistor based on the first active structure includes: Depositing a dummy gate material in a gate region of the stacked transistor to form a first dummy gate structure; removing the third sacrificial layer and depositing a dielectric material at a position of the removed third sacrificial layer to form a dielectric structure; the dielectric structure is used to electrically isolate the first active structure and the second active structure. The first semiconductor layer and the second semiconductor layer are single-layer structures or multi-layer structures; 10. The production method according to claim 8 or 9, wherein ​ The material forming the first semiconductor layer and the material forming the second semiconductor layer are the same; or the material forming the first semiconductor layer and the material forming the second semiconductor layer are different.

11. The production method according to claim 8 or 9, wherein The second material is a first silicon germanium material; The second semiconductor layer is a multi-layer structure, which comprises a bottom material layer; the bottom material layer is adjacent to the second material layer, and the bottom material layer is formed by depositing a second silicon germanium material; The germanium content in the first silicon germanium material and the germanium content in the second silicon germanium material are different.

12. A stacked transistor prepared using the production method according to any one of claims 1 to 11, wherein, Comprise: A first transistor; A second transistor stacked with the first transistor along a first direction; A first active structure of the first transistor and a second active structure of the second transistor constitute the active structure; a first gate structure of the first transistor and a second gate structure of the second transistor are arranged oppositely.

13. The stacked transistor of claim 12, wherein, The first transistor and the second transistor are any one of: Planar transistors, fin field effect transistors, all-around gate nanosheet transistors and stacked gate-all-around transistors.

14. A semiconductor device comprising: The stacked transistor of claim 12 or 13.

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