Vertical cavity surface emitting laser, and preparation method therefor

Abstract

A vertical cavity surface emitting laser, and a preparation method therefor. The preparation method comprises: S1: providing a substrate (10); S2: sequentially growing on the substrate (10) a buffer layer (20), an N-type DBR (30), an N-spacer layer (40), a multi-quantum well layer (50), a P-spacer layer (60), a thin layer (70) and a first P‑GaAs layer (81); S3: growing a plurality of parallel AlAs nanowires (82); S4: growing a second P‑GaAs layer (83) on the AlAs nanowires (82); S5: repeating S3-S4 so as to form a P-type DBR, wherein the P-type DBR comprises the first P‑GaAs layer (81), the AlAs nanowires (82) and the second P‑GaAs layer (83); S6: etching the P-type DBR to form a plurality of columnar structures; S7: using an HF solution to corrode the AlAs nanowires (82), so as to obtain a plurality of linear cavities (84); and S8: depositing a first electrode (91) and a second electrode (92), so as to obtain a vertical cavity surface emitting laser. In the preparation method, a nanowire array structure is prepared by means of laser-induced thin film deposition, and in combination with a selective corrosion process, the dependence on growth processes and devices can be reduced, thereby lowering the process barrier, improving the preparation efficiency and achieving low production costs.

Description

Vertical cavity surface emitting laser and preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a vertical cavity surface emitting laser and a preparation method thereof. BACKGROUND

[0002] With the development of the Internet of Things, Artificial Intelligence (AI), and 5th-Generation Mobile Communication Technology (5G), 3Dimensions (3D) and sensing technology are experiencing rapid growth, driving the development of smart phones, Augmented Reality (AR) / Virtual Reality (VR), smart cars, and other fields, and accelerating the arrival of the Internet of Everything era.

[0003] As the core device of 3D imaging and sensing systems, Vertical Cavity Surface Emitting Lasers (VCSELs) are at the top of the pyramid of the intelligent Internet industry. Currently, short-wave infrared VCSELs based on gallium arsenide substrates, such as 850nm and 980nm VCSELs, have been developed and well applied.

[0004] However, there are still many constraints in the preparation and research and development of VCSELs, such as the difficulty in preparing the distributed Bragg reflector mirror (DBR) of the VCSEL. The DBR is composed of multiple layers of high and low refractive index films arranged alternately, and requires precise control of the thickness and structure of each layer of film during growth to ensure reflectivity and wavelength selectivity. However, in the existing preparation method of VCSELs, the growth process of the DBR structure requires a high requirement, resulting in high production cost and low preparation efficiency.

[0005] Therefore, there is an urgent need for a VCSEL preparation method that reduces production cost and improves preparation efficiency. SUMMARY

[0006] The present application provides a vertical cavity surface emitting laser and a preparation method thereof to solve the technical problems of high production cost and low preparation efficiency in the existing preparation method of VCSELs.

[0007] The first aspect of the application provides a preparation method of a vertical cavity surface emitting laser, comprising: S1: providing an N-GaAs substrate; S2: sequentially growing an N-GaAs buffer layer, an N-type bottom DBR, an N-InAlAs spacer layer, an InGaAs / GaAs multi-quantum well layer, a P-InAlAs spacer layer, a P-InGaAs thin layer and a first P-GaAs layer on the N-GaAs substrate; S3: growing a plurality of parallel AlAs nanowires under the induction of interference fringes formed by two laser beams; wherein the plurality of AlAs nanowires are grown on a side of the first P-GaAs layer away from the P-InGaAs thin layer; S4: growing a second P-GaAs layer on the AlAs nanowires; S5: repeating S3-S4 for 5-15 times to form a P-type top DBR, and obtaining a wafer structure; wherein the P-type top DBR comprises the first P-GaAs layer, the AlAs nanowires and the second P-GaAs layer; S6: etching the P-type top DBR to form a plurality of columnar structures; wherein the height of the columnar structure is the same as the height of the P-type top DBR; S7: etching the AlAs nanowires by using an HF solution to obtain a plurality of linear cavities; and S8: depositing a first electrode and a second electrode on the N-GaAs substrate and the columnar structure respectively to obtain a vertical cavity surface emitting laser.

[0008] In some possible implementation manners, S6 comprises: S61: drawing a plurality of first pattern layers on the P-type top DBR; wherein the first pattern layers are arranged in an array on the P-type top DBR; and S62: etching regions of the P-type top DBR except the first pattern layers, and removing the plurality of first pattern layers to form the plurality of columnar structures.

[0009] In some possible implementation manners, in the P-type top DBR, the thicknesses of the first P-GaAs layer and the second P-GaAs layer are both 60 nm, and the diameter of the AlAs nanowire is 180-220 nm; wherein the distance between any two adjacent AlAs nanowires is 300-500 nm.

[0010] In some possible implementation manners, the number of periods of the N-type bottom DBR is 30-40, and the number of periods of the InGaAs / GaAs multi-quantum well layer is 2-10.

[0011] In some possible implementation manners, the number of periods of the N-type bottom DBR is 35, and the N-type bottom DBR comprises N-GaAs and N-AlAs sequentially grown on the N-GaAs buffer layer; in each period of the N-type bottom DBR, the thickness of the N-GaAs is 60 nm, and the thickness of the N-AlAs is 71 nm; the number of periods of the InGaAs / GaAs multi-quantum well layer is 3; and in each period of the InGaAs / GaAs multi-quantum well layer, the thickness of the InGaAs is 5 nm, and the thickness of the GaAs is 8 nm.

[0012] In some possible implementation manners, the thickness of the N-GaAs buffer layer is 500-1000 nm; the thickness of the N-InAlAs spacer layer is 100-300 nm; the thickness of the P-InAlAs spacer layer is 100-300 nm; and the thickness of the P-InGaAs thin layer is 5 nm.

[0013] In some possible implementation manners, the growth temperature of the N-GaAs buffer layer, the N-type bottom DBR, the N-InAlAs spacer layer, the InGaAs / GaAs multi-quantum well layer, the P-InAlAs spacer layer, the P-InGaAs thin layer, and the first P-GaAs layer, the AlAs nanowire, and the second P-GaAs layer is 600-700 ℃.

[0014] In some possible implementation manners, after S5 and before S6, the method further includes: S51: sequentially cleaning the wafer structure with acetone, alcohol, and deionized water.

[0015] The method for manufacturing the vertical cavity surface emitting laser provided in the first aspect of the present application can improve the production rate by using laser-induced preparation of a nanowire array structure and combining a selective etching process. The method can reduce the dependence on growth processes and growth equipment, lower the process threshold, and improve the preparation efficiency. Meanwhile, the method is simple in process, can realize growth and preparation of a large-size wafer structure, and is low in production cost.

[0016] The vertical cavity surface emitting laser provided in the second aspect of the present application is prepared by the method provided in the first aspect. The vertical cavity surface emitting laser includes: an N-GaAs substrate; an N-GaAs buffer layer, an N-type bottom DBR, an N-InAlAs spacer layer, an InGaAs / GaAs multi-quantum well layer, a P-InAlAs spacer layer, a P-InGaAs thin layer, and a columnar structure sequentially grown on the N-GaAs substrate; wherein the columnar structure is formed by etching a P-type top DBR, and the P-type top DBR includes a first P-GaAs layer, a plurality of second P-GaAs layers, and a plurality of linear cavities, the linear cavities are a plurality of AlAs nanowires grown in the second P-GaAs layers and formed by etching with an HF solution, and each second P-GaAs layer corresponds to a plurality of linear cavities; a first electrode deposited on the N-GaAs substrate; and a second electrode deposited on the columnar structure, wherein the second electrode corresponds to the columnar structure one by one.

[0017] In some possible implementation manners, in the P-type top DBR, the thickness of the first P-GaAs layer and the second P-GaAs layer is 60 nm, and the diameter of the AlAs nanowire is 180-220 nm; and the distance between any two adjacent AlAs nanowires is 300-500 nm.

[0018] The vertical cavity surface emitting laser provided in the second aspect of the present application is prepared by the preparation method of the vertical cavity surface emitting laser provided in the first aspect, and therefore has the beneficial technical effects of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, other drawings can also be obtained by those skilled in the art without any creative labor on the basis of these drawings.

[0020] Fig. 1 is a flowchart of a preparation method of a vertical cavity surface emitting laser according to an embodiment of the present application;

[0021] Fig. 2 is a structural schematic diagram of an AlAs nanowire according to an embodiment of the present application;

[0022] Fig. 3 is a perspective view of an AlAs nanowire according to an embodiment of the present application;

[0023] Fig. 4 is a schematic diagram of a wafer structure according to an embodiment of the present application;

[0024] Fig. 5 is a schematic diagram of another wafer structure according to an embodiment of the present application;

[0025] Fig. 6 is a schematic diagram of a wafer structure in which a columnar structure is etched according to an embodiment of the present application;

[0026] Fig. 7 is a schematic diagram of a wafer structure in which a linear cavity is etched according to an embodiment of the present application;

[0027] Fig. 8 is a structural schematic diagram of a vertical cavity surface emitting laser according to an embodiment of the present application.

[0028] Illustration mark: 100 - vertical cavity surface emitting laser; 10 - N-GaAs substrate; 20 - N-GaAs buffer layer; 30 - N-type bottom DBR; 40 - N-InAlAs spacer layer; 50 - InGaAs / GaAs multi-quantum well layer; 60 - P-InAlAs spacer layer; 70 - P-InGaAs thin layer; 80 - P-type top DBR; 81 - first P-GaAs layer; 82 - AlAs nanowire; 83 - second P-GaAs layer; 84 - linear cavity; 91 - first electrode; 92 - second electrode. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0030] Hereinafter, the terms "first", "second", and the like are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", and the like can explicitly or implicitly include one or more features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0031] In addition, in the present application, the orientation terms "upper", "lower", "inner", "outer", and the like are defined with respect to the orientation of the components shown in the drawings, and it should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the orientation of the components placed in the drawings.

[0032] The growth process of the DBR needs to strictly control the temperature and atmosphere to ensure the uniformity and stability of the multi-layer film, and avoid impurities or defects. The interface quality of each layer in the DBR is crucial for reflectivity and wavelength selectivity. It is required that the interface quality between the film layers during the growth process is as high as possible, and the interface scattering and absorption are reduced. The performance of the DBR is greatly affected by the thickness of the film layer, and the thickness of each film layer needs to be accurately controlled to ensure that the designed reflectivity and wavelength selectivity are achieved. The high refractive index and low refractive index materials selected in the DBR need to have high purity and excellent optical performance to ensure the realization of reflectivity and wavelength selectivity. However, in the existing preparation method of the VCSEL, the growth process of the DBR structure requires high requirements, resulting in high production cost and low preparation efficiency.

[0033] To solve the above technical problems, the embodiment of the present application provides a preparation method of a vertical cavity surface emitting laser.

[0034] In combination with FIG. 1, FIG. 2 and FIG. 3, the preparation method can be realized by the following steps S1 to S8.

[0035] Step S1: providing an N-GaAs substrate 10.

[0036] Step S2: sequentially growing an N-GaAs buffer layer 20, an N-type bottom DBR 30, an N-InAlAs spacer layer 40, an InGaAs / GaAs multi-quantum well layer 50, a P-InAlAs spacer layer 60, a P-InGaAs thin layer 70 and a first P-GaAs layer 81 on the N-GaAs substrate 10.

[0037] In step S2, the plurality of structure layers are sequentially grown on the N-GaAs substrate 10, which can be realized by the following steps S21 to S27.

[0038] Step S21: growing the N-GaAs buffer layer 20 on the N-GaAs substrate 10.

[0039] S22: growing the N-type bottom DBR 30 on the N-GaAs buffer layer 20.

[0040] Specifically, the N-type bottom DBR 30 comprises N-GaAs and N-AlAs sequentially grown on the N-GaAs buffer layer 20.

[0041] The period number of the N-type bottom DBR 30 can be 30-40.

[0042] For example, the period number of the N-type bottom DBR 30 can be one of 30, 32, 34, 36, 38 or 40. Of course, the period number of the N-type bottom DBR 30 can also be the remaining values in 30-40.

[0043] Step S23: growing the N-InAlAs spacer layer 40 on the N-type bottom DBR 30.

[0044] Step S24: growing the InGaAs / GaAs multi-quantum well layer 50 on the N-InAlAs spacer layer 40.

[0045] The period number of the InGaAs / GaAs multi-quantum well layer 50 can be 2-10.

[0046] For example, the number of periods of the InGaAs / GaAs multi-quantum well layer 50 can be one of 2, 4, 6, 8, or 10. Of course, the number of periods of the InGaAs / GaAs multi-quantum well layer 50 can also be the remaining values in the range of 2-10.

[0047] Step S25: growing a P-InAlAs spacer layer 60 on the InGaAs / GaAs multi-quantum well layer 50.

[0048] Step S26: growing a P-InGaAs thin layer 70 on the P-InAlAs spacer layer 60.

[0049] Step S27: growing a first P-GaAs layer 81 on the P-InGaAs thin layer 70.

[0050] The steps S21-S27 can employ the same growth technique. For example, the steps S21-S27 can employ a metal-organic chemical deposition technique or a molecular beam epitaxy technique, and the growth temperature can be in the range of 600-700°C.

[0051] Step S3: growing a plurality of parallel AlAs nanowires 82 under the induction of interference fringes formed by the two laser beams.

[0052] The plurality of AlAs nanowires 82 are grown on the side of the first P-GaAs layer 81 that faces away from the P-InGaAs thin layer 70. That is, the plurality of parallel AlAs nanowires 82 are continuously grown in the same direction as the growth direction in the step S2 described above.

[0053] The plurality of AlAs nanowires 82 prepared are shown in FIGS. 2 and 3.

[0054] The diameter of the AlAs nanowires 82 can be in the range of 180-220 nm, and the distance between any two adjacent AlAs nanowires 82 can be in the range of 300-500 nm.

[0055] For example, the diameter of the AlAs nanowires 82 can be one of 180 nm, 190 nm, 200 nm, 210 nm, or 220 nm, and of course, the diameter of the AlAs nanowires 82 can also be other values in the range of 180-220 nm.

[0056] For example, the distance between any two adjacent AlAs nanowires 82 can be one of 300 nm, 400 nm, or 500 nm, and of course, the distance between any two adjacent AlAs nanowires 82 can also be other values in the range of 300-500 nm.

[0057] The total number of the AlAs nanowires 82 is relatively more when the distance between two adjacent AlAs nanowires 82 is relatively smaller, and the total number of the AlAs nanowires 82 is relatively less when the distance between two adjacent AlAs nanowires 82 is relatively larger. The total number of the AlAs nanowires 82 can be adjusted according to the use requirement of the vertical cavity surface emitting laser.

[0058] In a specific implementation, the diameter of the AlAs nanowire 82 can be 200 nm, and the distance between any two adjacent AlAs nanowires 82 can be 400 nm.

[0059] In combination with FIG. 4 and FIG. 5, step S4: growing a second P-GaAs layer 83 on the AlAs nanowires 82.

[0060] The second P-GaAs layer 83 can be grown from the bottom of the AlAs nanowires 82. For example, the second P-GaAs layer 83 can be grown synchronously on the first P-GaAs layer 81 and the AlAs nanowires 82 until the gaps between the plurality of AlAs nanowires 82 are filled. The distance between the top of the AlAs nanowires 82 and the top of the second P-GaAs layer 83 is the height of the second P-GaAs layer 83.

[0061] Step S5: repeating steps S3-S4 for 5-15 times to form a P-type top DBR, and obtaining a wafer structure; wherein the P-type top DBR includes the first P-GaAs layer 81, the AlAs nanowires 82, and the second P-GaAs layer 83.

[0062] In step S5, the steps of growing the AlAs nanowires 82 and the second P-GaAs layer 83 are repeated.

[0063] Taking the second growth of the AlAs nanowires 82 and the second P-GaAs layer 83 as an example, the second growth of the AlAs nanowires 82 is on the first growth of the second P-GaAs layer 83, and then a layer of the second P-GaAs layer 83 is synchronously grown on the second P-GaAs layer 83 and the AlAs nanowires 82.

[0064] After being executed for 5-15 times, the P-type top DBR is obtained, and thus the wafer structure is obtained. The growth temperature of the P-type top DBR can be the same as the growth temperature of each structure layer in the aforementioned step S2, and can be 600-700°C.

[0065] In a specific implementation, the number of repetitions in step S5 is 10. In this way, the P-type top DBR includes one layer of the first P-GaAs layer 81, eleven layers of the AlAs nanowires 82, and eleven layers of the second P-GaAs layer 83.

[0066] In the implementation, the thickness of the first P-GaAs layer 81 and the second P-GaAs layer 83 can be the same, and the thickness of the first P-GaAs layer 81 and the second P-GaAs layer 83 can be 60 nm. The N-type bottom DBR 30 has 35 periods, and in each period of the N-type bottom DBR 30, the thickness of the N-GaAs is 60 nm, and the thickness of the N-AlAs is 71 nm; the InGaAs / GaAs multi-quantum well layer 50 has 3 periods, and in each period of the InGaAs / GaAs multi-quantum well layer 50, the thickness of the InGaAs is 5 nm, and the thickness of the GaAs is 8 nm. The thickness of the N-GaAs buffer layer 20 is 500-1000 nm; the thickness of the N-InAlAs spacer layer 40 is 100-300 nm; the thickness of the P-InAlAs spacer layer 60 is 100-300 nm; and the thickness of the P-InGaAs thin layer 70 is 5 nm.

[0067] After the growth of the multi-layer AlAs nanowire 82, the AlAs nanowire 82 array structure is formed. In FIG. 4, each layer of the AlAs nanowire 82 is located at the same position as the previous layer of the AlAs nanowire 82. In FIG. 5, each layer of the AlAs nanowire 82 is located at a different position than the previous layer of the AlAs nanowire 82.

[0068] That is, the position of each layer of the AlAs nanowire 82 can be the same as or different from the position of the previous layer of the AlAs nanowire 82 when each layer of the AlAs nanowire 82 is grown. The distance between each layer of the AlAs nanowire 82 can be the same or different.

[0069] The above FIG. 4 and FIG. 5 are only any two of a plurality of AlAs nanowire 82 growth structures, and in actual growth, the position and distance of the AlAs nanowire 82 can be adjusted according to the actual use requirements of the vertical cavity surface emitting laser.

[0070] In FIGs. 4 and 5, the number of repeated executions is twice, which is only an exemplary display of the position of the AlAs nanowire 82, and is not a limitation on the number of repeated executions.

[0071] Specifically, after step S5 is performed, the P-type top DBR is obtained.

[0072] In some possible implementation, after step S5, the method for manufacturing the vertical cavity surface emitting laser can further include:

[0073] Step S51: sequentially clean the wafer structure with acetone, alcohol, and deionized water.

[0074] The acetone and alcohol can be of analytical purity. The cleaning operation can be performed at room temperature. The number of cleaning operations can be determined according to the cleaning degree of the wafer structure.

[0075] Step S6: etching the P-type top DBR to form a plurality of columnar structures. The height of the columnar structure is the same as the height of the P-type top DBR.

[0076] In a feasible implementation, step S6 can be implemented by the following step S61 and step S62.

[0077] Step S61: drawing a plurality of first pattern layers on the P-type top DBR.

[0078] In step S61, the first pattern layer can be drawn by using a photolithography technology. The first pattern layer is circular, and the first pattern layers are arranged in an array on the P-type top DBR.

[0079] Referring to FIG. 6, step S62: etching the P-type top DBR except the first pattern layer, and removing the plurality of first pattern layers to form a plurality of columnar structures.

[0080] In step S62, the etching can be performed by using an inductively coupled plasma technology.

[0081] Of course, in the remaining feasible implementations, step S6 can also be implemented by the following step S63 and step S64.

[0082] Step S63: drawing a first patterning layer on the P-type top DBR.

[0083] The first patterning layer is the remaining area except the first pattern layer.

[0084] Step S64: etching the first patterning layer and the P-type top DBR covered by the first patterning layer.

[0085] The drawing and etching processes can be the same as those in steps S61 and S62.

[0086] Referring to FIG. 6, after the complete step S6 is performed, the wafer structure shown in FIG. 6 can be obtained.

[0087] Referring to FIG. 7, step S7: etching the AlAs nanowire 82 by using an HF solution to obtain a plurality of linear cavities 84.

[0088] Specifically, in step S7, the wafer structure can be soaked in the HF solution, so that the HF solution can etch away the AlAs nanowire 82 and form a plurality of linear cavities 84. The linear cavities 84 have the same shape as the AlAs nanowire 82.

[0089] After the execution of step S7 is completed, the wafer structure with linear cavities 84 shown in FIG. 7 can be obtained.

[0090] Step S8: depositing a first electrode 91 and a second electrode 92 on the N-GaAs substrate 10 and the columnar structure respectively to obtain a vertical cavity surface emitting laser.

[0091] The first electrode 91 and the second electrode 92 can be the same or different. The second electrode 92 corresponds to the columnar structure one by one.

[0092] The preparation method of the vertical cavity surface emitting laser provided in the embodiments of the present application adopts laser-induced preparation of nanowire array structure, and combines a selective etching process, so that the production rate can be improved. The preparation method can reduce the degree of dependence on the growth process and growth equipment, reduce the process threshold, and improve the preparation efficiency. At the same time, the preparation method is simple in process, can realize the growth and preparation of large-size wafer structure, and is low in production cost.

[0093] In combination with FIGS. 5, 6 and 8, the embodiments of the present application further provide a vertical cavity surface emitting laser 100, which is prepared by using the preparation method of the vertical cavity surface emitting laser provided in the above embodiments. The vertical cavity surface emitting laser 100 includes an N-GaAs substrate 10, an N-GaAs buffer layer 20, an N-type bottom DBR 30, an N-InAlAs spacer layer 40, an InGaAs / GaAs multi-quantum well layer 50, a P-InAlAs spacer layer 60, a P-InGaAs thin layer 70, a columnar structure P-type top DBR 80, a first electrode 91 and a second electrode 92 which are sequentially grown on the N-GaAs substrate 10.

[0094] The N-GaAs buffer layer 20 is grown on the N-GaAs substrate 10. The N-type bottom DBR 30 is grown on the N-GaAs buffer layer 20. Specifically, the N-type bottom DBR 30 includes N-GaAs and N-AlAs which are sequentially grown on the N-GaAs buffer layer 20. The N-InAlAs spacer layer 40 is grown on the N-type bottom DBR 30, the InGaAs / GaAs multi-quantum well layer 50 is grown on the N-InAlAs spacer layer 40, the P-InAlAs spacer layer 60 is grown on the InGaAs / GaAs multi-quantum well layer 50, the P-InGaAs thin layer 70 is grown on the P-InAlAs spacer layer 60, and the columnar structure P-type top DBR 80 is grown on the P-InGaAs thin layer 70. Specifically, the columnar structure is formed by etching the P-type top DBR 80 grown on the P-InGaAs thin layer 70.

[0095] The P-type top DBR 80 comprises a first P-GaAs layer 81, a plurality of second P-GaAs layers 83, and a plurality of linear cavities 84, the linear cavities 84 being a plurality of AlAs nanowires 82 grown in the second P-GaAs layers 83 and formed by etching with an HF solution, each second P-GaAs layer 83 corresponding to a plurality of linear cavities 84; wherein the second P-GaAs layer 83 can grow from the bottom of the plurality of AlAs nanowires 82 and fill the gap between the plurality of AlAs nanowires 82 to a preset height after post-growth.

[0096] The first electrode 91 is deposited on the side of the N-GaAs substrate 10 away from the N-GaAs buffer layer 20, and the second electrode 92 is deposited on the columnar structure, and the number of the second electrode 92 and the columnar structure is both a plurality, that is, the second electrode 92 and the columnar structure one-to-one correspond. Wherein, the growth temperature of the N-GaAs buffer layer 20, the N-type bottom DBR 30, the N-InAlAs spacer layer 40, the InGaAs / GaAs multi-quantum well layer 50, the P-InAlAs spacer layer 60, the P-InGaAs thin layer 70, and the first P-GaAs layer 81, the AlAs nanowire 82 and the second P-GaAs layer 83 are all 600-700℃.

[0097] In some possible implementation manners, the number of the second P-GaAs layers 83 is 6-16.

[0098] In some possible implementation manners, the number of periods of the N-type bottom DBR 30 is 30-40; the number of periods of the InGaAs / GaAs multi-quantum well layer 50 is 2-10.

[0099] In a specific implementation, the number of the second P-GaAs layers 83 is 11. The number of periods of the N-type bottom DBR 30 is 35, and the N-type bottom DBR 30 comprises N-GaAs and N-AlAs grown on the N-GaAs buffer layer 20 in sequence, wherein in each period of the N-type bottom DBR 30, the thickness of the N-GaAs is 60 nm, and the thickness of the N-AlAs is 71 nm; the number of periods of the InGaAs / GaAs multi-quantum well layer 50 is 3, and in each period of the InGaAs / GaAs multi-quantum well layer 50, the thickness of the InGaAs is 5 nm, and the thickness of the GaAs is 8 nm. In the P-type top DBR 80, the thickness of the first P-GaAs layer 81 is 60 nm, the diameter of the AlAs nanowire 82 is 180-220 nm, and the thickness of the second P-GaAs layer 83 is 60 nm; wherein the distance between any two adjacent AlAs nanowires 82 is 300-500 nm. The thickness of the N-GaAs buffer layer 20 is 500-1000 nm; the thickness of the N-InAlAs spacer layer 40 is 100-300 nm; the thickness of the P-InAlAs spacer layer 60 is 100-300 nm; and the thickness of the P-InGaAs thin layer 70 is 5 nm.

[0100] The vertical cavity surface emitting laser 100 provided by the embodiment of the present application can effectively improve the production rate, reduce the dependence on the growth process and growth equipment, reduce the process threshold, and improve the preparation efficiency by using the laser-induced thin film deposition method to prepare the nanowire array structure and combining the selective etching process. In addition, the growth and preparation of large-size wafer structures can also be realized.

[0101] It should be noted that other embodiments of the present application will occur to those skilled in the art having the benefit of the present disclosure. The present application is intended to embrace all such alternatives, modifications and variations of the application that are included within its scope, including those that presently known or developed in the future.

[0102] It should be understood that the application is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The true scope of the application is set forth in the attached claims.

Claims

1. A method of fabricating a vertical cavity surface emitting laser, characterized by, The preparation method comprises the following steps: S1: providing an N-GaAs substrate; S2: sequentially growing an N-GaAs buffer layer, an N-type bottom DBR, an N-InAlAs spacer layer, an InGaAs / GaAs multi-quantum well layer, a P-InAlAs spacer layer, a P-InGaAs thin layer and a first P-GaAs layer on the N-GaAs substrate; S3: growing a plurality of parallel AlAs nanowires under the induction of interference fringes formed by two laser beams; wherein the plurality of AlAs nanowires are grown on a side of the first P-GaAs layer away from the P-InGaAs thin layer; S4: growing a second P-GaAs layer on the AlAs nanowires; S5: repeating S3-S4 for 5-15 times to form a P-type top DBR, and obtaining a wafer structure; wherein the P-type top DBR comprises the first P-GaAs layer, the AlAs nanowires and the second P-GaAs layer; S6: etching the P-type top DBR to form a plurality of columnar structures; wherein the height of the columnar structures is the same as the height of the P-type top DBR; S7: etching the AlAs nanowires by using an HF solution to obtain a plurality of linear cavities; S8: depositing a first electrode and a second electrode on the N-GaAs substrate and the columnar structures respectively to obtain a vertical cavity surface emitting laser.

2. The preparation method of the vertical cavity surface emitting laser according to claim 1, wherein, S6 comprises: S61: drawing a plurality of first pattern layers on the P-type top DBR; wherein the first pattern layers are arranged in an array on the P-type top DBR; S62: etching regions of the P-type top DBR other than the first pattern layers, and removing the plurality of first pattern layers to form a plurality of columnar structures.

3. The preparation method of the vertical cavity surface emitting laser according to claim 1, wherein, in the P-type top DBR, the thickness of the first P-GaAs layer and the second P-GaAs layer is 60 nm, and the diameter of the AlAs nanowires is 180-220 nm; wherein the distance between any two adjacent AlAs nanowires is 300-500 nm.

4. The preparation method of the vertical cavity surface emitting laser according to claim 3, wherein, the period number of the N-type bottom DBR is 30-40, and the period number of the InGaAs / GaAs multi-quantum well layer is 2-10.

5. The preparation method of the vertical cavity surface emitting laser according to claim 4, wherein, the period number of the N-type bottom DBR is 35, and the N-type bottom DBR comprises N-GaAs and N-AlAs sequentially grown on the N-GaAs buffer layer; in each period of the N-type bottom DBR, the thickness of the N-GaAs is 60 nm, and the thickness of the N-AlAs is 71 nm. The InGaAs / GaAs multi-quantum well layer has 3 periods, and in each period, the thickness of InGaAs is 5 nm and the thickness of GaAs is 8 nm.

6. The preparation method of the vertical cavity surface emitting laser according to claim 4, wherein, The thickness of the N-GaAs buffer layer is 500-1000 nm, the thickness of the N-InAlAs spacer layer is 100-300 nm, the thickness of the P-InAlAs spacer layer is 100-300 nm, and the thickness of the P-InGaAs thin layer is 5 nm.

7. The preparation method of the vertical cavity surface emitting laser according to claim 1, wherein, The growth temperature of the N-GaAs buffer layer, the N-type bottom DBR, the N-InAlAs spacer layer, the InGaAs / GaAs multi-quantum well layer, the P-InAlAs spacer layer, the P-InGaAs thin layer, the first P-GaAs layer, the AlAs nanowire, and the second P-GaAs layer is 600-700 ℃.

8. The preparation method of the vertical cavity surface emitting laser according to claim 1, wherein, After the S5 and before the S6, the preparation method of the vertical cavity surface emitting laser further comprises: S51: sequentially cleaning the wafer structure with acetone, alcohol, and deionized water.

9. A vertical cavity surface emitting laser, characterized by The vertical cavity surface emitting laser is prepared by the preparation method of the vertical cavity surface emitting laser according to any one of claims 1-8, and comprises: an N-GaAs substrate; an N-GaAs buffer layer, an N-type bottom DBR, an N-InAlAs spacer layer, an InGaAs / GaAs multi-quantum well layer, a P-InAlAs spacer layer, a P-InGaAs thin layer, and a columnar structure sequentially grown on the N-GaAs substrate, wherein the columnar structure is a P-type top DBR etched to form, and the P-type top DBR comprises a first P-GaAs layer, a plurality of second P-GaAs layers, and a plurality of linear cavities, the linear cavities are a plurality of AlAs nanowires grown in the second P-GaAs layer and etched by an HF solution, and each second P-GaAs layer corresponds to a plurality of linear cavities; a first electrode deposited on the N-GaAs substrate; a second electrode deposited on the columnar structure, wherein the second electrode corresponds to the columnar structure one by one.

10. The vertical cavity surface emitting laser according to claim 9, wherein, In the P-type top DBR, the thickness of the first P-GaAs layer and the second P-GaAs layer is 60 nm, and the diameter of the AlAs nanowire is 180-220 nm; wherein the distance between any two adjacent AlAs nanowires is 300-500 nm.

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