Method for manufacturing an avalanche photodetector

Abstract

The disclosure relates to a method of manufacturing an avalanche photodetector (APD) (100). The method comprises: providing a silicon-on-insulator substrate comprising an oxide layer (101) and a silicon layer (102) disposed on the oxide layer, the silicon-on-insulator substrate comprising a central region (110) in which an n+ doped layer (103) is embedded in the silicon layer, an embedded intrinsic layer (104) is overlaying the n+ doped layer and an intrinsic multiplication layer (105) is overlaying the embedded intrinsic layer and the n+ doped layer; forming in the silicon layer on the central region, by a thermal drive-in process, a p+ doped charge layer (106) above the intrinsic multiplication layer, wherein the p+ doped charge layer forms with the embedded intrinsic layer, the intrinsic multiplication layer and the n+ doped layer a PIN junction of the APD which is configured to cause a photoelectric effect to convert light energy to electrical energy; and depositing on the central region a germanium absorption layer (107) overlaying the p+ doped charge layer, the germanium absorption layer being configured to function as a light absorption layer to absorb light.

Description

[0001] Method for manufacturing an Avalanche Photodetector

[0002] TECHNICAL FIELD

[0003] The disclosure relates to the field of Avalanche Photodetectors (APDs) and Avalanche Photodiodes, for example Infrared (IR) APDs and IR Si / Ge APDs and a method of manufacturing such devices.

[0004] BACKGROUND

[0005] Infrared (IR) Avalanche Photodiodes (APDs) are required for telecommunication optical integrated circuits, due to their higher sensitivity and internal gain compared to PIN photodiodes. Various examples of Si / Ge APD structures are already reported in the literature. The thin highly P doped charge layer between the Ge absorption and Si multiplication layers plays a key role in Si / Ge APD design. The charge layer controls the electric field distribution in the device by making the electric field in the Si layer large enough to cause avalanche breakdown while ensuring that the electric field in the Ge layer remains low such not to trigger avalanche but high enough to allow carriers to move at saturation speed to reduce transit time. The precise doping control over a very thin Si charge layer is fundamental to concentrate the high electrical field only in the underlying Si multiplication layer. Furthermore, the charge layer needs to be defect-free or almost defect-free in order to minimize the leakage, as the Ge is grown on his top, by creating an hetero structure with Si.

[0006] SUMMARY

[0007] This disclosure provides a solution for forming a charge layer in APDs, in particular Si / Ge APDs with very low detectivity and optimized doping control for electrical field confinement.

[0008] The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

[0009] Embodiments of the disclosure present a technique for the use of a heavy P-doped layer (doped in-situ or eventually locally implanted) on top of the intrinsic multiplication layer with thermal drive-in to diffuse impurities and form the charge layer in Si (~0.1um thickness and doping between 1016and 1018cm'3).

[0010] Embodiments of the disclosure present methods to diffuse impurities from the in-situ doped layer into Silicon through an inter dielectric layer and for eventually creating an oxide capping layer on top of the in-situ doped layer in order to prevent dopant out diffusion during the dopant drive-in process.

[0011] The methods described in this disclosure allow to overcome the main limitations of standard implantation or epitaxial methods currently used to create the charge layer in APDs, in particular Si / Ge APDs.

[0012] In order to describe the disclosure in detail, the following terms and notations will be used.

[0013] IR Infrared

[0014] APD Avalanche Photodetector, Avalanche Photodiode

[0015] Si / Ge Silicon / Germanium

[0016] GPB Gain bandwidth product

[0017] SACM Separate absorption charge multiplication

[0018] CVD Chemical Vapor Deposition

[0019] SOI Silicon on insulator

[0020] RTA Rapid Thermal Annealing

[0021] LTA Laser Thermal Anneal ALD Atomic Layer Deposition

[0022] PECVD Plasma Enhanced Chemical Vapor Deposition

[0023] ILD Interlayer Dielectric

[0024] In this disclosure, avalanche photodetectors and avalanche photodiodes, respectively, and particularly Infrared avalanche photodiodes are described. Such devices are required for telecommunication optical integrated circuits, due to their higher sensitivity and internal gain compared to PIN photodiodes. The avalanche multiplication process causes an internal noise related to the ratio of the electron and hole ionization coefficients which limits the performance of the device. Si has a large asymmetry of electron and hole ionization coefficients, which makes it a useful candidate for APDs. However, Si is not able to absorb light at telecommunication wavelengths in the IR range (e.g. 1.3 um, 1.55 um), unlike smaller bandgap materials such as Ge and InGaAs. However, InGaAs APDs have high multiplication noise that limits the gain-bandwidth product (GBP). APDs using Ge for absorption and Si for charge multiplication (Si / Ge APDs) are more promising candidates having shown much higher GBP. Moreover their fabrication is compatible with CMOS process flow, with relevant advantages in terms of integration, scalability and cost reduction. Relevant applications for Si / Ge APDs include high speed communications, spectroscopy and imaging systems (e.g. LIDARs).

[0025] Si / Ge APD is a separate-absorption-charge-multiplication (SACM) germanium on silicon avalanche photodiode. It is an advanced photodetector structure that combines the properties of germanium and silicon to achieve efficient light detection and signal amplification. In the SACM Si / Ge APD, the light is absorbed by the top Ge layer converting photons into e-h pairs while the underlying Si multiplication region provides the electric field required to accelerate the charge carriers and initiate the avalanche multiplication process. Thanks to its low bandgap (0.66 eV), Ge provides effective absorption at wavelengths in the entire visible and infrared ranges up to a maximum wavelength of approximately 1600 nm, while the fast mobility of electrons and holes offers the potential for fast response times. On the other hand, the low Si excess to noise factor, due to the much higher electrons impact ionization coefficient, compared to holes, results in a shorter time for avalanche buildup and multiplication and better gain-bandwidth product.

[0026] The thin highly P doped charge layer between the Ge absorption and Si multiplication layers plays a key role in Si / Ge APD design. The charge layer controls the electric field distribution in the device by making the electric field in the Si layer large enough to cause avalanche breakdown while ensuring that the electric field in the Ge layer remains low such not to trigger avalanche but high enough to allow carriers to move at saturation speed to reduce transit time. The charge layer has a typical thickness of about 0.1 um and doping between 1016and 1018cm'3, much larger compared to the Ge absorption and Si multiplication layers doping, both around 1015cm'3. Moreover the Ge may be grown by CVD on the Si charge layer. The precise doping control over a very thin Si charge layer is fundamental to concentrate the high electrical field only in the underlying Si multiplication layer. Furthermore, the charge layer needs to be defect-free in order to minimize the leakage, as the Ge is grown on his top, by creating an heterostructure with Si.

[0027] In the following, a solution for forming a charge layer in APDs, in particular Si / Ge APDs with very low detectivity and optimized doping control for electrical field confinement is presented.

[0028] The disclosure relates to an improved charge layer in Ge / Si Avalanche Photodiodes.

[0029] According to a first aspect, the disclosure relates to a method of manufacturing an avalanche photodetector (APD), the method comprising: providing a silicon-on-insulator substrate comprising an oxide layer and a silicon layer disposed on the oxide layer, the silicon-on-insulator substrate comprising a central region in which an n+ doped layer is embedded in the silicon layer, an embedded intrinsic layer is overlaying the n+ doped layer and an intrinsic multiplication layer is overlaying the embedded intrinsic layer and the n+ doped layer; forming in the silicon layer on the central region, by a thermal drive-in process, a p+ doped charge layer above the intrinsic multiplication layer, wherein the p+ doped charge layer forms with the embedded intrinsic layer, the intrinsic multiplication layer and the n+ doped layer a PIN junction of the APD which is configured to cause a photoelectric effect to convert light energy to electrical energy; and depositing on the central region a germanium absorption layer overlaying the p+ doped charge layer, the germanium absorption layer being configured to function as a light absorption layer to absorb light.

[0030] Such a method provides a solution for forming a charge layer in APDs, in particular Si / Ge APDs with very low detectivity and optimized doping control for electrical field confinement. Accordingly, lower leakage current and higher photoresponsivity (e.g., less recombination of the photogenerated e-h pairs) can be obtained, due to improved Ge layer quality and improved interface characteristics between Si multiplication and Ge absorption regions. Higher gain and lower excess to noise factor (e.g., faster avalanche multiplication and higher bandwidth) can be achieved, due to the better electrical field confinement in the charge layer ensured by the better doping profile and transition control.

[0031] In an exemplary implementation the method comprises: depositing a heavy p-doped layer on top of the intrinsic multiplication layer; and adopting the heavy p-doped layer with the thermal drive-in process to diffuse impurities and form the p+ doped charge layer in the silicon layer. This results in better control of the doping profile in the charge layer. Hence, very low defectivity and optimized doping control for electrical field confinement can be achieved.

[0032] In an exemplary implementation the method comprises: removing the heavy p-doped layer before depositing the germanium absorption layer on top of the p+ doped charge layer. Thus, the germanium absorption layer can be directly placed onto the charge layer resulting in better light detection.

[0033] In an exemplary implementation the heavy p-doped layer is formed by in-situ doping deposition or by depositing an undoped layer then locally implanted with p-type dopant. Accordingly, the doping profile in the charge layer can be better controlled.

[0034] In an exemplary implementation the method comprises: depositing an interlayer dielectric (ILD) oxide layer on top of the intrinsic multiplication layer; depositing an in-situ doped poly layer on top of the ILD oxide layer; and adopting the situ doped poly layer with the thermal drive-in process for dopant diffusion from the in-situ doped poly layer to form the p+ doped charge layer in the silicon layer. Dopant diffusion from an insitu p-type doped layer into silicon through a thin inter dielectric layer results in better control of the doping profile in the charge layer.

[0035] In an exemplary implementation the method comprises: removing the in-situ doped poly layer and the ILD oxide layer before depositing the germanium absorption layer on top of the p+ doped charge layer. Dopant diffusion from an in-situ p-type doped layer into silicon through a thin inter dielectric layer results in better control of the wet etch process used to strip the poly layer after dopant annealing.

[0036] In an exemplary implementation the method comprises: depositing an in-situ doped poly layer on top of the intrinsic multiplication layer; oxidizing the in-situ doped poly layer to form an oxide capping layer on top of the in-situ doped poly layer; and adopting the situ doped poly layer with the thermal drive-in process for dopant diffusion from the in-situ doped poly layer to form the p+ doped charge layer in the silicon layer. Formation of a thin capping layer on the surface of the in-situ doped layer before dopant rapid annealing avoids dopant out-diffusion during annealing, resulting in more precise control of the dopant profile in the charge layer. In an exemplary implementation the method comprises: removing the oxide capping layer and the in-situ doped poly layer before depositing the germanium absorption layer on top of the p+ doped charge layer. Thus, the germanium absorption layer can be directly placed onto the charge layer resulting in better light detection.

[0037] In an exemplary implementation the method comprises: forming the p+ doped charge layer with a thickness of about 0.1 pm and a doping between 1016cm'3and 1018cm'3. Such values for the doping have shown to be optimal for the manufacturing process.

[0038] In an exemplary implementation the thermal drive-in process comprises one of the following rapid anneal processes: Rapid thermal annealing (RTA); or Laser thermal annealing (LTA). These annealing processes result in less defectivity at the interface between the Si multiplication and Ge absorption layers. They guarantee better control of the doping profile in the charge layer. Si / Ge APD charge layer formed from pre-deposition of an in-situ P type doped layer (e.g., poly) followed by a rapid anneal process (e.g., RTA (Rapid Thermal Annealing), LTA (Laser Thermal Anneal)) for dopant diffusion into the low doped Si multiplication layer results in less defectivity at the interface between the Si multiplication and Ge absorption layers; and better control of the doping profile in the charge layer.

[0039] In an exemplary implementation the silicon-on-insulator substrate comprises a passivation overcoating layer disposed on top of the silicon layer, wherein a window in the central region of the silicon-on-insulator substrate is not covered by the passivation overcoating layer; and the p+ doped charge layer is formed in the window of the silicon-on-insulator substrate. The active area of the APD can be positioned in the central area of the power device allowing an efficient design of a vertical power device.

[0040] In an exemplary implementation the silicon-on-insulator substrate comprises a p-doped termination ring formed on top of the intrinsic multiplication layer, the p-doped termination ring framing the window of the silicon-on-insulator substrate. Such termination ring can shield protect the power device and its environment against strong electric fields generated in the active area.

[0041] In an exemplary implementation the p+ doped charge layer is formed with a thickness smaller than a thickness of the p-doped termination ring. A thin charge layer results in lower defectivity at the Si / Ge interface and hence better reliability of the APD.

[0042] In an exemplary implementation of the method, the method comprises: forming in the silicon layer and in the germanium absorption layer a plurality of electrode regions that are configured to apply a reverse bias voltage across the PIN junction to cause the photoelectric effect to convert light energy to electrical energy. The electrode regions can be used to control the APD and integrate it in a circuit design.

[0043] According to a second aspect, the disclosure relates to an avalanche photodetector (APD), obtainable by the method of manufacture according to the first aspect. The avalanche photodetector has a charge layer with very low defectivity and optimized doping control for electrical field confinement. The APD provides lower leakage current and higher photoresponsivity (e.g., less recombination of the photogenerated e-h pairs), due to better Ge layer quality and better interface characteristics between Si multiplication and Ge absorption regions. The APD has higher gain and lower excess to noise factor (e.g., faster avalanche multiplication and higher bandwidth), due to the better electrical field confinement in the charge layer ensured by the better doping profile and transition control. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Further embodiments of the disclosure will be described with respect to the following figures, in which:

[0045] Figures la to le show different cross sections of an avalanche photodetector (APD) after respective processing stages of a method of manufacturing the APD 100 according to the disclosure;

[0046] Figures 2a to 2e show different cross sections of an avalanche photodetector (APD) after respective processing stages of a method of manufacturing the APD 200 according to a first embodiment;

[0047] Figures 3a to 3c show different cross sections of an avalanche photodetector (APD) after respective processing stages of a method of manufacturing the APD 300 according to a second embodiment;

[0048] Figures 4a to 4c show different cross sections of an avalanche photodetector (APD) after respective processing stages of a method of manufacturing the APD 400 according to a third embodiment; and

[0049] Figure 5 shows a schematic diagram illustrating a method 500 of manufacturing an avalanche photodetector (APD) according to the disclosure.

[0050] DETAILED DESCRIPTION OF EMBODIMENTS

[0051] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims.

[0052] It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

[0053] Figures la to le show different cross sections of an avalanche photodetector (APD) after respective processing stages of a method of manufacturing the APD 100 according to the disclosure.

[0054] Figure la shows the process using SiOx to create Si window 115 for Ge epi growing selectively on Si charge layer 106 (as shown in Figures 1c to le). The charge layer implantation can be skipped and proceeded until Si window opening 115. Figure lb shows depositing heavy p-doped layer, which can be, for example, poly, high-k charged Ox, etc.

[0055] Figure 1c shows the thermal drive-in, furnace, RTP or LTA surface anneal to form charge layer 106. Figure Id shows removal of p-doped layer. Figure le shows CVD Ge epi.

[0056] The method comprises providing a silicon-on-insulator substrate comprising an oxide layer 101, e.g., made of SiO?, and a silicon layer 102 disposed on the oxide layer 101 as shown in Figure la. The silicon-on-insulator substrate comprises a central region 110 in which an n+ doped layer 103 is embedded in the silicon layer 102, an embedded intrinsic layer 104 is overlaying the n+ doped layer 103 and an intrinsic multiplication layer 105 is overlaying the embedded intrinsic layer 104 and the n+ doped layer 103.

[0057] As shown in Figures la to le, two electrode regions 111, 112 are formed in the silicon layer 102.

[0058] The silicon-on-insulator substrate comprises a passivation overcoating layer 113 disposed on top of the silicon layer 102. A window 115 in the central region 110 of the silicon-on- insulator substrate is not covered by the passivation overcoating layer 113 as shown in Figures la to le. The p+ doped charge layer 106 can be formed in the window 115 of the silicon-on-insulator substrate.

[0059] The silicon-on-insulator substrate comprises a p-doped termination ring 114 formed on top of the intrinsic multiplication layer 105. The p-doped termination ring 114 is framing the window 115 of the silicon-on-insulator substrate.

[0060] The p+ doped charge layer 106 may be formed with a thickness smaller than a thickness of the p-doped termination ring 114 as shown in Figure 1c.

[0061] A heavy p-doped layer 108 is deposited on top of the intrinsic multiplication layer 105 as shown in Figure lb.

[0062] The method comprises forming in the silicon layer 102 on the central region 110, by a thermal drive-in process 120, a p+ doped charge layer 106 above the intrinsic multiplication layer 105. The p+ doped charge layer 106 forms with the embedded intrinsic layer 104, the intrinsic multiplication layer 105 and the n+ doped layer 103 a PIN junction of the APD 100 which is configured to cause a photoelectric effect to convert light energy to electrical energy.

[0063] The heavy p-doped layer 108 is adopted with the thermal drive-in process 120 to diffuse impurities and form the p+ doped charge layer 106 in the silicon layer 102, as shown in Figure 1c.

[0064] The heavy p-doped layer 108 can be formed by in-situ doping deposition or by depositing an undoped layer then locally implanted with p-type dopant.

[0065] The method further comprises depositing on the central region 110 a germanium absorption layer 107 overlaying the p+ doped charge layer 106 as shown in Figure le. The germanium absorption layer 107 is configured to function as a light absorption layer to absorb light.

[0066] The method may comprise removing the heavy p-doped layer 108 before depositing the germanium absorption layer 107 on top of the p+ doped charge layer 106 as shown in Figure Id.

[0067] The p+ doped charge layer 106 may be formed with an exemplary thickness of about 0.1 pm and an exemplary doping between 1016cm'3and 1018cm'3.

[0068] The thermal drive-in process 120 as shown in Figure 1c may comprise one of the following rapid anneal processes: Rapid thermal annealing, KTA: or Laser thermal annealing, LTA, for example. Other similar thermal annealing processes may be applied as well.

[0069] The method may further comprise: forming in the silicon layer 102 and in the germanium absorption layer 107 a plurality of electrode regions 111, 112 that are configured to apply a reverse bias voltage across the PIN junction to cause the photoelectric effect to convert light energy to electrical energy . In F igures 1 a to 1 e, only electrode regions 111 , 112 in the silicon layer 102 are shown, not electrode region in the germanium absorption layer 107.

[0070] An avalanche photodetector 100 as shown in Figure le can be obtained by the method of manufacture as described above.

[0071] In the following, specific embodiments of the method of manufacturing the APD 100 are described. The charge layer 106 between the Si multiplication 105 and Ge absorption 107 regions can be created by rapid thermal / laser annealing process from a p-type in-situ doped layer.

[0072] In the Si / Ge APD manufacturing flow after the deposition and patterning of the Si multiplication layer 105 as shown in Figure la, an SiOx passivation layer (e.g. SiCh) 113 is deposited on the surface of the photodiode 100a. The passivation layer 113 is then opened on the active area through photolithographic and etching processes as shown in Figure Id. This process defines the area where the Ge will grow by C VD, for example.

[0073] Before Ge epitaxial growth 107, a thin in-situ doped P-type layer like poly silicon or any other material having the same function (e.g., charged oxide) can be used. A suitable rapid annealing process (e.g., thermal or laser annealing) can be used to drive the dopant from the in-situ doped layer into the Silicon in order to form the charge layer 106.

[0074] After the dopant diffusion, the in-situ doped layer 108 may be stripped and the process flow can continue with the Ge CVD epitaxial growth, by using the same passivation layer opening as window 115 for the Ge absorption layer 107 growth.

[0075] A schematic cross section including the charge layer 106 formed by diffusion of the in-situ doped layer 108 is shown in Figure le with the exclusion of the metallization contacts for the anode on the Ge layer 107 and cathode on the Si layer on the buried SOI substrate 102.

[0076] As general device architecture, the process sequence illustrated and described at high level in Figures la to le can be applied to any hetero structure SACM APDs between the phases of formation of an underlying low doped avalanche region (e.g. Si in the Si / Ge APDs) and an overlying low doped absorption region (e.g. Ge in the Si / Ge APDs), where the absorption and multiplication regions have low doping compared to the charge layer and are given by different semiconductor materials.

[0077] Figures 2a to 2e show different cross sections of an avalanche photodetector (APD) after respective processing stages of a method of manufacturing the APD 200 according to a first embodiment. In particular, the first embodiment is without ILD between in-situ doped layer and Si multiplication layer.

[0078] Figure 2b shows heavy p-doped layer deposition by in-situ doped poly layer deposition, for example by LPCVC, 600C, B doping, 1018cm'3, 0.2 pm poly thickness. Figure 2c shows thermal drive-in with dopant diffusion from in-situ doped poly layer, for example by RTA, 1000C, 2 min, N2 or LTA, 1.5-2 J7cm2, 160 ns. Figure 2d shows p doped layer removal, e.g., by poly layer wet etching. Figure 2e shows Ge CVD growth to produce APD device 100.

[0079] The charge layer 106 is formed on silicon by rapid thermal / laser annealing process from a p-type in-situ doped poly silicon layer deposited on the Si multiplication region.

[0080] The processing stages are similar to the processing stages described above with respect to Figures la to le, however, a specific processing of the thermal drive-in 120 is applied. In the process shown in Figures 2a to 2e, the thermal drive-in process 120 comprises a rapid annealing process, e.g., Rapid thermal annealing (RTA) or Laser thermal annealing (LTA) from a p-type in- situ doped polysilicon layer deposited on the Si multiplication region.

[0081] The method comprises depositing the heavy p-doped layer 108 as shown in Figure 2b on top of the intrinsic multiplication layer 105; and adopting the heavy p-doped layer 108 with the thermal drive-in process 120 to diffuse impurities and form the p+ doped charge layer 106 in the silicon layer 102 as shown in Figure 2c. The method may comprise: removing the heavy p-doped layer 108 before depositing the germanium absorption layer 107 on top of the p+ doped charge layer 106 as shown in Figure 2d.

[0082] The heavy p-doped layer 108 may be formed by in-situ doping deposition or by depositing an undoped layer then locally implanted with p-type dopant.

[0083] The first embodiment shown in Figures 2a to 2e corresponds to the device architecture described above with respect to Figures la to le. As specific embodiment, an in-situ doped poly layer and a suitable (thermal / laser) annealing process is used for the dopant drive-in into the silicon to form the charge layer 106. Details about the process steps used for in-situ doped deposition and annealing processes are illustrated in Figures 2a to 2e. The other layers in the final structure correspond to the final structure described above with respect to Figure le.

[0084] The outlined above with respect to Figures la to le can be easily integrated in the Si / Ge APD structure, by making use of materials (poly) and processes (RTA / LTA) largely consolidated in large scale microelectronics manufacturing.

[0085] Figures 3a to 3c show different cross sections of an avalanche photodetector (APD) after respective processing stages of a method of manufacturing the APD 300 according to a second embodiment. In particular, the second embodiment is with ILD between in-situ doped layer and Si multiplication layer.

[0086] Figure 3a shows thin ILD oxide layer deposition (ALD oxide or metal oxide, 5-15 nm thickness); in-situ doped poly layer deposition (LPCVD, 600C, B doping, 5xl018cm'3; 0.2 pm poly thickness). Figure 3b shows dopant diffusion from in-situ doped poly layer (RTA, 1000C, 5 min, N2, or LTA, 1.5-2 J / cm2, 180 ns). Figure 3c show poly layer wet etching; ILD oxide wet etching (or use Ge CVD in-situ preclean to remove ILD oxide for better interface between Ge / Si).

[0087] The charge layer 106 is formed on silicon by RTA / LTA process from a p-type in-situ doped poly layer through an inter dielectric layer deposited between the Si multiplication and poly layers.

[0088] The processing stages are similar to the processing stages described above with respect to Figures la to le, however, a specific processing of the thermal drive-in 120 is applied. In the process shown in Figures 3a to 3c, the thermal drive-in process 120 comprises a rapid annealing process, e.g., Rapid thermal annealing (RTA) or Laser thermal annealing (LTA) through an inter dielectric layer deposited between the Si multiplication and poly layers.

[0089] The method may comprise: depositing an interlayer dielectric (ILD) oxide layer 301 on top of the intrinsic multiplication layer 105 as shown in Figure 3a; depositing an in-situ doped poly layer 302 on top of the ILD oxide layer 301 as shown in Figure 3b; and adopting the situ doped poly layer 302 with the thermal drive-in process 120 for dopant diffusion from the in-situ doped poly layer 302 to form the p+ doped charge layer 106 in the silicon layer 102 as shown in Figure 3b.

[0090] The method may further comprise: removing the in-situ doped poly layer 302 and the ILD oxide layer 301 before depositing the germanium absorption layer 107 on top of the p+ doped charge layer 106 as shown in Figure 3c.

[0091] Figures 4a to 4c show different cross sections of an avalanche photodetector (APD) after respective processing stages of a method of manufacturing the APD 400 according to a third embodiment. In particular, the third embodiment is with thermal oxide capping layer on poly before dopant drive-in. Figure 4a shows in-situ doped poly layer deposition (LPCVD, 600C, B doping, 1018cm'3; 0.2 pm poly thickness). Figure 4b shows poly layer oxidation (Ox capping layer) at 770C, 20 min, 02); dopant diffusion from in-situ doped poly layer; RTA, 1000C, 2 min, N2, or LTA, 1.5-2 J / cm2, 160 ns). Figure 4c shows thin oxide wet etching; and poly wet etching.

[0092] The processing stages are similar to the processing stages described above with respect to Figures la to le, however, a thin oxide capping layer 403 is thermally grown on the in-situ doped poly layer surface before the annealing process, such to prevent dopant out-diffusion.

[0093] The method may comprise: depositing an in-situ doped poly layer 302 on top of the intrinsic multiplication layer 105 as shown in Figure 4a; oxidizing the in-situ doped poly layer 302 to form an oxide capping layer 403 on top of the in-situ doped poly layer 302 as shown in Figure 4b; and adopting the situ doped poly layer 302 with the thermal drive-in process 120 for dopant diffusion from the in-situ doped poly layer 302 to form the p+ doped charge layer 106 in the silicon layer 102 as shown in Figure 4b.

[0094] The method may comprise: removing the oxide capping layer 403 and the in-situ doped poly layer 302 as shown in Figure 4c before depositing the germanium absorption layer 107 on top of the p+ doped charge layer 106.

[0095] In this third embodiment the surface of the in-situ doped poly layer is oxidized before the dopant drive-in annealing process 120. The oxide capping layer 403 formed on top of the poly layer helps to prevent out-diffusion and thus guarantee a better doping control in the charge layer 106. The solution according to this third embodiment can be combined with the one according to the second embodiment described above with respect to Figures 3a to 3c.

[0096] Figure 5 shows a schematic diagram illustrating a method 500 of manufacturing an avalanche photodetector (APD) according to the disclosure.

[0097] The method 500 comprises providing 501 a silicon-on-insulator substrate comprising an oxide layer 101 and a silicon layer 102 disposed on the oxide layer 101, the silicon-on-insulator substrate comprising a central region 110 in which an n+ doped layer 103 is embedded in the silicon layer 102, an embedded intrinsic layer 104 is overlaying the n+ doped layer 103 and an intrinsic multiplication layer 105 is overlaying the embedded intrinsic layer 104 and the n+ doped layer 103, e.g., as described above with respect to Figures la to 4c.

[0098] The method 500 comprises forming 502 in the silicon layer 102 on the central region 110, by a thermal drive-in process, a p+ doped charge layer 106 above the intrinsic multiplication layer 105, wherein the p+ doped charge layer 106 forms with the embedded intrinsic layer 104, the intrinsic multiplication layer 105 and the n+ doped layer 103 a PIN junction of the APD 100 which is configured to cause a photoelectric effect to convert light energy to electrical energy, e.g., as described above with respect to Figures la to 4c.

[0099] The method 500 comprises depositing 503 on the central region 110 a germanium absorption layer 107 overlaying the p+ doped charge layer 106, the germanium absorption layer 107 being configured to function as a light absorption layer to absorb light, e.g., as described above with respect to Figures la to 4c.

[0100] The solution described in this disclosure can be applied to any kind of avalanche photodiode based on the use of separate absorption and charge multiplication layers (SACM) forming heterojunctions like Si / Ge APDs. While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

[0101] Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and / or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

[0102] Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

[0103] Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.

Claims

CLAIMS:

1. A method of manufacturing an avalanche photodetector, APD (100), the method comprising: providing a silicon-on-insulator substrate comprising an oxide layer (101) and a silicon layer (102) disposed on the oxide layer (101), the silicon-on-insulator substrate comprising a central region (110) in which an n+ doped layer (103) is embedded in the silicon layer (102), an embedded intrinsic layer (104) is overlaying the n+ doped layer (103) and an intrinsic multiplication layer (105) is overlaying the embedded intrinsic layer (104) and the n+ doped layer (103); forming in the silicon layer (102) on the central region (110), by a thermal drive-in process, a p+ doped charge layer (106) above the intrinsic multiplication layer (105), wherein the p+ doped charge layer (106) forms with the embedded intrinsic layer (104), the intrinsic multiplication layer (105) and the n+ doped layer (103) a PIN junction of the APD (100) which is configured to cause a photoelectric effect to convert light energy to electrical energy; and depositing on the central region (110) a germanium absorption layer (107) overlaying the p+ doped charge layer (106), the germanium absorption layer (107) being configured to function as a light absorption layer to absorb light.

2. The method of claim 1 , comprising: depositing a heavy p-doped layer (108) on top of the intrinsic multiplication layer (105); and adopting the heavy p-doped layer (108) with the thermal drive-in process to diffuse impurities and form the p+ doped charge layer (106) in the silicon layer (102).

3. The method of claim 2, comprising: removing the heavy p-doped layer (108) before depositing the germanium absorption layer (107) on top of the p+ doped charge layer (106).

4. The method of claim 2 or 3, wherein the heavy p-doped layer (108) is formed by in-situ doping deposition or by depositing an undoped layer then locally implanted with p-type dopant.

5. The method of claim 1 , comprising : depositing an interlayer dielectric, ILD, oxide layer (301) on top of the intrinsic multiplication layer (105); depositing an in-situ doped poly layer (302) on top of the ILD oxide layer (301); and adopting the situ doped poly layer (302) with the thermal drive-in process for dopant diffusion from the in-situ doped poly layer (302) to form the p+ doped charge layer (106) in the silicon layer (102).

6. The method of claim 5, comprising: removing the in-situ doped poly layer (302) and the ILD oxide layer (301) before depositing the germanium absorption layer (107) on top of the p+ doped charge layer (106).

7. The method of claim 1 , comprising: depositing an in-situ doped poly layer (302) on top of the intrinsic multiplication layer (105); oxidizing the in-situ doped poly layer (302) to form an oxide capping layer (403) on top of the in-situ doped poly layer (302); and adopting the situ doped poly layer (302) with the thermal drive-in process for dopant diffusion from the in-situ doped poly layer (302) to form the p+ doped charge layer (106) in the silicon layer (102).

8. The method of claim 7, comprising: removing the oxide capping layer (403) and the in-situ doped poly layer (302) before depositing the germanium absorption layer (107) on top of the p+ doped charge layer (106).

9. The method of any of the preceding claims, comprising: forming the p+ doped charge layer (106) with a thickness of about 0.1 pm and a doping between 1016cm'3and 1018cm'3.

10. The method of any of the preceding claims, wherein the thermal drive-in process comprises one of the following rapid anneal processes:Rapid thermal annealing, KT A: orLaser thermal annealing, LTA.

11. The method of any of the preceding claims, wherein the silicon-on-insulator substrate comprises a passivation overcoating layer (113) disposed on top of the silicon layer (102), wherein a window (115) in the central region (110) of the silicon-on-insulator substrate is not covered by the passivation overcoating layer (113); and wherein the p+ doped charge layer (106) is formed in the window (115) of the silicon-on-insulator substrate.

12. The method of any of the preceding claims, wherein the silicon-on-insulator substrate comprises a p-doped termination ring (114) formed on top of the intrinsic multiplication layer (105), the p-doped termination ring (114) framing the window (115) of the silicon-on-insulator substrate.

13. The method of claim 12, wherein the p+ doped charge layer (106) is formed with a thickness smaller than a thickness of the p-doped termination ring (114).

14. The method of any of the preceding claims, comprising: forming in the silicon layer (102) and in the germanium absorption layer (107) a plurality of electrode regions (111, 112) that are configured to apply a reverse bias voltage across the PIN junction to cause the photoelectric effect to convert light energy to electrical energy.

15. An avalanche photodetector, APD (100), obtainable by the method of manufacture according to any one of the preceding claims.

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