Semiconductor device

Abstract

Provided is a semiconductor device in which solder bonding of semiconductor chips has been improved. The semiconductor device comprises: a semiconductor chip (3) having a lower main electrode (3a) on the lower side thereof; an insulating circuit substrate including an insulating substrate (11) and an upper conductor layer (12a) disposed on the upper surface of the insulating substrate (11); and a bonding layer (2) for bonding the lower main electrode (3a) of the semiconductor chip (3) to the upper conductor layer (12a). The bonding layer (2) includes: a solder material (2a) containing tin; a filler (2b) containing a first metal having a melting point higher than that of the solder material (2a) and disposed in the solder material (2a); and an alloy layer (2c) comprising an alloy of the first metal and tin contained in the solder material (2a) and provided on the surface of the filler (2b). The alloy layer (2c) connects the lower main electrode (3a) and the upper conductor layer (12a).

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device (semiconductor module) equipped with a power semiconductor chip.

[0002] Semiconductor devices equipped with power semiconductor chips (hereinafter simply referred to as "semiconductor chips") are primarily used for variable speed drive applications such as motors and inverters, and for power conversion applications. Examples of bonding materials for bonding semiconductor chips to insulating circuit boards include solder and sintered materials. An advantage of using solder as a bonding material is that its price is lower than that of sintered materials.

[0003] Patent Document 1 describes that a semiconductor element is joined to the surface of a land-shaped conductive pattern via solder, that metal powder is mixed into the solder in areas corresponding to the corners of the semiconductor element, and that by mixing in the metal powder, the thickness T1 of the solder is formed to be approximately 100 μm or thicker.

[0004] Patent document 2 describes that the collector electrode of the semiconductor device and a heat sink arranged on the back side of the semiconductor element are connected via solder, that multiple wire pieces are provided at the solder joint, and that all of the wire pieces are joined to the mounting surface of the heat sink and protrude toward the semiconductor element, that four or more wire pieces are arranged in the outer peripheral region of the solder corresponding to at least each of the four corners of the semiconductor element, and that at least one of the wire pieces extends toward the center of the element when viewed in a plane.

[0005] Patent Document 3 relates to a joint structure to be formed when a pair of materials to be joined, such as a Si semiconductor or the like, and a substrate, are joined by liquid phase diffusion bonding, and when an arbitrary cross section of the joint is observed, island-shaped Ag phases containing 95 mass % or more of Ag and Ag surrounding the island-shaped Ag phases are observed. ３ Ag consisting of Sn intermetallic compounds ３ It is described that the alloy exhibits a characteristic material structure composed of a Sn phase.

[0006] Patent Document 4 describes a semiconductor device comprising a first substrate, a bonding layer provided on one main surface of the first substrate, a second substrate provided on the bonding layer, a wiring portion provided on the second substrate, and a semiconductor mounting component including at least one semiconductor chip mounted on the wiring portion, and describes that the bonding material of the bonding layer contains material particles that form the bonding layer by sintering, the material particles including particles having a size on the order of nanometers to micrometers and spacer particles having a size that controls the thickness of the bonding layer, and that the spacer particles include a coating on their particle surfaces for reaction control.

[0007] Patent Document 5 describes a solder paste containing powder of a lead-free solder alloy containing Sn as a main component and metal particles having a melting point higher than that of the lead-free solder alloy, and describes that the metal particles are formed of a Cu—Ni alloy with a Ni content of 0.1 to 90 mass % or a Cu—Co alloy with a Co content of 0.1 to 90 mass %.

[0008] Patent Document 6 describes that in the process of bonding printed circuit boards together, the electrodes are connected by soldering using Cu-core solder-plated balls, the boards are bonded together using a three-layer adhesive material consisting of an adhesive layer / ball-retaining core layer / adhesive layer, and the solder of the Cu-core solder-plated balls inserted into the holes in the three layers is formed by thermocompression bonding all at once.

[0009] Patent Document 7 describes a solder sheet in which metal balls with a higher melting point than the solder that makes up the matrix are dispersed, and describes that the average diameter of the metal balls is 30 to 300 μm and the standard deviation of the diameter distribution is 2.0 μm or less.

[0010] Patent Document 8 describes that an electronic component is constructed by joining solder bumps on a semiconductor chip and electrodes on a printed circuit board with solder paste, and that the solder bumps are formed by joining Cu balls to the electrodes on the semiconductor chip.

[0011] Patent Document 9 describes a method in which a filler smaller than the thickness of the solder joint layer before melting is placed on the solder joint layer before melting, and the solder joint layer is heated to melt the solder joint layer, and the filler falls into the melted solder joint layer, and the solder joint layer is cooled to solidify, thereby achieving the desired thickness of the solder joint layer that joins the heat sink and the insulating substrate.

[0012] Patent Document 10 describes a process of applying a paste-like coating agent containing a conductive material that is solid at room temperature and melts when heated and a solvent onto a substrate to form a coating agent layer; a process of embedding a plurality of conductive solid spacers that do not change shape when heated into the coating agent layer to regulate the gap between the substrate and the electronic component; a process of placing the electronic component on the coating agent layer; and a process of heating the substrate while pressing the electronic component against the substrate to melt the conductive material in the coating agent layer, and then allowing the substrate to cool naturally or cooling to re-solidify the conductive material, thereby joining the electronic component to the substrate.

[0013] Japanese Patent Publication No. 2006-073554 International Publication No. 2021 / 065736 International Publication No. 2022 / 091988 Japanese Patent Publication No. 2014-131076 International Publication No. 2021 / 045131 Japanese Patent Publication No. 2013-138169 Japanese Patent Publication No. 2005-161338 Japanese Patent No. 5585751 Japanese Patent Publication No. 2008-270846 Japanese Patent Publication No. 2012-028433

[0014] As a joining material, solder is cheaper, but sintered materials have better performance.

[0015] In view of the above-mentioned problems, the present disclosure has an object to provide a semiconductor device with improved solder joints of a semiconductor chip.

[0016] In order to achieve the above object, a semiconductor device according to one embodiment of the present disclosure comprises: (a) a semiconductor chip having a lower main electrode on its underside; (b) an insulated circuit board including an insulating substrate and an upper conductor layer disposed on the upper surface of the insulating substrate; and (c) a bonding layer that bonds the lower main electrode of the semiconductor chip to the upper conductor layer, wherein (d) the bonding layer includes a solder material containing tin, a filler that contains a first metal having a higher melting point than the solder material and is disposed in the solder material, and an alloy layer that is made of an alloy of tin contained in the solder material and the first metal and is disposed on the surface of the filler, and (e) the alloy layer connects the lower main electrode and the upper conductor layer.

[0017] The alloy layer may be provided on the surface of the filler with a thickness of 10 μm or more.

[0018] The thickness of the filler may be the same as the thickness of the bonding layer.

[0019] The filler may be provided at least at each of the four corners of the semiconductor chip when viewed from above.

[0020] Furthermore, a laser resist region may be provided on the top surface of the upper conductor layer, and the filler may be disposed on the laser resist region.

[0021] The first metal may be a metal capable of forming an alloy with tin, and may have a melting point of 270° C. or higher.

[0022] Additionally, the first metal may be any of tellurium, titanium, thallium, vanadium, yttrium, zinc, zirconium, arsenic, gold, silver, bismuth, cadmium, cobalt, copper, iron, germanium, magnesium, manganese, niobium, nickel, lead, palladium, platinum, and antimony.

[0023] The alloy layer may be provided on the surface of the filler with a thickness of 2 μm or more.

[0024] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0025] According to the present disclosure, it is possible to provide a semiconductor device with improved solder joints of a semiconductor chip.

[0026] FIG. 2 is a schematic longitudinal sectional view showing an example of a schematic configuration of a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a schematic longitudinal sectional view showing an enlarged schematic configuration of an upper conductor layer, a bonding layer, and a semiconductor chip of FIG. 1. FIG. 4 is a plan view showing an example of a schematic configuration of a bonding layer according to a first modified example of the first embodiment of the present disclosure. FIG. 5 is a plan view showing an example of a schematic configuration of an upper conductor layer and a laser resist region according to a second modified example of the first embodiment of the present disclosure. FIG. 6 is a plan view showing another example of a schematic configuration of an upper conductor layer and a laser resist region according to a second modified example of the first embodiment of the present disclosure. FIG. 7 is a table showing the properties of various bonding materials.

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the embodiments shown below are examples of devices and methods for embodying the technical concept of the present disclosure, and the technical concept of the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of component parts as described below. Furthermore, the technical concept of the present disclosure may be modified in various ways within the technical scope defined by the claims.

[0028] In this specification, the source region of a metal-oxide semiconductor field-effect transistor (MOSFET) is "one main region (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a thyristor such as a MOS-controlled static induction thyristor (SI thyristor), "one main region" can be selected as the cathode region. The drain region of a MOSFET is "the other main region (second main region)" of the semiconductor device that can be selected as the collector region in an IGBT or as the anode region in a thyristor. In this specification, the term "main region" simply refers to either the first main region or the second main region, as appropriate from the common technical knowledge of a person skilled in the art.

[0029] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are inverted and read as such. Furthermore, "top surface" may be read as "front surface" and "bottom surface" may be read as "rear surface."

[0030] First Embodiment Configuration of Semiconductor Device As shown in Fig. 1, a semiconductor device according to a first embodiment includes an insulating circuit board 1 and a semiconductor chip 3 mounted on the insulating circuit board 1 via a bonding layer 2. The bottom surface of the insulating circuit board 1 is bonded to a cooling plate 8 with solder 7. The periphery of the semiconductor chip 3 is sealed with a sealing member 9, and the semiconductor chip 3 is electrically insulated from the surroundings. The sealing member 9 is, for example, a gel, but may also be a resin such as an epoxy resin.

[0031] <Insulated Circuit Board> The insulating circuit board 1 includes an insulating substrate 11, an upper conductor layer 12 disposed on the upper surface of the insulating substrate 11, which is the circuit side, and a lower conductor layer 13 disposed on the lower surface of the insulating substrate 11, which is the cooling side. The upper conductor layer 12 includes upper conductor layers 12a, 12b, and 12c that are provided separately from one another. When the upper conductor layers 12a, 12b, and 12c are not to be distinguished from one another, they are simply referred to as upper conductor layers 12. The number of upper conductor layers 12 that are provided separately is not limited to that shown in FIG. 1 .

[0032] The insulating circuit board 1 may be, for example, a direct copper bond (DCB) board or an active matrix brazing (AMB) board. The insulating substrate 11 may be, for example, an aluminum oxide (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ The upper conductor layer 12 and the lower conductor layer 13 are made of a conductive foil or a conductive plate using a metal material such as copper (Cu) or aluminum (Al). In this embodiment, the upper conductor layer 12 and the lower conductor layer 13 are made of copper.

[0033] <Semiconductor Chip> The type of semiconductor chip 3 varies depending on the application, but for example, field effect transistors (FETs) such as IGBTs, reverse conducting IGBTs (RC-IGBTs), reverse blocking IGBTs (RB-IGBTs), MOSFETs, power semiconductor elements such as static induction (SI) thyristors and gate turn-off (GTO) thyristors, rectifying elements such as Schottky barrier diodes (SBDs), etc. can be used. The semiconductor chip 3 may be made of, for example, a silicon (Si) substrate, or may be made of silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ２ O ３ The semiconductor device according to the first embodiment may be configured with a compound semiconductor substrate made of a wide bandgap semiconductor such as a silicon nitride film. The semiconductor device according to the first embodiment may include one or more semiconductor chips 3. The semiconductor chip 3 is, for example, a power semiconductor chip.

[0034] When a MOSFET is mounted as the semiconductor chip 3, the semiconductor chip 3 has a control electrode (gate electrode) and an upper main electrode (source electrode) on the upper surface side, and a lower main electrode (drain electrode) on the lower surface side. When an IGBT or RC-IGBT is mounted as the semiconductor chip 3, the semiconductor chip 3 has a control electrode (gate electrode) and an upper main electrode (emitter electrode) on the upper surface side, and a lower main electrode (collector electrode) on the lower surface side. When an SI thyristor, GTO thyristor, or SBD is mounted as the semiconductor chip 3, the semiconductor chip 3 has an upper main electrode on the upper surface side, and a lower main electrode on the lower surface side. In this embodiment, a case where the semiconductor chip 3 is mounted with a MOSFET will be described as an example.

[0035] As shown in FIG. 3 , the semiconductor chip 3 has a rectangular shape in a plan view and four corners. As shown in FIG. 2 , the lower main electrode 3 a of the semiconductor chip 3 is bonded to the upper conductor layer 12 a by a bonding layer 2. The material constituting the lower main electrode 3 a is a metal material. In this embodiment, the lower main electrode 3 a is formed using nickel (Ni) and gold (Au). The lower main electrode 3 a is formed mainly using nickel, and its surface is covered with gold. As shown in FIG. 1 , the upper main electrode (not shown) of the semiconductor chip 3 is electrically connected to the upper conductor layer 12 b via, for example, a lead frame 5 made of a metal material. More specifically, one end of the lead frame 5 is bonded to the upper main electrode by solder 4 a, and the other end of the lead frame 5 is bonded to the upper conductor layer 12 b by solder 4 b. The control electrode (not shown) of the semiconductor chip 3 is electrically connected to the upper conductor layer 12 c via, for example, a wire 6 made of a metal material. More specifically, one end of the wire 6 is bonded to the control electrode, and the other end of the wire 6 is bonded to the upper conductor layer 12c. The solders 4a, 4b, and 7 shown in Fig. 1 are bonding materials made of a metallic material. Examples of the solder material that can be used include tin-antimony (SnSb)-based and tin-silver (SnAg)-based solder materials.

[0036] 2 , the bonding layer 2 is interposed between the lower main electrode 3 a and the upper conductor layer 12 a. The bonding layer 2 includes a solder material 2 a containing tin (Sn), a filler 2 b disposed in the solder material 2 a, and an alloy layer 2 c formed on the surface of the filler 2 b and made of an alloy of the tin contained in the solder material 2 a and the metal contained in the filler 2 b. The bonding layer 2 further includes an alloy layer 2 d formed on the surface of the lower main electrode 3 a and an alloy layer 2 e formed on the surface of the upper conductor layer 12 a.

[0037] The solder material 2a is a joining material made of a metallic material. The main material constituting the solder material 2a is, for example, tin, with various materials added to the tin. Examples of solder materials that can be used for the solder material 2a include tin-antimony (SnSb) and tin-silver (SnAg) solder materials. In this embodiment, an example using Sn-5Sb as the solder material 2a will be described. Note that the same material as the solder material 2a may be used for the solders 4a, 4b, and 7. In the manufacturing process of the semiconductor device according to the first embodiment, the solder material 2a melts when heated. The molten solder material 2a then joins the lower main electrode 3a to the upper conductor layer 12a. The tin contained in the molten solder material 2a forms an alloy layer 2d with the metal material (mainly nickel) constituting the lower main electrode 3a and an alloy layer 2e with the metal material (mainly copper) constituting the upper conductor layer 12a. The solder material 2a then solidifies when cooled. The solidified solder material 2a extends between the alloy layer 2d and the alloy layer 2e. The alloy layer 2d is formed so as to cover the lower main electrode 3a, and the alloy layer 2e is formed so as to cover the upper conductor layer 12a.

[0038] As shown in Fig. 3, the fillers 2b are provided at each of the four corners of the semiconductor chip 3 in a planar view. More specifically, the fillers 2b are arranged at positions that overlap with the four corners of the semiconductor chip 3 in a planar view. Note that, although one filler 2b is arranged at each corner in Fig. 3, multiple fillers 2b may be arranged at each corner. Furthermore, the number of fillers 2b arranged at each corner may be the same for all corners, or may be different for each corner.

[0039] As shown in FIG. 2 , the thickness d1 of the filler 2b is equivalent to the thickness d2 of the bonding layer 2. "Equivalent" means that the thickness d1 of the filler 2b is approximately 90% or more of the thickness d2 of the bonding layer 2 and is equal to or less than the thickness d2 of the bonding layer 2 (0.9 × d2 ≦ d1 ≦ d2). Furthermore, to prevent large differences in the thickness of the bonding layer 2 in plan view, it is desirable that the thicknesses d1 of the filler 2b be as uniform as possible across multiple fillers. For example, by sieving the filler 2b in advance, fillers that are too large or too small can be removed. For example, by sieving the filler 2b through multiple sieves with different mesh sizes, fillers that are too large or too small can be removed. The thickness d1 of the filler 2b can be determined based on the target thickness d2 of the bonding layer 2. The thickness d1 of the filler 2b is, for example, approximately 20 μm or more and 50 μm or less. Furthermore, for example, when the target thickness d2 of the bonding layer 2 is 50 μm, it is sufficient to use filler 2b having a thickness d1 of about 90% or more of 50 μm and about 50 μm or less.

[0040] In this embodiment, the filler particles 2b have a spherical shape as shown in FIGS. 2 and 3 . The shape of the filler particles 2b may be other than spherical, such as a scale-like or needle-like shape. The scale-like filler particles 2b have a scale-like, metal flake-like, or crushed sphere-like shape, and can be formed, for example, as a fine powder obtained by scraping or melting a raw metal material. The needle-like filler particles 2b are, for example, needle-like metal crystals. The longitudinal dimension of the needle-like filler particles 2b is equal to or greater than the diameter and approximately 110% or less of the diameter. Compared to flat, plate-like metal pieces, the spherical, scale-like, and needle-like crystal filler particles 2b have a smaller contact area with the lower main electrode 3a and the upper conductor layer 12a.

[0041] The filler 2b includes a metal material capable of forming an alloy with the solder material 2a. More specifically, the filler 2b includes a metal material capable of forming an alloy with tin contained in the solder material 2a. Hereinafter, the metal material capable of forming an alloy with tin will be referred to as the first metal. The filler 2b consists solely of the first metal or mainly contains the first metal. Furthermore, the inside of the filler 2b, for example, within 10 μm, may not contain the first metal and may instead be made of an insulator such as ceramic. Furthermore, a metal material with a melting point higher than that of the solder material 2a is used as the first metal. For example, the melting point of the solder material 2a is approximately 240°C, and the melting point of the first metal is 270°C or higher. The first metal may be, for example, tellurium (Te: 449.5°C), titanium (Ti: 1668.0°C), thallium (Tl: 304.0°C), vanadium (V: 1910.0°C), yttrium (Y: 1526.0°C), zinc (Zn: 419.5°C), zirconium (Zr: 1855.0°C), arsenic (As: 817.0°C), gold (Au: 1064.2°C), silver (Ag: 961.8°C), bismuth (Bi: 271.5°C), cadmium (Cd: 321.1°C), or cobalt. The melting point of the first metal is any one of the following: (Co: 1495.0°C), copper (Cu: 1084.6°C), iron (Fe: 1538.0°C), germanium (Ge: 938.3°C), magnesium (Mg: 650.0°C), manganese (Mn: 1246.0°C), niobium (Nb: 2477.0°C), nickel (Ni: 1455.0°C), lead (Pb: 327.5°C), palladium (Pd: 1554.9°C), platinum (Pt: 1768.3°C), and antimony (Sb: 630.6°C). Note that for some of the above first metals, the melting point is shown along with the substance name. In this embodiment, the first metal is described as copper.

[0042] The alloy layer 2c will now be described. In the manufacturing process of the semiconductor device according to the first embodiment, the solder material 2a melts when heated. The tin contained in the molten solder material 2a combines with the first metal (copper) contained in the filler 2b to form an alloy layer 2c. The alloy layer 2c is formed to cover the filler 2b. The alloy layer 2c is a pillar connecting the lower main electrode 3a and the upper conductor layer 12a along the thickness direction of the bonding layer 2. The junction between the alloy layer 2c and the upper conductor layer 12a may include both the alloy layer 2c and the alloy layer 2e. The junction between the alloy layer 2c and the lower main electrode 3a may include both the alloy layer 2c and the alloy layer 2d. The alloy layer 2c is provided on the surface of the filler 2b to a thickness of, for example, about 10 μm or more and about 15 μm or less. The alloy layer 2d is provided on the surface of the lower main electrode 3a to a thickness of, for example, about 1 μm. The alloy layer 2e is provided on the surface of the upper conductor layer 12a to a thickness of, for example, approximately 2 μm. The filler 2b and the upper conductor layer 12a are made of copper, but because the filler 2b, unlike the upper conductor layer 12a, is not subjected to high-temperature heat treatment, the thickness of the alloy layer 2c is greater than the thickness of the alloy layer 2e. The thicker the alloy layer 2c, the stronger the connection strength between the lower main electrode 3a and the upper conductor layer 12a. By providing the alloy layer 2c as a thick film with a thickness of 10 μm or more, the connection strength between the lower main electrode 3a and the upper conductor layer 12a can be further increased. Note that, because the mere presence of the alloy layer 2c is sufficient to increase the connection strength between the lower main electrode 3a and the upper conductor layer 12a, the thickness of the alloy layer 2c may be less than 10 μm. The thickness of the alloy layer 2c may be, for example, 2 μm or more. The thickness of the alloy layer 2c may also be, for example, a thin film with a thickness of 2 μm or more but less than 10 μm.

[0043] Since the melting point and strength of the first metal are higher than those of the solder material 2a, the melting point and strength of the alloy layer 2c are also higher than those of the solder material 2a. Similarly, the melting points and strengths of the alloy layers 2d and 2e are also higher than those of the solder material 2a. Because the alloy layer 2c is formed on the surface of the filler 2b, the planar position of the alloy layer 2c can be controlled by controlling the planar position of the filler 2b. In this embodiment, by providing the filler 2b at each of the four corners of the semiconductor chip 3 in a planar view, the alloy layer 2c can be provided at each of the four corners of the semiconductor chip 3 in a planar view.

[0044] <Method for Manufacturing Semiconductor Device> The following describes a method for manufacturing a semiconductor device according to the first embodiment. Note that in this embodiment, the joining of the semiconductor chip 3 to the upper conductor layer 12 a of the insulating circuit board 1 will be described, and descriptions of other solder joining and other manufacturing steps will be omitted.

[0045] First, a paste solder material is applied to the area of ​​the upper surface of the upper conductor layer 12a where the semiconductor chip 3 will be mounted. The solder material is applied using, for example, a squeegee. The particle diameter of the particles contained in the paste solder material is equal to or smaller than the target thickness of the bonding layer 2. The particle diameter is, for example, approximately 15 μm or less. Next, filler 2b is placed on the upper surface of the applied paste solder material using, for example, a mounter. The filler 2b is premixed with liquid flux and applied to the four corners of the paste solder material together with the liquid flux. The amount of filler 2b placed in one location is approximately 1 / 2000 or more and 1 / 1000 or less by weight (wt%) of the paste solder material. The number of fillers 2b placed in one location may be one or more. Then, the semiconductor chip 3 is placed on the paste solder material and filler 2b. When the semiconductor chip 3 is placed, the filler 2b is pressed by the semiconductor chip 3 and sinks into the paste-like solder material. Filler 2b, which has a small contact area with the lower main electrode 3a and the upper conductor layer 12a, sinks into the paste-like solder material more easily than a flat, plate-like metal piece. The solder material is then heated in a nitrogen furnace or formic acid furnace. The heating temperature is, for example, about 270°C, and the heating time is about 3 minutes at peak temperature. The solder material is melted to bond the semiconductor chip 3 to the upper conductor layer 12a, forming alloy layers 2c, 2d, and 2e. The solder material is then cooled and solidified, yielding the solder material 2a.

[0046] <<Major Effects of the First Embodiment>> In the semiconductor device according to the first embodiment, the bonding layer 2, which bonds the lower main electrode 3a of the semiconductor chip 3 to the upper conductor layer 12a, includes a solder material 2a containing tin and a filler 2b containing a first metal having a melting point higher than that of the solder material 2a and disposed within the solder material 2a. Therefore, the filler 2b functions as a spacer, allowing the thickness of the bonding layer 2 to be formed to be approximately the same as that of the filler 2b. This allows the thickness of the bonding layer 2 to be reduced, thereby reducing the thermal resistance and electrical resistance of the bonding layer 2. Furthermore, the melting point and strength of the alloy layer 2c are higher than those of the solder material 2a. Therefore, even when the bonding layer 2 is thin, a decrease in reliability can be suppressed. Furthermore, the alloy layer 2c, which has a melting point and strength higher than those of the solder material 2a, connects the lower main electrode 3a and the upper conductor layer 12a, thereby increasing the bonding strength between the semiconductor chip 3 and the insulating circuit board.

[0047] Furthermore, in the semiconductor device according to the first embodiment, the alloy layer 2c is provided on the surface of the filler 2b to a thickness of 2 μm. Therefore, even if the bonding layer 2 is provided to be thin, a decrease in reliability can be suppressed. Furthermore, in the semiconductor device according to the first embodiment, the alloy layer 2c is provided on the surface of the filler 2b to a thickness of 10 μm or more. By providing the alloy layer 2c as a thick film, a decrease in reliability can be further suppressed even if the bonding layer 2 is provided to be thin.

[0048] Furthermore, in the semiconductor device according to the first embodiment, filler 2b and alloy layer 2c are provided at each of the four corners of semiconductor chip 3 in a plan view. This increases the strength of bonding layer 2 located near the four corners of semiconductor chip 3. This makes it less likely for cracks to occur at the corners of bonding layer 2. Furthermore, since filler 2b is disposed at multiple positions, it is possible to prevent the thickness of bonding layer 2 from becoming significantly uneven.

[0049] 4, the semiconductor device according to the first modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 3 in that fillers 2b are provided not only at the four corners in a plan view of the semiconductor chip 3 but also on the outer periphery in a plan view of the semiconductor chip 3. Other configurations of the semiconductor device according to the first modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted.

[0050] By disposing filler 2b and alloy layer 2c in the portion of bonding layer 2 where cracks are likely to occur, it is possible to reinforce the portion of bonding layer 2 where cracks are likely to occur. Cracks may occur not only at the corners of bonding layer 2 but also at the outer periphery of bonding layer 2. Therefore, filler 2b is also disposed in a position that overlaps with the outer periphery of semiconductor chip 3 in a plan view. Filler 2b may be disposed in multiple positions along the outer periphery of semiconductor chip 3. This allows alloy layer 2c to be provided also on the outer periphery of bonding layer 2.

[0051] According to the semiconductor device of the first modification of the first embodiment, filler 2b is provided near both the four corners and the outer periphery of semiconductor chip 3, which makes it possible to further suppress a decrease in reliability even when bonding layer 2 is made thin. Also, the bonding strength between semiconductor chip 3 and insulating circuit board can be further increased.

[0052] 5 and 6, the semiconductor device according to the second modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 3 in that a laser resist region LR is provided on the top surface of the upper conductor layer 12a. Other configurations of the semiconductor device according to the second modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted.

[0053] A laser resist region LR is provided on the upper surface of the upper conductor layer 12a before applying the solder material. The laser resist region LR is formed by irradiating the upper surface of the upper conductor layer 12a with laser light. Irradiation with laser light creates unevenness on the upper surface of the upper conductor layer 12a. The laser resist region LR may also be a groove recessed from the rest of the upper surface of the upper conductor layer 12a. The laser resist LR may also be in the form of an oxide film. The filler 2b is disposed on the laser resist region LR. By providing the laser resist region LR on the upper surface of the upper conductor layer 12a, the filler 2b disposed on the laser resist region LR is less likely to move when the solder material 2a is heated and melted during the manufacturing process. Note that when the filler 2b is disposed on the upper surface of the paste-like solder material during the manufacturing process, the laser resist region LR is covered by the paste-like solder material. However, by determining the position of the laser resist region LR using coordinates, the filler 2b can be disposed above the laser resist region LR.

[0054] As shown in Fig. 5, the laser resist region LR may be linear in plan view. More specifically, the laser resist region LR may be rectangular and annular in plan view. Furthermore, as shown in Fig. 6, the laser resist region LR may be provided in the form of a spot at the position where the filler 2b is to be disposed.

[0055] According to the semiconductor device of the second modification of the first embodiment, the laser resist region LR is provided on the upper surface of the upper conductor layer 12 a, which prevents the filler 2 b from being significantly misaligned during the manufacturing process. This prevents the filler 2 b from being significantly misaligned from the portion of the bonding layer 2 where cracks are likely to occur, and allows the portion of the bonding layer 2 where cracks are likely to occur to be reinforced with high precision.

[0056] [Summary] Power semiconductors are semiconductor devices capable of passing large currents at high voltages, handling DC and AC voltages, and converting them into DC and AC voltages. Power semiconductors can change the voltage and frequency of AC voltages and are often used to control motor rotation. A typical power semiconductor device includes, for example, a semiconductor chip with semiconductor elements such as an IGBT or MOSFET, a printed circuit board (PCB), an insulating circuit board, and a heat dissipation base. Solder materials and sintered materials are used to bond the semiconductor chip, insulating circuit board, and heat dissipation base. In recent years, power semiconductor devices have become increasingly highly integrated due to demands for smaller, lighter, and more sophisticated functionality. Furthermore, development is underway for semiconductor devices using semiconductor elements such as silicon carbide (SiC) capable of high-temperature operation, and high reliability is required for semiconductor devices in high-temperature operating environments.

[0057] Tin-antimony (SnSb)-based and tin-silver (SnAg)-based solders have been widely used as bonding materials for semiconductor devices. However, as the operating temperature of semiconductor devices approaches the melting point of the solder, there are concerns about a decrease in reliability. Therefore, sintered metal layers that utilize the sintering action of metal particles such as silver (Ag) and copper (Cu) have begun to be used as bonding materials that can withstand high-temperature operation.

[0058] Power semiconductor devices incorporate circuits that handle large currents, generating heat locally due to high resistance and poor heat transfer in the circuit wiring connections. In power semiconductor devices using silicon carbide (SiC) and other materials, the internal current increases, making it important for the electrical circuit to minimize heat generation (internal loss). However, conventional soldering methods require a thick solder joint layer to ensure reliability, making it difficult to minimize thermal and electrical conduction.

[0059] Sintered materials are available in two pre-bonding forms: paste and sheet. In either case, achieving high-strength sintered material joints requires simultaneous pressure (20 MPa or greater) and heating (250°C or greater). Therefore, during bonding, multiple semiconductor chips are placed on the sintered material placed on an insulating substrate, and the chips are sintered by simultaneously applying pressure and heating to the top surface of the chips. As shown in Figure 7, the electrical resistance and thermal resistance of solder are an order of magnitude higher (thermal conductivity is an order of magnitude lower) than those of sintered materials and copper materials, and the volume resistance increases even further when heated to 200°C. Therefore, the soldered joints are both a heat source and a thermal resistance to the chip's heat dissipation, resulting in temperature increases. The bonding material must be strong enough to withstand high temperatures, and soldered joints lose strength at high temperatures.

[0060] However, when comparing costs, the cost of soldering materials is about 1 / 100 of the cost of sintered materials, and the price of the joining equipment can also be kept low at about 1 / 10, so there are significant cost benefits to using soldering materials.

[0061] Although alloying the solder joint layer with the first metal increases its strength, forming an alloy layer throughout the entire surface requires a long heating time, making it an extremely difficult manufacturing method. With current solder joints, a solder alloy layer is formed on the chip surface electrodes or the surface of the object to be joined, with a thickness of several microns. Adding another object to be joined within the solder layer and bringing the chip and object into contact with each other forms an alloy layer with the object as the core, enabling the chip and object to be connected by an alloy layer. Because the solder alloy layer has high mechanical strength, high reliability can be achieved even when the solder joint layer is thin. Furthermore, thinning the solder joint layer also makes it possible to keep electrical resistance and thermal conductivity low.

[0062] [Other Embodiments] As described above, the first embodiment of the present disclosure and its modified examples have been described, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0063] Furthermore, the configurations disclosed in the first embodiment and its modified examples can be appropriately combined within a range that does not cause contradictions. For example, the filler 2b shown in FIG. 4 may be combined with the laser resist region LR shown in FIGS. 5 and 6. As such, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is defined only by the invention-specifying matters according to the claims that are appropriate from the above description.

[0064] REFERENCE SIGNS LIST 1 Insulated circuit board 2 Bonding layer 2a Solder material 2b Filler 2c, 2d, 2e Alloy layer 3 Semiconductor chip 3a Lower main electrode 4a, 4b, 7 Solder 5 Lead frame 8 Cooling plate 9 Sealing member 11 Insulating substrate 12, 12a, 12b, 12c Upper conductor layer 13 Lower conductor layer

Claims

1. A semiconductor device comprising: a semiconductor chip having a lower main electrode on its underside; an insulated circuit board including an insulating substrate and an upper conductor layer disposed on the upper surface of the insulating substrate; and a bonding layer that bonds the lower main electrode of the semiconductor chip to the upper conductor layer, wherein the bonding layer includes a solder material containing tin, a filler that contains a first metal having a higher melting point than the solder material and is disposed in the solder material, and an alloy layer that is made of an alloy of the tin contained in the solder material and the first metal and is provided on the surface of the filler, and the alloy layer connects the lower main electrode and the upper conductor layer.

2. The semiconductor device according to claim 1, wherein the alloy layer is provided on the surface of the filler to a thickness of 10 μm or more.

3. The semiconductor device according to claim 1 or 2, wherein the thickness of the filler is equal to the thickness of the bonding layer.

4. The semiconductor device according to claim 1 or 2, wherein the filler is provided at least at each of four corners of the semiconductor chip in a plan view.

5. The semiconductor device according to claim 4, wherein a laser resist region is provided on the upper surface of the upper conductor layer, and the filler is disposed on the laser resist region.

6. The semiconductor device according to claim 1 or 2, wherein the first metal is a metal capable of forming an alloy with tin, and the melting point of the first metal is 270°C or higher.

7. The semiconductor device according to claim 6, wherein the first metal is any one of tellurium, titanium, thallium, vanadium, yttrium, zinc, zirconium, arsenic, gold, silver, bismuth, cadmium, cobalt, copper, iron, germanium, magnesium, manganese, niobium, nickel, lead, palladium, platinum, and antimony.

8. The semiconductor device according to claim 1, wherein the alloy layer is provided on the surface of the filler to a thickness of 2 μm or more.

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