Chip interconnection processing method, and chip

Abstract

Provided in the embodiments of the present disclosure are a chip interconnection processing method, and a chip. The method comprises: providing at least two controllers inside each chip among some or all of a plurality of chips, wherein the at least two controllers are connected to an internal bus; and by means of the at least two controllers of each chip among some or all of the chips, interconnecting the plurality of chips on the basis of a peripheral component interconnect express (PCIe) bus.

Description

Chip interconnection processing method and chip

[0001] Cross-reference of related disclosures

[0002] The present disclosure is based on Chinese Patent Publication 2024108397944 entitled "Chip interconnection processing method and chip" filed on June 26, 2024, and claims priority to the patent publication, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the field of chips, in particular, to a chip interconnection processing method and a chip. BACKGROUND

[0004] Peripheral Component Interconnect Express (PCIe) is a high-performance serial computer bus standard, that is, it can be applied to the connection of peripheral devices (such as graphics processors, network adapters, storage devices, etc.) and the interconnection between internal subsystems of chips. A device / chip that supports PCIe bus interface for interconnection can be referred to as a PCIe device / chip.

[0005] When there are only 2 PCIe chips that need to be interconnected in a system, they can be directly connected through a PCIe link, one of which is a Root Complex (RC) and the other is an End Point (EP). When multiple (more than 2) PCIe chips need to be interconnected in an actual system, a PCIe Switch chip needs to be used. The chips that need to be interconnected are all connected to a multi-port PCIe Switch through a PCIe link, realizing access between any two chips, as shown in FIG. 2, one of which is an RC and the others are EPs. However, the addition of a PCIe Switch chip in the system causes all communication links between chips in the system to pass through the PCIe Switch, which not only greatly increases the complexity of system communication link management and software and hardware design, but also increases the power consumption and cost of chips. Moreover, the number of single-chip ports of a PCIe Switch is limited, and the interconnection networking structure is usually limited to star or tree, which makes the flexibility of the system interconnection structure not high. In addition, the PCIe Switch needs to be integrated into a certain single board in the system, which will cause some single boards to contain a PCIe Switch chip and some not to contain, resulting in insufficient symmetry of the interconnection single board.

[0006] There is no solution to the problem of the contradiction between the interconnection needs of multiple chips and the system complexity and cost in the related art. SUMMARY

[0007] The chip interconnection processing method and chip are provided.

[0008] According to an embodiment of the present disclosure, a chip interconnection processing method is provided, applied to a chip, and the method comprises:

[0009] At least two controllers are arranged in part or all of the plurality of chips, wherein the at least two controllers are connected to an internal bus;

[0010] The plurality of chips are interconnected by the at least two controllers of the part or all of the plurality of chips based on a Peripheral Component Interconnect Express (PCIe) bus.

[0011] According to another embodiment of the present disclosure, a chip is provided, comprising: at least two controllers connected to an internal bus, wherein,

[0012] The at least two controllers are configured to be interconnected with controllers of other chips based on a Peripheral Component Interconnect Express (PCIe) bus.

[0013] According to still another embodiment of the present disclosure, a computer program product is also provided, comprising computer program instructions, wherein the computer program instructions cause a computer to implement the steps in any of the above method embodiments.

[0014] According to still another embodiment of the present disclosure, a computer readable storage medium is also provided, wherein the storage medium stores a computer program, and the computer program is configured to execute the steps in any of the above method embodiments when running.

[0015] According to still another embodiment of the present disclosure, an electronic device is also provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0016] FIG. 1 is a hardware structure block diagram of a computer device of a chip interconnection processing method according to an embodiment of the present disclosure;

[0017] FIG. 2 is a flowchart of a chip interconnection processing method according to an embodiment of the present disclosure;

[0018] FIG. 3 is a flowchart of a chip interconnection processing method according to an optional embodiment of the present disclosure;

[0019] FIG. 4 is a schematic diagram of a plurality of chips interconnected by a PCIe Switch in the related art;

[0020] FIG. 5 is a structural schematic diagram of software configuration according to an embodiment of the present disclosure;

[0021] FIG. 6 is a schematic diagram of a chain topology according to an embodiment of the present disclosure;

[0022] FIG. 7 is a schematic diagram of a star topology according to an embodiment of the present disclosure;

[0023] FIG. 8 is a schematic diagram of a ring topology according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0025] It should be noted that the terms "first", "second" and the like in the description and claims of the embodiments of the present disclosure and the above-described accompanying drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence.

[0026] The method embodiments provided in the embodiments of the present disclosure can be executed in a computer device or a similar computing device. Taking an example of running on a computer device, FIG. 1 is a hardware structure block diagram of a computer device for a chip interconnection processing method according to an embodiment of the present disclosure, as shown in FIG. 1, the computer device can include one or more (only one is shown in FIG. 1) processors 102 (the processor 102 can include but is not limited to a processing device such as a microprocessor MCU or programmable logic device) and a memory 104 configured to store data, wherein the above-mentioned computer device can further include a transmission device 106 configured to have a communication function and an input and output device 108. Those skilled in the art can understand that the structure shown in FIG. 1 is only schematic, which does not limit the structure of the above-mentioned computer device. For example, the computer device can further include more or less components than those shown in FIG. 1, or have a different configuration from that shown in FIG. 1.

[0027] The memory 104 can be configured to store computer programs, for example, software programs of application software and modules, such as a computer program corresponding to the chip interconnection processing method in the embodiments of the present disclosure. The processor 102 executes various function applications and single board matching by running the computer program stored in the memory 104, that is, implements the above-mentioned method. The memory 104 can include a high-speed random access memory, and can further include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, and these remote memories can be connected to the computer device through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0028] The transmission device 106 is configured to receive or send data via a network. The network can include a wireless network provided by a communication provider of the computer device. In an example, the transmission device 106 includes a network interface controller (NIC) that can be connected to other network devices through a base station to communicate with the Internet. In an example, the transmission device 106 can be a radio frequency (RF) module configured to communicate with the Internet in a wireless manner.

[0029] In the embodiment, a chip interconnection processing method running on the computer device is provided. FIG. 2 is a flowchart of the chip interconnection processing method according to the embodiment of the present disclosure. As shown in FIG. 2, the method is applied to a chip and includes the following steps.

[0030] In step S202, at least two controllers are arranged in part or all of the plurality of chips, and the at least two controllers are connected to an internal bus.

[0031] In step S204, the plurality of chips are interconnected based on a peripheral component interconnect express (PCIe) bus through the at least two controllers of part or all of the plurality of chips.

[0032] Through the above steps S202 to S204, at least two controllers are arranged in part or all of the plurality of chips, and the at least two controllers are connected to an internal bus. The plurality of chips are interconnected based on a peripheral component interconnect express (PCIe) bus through the at least two controllers of part or all of the plurality of chips. The problem that the interconnection requirement of the plurality of chips and the system complexity and cost are contradictory in the related art can be solved. The PCIe switch is not needed, and the interconnection access between the plurality of PCIe chips can be implemented. The hardware structure is simpler, and the cost is lower.

[0033] In the embodiments of the present disclosure, the at least two controllers include original controllers and newly added controllers, and the step S204 can specifically include: determining an interconnection topology of the plurality of chips based on system requirements; and interconnecting the controllers in the two chips to be connected in the plurality of chips based on the PCIe bus according to the interconnection topology, wherein in the process of interconnection, the two chips to be connected are connected through the controllers. The interconnection topology in the embodiments includes at least one of the following: a chain topology, a star topology, and a ring topology. If the chain topology is adopted, the chips at both ends of the topology do not need to add controllers, that is, the original controllers can be retained, and the chips at both ends only need to be connected with adjacent chips, and the chips in the middle of the topology all include two controllers and are connected with the controllers of adjacent chips. If the star topology is adopted, the chips at the end points of the topology do not need to add controllers, and the chips that are not at the end points include at least two controllers. If the ring topology is adopted, each chip includes two controllers.

[0034] FIG. 3 is a flowchart of a chip interconnection processing method according to an optional embodiment of the present disclosure. As shown in FIG. 3, the method further includes:

[0035] Step S302: determining the type of the controller of each chip relative to the bus;

[0036] Step S304: configuring an internal bus address range for the controller of each chip.

[0037] Step S306: performing address routing across chips according to the type of the controller relative to the bus and the internal bus address range.

[0038] In an embodiment, the step S306 can specifically include: for each chip, if the type of the controller relative to the bus is a master device, initiating a first address access request; if the type of the controller relative to the bus is a slave device, receiving the first address access request, wherein the first address access request carries a to-be-accessed address; in a case where the to-be-accessed address is within the corresponding internal bus address range, accessing an internal component according to the to-be-accessed address; and in a case where the to-be-accessed address is outside the corresponding internal bus address range, sending the first address access request to the controller of the next chip connected based on the PCIe bus.

[0039] In another embodiment, step S306 can specifically include: for each chip, if the controller is a master device relative to the bus, initiating the first address access request; if the controller is a slave device relative to the bus, receiving the first address access request carrying the to-be-accessed address; in a case where the to-be-accessed address is within the corresponding internal bus address range, accessing the internal component according to the to-be-accessed address; in a case where the to-be-accessed address is outside the corresponding internal bus address range, converting the to-be-accessed address into an external PCIe address based on a preset mapping relationship between the internal bus address and the external PCIe address, and sending a second address access request carrying the converted external PCIe address to the controller of the next-level chip based on the PCIe bus.

[0040] Further, in the preset inbound register or outbound register of the controller, the to-be-accessed address is converted into the external PCIe address based on the mapping relationship.

[0041] In the embodiments of the present disclosure, step S302 can specifically include:

[0042] S3021, determining the access requirement of the controller.

[0043] S3022, determining the type of the controller relative to the bus according to the access requirement of the controller.

[0044] Further, S3022 can specifically include: in a case where the access requirement of the controller is to access the internal space of other chips through the PCIe bus, setting the type of the controller as a master device, which means supporting initiating access to the bus; in a case where the access requirement of the controller is to support other chips to access the local space, setting the type of the controller as a slave device, which means supporting responding to the access of other master devices on the bus; in a case where the access requirement of the controller is to access the internal space of other chips through the PCIe bus and to support other chips to access the local space, setting the type of the controller as a master device and a slave device, that is, as a master device and a slave device.

[0045] In an embodiment, the method further includes: setting a root component (RC) side chip for the PCIe link between each two connected chips; monitoring and collecting the status of the PCIe link through the RC side chip, and reporting the link status to the upper-level chip, which can be reported according to a reporting period preset by the master control chip; in a case where the link status reported by the next-level chip is not received within a timeout period preset by the master control chip, determining that the PCIe link with the next-level chip is faulty, and reporting the link status of the faulty PCIe link to the upper-level chip.

[0046] On the basis of the original PCIe interface of the chip of the embodiment of the disclosure, a PCIe interface for interconnection with other chips is added, and these interfaces are interconnected through an internal bus in the chip through a PCIe controller. With the address routing of the internal bus, the access from the original interface can be routed to the internal modules of the chip or to the interconnected PCIe interface to reach another chip. When similar interface expansion and internal bus address routing are also adopted on other chips in the system, multiple PCIe chips can be interconnected. Without using a PCIe switch, the interconnection and access between multiple PCIe chips can be realized, the hardware structure is simpler, and the cost is lower. Meanwhile, in the interconnection of single boards of the same type, a PCIe switch chip does not need to be embedded in a single board, and the symmetry of the hardware structure of the single board is better. The interconnection structure between multiple PCIe chips of the embodiment of the disclosure is more flexible, can form various topological structures such as a chain, a ring, and a star, and can reduce access delay through a similar ring topological structure. Based on the internal bus address routing of the chip, the 64-bit address space can be fully utilized for unified addressing, and the upper-layer software application is more friendly. The contradiction between the interconnection demand of multiple PCIe chips and the system complexity and cost can be well solved.

[0047] The hardware part of the embodiment of the disclosure is one or more additional PCIe controllers in the chip, which are arranged to be interconnected with other chips through a PCIe bus. FIG. 4 is a schematic diagram of the interconnection of multiple chips through a PCIe switch in the related art. As shown in FIG. 4, only one PCIe controller is needed for each chip. Compared with the interconnection after the PCIe switch is removed, one or more additional PCIe controllers need to be added in the chip, the controller is connected to an internal bus (such as an AMBA AXI bus, a MicroBlaze bus, etc.) in the chip, and is connected to other chips outside the chip. After the PCIe switch is removed, the interconnection between the chips can form various topological structures, including but not limited to the following structures: a chain structure, in which one PCIe controller 2 needs to be added to each of the intermediate chips except chip 1 and chip N; a star structure, in which N-2 PCIe controllers need to be added to the intermediate chip 2; and a ring structure, in which one PCIe controller 2 needs to be added to each of the chips 1-N, which is arranged to be connected to other chips. N is the number of chips to be interconnected.

[0048] The software part of the embodiment of the disclosure includes the following three modules. FIG. 5 is a structural schematic diagram of the software configuration according to the embodiment of the disclosure. As shown in FIG. 5, the software configuration includes the following three modules:

[0049] Bus address space configuration module inside the chip: PCIe controller inside the chip can be master or slave relative to internal bus. If PCIe controller needs to be slave device of the bus, it needs to configure its address range in internal bus.

[0050] Address mapping configuration module of PCIe controller: configure inbound and outbound registers of PCIe controller of each chip, set address mapping of inbound and outbound, complete address conversion between internal bus domain and external PCIe bus domain.

[0051] Link management module: set to manage link state, including bandwidth management, error detection and reporting, etc. First, set the system master chip as the management master; then each pair of RC and EP as a standard point-to-point PCIe link, independently perform link management (for example, use standard PCIe link management technology LTM); finally, the CPU of each chip reports to the CPU of the upper RC by interrupt and other ways until it is reported to the first chip. The first chip presents the global link state to the user after obtaining it.

[0052] The multi-chip interconnection in the embodiment of the disclosure can include the following steps:

[0053] Step 1, determine the hardware interconnection relationship between chips. According to system requirements, select a suitable chip interconnection topology, including but not limited to chain topology, star topology, ring topology and their combinations. In order to meet the connection relationship, the corresponding chip needs to add additional PCIe controller and PCIe bus. At the same time, according to the system interconnection requirement, configure RC / EP relationship for each PCIe link.

[0054] Step 2, determine the type of each PCIe controller relative to the internal bus inside each chip. It can be master (master device initiates access to the bus), slave (slave device responds to access of other master devices on the bus) or both master and slave. If the chip needs to access the internal space of other chips through the PCIe bus, it needs to be configured as a master type; if the chip supports access to the local space by other chips, it needs to be configured as a slave type.

[0055] Step 3, initialize the bus address space configuration module, configure the internal bus address range (BAR space) for each chip's individual PCIe controller. For the slave type, assign a bus address space range, when there is a master inside the chip initiating an address access to the bus, if the address falls within the PCIe controller's bus address range space, the PCIe controller will respond. For the master type, no internal bus address range needs to be assigned.

[0056] Step 4, initialize the inbound / outbound address mapping configuration module, configure the inbound and outbound registers for each chip's individual PCIe controller, and determine the mapping relationship between the chip's internal bus address space and the external PCIe address space.

[0057] Through steps 3 and 4, after the chips are interconnected through the PCIe bus hardware, the address routing across the chips can be realized through one or more levels of chip internal bus address space and PCIe bus domain address space conversion, achieving the purpose of mutual access between chips.

[0058] Step 5, initialize the link management module. Determine the master chip as the link management master, then the RC side of each PCIe link is responsible for completing the management initialization of the link, and starts monitoring the link state.

[0059] Step 6, initiate address access. When a certain module (such as a CPU core) inside a chip initiates an address access, the bus routes the address, and when the address falls within the PCIe controller's bus address range, the access is routed to the PCIe controller, and after the PCIe controller outbound address conversion, the address is converted into a PCIe bus address and sent to the PCIe bus. After being sent to the opposite chip, the opposite chip receives and converts it into the internal bus address of the chip through inbound address conversion, and routes it by the chip bus. If the address is within the address range of a module of the chip, access the module; if the address is within the address range of another PCIe controller, route the next PCI link. Repeat the process, and different addresses will eventually be routed to different internal modules of the chip.

[0060] Step 7, link state management reporting. The master chip configures the link reporting period T0 and the timeout time T1, and the RC side chip of each PCIe link is responsible for monitoring and collecting the state of the PCIe link, and periodically reporting to the upper level according to the configured T0 time. If a link is timed out due to a fault, the fault state of the link needs to be reported in the report.

[0061] The embodiments of the present disclosure are described in detail below by way of examples.

[0062] Figure 6 is a schematic diagram of a chain topology according to an embodiment of the present disclosure. As shown in Figure 6, N is 4, i.e. 4-chip interconnection, and chip 1 needs to access the internal space of all other chips. The internal address size of each chip is 2G, and 8G of address space is required for uniform addressing of 4 chips. Specifically, the following steps are included:

[0063] 1. Determine the hardware interconnection relationship between chips. According to system requirements, a suitable chip interconnection topology is selected as a chain topology. In order to meet the connection relationship, chip 2 and chip 3 need to add PCIe controller 2. The chain connection relationship is as follows:

[0064] Chip 1 PCIe controller 1 (RC) --- Chip 2 PCIe controller 1 (EP);

[0065] Chip 2 PCIe controller 2 (RC) --- Chip 3 PCIe controller 1 (EP);

[0066] Chip 3 PCIe controller 2 (RC) --- Chip 4 PCIe controller 1 (EP);

[0067] 2. Determine the type of each PCIe controller relative to the bus in each chip. Since only chip 1 has the need to access the internal space of other chips, the type of each PCIe controller relative to the bus in each chip is as follows:

[0068] Chip 1 PCIe controller 1: slave;

[0069] Chip 2 PCIe controller 1: master;

[0070] Chip 2 PCIe controller 2: slave;

[0071] Chip 3 PCIe controller 1: master;

[0072] Chip 3 PCIe controller 2: slave;

[0073] Chip 4 PCIe controller 1: master.

[0074] 3. Initialize the bus address space configuration module to configure the internal bus address range (BAR space) for each PCIe controller of each chip as follows:

[0075] Chip 1 PCIe controller 1: 2G-8G;

[0076] Chip 2 PCIe controller 2: 2G-6G;

[0077] Chip 3 PCIe controller 2: 2G-4G.

[0078] 4, initialize inbound / outbound address mapping configuration module, configure inbound and outbound registers for each chip's respective PCIe controller, determine the mapping relationship between the chip internal bus address space and the external PCIe address space.

[0079] RC side does not map, address is passed through; EP side maps, address conversion is performed:

[0080] Chip 1 PCIe controller 1: inbound / outbound remains unchanged;

[0081] Chip 2 PCIe controller 1: inbound addr2->addr2-2G; outbound remains unchanged;

[0082] Chip 2 PCIe controller 2: inbound / outbound remains unchanged;

[0083] Chip 3 PCIe controller 1: inbound addr3->addr3-2G; outbound remains unchanged;

[0084] Chip 3 PCIe controller 2: inbound / outbound remains unchanged;

[0085] Chip 4 PCIe controller 1: inbound addr4->addr4-2G; outbound remains unchanged.

[0086] 5, initialize link management module. Determine chip 1 as the master chip, then the RC side of each PCIe link is responsible for completing the management initialization of the link, and starts monitoring the state of the link.

[0087] 6, initiate address access:

[0088] When the CPU of chip 1 initiates an address addr=0G-2G, the bus is routed to the internal module, and the chip 1 internal address space is accessed;

[0089] When the CPU of chip 1 initiates an address addr=2G-4G, the bus is routed to PCIe controller 1, and after outbound address mapping, addr1=addr is sent to chip 2. The chip 2 PCIe controller 1 receives the access, and after inbound address mapping, addr2=addr1-2G=addr-2G=0G-2G, is sent to the chip 2 internal bus, and the chip 1 internal module is routed to the chip 2 internal bus. When the CPU of chip 1 initiates an address addr=2G-4G, the access is to the internal address space of chip 2;

[0090] When the CPU of chip 1 initiates an address addr=4G-6G, similarly, the address add2=addr-2G=2G-4G is sent to the internal bus of chip 2, the internal bus of chip 2 is routed to the PCIe controller 2, after the address mapping of the outbound of the PCIe controller 2 of chip 2 and the inbound of the PCIe controller 1 of chip 3, the address add3=addr2-2G=0G-2G is sent to the internal bus of chip 3, and is routed to the internal module of the chip. When the CPU of chip 1 initiates an address addr=4G-6G, the internal address space of chip 3 is accessed;

[0091] When the CPU of chip 1 initiates an address addr=6G-8G, similarly, the address add3=addr-4G=2G-4G is sent to the internal bus of chip 3, the internal bus of chip 3 is routed to the PCIe controller 2, after the address mapping of the outbound of the PCIe controller 2 of chip 3 and the inbound of the PCIe controller 1 of chip 4, the address add4=addr3-2G=0G-2G is sent to the internal bus of chip 4, and is routed to the internal module of the chip. When the CPU of chip 1 initiates an address addr=6G-8G, the internal address space of chip 4 is accessed;

[0092] The address sent by the CPU of chip 1 will access different chips:

[0093] 0G-2G: internal address space of chip 1;

[0094] 2G-4G: internal address space of chip 2;

[0095] 4G-6G: internal address space of chip 3;

[0096] 6G-8G: internal address space of chip 4.

[0097] 7, link state management reporting. Chip 1 configures a link reporting period T0 and a timeout time T1, and the RC side chip of each PCIe link is responsible for monitoring and collecting the state of the PCIe link, and periodically reporting to the upper level according to the configured T0. If a link fails, such as the link between chip 2 and chip 3, chip 2 does not receive the state reported by chip 3 within the timeout time, and then marks it as a fault, and sends the state to chip 1 through the PCIe link between chip 1 and chip 2 (such as an interrupt), so that the software on the CPU of chip 1 can know that the link between chip 1 and chip 2 is normal, but the link between chip 2 and chip 3 has failed, and the information is further reported to the upper layer software or presented to the user.

[0098] Figure 7 is a schematic diagram of a star topology according to an embodiment of the present disclosure. As shown in Figure 7, N is 4, i.e. 4-chip interconnection, and each chip needs to access all other chip internal spaces. The address space sizes of chips 1-4 are 1 / 2 / 3 / 4G respectively, and 4-chip unified addressing requires 10G of address space. The specific steps include the following:

[0099] 1. Determine the hardware interconnection relationship between chips. According to system requirements, select a suitable chip interconnection topology as a star topology. In order to meet the connection relationship, chip 2 needs to add PCIe controller 2 connected to chip 3, and add PCIe controller 3 connected to chip 4.

[0100] 2. Determine the type of each PCIe controller relative to the bus inside each chip. Since all chips have the need to access other chip internal spaces, the type of each PCIe controller relative to the bus inside each chip is both master and slave.

[0101] 3. Initialize the bus address space configuration module to configure the internal bus address range (BAR space) for each PCIe controller of each chip as follows:

[0102] Chip 1 PCIe controller 1: 1G-10G;

[0103] Chip 2 PCIe controller 1: 0G-1G;

[0104] Chip 2 PCIe controller 2: 3G-6G;

[0105] Chip 2 PCIe controller 3: 6G-10G;

[0106] Chip 3 PCIe controller 1: 0G-3G, 6G-10G;

[0107] Chip 4 PCIe controller 1: 0G-6G.

[0108] 4. Initialize the inbound / outbound address mapping configuration module to configure the inbound and outbound registers for each PCIe controller of each chip, and determine the mapping relationship between the chip internal bus address space and the external PCIe address space.

[0109] All PCIe link RC and EP side inbound / outbound do not perform address mapping, and all are transparently transmitted.

[0110] 5. Initialize the link management module. Determine the master chip as chip 1, and then the RC side of each PCIe link is responsible for completing the management initialization of the link, and starts to monitor the state of the link.

[0111] 6, address access initiation:

[0112] When the CPU of chip 1 initiates an address addr = 0G-1G, the bus is routed to the internal module, and the internal address space of chip 1 is accessed; when the CPU initiates an address addr = 1G-3G, the bus is routed to PCIe controller 1, and is transmitted to the bus address space of chip 2, and the bus of chip 2 is routed to the internal module; when the CPU initiates an address addr = 3G-6G, the bus is routed to PCIe controller 1, and is transmitted to the bus address space of chip 2, and the bus of chip 2 is routed to PCIe controller 2, and is transmitted to the bus address space of chip 3, and the bus of chip 3 is routed to the internal module; when the CPU initiates an address addr = 6G-10G, the bus is routed to PCIe controller 1, and is transmitted to the bus address space of chip 2, and the bus of chip 2 is routed to PCIe controller 3, and is transmitted to the bus address space of chip 4, and the bus of chip 4 is routed to the internal module;

[0113] The CPU address routing processes of chips 2, 3, and 4 are similar. The addresses initiated by the CPUs of all chips will access different chips:

[0114] 0G-1G: internal address space of chip 1;

[0115] 1G-3G: internal address space of chip 2;

[0116] 4G-6G: internal address space of chip 3;

[0117] 6G-10G: internal address space of chip 4.

[0118] 7, link state management reporting. Chip 1 configures a link reporting period T0 and a timeout time T1, and the RC side chip of each PCIe link is responsible for monitoring and collecting the state of the PCIe link, and periodically reports to the upper level according to the configured T0 time. If a link fails, such as the link between chip 2 and chip 3, and chip 2 does not receive the state reported by chip 3 within the timeout time, it is marked as a fault, and the state is sent to chip 1 through the PCIe link between chip 1 and chip 2 (such as an interrupt), so that the software on the CPU of chip 1 can know that the link between chip 1 and chip 2 is normal, but the link between chip 2 and chip 3 has failed, and the information is further reported to the upper layer software or presented to the user.

[0119] Figure 8 is a schematic diagram of a ring topology according to an embodiment of the present disclosure. As shown in Figure 8, N is 4, i.e. 4-chip interconnection, and each chip needs to access all other chip internal spaces. The address space size of chips 1-4 is 2G, and 4-chip unified addressing requires 8G of address space. Since the address routing of the ring topology has two paths, clockwise and counterclockwise, each path has half of the address space, and the upper software decides which access path to take according to the address. For example, chip 1 accesses the address space of chip 2, and the counterclockwise address routing is shorter than the clockwise path, so the counterclockwise path can be selected; conversely, when chip 1 accesses the address space of chip 4, the clockwise path is shorter. The specific steps include the following:

[0120] 1. Determine the hardware interconnection relationship between chips. According to system requirements, select a suitable chip interconnection topology as a ring topology. In order to meet the connection relationship, chips 1-4 all need to increase PCIe controller 2 to connect with other chips.

[0121] 2. Determine the type of each PCIe controller relative to the bus inside each chip. Since all chips have the need to access other chip internal spaces, the type of each PCIe controller relative to the bus inside each chip is both master and slave.

[0122] 3. Initialize the bus address space configuration module to configure the internal bus address range (BAR space) for each PCIe controller of each chip as follows:

[0123] Chip 1 PCIe controller 1: 5G-8G;

[0124] Chip 1 PCIe controller 2: 1G-4G;

[0125] Chip 2 PCIe controller 1: 4G-5G, 6G-8G;

[0126] Chip 2 PCIe controller 2: 0G-1G, 2G-4G;

[0127] Chip 3 PCIe controller 1: 4G-6G, 7G-8G;

[0128] Chip 3 PCIe controller 2: 0G-2G, 3G-4G;

[0129] Chip 4 PCIe controller 1: 4G-7G;

[0130] Chip 4 PCIe controller 2: 0G-3G.

[0131] 4, initialize inbound / outbound address mapping configuration module, configure inbound and outbound registers for each PCIe controller of each chip, and determine the mapping relationship between the internal bus address space and the external PCIe address space.

[0132] No address mapping is made for the RC and EP side inbound / outbound of all PCIe links, and all are transparently transmitted.

[0133] 5, initialize the link management module. Determine that the master chip is chip 1, then the RC side of each PCIe link is responsible for completing the management initialization of the link, and starts monitoring the state of the link.

[0134] 6, initiate address access:

[0135] When the CPU of chip 1 initiates an address addr=0G-1G, the bus is routed to the internal module to access the internal address space of chip 1; when the address addr=1G-2G is initiated, the bus is routed to the PCIe controller 2 and transparently transmitted to the bus address space of chip 2, and the bus of chip 2 is routed to the internal module; when the address addr=2G-3G is initiated, the bus is routed to the PCIe controller 2 and transparently transmitted to the bus address space of chip 2, and the bus of chip 2 is routed to the PCIe controller 2 and transparently transmitted to the bus address space of chip 3, and the bus of chip 3 is routed to the internal module; when the address addr=3G-4G is initiated, the bus is routed to the PCIe controller 2 and transparently transmitted to the bus address space of chip 2, and the bus of chip 2 is routed to the PCIe controller 2 and transparently transmitted to the bus address space of chip 4, and the bus of chip 4 is routed to the internal module; at this time, the address routing is counterclockwise path.

[0136] When the CPU of chip 1 initiates an address addr=4G-5G, the bus is routed to the internal module to access the internal address space of chip 1; when the address addr=5G-6G is initiated, the bus is routed to the PCIe controller 1 and transparently transmitted to the bus address space of chip 4, and the bus of chip 4 is routed to the PCIe controller 1 and transparently transmitted to the bus address space of chip 3, and the bus of chip 3 is routed to the PCIe controller 1 and transparently transmitted to the bus address space of chip 2, and the bus of chip 2 is routed to the internal module; when the address addr=6G-7G is initiated, the bus is routed to the PCIe controller 1 and transparently transmitted to the bus address space of chip 4, and the bus of chip 4 is routed to the PCIe controller 1 and transparently transmitted to the bus address space of chip 3, and the bus of chip 3 is routed to the internal module; when the address addr=7G-8G is initiated, the bus is routed to the PCIe controller 1 and transparently transmitted to the bus address space of chip 4, and the bus of chip 4 is routed to the internal module; at this time, the address routing is counterclockwise path.

[0137] The CPU address routing process of the chips 2, 3 and 4 is similar. The addresses sent by the CPUs of all the chips will access different chips:

[0138] 0G-1G / 4G-5G: chip 1 internal address space;

[0139] 1G-2G / 5G-6G: chip 2 internal address space;

[0140] 2G-3G / 6G-7G: chip 3 internal address space;

[0141] 3G-4G / 7G-8G: chip 4 internal address space.

[0142] 7, link state management reporting. Chip 1 configures a link reporting period T0 and a timeout time T1. The RC side chip of each PCIe link is responsible for monitoring and collecting the state of the PCIe link, and periodically reporting to the upper level according to the configured T0 time. If a link fails, such as the link between chip 2 and chip 3, chip 2 will not receive the state reported by chip 3 within the timeout time, and will be marked as a fault, and the state will be sent to chip 1 through the PCIe link between chip 1 and chip 2 (such as an interrupt). Thus, the software on the CPU of chip 1 can know that the link between chip 1 and chip 2 is normal, but the link between chip 2 and chip 3 has failed, and the information will be further reported to the upper layer software or presented to the user.

[0143] The chip provided by the embodiment of the present disclosure comprises at least two controllers connected to an internal bus, wherein,

[0144] The at least two controllers are configured to interconnect with the controllers of other chips based on a Peripheral Component Interconnect Express (PCIe) bus.

[0145] The embodiment of the present disclosure also provides a computer program product comprising computer program instructions, wherein the computer program instructions enable a computer to implement the steps in any of the method embodiments described above.

[0146] The embodiment of the present disclosure also provides a computer readable storage medium having a computer program stored therein, wherein the computer program is configured to execute the steps in any of the method embodiments described above when running.

[0147] In an exemplary embodiment, the computer readable storage medium described above can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0148] Embodiments of the present disclosure also provide an electronic device, comprising a memory and a processor, the memory storing a computer program, and the processor being configured to execute the computer program to perform the steps in any of the above method embodiments.

[0149] In an example embodiment, the electronic device described above can further comprise a transmission device connected to the processor, and an input / output device connected to the processor.

[0150] The specific examples in the embodiments can refer to the examples described in the above embodiments and example implementations, which will not be repeated here.

[0151] Obviously, those skilled in the art should understand that the modules or steps of the present disclosure described above can be realized by general computing devices, which can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, which can be realized by program codes executable by computing devices, so that they can be stored in storage devices and executed by computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be made into individual integrated circuit modules, or multiple modules or steps can be made into a single integrated circuit module. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0152] The above only describes the preferred embodiments of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art can make various modifications and changes to the present disclosure. Any modification, equivalent replacement, improvement, etc. within the principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A chip interconnection processing method applied to a chip, the method comprising: providing at least two controllers inside part or all of a plurality of chips, wherein the at least two controllers are connected to an internal bus; interconnecting the plurality of chips based on a Peripheral Component Interconnect Express (PCIe) bus by the at least two controllers of the part or all of the plurality of chips.

2. The method of claim 1, wherein, interconnecting the plurality of chips based on a Peripheral Component Interconnect Express (PCIe) bus by the at least two controllers of the part or all of the plurality of chips comprises: determining an interconnection topology of the plurality of chips based on system requirements; interconnecting controllers in two chips to be connected in the plurality of chips based on the PCIe bus according to the interconnection topology.

3. The method of claim 1, wherein, The method further comprises: determining a type of the controller of each chip relative to a bus; configuring an internal bus address range for the controller of each chip; performing cross-chip address routing according to the type of the controller relative to the bus and the internal bus address range.

4. The method of claim 3, wherein, The cross-chip address routing according to the type of the controller relative to the bus and the internal bus address range comprises: for each chip, if the type of the controller relative to the bus is a master device, initiating a first address access request, and if the type of the controller relative to the bus is a slave device, receiving the first address access request, wherein the first address access request carries a to-be-accessed address; in a case where the to-be-accessed address is within a corresponding internal bus address range, accessing an internal component according to the to-be-accessed address; in a case where the to-be-accessed address is outside the corresponding internal bus address range, sending the first address access request to a controller of a next-level chip connected based on the PCIe bus.

5. The method of claim 3, wherein, The cross-chip address routing according to the type of the controller relative to the bus and the internal bus address range comprises: for each chip, if the type of the controller relative to the bus is a master device, initiating a first address access request, and if the type of the controller relative to the bus is a slave device, receiving the first address access request, wherein the first address access request carries a to-be-accessed address; in a case where the to-be-accessed address is within a corresponding internal bus address range, accessing an internal component according to the to-be-accessed address; in a case where the to-be-accessed address is outside the corresponding internal bus address range, converting the to-be-accessed address into an external PCIe address based on a pre-set mapping relationship between an internal bus address and an external PCIe address, and sending a second address access request to a controller of a next-level chip based on the PCIe bus, wherein the second address access request carries the converted external PCIe address.

6. The method of claim 5, wherein, The converting the to-be-accessed address into an external PCIe address based on a pre-set mapping relationship between an internal bus address and an external PCIe address comprises: in a pre-set inbound register or outbound register of the controller, converting the to-be-accessed address into the external PCIe address based on the mapping relationship.

7. The method of claim 3, wherein, determining the type of the controller relative to the bus for each chip comprises: determining access requirements of the controller; determining the type of the controller relative to the bus according to the access requirements of the controller.

8. The method of claim 7, wherein, determining the type of the controller relative to the bus according to the access requirements of the controller comprises: in a case where the access requirements of the controller are to access internal space of other chips through the PCIe bus, setting the type of the controller as a host device, wherein the host device represents support for initiating access to the bus; in a case where the access requirements of the controller are to support access of other chips to local space, setting the type of the controller as a slave device, wherein the slave device represents support for responding to access of other host devices on the bus; in a case where the access requirements of the controller are to access internal space of other chips through the PCIe bus and to support access of other chips to local space, setting the type of the controller as a host device and a slave device.

9. The method of any one of claims 1 to 8, wherein, The method further comprises: setting a root component (RC) side chip for each two chips connected by a PCIe link; monitoring and collecting the status of the PCIe link through the RC side chip, and reporting the link status to the upper chip; in a case where the link status reported by the next level chip is not received within a preset timeout time, determining that the PCIe link with the next level chip is faulty, and reporting the link status of the faulty PCIe link to the upper chip.

10. A chip comprising: at least two controllers, the at least two controllers being connected to an internal bus, wherein the at least two controllers are configured to interconnect with controllers of other chips based on a Peripheral Component Interconnect Express (PCIe) bus.

11. A computer-readable storage medium having stored therein a computer program, wherein, The computer program is configured to execute the method described in any one of claims 1 to 9 when running.

12. An electronic device comprising a memory and a processor, the memory having stored therein a computer program, the processor being configured to execute the computer program to perform the method described in any one of claims 1 to 9.

13. A computer program product comprising a computer program which, when executed by a processor, implements the steps of the method described in any one of claims 1 to 9.

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