Junctionless transistor

Abstract

The present application provides a junctionless transistor, comprising a substrate (100), and a buried oxide layer (110), a core layer (150), and a shell layer (160) sequentially stacked on the substrate (100). The doping concentration of the shell layer (160) is less than the doping concentration of the core layer (150), a gate (170) is provided on the shell layer (160), and the dimension of the shell layer (160) in a first direction parallel to the surface of the substrate (100) is greater than the dimension of the gate (170) in the first direction. Compared with a scenario where the dimension of the shell layer (160) in the first direction is equal to the dimension of the gate (170) in the first direction, in the present application, the dimension of the shell layer (160) in the first direction is increased, so that charge carriers in a channel are less influenced by source-drain electric fields and are controlled almost exclusively by a gate electric field. During device operation, due to the low doping concentration or absence of doping in the shell layer (160), the charge carrier mobility is high, and therefore, the device can have a lower off-state current and a higher on-state current, thereby improving the device performance.

Description

A junctionless transistor

[0001] This application claims priority to Chinese Patent Application No. 202410918034.2, filed on July 9, 2024, entitled "A Junctionless Transistor", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductors, and particularly to a junctionless transistor. Background Technology

[0003] A fully depleted silicon-on-insulator (FDSOI) transistor employs a special structure to improve the performance and power consumption of semiconductor devices. It consists of an insulating layer and a thin layer of single-crystal silicon within the insulating layer, typically made of silicon dioxide and called a buried oxide (BOX) layer. The thin single-crystal silicon layer is called the top silicon or SOI layer, achieving a top silicon-buried oxide-bottom silicon SOI structure. By thinning the top silicon layer, the depletion layer fills the entire channel region, achieving full depletion, thus realizing the fully depleted silicon-on-insulator structure.

[0004] Junction-less (JL) transistors have attracted considerable attention due to their simple fabrication process and potential in 3D integration requiring low thermal budgets. JL transistors have uniform doping between the source / drain and the channel, thus lacking a junction. They achieve turn-off by depleting carriers in the channel, exhibiting strong suppression of short-channel effects and possessing full CMOS functionality. Furthermore, JL transistors offer advantages such as simple fabrication, multiple threshold adjustment options, and low noise.

[0005] However, JL transistors also have some fundamental weaknesses: low mobility, high contact resistance, and a negative threshold voltage. Therefore, to address these challenges, a core-shell junction-less (CS-JL) transistor is proposed. The core-shell junction-less transistor is a novel junction-less transistor based on FDSOI technology. Compared to traditional junction-less transistors, the core-shell structure uses the heavily doped top silicon layer of a traditional FDSOI wafer as the core layer, and adds an ultrathin lightly doped or undoped shell layer on top. This achieves a positive threshold voltage and high on-state current, retaining the advantages of JL transistors while avoiding their disadvantages.

[0006] However, there is also a need to improve the performance of CS-JL transistors. Summary of the Invention

[0007] In view of this, the purpose of this application is to provide a junctionless transistor that increases the on-state current, reduces the off-state current, and improves the device performance.

[0008] This application provides a junctionless transistor, including:

[0009] Substrate;

[0010] The substrate has a buried oxide layer, a core layer and a shell layer stacked sequentially, wherein the doping concentration of the shell layer is less than that of the core layer;

[0011] The gate on the shell; the dimension of the shell in a first direction along the surface of the substrate is greater than the dimension of the gate in the first direction.

[0012] Optionally, the shell layer has a smaller dimension along the first direction than the core layer has a smaller dimension along the first direction, and the core layer extends upward on both sides of the shell layer to be flush with the shell layer.

[0013] Optionally, the junctionless transistor further includes:

[0014] The sidewall of the gate sidewall; the dimension of the shell along the first direction is the sum of 2n times the dimension of the gate along the first direction and the dimension of the sidewall along the first direction, where n is a positive integer.

[0015] Optionally, the shell layer has a dimension greater than or equal to 70 nm along the first direction.

[0016] Optionally, the dimension of the shell layer along the first direction is equal to the dimension of the core layer along the first direction.

[0017] Optionally, the doping concentration of the core layer is greater than or equal to 10. 19 cm -3 .

[0018] Optionally, the thickness of the core layer ranges from 3 to 10 nm, and the thickness of the shell layer ranges from 3 to 10 nm.

[0019] Optionally, the thickness of the core layer ranges from 3 to 5 nm, and the thickness of the shell layer ranges from 3 to 5 nm.

[0020] Optionally, the junctionless transistor further includes:

[0021] The gate dielectric layer between the gate and the shell layer;

[0022] The source and the drain are located on one side of the gate and the other side in the first direction.

[0023] Optionally, the core layer and the shell layer are made of silicon.

[0024] This application provides a junctionless transistor, including a substrate and a buried oxide layer, a core layer, and a shell layer sequentially stacked on the substrate. The doping concentration of the shell layer is lower than that of the core layer. The shell layer has a gate. The size of the shell layer in a first direction along the surface of the substrate is larger than the size of the gate in the first direction. That is, compared with the case where the size of the shell layer in the first direction is equal to the size of the gate in the first direction, this solution increases the size of the shell layer in the first direction, so that the carriers in the channel are less affected by the source and drain electric fields and are almost only controlled by the gate electric field. At the beginning of the device, the shell layer has a high carrier mobility due to the low or no doping concentration. Therefore, the device can have a lower off-state current and a higher on-state current, thereby improving the device performance. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 shows a schematic diagram of a junctionless transistor provided in an embodiment of this application;

[0027] Figure 2 is a schematic diagram of another junctionless transistor provided in an embodiment of this application;

[0028] Figure 3 is a schematic diagram of another junctionless transistor provided in an embodiment of this application;

[0029] Figure 4 is a schematic diagram of another junctionless transistor provided in an embodiment of this application;

[0030] Figure 5 is a schematic diagram of various shell lengths provided in the embodiments of this application;

[0031] Figure 6 is a schematic diagram of the transmission characteristics of transistors with different shell lengths provided in the embodiments of this application;

[0032] Figure 7 is a schematic diagram of the simulation results of low field mobility provided in the embodiments of this application;

[0033] Figure 8 is a comparison of electron concentrations of junctionless transistors with different shell lengths provided in the embodiments of this application;

[0034] Figure 9 is a comparison of the current density of planar CS-JL transistors with different shell layer lengths provided in the embodiments of this application. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0036] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0037] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0038] Referring to Figure 1, which is a schematic diagram of a junctionless transistor provided in an embodiment of this application, a core-shell structure layer is formed on a buried oxide layer 110 on a substrate 100, including a core layer 150 and a shell layer 160. The shell layer 160 has a low doping concentration or is undoped, while the core layer 150 has a high doping concentration. The core layer 150 is located below the gate 170 and is flush with the gate 170. Compared with ordinary junctionless transistors, it achieves low off-state current, high on-state current, and positive threshold voltage, avoiding the problems of low mobility and poor consistency caused by high doping of the source, drain, and channel in JL transistors.

[0039] However, the inventors discovered through research that the vertical gate electric field and the lateral source-drain electric field superimposed below the sidewall would produce a current crowding effect. The carriers were severely scattered at the interface between the shell and the source, resulting in a degradation of mobility, which affected the on-state current and caused high power consumption.

[0040] Based on the above technical problems, this application provides a junctionless transistor, including a substrate and a buried oxide layer, a core layer, and a shell layer sequentially stacked on the substrate. The doping concentration of the shell layer is less than that of the core layer. The shell layer has a gate. The size of the shell layer in a first direction along the surface of the substrate is larger than the size of the gate in the first direction. That is, compared with the case where the size of the shell layer in the first direction is equal to the size of the gate in the first direction, this solution increases the size of the shell layer in the first direction, so that the carriers in the channel are less affected by the source and drain electric fields and are almost only controlled by the gate electric field. At the beginning of the device, the shell layer has a high carrier mobility due to the low or no doping concentration. Therefore, the device can have a lower off-state current and a higher on-state current, thus improving the device performance.

[0041] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0042] Referring to Figure 2, which is a schematic diagram of another junctionless transistor provided in an embodiment of this application, the junctionless transistor includes: a substrate 100, and a buried oxide layer 110, a core layer 150 and a shell layer 160 sequentially stacked on the substrate 100.

[0043] In this embodiment, the substrate 100 can be a semiconductor substrate to provide support for the film layer thereon. For example, it can be a silicon substrate, germanium substrate, etc. The substrate 100 can be circular during the manufacturing process. For example, it can be a silicon wafer. Multiple chips can be formed on it to form an array, so as to realize the same batch manufacturing of multiple chips and improve manufacturing efficiency.

[0044] A buried oxide layer 110, a core layer 150, and a shell layer 160 can be formed on the substrate 100. The core layer 150 and the shell layer 160 can be made of the same material. When the core layer 150 and the shell layer 160 are made of silicon, the substrate 100, the buried oxide layer 110, the core layer 150, and the shell layer 160 constitute an SOI substrate.

[0045] The buried oxide layer 110 is an insulating layer used to isolate the core layer and the substrate 100, and to prevent carriers in the core layer from leaking from the substrate 100 during device operation. The buried oxide layer 110 can be, for example, silicon oxide, germanium oxide, etc.

[0046] The core layer 150, as part of the channel layer, can be made of silicon or germanium, and its thickness can range from 3 to 10 nm, specifically 3 to 5 nm, for example, 3 nm. The doping concentration of the core layer 150 is greater than or equal to 10. 19 cm -3 .

[0047] The shell 160, as part of the channel layer, can be made of silicon or germanium, and its thickness can range from 3 to 10 nm, specifically 3 to 5 nm, for example, 4 nm. The doping concentration of the shell 160 is less than that of the core layer 150, and it can be lightly doped or undoped, for example, the shell 160 can be an undoped film.

[0048] The shell 160 has a gate 170. The size of the shell 160 in the first direction along the surface of the substrate 100 is larger than the size of the gate 170 in the first direction. That is, compared with the case where the size of the shell 160 in the first direction is equal to the size of the gate 170 in the first direction, this solution increases the size of the shell 160 in the first direction, so that the carriers in the channel are less affected by the source and drain electric fields and are almost only controlled by the gate electric field. At the beginning of the device, the shell has a high carrier mobility due to low or no doping concentration. Therefore, the device can have a lower off-state current and a higher on-state current, thus improving the device performance.

[0049] Furthermore, a gate dielectric layer 171 may be formed between the gate 170 and the shell 160 to isolate the gate 170 and the shell 160. The gate dielectric layer 171 may be a high-k dielectric layer or silicon oxide, etc. In the first direction, a source electrode 1300 may be formed on one side of the gate 170, and a drain electrode 140 may be formed on the other side. Sidewalls may be formed on the sidewalls of the gate 170 facing the source electrode 130 and the sidewalls facing the drain electrode 140. The sidewalls include a first sidewall 172 and a second sidewall 173, which are used to isolate the gate 170 from the source electrode 130 and the drain electrode 140, respectively. A source contact 131 may be formed on the source electrode 130, and a drain contact 141 may be formed on the drain electrode 140. The source contact 131 and the drain contact 141 may be metal silicides to reduce contact resistance.

[0050] In one possible implementation, the dimension of the shell 160 along the first direction is equal to the dimension of the core layer 150 along the first direction, that is, the shell 160 extends to the entire transistor, and the sidewalls of the shell 160 are flush with the sidewalls of the core layer 150. Referring to Figure 3, this is a schematic diagram of another junctionless transistor structure provided in an embodiment of this application. Let the dimension of the shell 160 in the first direction be L. shell The transistor has a dimension L in the first direction. Device Then we have L shell =L Device .

[0051] In another possible implementation, the size of the shell layer 160 along the first direction is smaller than the size of the core layer 150 along the first direction. In this case, the core layer 150 can extend upwards on both sides of the shell layer 160 to be flush with the shell layer, so that the bottom of the source 130 and drain 140 on the core layer 150 is flush with the bottom of the gate 170 on the shell layer 160, as shown in FIG2. Of course, the core layer 150 may not extend upwards, so that the bottom of the source 130 and drain 140 on the core layer 150 is lower than the bottom of the gate 170 on the shell layer 160.

[0052] Specifically, the dimension of the shell 160 extending beyond the gate 170 on the source-to-source side can be equal to the dimension of the shell 160 extending beyond the gate 170 on the drain-to-drain side. That is, the center of the shell 160 and the center of the gate 170 are aligned, and both can be located at the center of the device. The dimension of the shell 160 extending beyond the gate 170 on the source-to-source side can be n times the dimension of the sidewall in the first direction. Specifically, the dimension of the shell 160 along the first direction is the sum of the dimension of the gate 170 along the first direction and 2n times the dimension of the sidewall along the first direction, where n is a positive integer.

[0053] Let the dimension of the shell in the first direction be L. shell The dimension of the sidewall in the first direction is L. spacer The gate has a dimension of L in the first direction. g Then, the case where the shell is flush with the gate sidewall is denoted as n=0, in which case L shell =L g When n=1, L shell =L g +2*L spacer When n=2, L shell =L g +4*L spacer And so on. In Figure 2, n=1. Referring to Figure 4, which shows another junctionless transistor structure provided in an embodiment of this application, n=2. The following explanation addresses the cases where n is 0, 1, or 2, and where the shell extends to the entire transistor. Referring to Figure 5, which shows various shell lengths provided in an embodiment of this application.

[0054] Referring to Figure 6, this is a schematic diagram of the transmission characteristics of transistors with different shell lengths provided in the embodiments of this application. The horizontal axis represents the gate voltage V. G The vertical axis represents the output current I. D V D L is the drain voltage. g T is the length of the gate in the first direction. core T represents the core layer thickness. si N is the shell thickness. DThe value represents the drain doping concentration. As shown in the figure, when the gate voltage is greater than 0.8V, the shell extends to the entire transistor, and the output characteristics when n is 1 and 2 are both due to the shell size being equal to the gate size. That is, after the shell is extended, the transistor current is much higher than that of a traditional CS-JL transistor, while retaining the good subthreshold characteristics of a traditional CS-JL transistor.

[0055] In the junctionless transistor provided in this application embodiment, turn-off is achieved by depleting the carriers in the channel through the gate work function. During turn-off, the electric field lines at the gate edge of the transistor deplete part of the source and drain, resulting in an effective channel modulation effect. Its working principle is to combine the doped electrons in the heavily doped core with the gate-induced electrons in the undoped shell. The gate turns the core from a fully depleted state to a near-flat band state, and then activates the shell. Normally, the shell length is equivalent to the effective channel length. The formula for the current in the linear region of a MOSFET transistor is:

[0056] Based on the above formula, it can be seen that the longer the channel length of a transistor, the lower the output current of the transistor. When the length of the shell layer after expansion exceeds the gate length, some regions that are not controlled by the gate appear. The appearance of these regions will increase the series resistance of the transistor, further reducing the output current of the transistor.

[0057] However, as shown in Figure 6, the simulation results contradict the formula derivation; the expansion of the shell actually increases the transistor output current. This is because as the gate length of the transistor continues to decrease, the shell length decreases accordingly, the effective channel length also decreases, and the effective mobility of the transistor decreases. Referring to Figure 7, which is a schematic diagram of the simulation results for low field mobility provided in the embodiments of this application, the horizontal axis represents the gate length, and the vertical axis represents the electron mobility. It can be seen from the figure that at gate length L... G At wavelengths <70nm, the transistor mobility rapidly declines due to the enhanced lateral electric field, increased series resistance, and neutral defects introduced during ion implantation.

[0058] Therefore, in scenarios with a small gate length, when n is 0, the vertical gate electric field and the lateral source-drain electric field are superimposed below the spacer, resulting in a current crowding effect. When the carriers are transported to the interface between the shell and the source, the high carrier concentration causes severe Coulomb scattering, leading to a degradation in mobility and a low on-state current of the device.

[0059] Extending the shell layer outwards has two advantages. First, most of the electric field from the drain falls at the PN junction between the drain and the shell layer, and the carriers in the channel are almost entirely controlled by the gate electric field. Second, when the device is turned on, since the shell layer is undoped, the carriers entering the shell layer will participate in conduction through the channel with a very high mobility. Therefore, the carrier mobility is greatly improved. This gain covers the negative impact of the increased series resistance caused by the shell layer extension, so the transistor current rises rapidly.

[0060] Therefore, even if the gate length is less than 70 nm, the size of the shell along the first direction is greater than or equal to 70 nm, which expands the shell and helps to increase the output current of the transistor.

[0061] For n = 0, 1, 2, and the case where the shell extends to the entire transistor, referring to Figure 8, a comparison diagram of electron concentration for junctionless transistors corresponding to different shell lengths provided in the embodiments of this application is shown. G =1.5V. Referring to Figure 9, it is a comparison diagram of the current density of planar CS-JL transistors with different shell layer lengths provided in the embodiments of this application. The carriers are mainly concentrated in the shell layer and the source and drain near the sidewalls. After extending the shell layer, the carriers under the sidewalls and the source and drain can obtain higher mobility, which compensates for the negative impact of increasing the effective channel length.

[0062] The planar CS-JL transistor provided in this application has a manufacturing process that is fully compatible with the FDSOI manufacturing process, and is simpler to manufacture than traditional planar CS-JL transistors. The core and shell layers of the top silicon layer can be fabricated in a wafer fab without additional etching steps, reducing manufacturing costs. This also has significant value and importance for the research of advanced nodes of CS-JL transistors.

[0063] Compared to traditional CS-JL transistors, the planar CS-JL transistor provided in this application, by extending the shell layer, retains the advantages of traditional CS-JL transistors while improving the on-state current and achieving low-power performance. The improved CS-JL transistor exhibits superior characteristics in terms of drive current, with a lower off-state current in the off state, achieving low-power device characteristics; simultaneously, it has a higher on-state current when the device is turned on, achieving a high-performance operating mode. This invention is applicable to various application scenarios, has high market demand, and is expected to generate high economic benefits.

[0064] This application provides a junctionless transistor, including a substrate and a buried oxide layer, a core layer, and a shell layer sequentially stacked on the substrate. The doping concentration of the shell layer is lower than that of the core layer. The shell layer has a gate. The size of the shell layer in a first direction along the surface of the substrate is larger than the size of the gate in the first direction. That is, compared with the case where the size of the shell layer in the first direction is equal to the size of the gate in the first direction, this solution increases the size of the shell layer in the first direction, so that the carriers in the channel are less affected by the source and drain electric fields and are almost only controlled by the gate electric field. At the beginning of the device, the shell layer has a high carrier mobility due to the low or no doping concentration. Therefore, the device can have a lower off-state current and a higher on-state current, thereby improving the device performance.

[0065] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A junctionless transistor, characterized in that, include: Substrate; The substrate has a buried oxide layer, a core layer and a shell layer stacked sequentially, wherein the doping concentration of the shell layer is less than that of the core layer; The gate on the shell; the dimension of the shell in a first direction along the surface of the substrate is greater than the dimension of the gate in the first direction.

2. The junctionless transistor according to claim 1, characterized in that, The shell layer has a smaller dimension along the first direction than the core layer has a smaller dimension along the first direction, and the core layer extends upward on both sides of the shell layer to be flush with the shell layer.

3. The junctionless transistor according to claim 2, characterized in that, Also includes: The sidewall of the gate sidewall; The dimension of the shell along the first direction is the sum of 2n times the dimension of the gate along the first direction and the dimension of the sidewall along the first direction, where n is a positive integer.

4. The junctionless transistor according to claim 3, characterized in that, The size of the shell along the first direction is greater than or equal to 70 nm.

5. The junctionless transistor according to claim 1, characterized in that, The dimension of the shell layer along the first direction is equal to the dimension of the core layer along the first direction.

6. The method according to any one of claims 1-5, characterized in that, The doping concentration of the core layer is greater than or equal to 10. 19 cm -3 .

7. The method according to any one of claims 1-6, characterized in that, The thickness of the core layer ranges from 3 to 10 nm, and the thickness of the shell layer ranges from 3 to 10 nm.

8. The junctionless transistor according to claim 7, characterized in that, The thickness of the core layer ranges from 3 to 5 nm, and the thickness of the shell layer ranges from 3 to 5 nm.

9. The method according to any one of claims 1-8, characterized in that, Also includes: The gate dielectric layer between the gate and the shell layer; The source and the drain are located on one side of the gate and the other side in the first direction.

10. The method according to any one of claims 1-9, characterized in that, The core layer and the shell layer are made of silicon.

Images