Memory and access method therefor, and electronic device

Abstract

A memory and an access method therefor, and an electronic device. The memory comprises: a multi-layer memory cell array stacked in a direction perpendicular to a substrate, and a plurality of word lines (WL), wherein the word lines (WL) in the same column or at multiple layers and in the same column which are distributed in a second direction are divided into K first word line groups, and the word lines (WL) of the same first word line group are respectively connected to a same first word line driver SWD_X by means of corresponding gating sub-circuits (20); the word lines are divided into a plurality of second word line groups, each of the second word line groups comprises K rows or K layers of word lines, and each word line among the K rows or K layers of word lines is connected to a different first word line driver SWD_X; and the word lines of the same second word line group are respectively connected to a same second word line driver SWD_Y by means of corresponding gating sub-circuits.

Description

Memory and access method thereof, and electronic device

[0001] The present application claims priority to the Chinese patent application No. 2024111408681, filed on August 19, 2024, and entitled "Memory and access method thereof, and electronic device", the contents of which are hereby incorporated by reference into the present application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing thereof in the field of semiconductor technology, and in particular to a memory and access method thereof, and electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of the device is becoming smaller and smaller, and the types and number of devices contained in a single chip are increasing, so that any slight difference in the process production may affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a memory, comprising: a plurality of layers of memory cell arrays stacked perpendicularly to the substrate direction; the memory cell array comprises: a plurality of memory cells arranged along a first direction and a second direction,

[0008] The memory further comprises: a plurality of word lines extending in a direction perpendicular to the substrate and arranged along the first direction and the second direction; the memory cell array further comprises: a plurality of bit lines extending along the second direction and spaced along the first direction; each bit line connects a column of memory cells arranged along the second direction; the word line connects a plurality of memory cells at the same position of different layers; and the word lines arranged along the second direction are divided into K first word line groups; the word lines of the memory cell array are divided into a plurality of second word line groups, each second word line group comprises K rows of word lines, and each word line in the K rows of word lines is connected to a different first word line driver;

[0009] Or the memory further comprises: a plurality of bit lines extending in a direction perpendicular to the substrate and arranged in an array along the first direction and the second direction; the memory cell array further comprises: a plurality of word lines extending along the second direction and arranged in an array along the first direction; each of the word lines is connected to a column of memory cells arranged along the second direction, and the bit lines are connected to a plurality of memory cells at the same position in different layers; and the word lines of the same column in the plurality of layers arranged in a direction perpendicular to the substrate are divided into K first word line groups; the word lines of the memory cell array are divided into a plurality of second word line groups, each of which comprises K word lines, and each of the K word lines is connected to a different first word line driver.

[0010] Each of the word lines corresponds to a selection sub-circuit, and the word lines of the same first word line group are respectively connected to the same first word line driver through the corresponding selection sub-circuits; the word lines of the same second word line group are respectively connected to the same second word line driver through the corresponding selection sub-circuits, K is greater than or equal to 2, and the first direction and the second direction are parallel to the substrate and intersect.

[0011] In some embodiments, K-1 word lines are arranged between adjacent word lines in the same first word line group; and each of the K rows or K layers of word lines is divided into a second word line group.

[0012] In some embodiments, K=2.

[0013] In some embodiments, the selection sub-circuit and the memory cell array are located in the same die, and the first word line driver and the second word line driver are located in different dies.

[0014] In some embodiments, the selection sub-circuit comprises a first transistor and a second transistor, the first transistor and the second transistor are opposite in polarity, the first transistor comprises a first gate electrode, a first electrode and a second electrode, the second transistor comprises a second gate electrode, a third electrode and a fourth electrode;

[0015] The first gate electrode and the second gate electrode are connected to the first word line driver, the first electrode is connected to a preset voltage terminal, the second electrode is connected to the third electrode and an output terminal, and the fourth electrode is connected to the second word line driver; or, the first gate electrode and the second gate electrode are connected to the second word line driver, the first electrode is connected to a preset voltage terminal, the second electrode is connected to the third electrode and an output terminal, and the fourth electrode is connected to the first word line driver.

[0016] The output terminal is connected to the word line corresponding to the selection sub-circuit.

[0017] In some embodiments, the first transistor is an N-type transistor, and the second transistor is a P-type transistor.

[0018] In some embodiments, the first word line driver is loaded with a turn-on voltage and a turn-off voltage, the second word line driver is loaded with a first voltage and a second voltage, and the preset voltage terminal is loaded with the first voltage, wherein the first voltage is less than the turn-off voltage, and the second voltage is greater than the turn-on voltage.

[0019] Embodiments of the present disclosure provide an access method, applied to the above memory, comprising:

[0020] In the data read / write phase, according to the first word line group and the second word line group in which the word line connected to the target storage unit to be operated is located, a corresponding signal is loaded on the first word line driver connected to the word line of the first word line group and the second word line driver connected to the word line of the second word line group, so as to output an activation level signal to the target storage unit through the gating sub-circuit.

[0021] In some embodiments, loading a corresponding signal on the first word line driver connected to the word line of the first word line group and the second word line driver connected to the word line of the second word line group comprises:

[0022] When the first gate electrode and the second gate electrode are connected to the first word line driver, and the fourth electrode is connected to the second word line driver, the first word line driver is loaded with a signal opposite to the level of the activation level signal, and the second word line driver is loaded with the activation level signal.

[0023] When the first gate electrode and the second gate electrode are connected to the second word line driver, and the fourth electrode is connected to the first word line driver, the second word line driver is loaded with a signal opposite to the level of the activation level signal, and the first word line driver is loaded with the activation level signal.

[0024] Embodiments of the present disclosure provide an electronic device comprising the above-mentioned memory.

[0025] Other features and advantages of the present application will be set forth in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. Other advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the description and appended claims.

[0026] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description with reference to the accompanying drawings.

[0027] SUMMARY

[0028] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of this specification that is incorporated herein by reference. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0029] Fig. 1 is a schematic diagram of a memory according to an example embodiment;

[0030] Fig. 2 is a schematic diagram of a connection between each column of word lines and a first word line driver according to an example embodiment;

[0031] Fig. 3 is a schematic diagram of a connection between word lines and a first word line driver and a second word line driver according to an example embodiment;

[0032] Fig. 4 is a schematic diagram of a gating sub-circuit according to an example embodiment;

[0033] Fig. 5 is a schematic diagram of a gating sub-circuit according to another example embodiment;

[0034] Fig. 6 is a schematic diagram of a connection between a gating sub-circuit and a first word line driver and a second word line driver according to an example embodiment;

[0035] Fig. 7 is a schematic diagram of a connection between a memory die and a peripheral circuit die according to an example embodiment.

[0036] DETAILED DESCRIPTION

[0037] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The features of the embodiments of the present disclosure and the embodiments can be arbitrarily combined with each other unless they conflict.

[0038] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as those understood by a person of ordinary skill in the art to which the present disclosure belongs.

[0039] The embodiments of the present disclosure are not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0040] In the present disclosure, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of the components, and do not represent any order, number, or importance.

[0041] In the present disclosure, for convenience, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0042] In the present disclosure, unless clearly specified and limited otherwise, the terms "mounting", "connection", "coupling" should be interpreted broadly. For example, it can be a physical connection or a signal connection, it can be a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate, or internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0043] In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0044] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the operation of a circuit, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.

[0045] In the present disclosure, "connection" includes the case where the constituent elements are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0046] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0047] Figure 1 is a schematic diagram of a memory according to an example embodiment. As shown in Figure 1, the memory includes a plurality of layers of memory cell arrays (only one layer is shown in Figure 1) stacked along a direction perpendicular to a substrate, and a plurality of word lines (WL) extending along a direction perpendicular to the substrate. Each layer of the memory cell arrays can include a plurality of memory cells 11 arranged along a first direction X and a second direction Y, and a plurality of bit lines (BL) extending along the second direction Y. The plurality of bit lines in the same layer are spaced apart along the first direction X. The memory cells 11 in the same column along the second direction Y in the same layer are connected to the same BL. The memory cells 11 in different columns are connected to different BLs. The memory cells 11 in the same position in different layers are connected to the same WL. The plurality of WLs are arranged along the first direction X and the second direction Y.

[0048] In one technical solution, one row of word lines is connected to one first word line driver, and one column of word lines is connected to one second word line driver. One word line is selected by a first driving signal of the first word line driver and a second driving signal of the second word line driver. When there are M rows and N columns of word lines, M+N word line drivers are needed. In this solution, the number of word line drivers is large.

[0049] In some embodiments, the memory cell 11 includes but is not limited to a 1T1C memory cell.

[0050] In some embodiments, each word line can correspond to one gating sub-circuit 20. The word line is connected to the first word line driver SWD_X and the second word line driver SWD_Y through the corresponding gating sub-circuit 20.

[0051] The word lines in the same column along the second direction Y are divided into K first word line groups. The word lines in the same first word line group are respectively connected to the same first word line driver SWD_X through the corresponding gating sub-circuit 20. The word lines in different first word line groups are connected to different first word line drivers SWD_X. In this case, one column of word lines needs K first word line drivers SWD_X. The word lines in different first word line groups do not overlap, i.e., one word line belongs to only one first word line group. Taking the memory cell array including N columns of word lines as an example, K*N first word line drivers SWD_X are needed. K is greater than or equal to 2. K is for example 2, 3, or 4.

[0052] In some embodiments, the word lines in the same first word line group can be spaced apart by K-1 word lines.

[0053] For example, as shown in FIG. 2, when K = 2, the 1st, 3rd, 5th, …, M-1th word lines in the same column are in a first word line group, and the 2nd, 4th, 6th, …, Mth word lines in the same column are in another first word line group. Adjacent word lines in the same first word line group are separated by one word line (for example, the 1st word line and the 3rd word line are separated by the 2nd word line). Adjacent word lines in the same first word line group refer to two word lines in the first word line group that are located in adjacent positions after the word lines in the first word line group are arranged in the order of the word lines in the column. At this time, 2N first word line drivers SWD_X(i) are needed, i is 0 to 2N-1. As shown in FIG. 2, the word lines in the 1st, 3rd, 5th, …, M-1th rows and the 1st column are connected to SWD_X(0), the word lines in the 2nd, 4th, 6th, …, Mth rows and the 1st column are connected to SWD_X(1), the word lines in the 1st, 3rd, 5th, …, M-1th rows and the 2nd column are connected to SWD_X(2), the word lines in the 2nd, 4th, 6th, …, Mth rows and the 2nd column are connected to SWD_X(3), and so on, the word lines in the 1st, 3rd, 5th, …, M-1th rows and the Nth column are connected to SWD_X(2N-2), and the word lines in the 2nd, 4th, 6th, …, Mth rows and the Nth column are connected to SWD_X(2N-1).

[0054] In some embodiments, among the M rows of word lines, K rows of word lines form a second word line group, and each word line in the K rows of word lines is connected to a different first word line driver SWD_X. The word lines in the same second word line group are connected to the same second word line driver SWD_Y through the corresponding selection sub-circuit 20. The word lines in different second word line groups are connected to different second word line drivers SWD_Y. The word lines in different second word line groups do not overlap, that is, a word line belongs to only one second word line group. Taking the example that the storage unit array includes M rows of word lines, at this time, M / K second word line drivers SWD_Y are needed.

[0055] In some embodiments, a second word line group can be formed every K consecutive rows of word lines.

[0056] For example, as shown in FIG. 3, the 1st and 2nd rows of word lines are in a second word line group, the 3rd and 4th rows of word lines are in a second word line group, and so on, the M-1th and Mth rows of word lines are in a second word line group. At this time, M / 2 second word line drivers SWD_Y(j) are needed, j is 0 to M / 2-1, wherein the 1st and 2nd rows of word lines are connected to SWD_Y(0), the 3rd and 4th rows of word lines are connected to SWD_Y(1), and so on, the M-1th and Mth rows of word lines are connected to SWD_Y(M / 2-1).

[0057] Therefore, when K=2, the number of word line drivers required by the memory cell array is 2N+M / 2, compared with the scheme of using M+N word line drivers, in the case of M>>N, the number of word line drivers can be greatly reduced, the device area can be reduced, the cost can be reduced, and the layout is easier. Generally, the number of M is 512 or even more, N is less than or equal to 50, M+N-(2N+M / 2)=M / 2-N, when M is large, the number of word line drivers can be greatly reduced.

[0058] In some embodiments, a plurality of word lines continuously distributed in the same column can be divided into a first word line group, and a plurality of word lines in non-continuous rows can be divided into a second word line group. The division of the first word line group and the second word line group is such that the word lines in the second word line group are connected to different first word line drivers, and the word lines in the first word line group are connected to different second word line drivers. Therefore, the connection mode shown in FIG. 3 is only an example, and the embodiments of the present disclosure are not limited thereto. However, the connection mode shown in FIG. 3 is more convenient for wiring.

[0059] In some embodiments, when the memory cell 11 is a 1T1C memory cell, the source / drain, the channel, and the capacitor of the memory cell 11 are arranged along the first direction X, so that the size a of the memory cell 11 along the first direction X is greater than the size b of the memory cell 11 along the second direction Y. The first word line driver SWD_X is usually arranged along the first direction X, and the second word line driver SWD_Y is usually arranged along the second direction Y. Therefore, the layout difficulty of the second word line driver SWD_Y is greater than that of the first word line driver SWD_X. Therefore, reducing the number of second word line drivers SWD_Y can reduce the layout difficulty of the second word line driver SWD_Y, and the number of first word line drivers SWD_X is not increased much, which has little effect on the layout difficulty of the first word line driver SWD_X. In some embodiments, the appropriate K value can be determined according to the layout difficulty and the number of word line drivers.

[0060] The gate sub-circuit 20 can be of various structures and can select a word line through the first word line driver SWD_X and the second word line driver SWD_Y. In some embodiments, the gate sub-circuit 20 can be an inverter. FIG. 4 is an equivalent circuit diagram of the gate sub-circuit 20 provided in some embodiments. As shown in FIG. 4, the gate sub-circuit 20 can include a first transistor T1 and a second transistor T2. The first transistor T1 can include a first gate electrode G1, a first electrode E11 and a second electrode E12. The second transistor T2 can include a second gate electrode G2, a third electrode E21 and a fourth electrode E22. The first gate electrode G1 and the second gate electrode G2 are connected to the first word line driver SWD_X. The first electrode E11 is connected to a preset voltage terminal Vkk. The second electrode E12 is connected to the third electrode E21 and to an output terminal SWD. The fourth electrode E22 is connected to the second word line driver SWD_Y. The output terminal SWD can be connected to a word line corresponding to the gate sub-circuit 20.

[0061] In some embodiments, the first transistor T1 and the second transistor T2 are of opposite polarities. For example, the first transistor T1 can be an N-type transistor and the second transistor T2 can be a P-type transistor.

[0062] When the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor, the working process of the selection sub-circuit 20 is as follows: when the first word line driver SWD_X loads a high-level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, and the voltage of the preset voltage terminal Vkk is loaded to the output terminal SWD. At this time, the voltage of the second word line driver SWD_Y can be the first voltage V1; when the first word line driver SWD_X loads a low-level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the voltage of the second word line driver SWD_Y, that is, the second voltage Vpp, is loaded to the output terminal SWD. The voltage of the second word line driver SWD_Y can be the second voltage Vpp. The voltage loaded on the first word line driver SWD_X can be 0 or VDD, and the voltage loaded on the second word line driver SWD_Y can be the first voltage V1 or the second voltage Vpp. The preset voltage terminal Vkk loads the first voltage V1, where the first voltage V1 < 0, and the second voltage Vpp > VDD. The signal of the output terminal SWD is loaded to the corresponding word line, that is, the storage unit 11 connected to the word line can be activated or inactivated. That is, the output terminal SWD can output the first voltage V1 or the second voltage Vpp, and one of the first voltage V1 and the second voltage Vpp is the activation level signal of the storage unit 11, and the other is the non-activation level signal of the storage unit 11. When it is needed to output the activation level signal to the corresponding word line, since the selection sub-circuit 20 is an inverter, the first word line driver SWD_X can load a signal opposite to the activation level signal. For example, when the activation level signal is Vpp, the first word line driver SWD_X loads a low-level signal, and when the activation level signal is Vkk, the first word line driver SWD_X loads a high-level signal.

[0063] In some embodiments, VDD is, for example, 1.1 volts (V) to 1.2 V, Vkk is, for example, -0.5 V to -0.3 V, and Vpp is, for example, 2.5 V to 3.0 V. Here, only an example is given, and the embodiments of the present disclosure are not limited thereto. Other values can be set as needed.

[0064] In some embodiments, as shown in FIG. 5, the first gate electrode G1 and the second gate electrode G2 can be connected to the second word line driver SWD_Y, and the fourth electrode E22 can be connected to the first word line driver SWD_X. At this time, the voltage loaded on the second word line driver SWD_Y is 0 or VDD, and the voltage loaded on the first word line driver SWD_X can be the first voltage V1 or the second voltage Vpp.

[0065] Figure 6 is a schematic diagram of the connection of the gating sub-circuit 20 and the first word line driver SWD_X, the second word line driver SWD_Y according to some embodiments. As shown in Figure 6, the memory can include M rows and N columns of word lines, 2N first word line drivers SWD_X(i), i is 0 to 2N-1, and M / 2 second word line drivers SWD_Y(j), j is 0 to M / 2-1, the first word line driver SWD_X(i) and the second word line driver SWD_Y(j) are connected to the gating sub-circuit 20, the gating sub-circuit 20 outputs a signal to the corresponding word line through the output terminal SWD_ij, then:

[0066] The word line of the first row and the first column is connected to SWD_00, the word line of the first row and the second column is connected to SWD_20, the word line of the first row and the third column is connected to SWD_40, and so on, the word line of the first row and the Nth column is connected to SWD_(2N-2)0;

[0067] The word line of the second row and the first column is connected to SWD_10, the word line of the second row and the second column is connected to SWD_30, the word line of the second row and the third column is connected to SWD_50, and so on, the word line of the second row and the Nth column is connected to SWD_(2N-1)0;

[0068] The word line of the third row and the first column is connected to SWD_01, the word line of the third row and the second column is connected to SWD_21, the word line of the third row and the third column is connected to SWD_41, and so on, the word line of the third row and the Nth column is connected to SWD_(2N-2)1;

[0069] The word line of the fourth row and the first column is connected to SWD_11, the word line of the fourth row and the second column is connected to SWD_31, the word line of the fourth row and the third column is connected to SWD_51, and so on, the word line of the fourth row and the Nth column is connected to SWD_(2N-1)1;

[0070] By analogy, the word line of the M-1th row and the first column is connected to SWD_0(M / 2-1), the word line of the M-1th row and the second column is connected to SWD_2(M / 2-1), the word line of the M-1th row and the third column is connected to SWD_4(M / 2-1), and so on, the word line of the M-1th row and the Nth column is connected to SWD_(2N-2)(M / 2-1);

[0071] The word line of the Mth row and the first column is connected to SWD_1(M / 2-1), the word line of the Mth row and the second column is connected to SWD_3(M / 2-1), the word line of the Mth row and the third column is connected to SWD_5(M / 2-1), and so on, the word line of the Mth row and the Nth column is connected to SWD_(2N-1)(M / 2-1).

[0072] In some embodiments, the gating sub-circuit 20 can be arranged on the same die as the memory cell 11. As shown in FIG. 7, the gating sub-circuit 20 and the memory cell 11 are arranged on a memory die, and the first word line driver SWD_X and the second word line driver SWD_Y are arranged on a peripheral circuit die. The peripheral circuit die loads signals of the first word line driver SWD_X and the second word line driver SWD_Y to the memory die, and only K*N+M / K signals need to be transmitted between the two dies. Compared with the scheme of arranging the gating sub-circuit 20 on the peripheral circuit die (in which case M+N signals need to be transmitted between the two dies), the number of signals transmitted between the two dies can be greatly reduced. The memory die and the peripheral circuit die can be connected by hybrid bonding, but the embodiments of the present disclosure are not limited thereto, and can be connected by other means. The positions and shapes of the SWD_X hybrid bonding region and the SWD_Y hybrid bonding region shown in FIG. 7 are only examples, and the embodiments of the present disclosure are not limited thereto.

[0073] In the above embodiments, the word lines can extend in a direction perpendicular to the substrate, and the bit lines can extend in a direction parallel to the substrate. In other embodiments, the word lines can extend in a direction parallel to the substrate, and the bit lines can extend in a direction perpendicular to the substrate. That is, the memory can include a plurality of layers of memory cell arrays stacked in a direction perpendicular to the substrate, a plurality of bit lines extending in a direction perpendicular to the substrate and arranged in a first direction X and a second direction Y;

[0074] The memory cell array can include: a plurality of memory cells 11 arranged in the first direction X and the second direction Y, a plurality of word lines extending in the second direction Y and spaced apart in the first direction X; each word line corresponds to a gating sub-circuit 20; each word line is connected to a column of memory cells 11 arranged in the second direction Y, and the bit line is connected to a plurality of memory cells 11 at the same position in different layers;

[0075] The plurality of layers of word lines arranged in a direction perpendicular to the substrate (i.e., the word lines in each layer) are divided into K first word line groups, and the word lines in the same first word line group are connected to the same first word line driver SWD_X through the corresponding gating sub-circuit 20; K is greater than or equal to 2;

[0076] The word lines of the memory cell array are divided into a plurality of second word line groups, each second word line group includes K layers of word lines, and each word line in the K layers of word lines is connected to a different first word line driver SWD_X; the word lines in the same second word line group are connected to the same second word line driver SWD_Y through the corresponding gating sub-circuit 20.

[0077] In some embodiments, K-1 word lines (which are word lines in K-1 layers and in the same column) can be arranged between adjacent word lines in the same first word line group. For example, when K=2, word lines in layers 1, 3, 5, …, r-1 are in one first word line group, and word lines in layers 2, 4, 6, …, r are in another first word line group. r is the number of layers of the memory cell array stack, and the example is described with r being even.

[0078] In some embodiments, each K layers of word lines can be divided into one second word line group. For example, word lines in layers 1 and 2 are in one second word line group, word lines in layers 3 and 4 are in one second word line group, and so on, and word lines in layers r-1 and r are in one second word line group.

[0079] The embodiments of the present disclosure are not limited to the above-mentioned division of the first word line group and the second word line group. For example, a plurality of layers of word lines in the same column that are continuously distributed can be divided into one first word line group, and a plurality of layers of word lines that are not continuously distributed can be divided into one second word line group. The division of the first word line group and the second word line group can be such that the word lines in the same second word line group are connected to different first word line drivers, and the word lines in the same first word line group are connected to different second word line drivers.

[0080] The structure of the gating sub-circuit 20 and the connection relationship between the gating sub-circuit 20 and the first word line driver SWD_X and the second word line driver SWD_Y can refer to the previous embodiment, and will not be described again.

[0081] The embodiments of the present disclosure also provide an electronic device including the memory described in any of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0082] The embodiments of the present disclosure provide an access method of the above-mentioned memory, which is applied to the memory described in any of the preceding embodiments, and includes the following steps.

[0083] In the data read / write phase, according to the first word line group and the second word line group in which the word line connected to the target memory cell to be operated is located, a corresponding signal is loaded on the first word line driver connected to the word line in the first word line group and the second word line driver connected to the word line in the second word line group, so as to output an activation level signal to the target memory cell through the gating sub-circuit.

[0084] When the gating sub-circuit 20 is the circuit shown in FIG. 4, loading a corresponding signal on the first word line driver connected to the word line in the first word line group and the second word line driver connected to the word line in the second word line group includes:

[0085] The first word line driver SWD_X is loaded with a signal opposite to the level of the activation level signal, and the second word line driver SWD_Y is loaded with the activation level signal (here, a signal required for activating the storage unit connected to the word line) ; for example, the second word line driver SWD_Y is loaded with Vpp, and the first word line driver SWD_X is loaded with a voltage value of 0.

[0086] When the gate-on sub-circuit 20 is the circuit shown in Fig. 5, loading the respective signals on the first word line driver connected to the word line of the first word line group and the second word line driver connected to the word line of the second word line group includes:

[0087] The second word line driver SWD_Y is loaded with a signal opposite to the level of the activation level signal, and the first word line driver SWD_X is loaded with the activation level signal. For example, the first word line driver SWD_X is loaded with Vpp, and the second word line driver SWD_Y is loaded with a voltage value of 0.

[0088] Although the embodiments of the present application are disclosed as above, the content described is only the embodiments adopted for facilitating the understanding of the present application, and is not intended to limit the present application. Any person skilled in the art of the present application can make any modification and change in the implementation form and details without departing from the spirit and scope of the present application disclosed, but the patent protection scope of the present application shall be subject to the range defined by the appended claims.

Claims

1. A memory, comprising: A multi-layer memory cell array stacked in a direction perpendicular to a substrate; The memory cell array comprises a plurality of memory cells arranged in a first direction and a second direction; The memory further comprises a plurality of word lines extending in a direction perpendicular to the substrate arranged in the first direction and the second direction, the word lines connecting a plurality of memory cells at the same position in different layers; the memory cell array further comprises a plurality of bit lines extending in the second direction and spaced apart in the first direction; each of the bit lines connects a column of memory cells arranged in the second direction; and word lines of the same column arranged in the second direction are divided into K first word line groups; the word lines of the memory cell array are divided into a plurality of second word line groups, each second word line group comprising K rows of word lines, and each word line in the K rows of word lines being connected to a different first word line driver; Or the memory further comprises a plurality of bit lines extending in a direction perpendicular to the substrate arranged in the first direction and the second direction, the bit lines connecting a plurality of memory cells at the same position in different layers; the memory cell array further comprises a plurality of word lines extending in the second direction and spaced apart in the first direction; each of the word lines connects a column of memory cells arranged in the second direction, and word lines of the same column arranged in a direction perpendicular to the substrate are divided into K first word line groups; the word lines of the memory cell array are divided into a plurality of second word line groups, each second word line group comprising K layers of word lines, and each word line in the K layers of word lines being connected to a different first word line driver; Wherein each word line corresponds to a selection sub-circuit, and the word lines of the same first word line group are respectively connected to the same first word line driver through the corresponding selection sub-circuits; the word lines of the same second word line group are respectively connected to the same second word line driver through the corresponding selection sub-circuits, K is greater than or equal to 2, and the first direction and the second direction are parallel to the substrate and intersect.

2. The memory of claim 1, wherein, The adjacent word lines in the same first word line group are spaced apart by K-1 word lines; each continuous K rows or K layers of word lines are divided into a second word line group.

3. The memory of claim 1, wherein, The K=2.

4. The memory according to claim 1, wherein the selection sub-circuits and the memory cell array are located in the same die, and the first word line drivers and the second word line drivers are located in different dies.

5. The memory of any one of claims 1 to 4, wherein, The selection sub-circuit comprises a first transistor and a second transistor, the first transistor and the second transistor are opposite in polarity, the first transistor comprises a first gate electrode, a first electrode and a second electrode, and the second transistor comprises a second gate electrode, a third electrode and a fourth electrode; The first gate electrode and the second gate electrode are connected to the first word line driver, the first electrode is connected to a preset voltage terminal, the second electrode is connected to the third electrode and connected to an output terminal, and the fourth electrode is connected to the second word line driver; Or, the first gate electrode and the second gate electrode are connected to the second word line driver, the first electrode is connected to a preset voltage terminal, the second electrode is connected to the third electrode and connected to an output terminal, and the fourth electrode is connected to the first word line driver; The output end is connected to a word line corresponding to the gating sub-circuit.

6. The memory of claim 5, wherein, The first transistor is an N-type transistor, and the second transistor is a P-type transistor.

7. The memory of claim 6, wherein, The first word line driver is loaded with an on voltage and an off voltage, the second word line driver is loaded with a first voltage and a second voltage, and the preset voltage end is loaded with the first voltage, wherein the first voltage is less than the off voltage, and the second voltage is greater than the on voltage.

8. An access method applied to the memory of any one of claims 1 to 7, comprising: In a data read / write phase, according to a first word line group and a second word line group in which a word line connected to a target memory cell to be operated is located, a corresponding signal is loaded on a first word line driver connected to a word line of the first word line group and a second word line driver connected to a word line of the second word line group, so as to output an activation level signal to the target memory cell through the gating sub-circuit. The memory is the memory of claim 7, and loading the corresponding signal on the first word line driver connected to the word line of the first word line group and the second word line driver connected to the word line of the second word line group comprises:

9. The access method of claim 8, wherein, When the first gate electrode and the second gate electrode are connected to the first word line driver and the fourth electrode is connected to the second word line driver, the first word line driver is loaded with a signal opposite to a level of the activation level signal, and the second word line driver is loaded with the activation level signal; When the first gate electrode and the second gate electrode are connected to the second word line driver and the fourth electrode is connected to the first word line driver, the second word line driver is loaded with a signal opposite to a level of the activation level signal, and the first word line driver is loaded with the activation level signal.

10. An electronic device comprising the memory of any one of claims 1 to 7. ​

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