Method for producing a component, and assembly

Abstract

The invention relates to a method for producing a component. The method comprises the following steps: providing at least one semiconductor element and a control structure on a carrier, applying a first layer to a side of the semiconductor element facing away from the carrier and a second layer to a side of the control structure facing away from the carrier, wherein the second layer covers portions of the side of the control structure facing away from the carrier, the first layer has a first surface facing away from the semiconductor element, the second layer has a second surface facing away from the control structure, and the first surface and the second surface are at least approximately partial surfaces of a notional common plane. The invention also relates to an assembly.

Description

[0001] 2023PF01465 19 . August 2025 P2024 , 0132 WO N

[0002] 1

[0003] Description

[0004] METHOD FOR MANUFACTURING A BUILDING ELEMENT AND ARRANGEMENT

[0005] A method for manufacturing at least one component and an arrangement are specified.

[0006] One task to be solved is to specify a method for manufacturing a component or a plurality of components with particular efficiency. Another task is to specify a particularly efficient arrangement, for example, an arrangement of components or of main components.

[0007] The problems are solved by the subject matter of the independent patent claims. Advantageous embodiments and further developments are specified in the dependent claims.

[0008] According to at least one embodiment of the method for manufacturing a component, the method comprises providing at least one semiconductor body or a plurality of semiconductor bodies and a control structure or a plurality of control structures on a substrate.

[0009] The semiconductor body may have a sequence of semiconductor layers. For example, the sequence of semiconductor layers and / or the semiconductor body is configured to generate electromagnetic radiation. The semiconductor body may have a light-emitting surface. For example, the electromagnetic radiation is emitted at the light-emitting surface of the 2023PF01465 19 August 2025

[0010] P2024 , 0132 WO N

[0011] 2

[0012] emitted from or coupled out of the semiconductor body.

[0013] The support can be, for example, a growth substrate. This can mean that the semiconductor body is grown onto the support. However, it is also possible that the support is different from a growth substrate. The support can have a principal extent plane. The thickness of the support, the control structure, and / or the semiconductor body can be an extent of the support, the control structure, and / or the semiconductor body along a direction that is perpendicular or at least approximately perpendicular to the principal extent plane of the support. The thickness can be an extent along a vertical direction. Lateral directions, for example, run parallel to the principal extent plane of the support.

[0014] The control structure can be a marker, in particular an OCR marker (Optical Character Recognition Marker). This can mean that the control structure contains characters and / or text. In particular, the control structure can be machine-readable. The control structure can, for example, be configured as a position reference marker in one or more systems. For example, the control structure can be used for automated optical inspection. Alternatively or additionally, the control structure can be used to sort LEDs. The control structure can also be referred to as a test structure or marker. 2023PF01465 August 19, 2025

[0015] P2024 , 0132 WO N

[0016] - 3 -

[0017] It is also possible for multiple control structures to be arranged on the carrier. For example, more than one control structure, such as three control structures or a multitude of control structures, may be arranged on the carrier. The control structures can be spaced apart from each other. For example, the control structures may be distributed across the carrier.

[0018] The thickness of the control structure can be less than or equal to the thickness of the semiconductor body.

[0019] According to at least one embodiment of the method for manufacturing a component, the method comprises the deposition of a first layer onto a side of the semiconductor body facing away from the substrate. The method may comprise the deposition of a second layer onto a side of the control structure facing away from the substrate.

[0020] The first layer and / or the second layer may be configured to influence or modify the electromagnetic radiation generated or emitted by the semiconductor body.

[0021] The first layer and / or the second layer may, for example, include or consist of an extraction coupling aid. An extraction coupling aid can mean that the layer improves the extraction of the electromagnetic radiation generated by the semiconductor body. For example, the extraction coupling aid prevents or at least reduces total reflection of the electromagnetic radiation at the light-emitting surface. 2023PF01465 August 19, 2025

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[0023] - 4 -

[0024] Alternatively or additionally, the first layer and / or the second layer may have or consist of a color-over-angle coating. It is also possible that the first layer and / or the second layer may include or consist of a protective layer. Alternatively or additionally, the first layer and / or the second layer may be a conversion layer, or the first layer and / or the second layer may have a conversion layer. This can mean that the first layer, the second layer, and / or the layer is configured to change the wavelength of the electromagnetic radiation emitted or generated by the semiconductor device. For example, the wavelength or wavelength distribution of the electromagnetic radiation emitted by the device can be set using the first layer, the second layer, or the layer.

[0025] For example, the first layer can be spaced apart from the second layer.

[0026] According to at least one embodiment of the method for manufacturing a component, the second layer partially covers, and in particular only partially covers, the side of the control structure facing away from the substrate. This simplifies the reading of information from the control structure. For example, an inner area of ​​the control structure is free of the second layer. The second layer may be arranged on the control structure in a frame-like, ring-like, and / or donut-shaped configuration. The second layer may be designed to ensure sufficient mechanical stability during re-taping or relamination. This may mean that the second layer 2023PF01465 19 August 2025

[0027] P2024 , 0132 WO N

[0028] - 5 - a sufficiently large area of ​​the control structure is covered. The second layer can be applied to the control structure using a photolithographic process.

[0029] According to at least one embodiment of the method for manufacturing a component, the first layer has a first surface facing away from the semiconductor body. This first surface can be an outer surface of the first layer.

[0030] According to at least one embodiment of the method for manufacturing a component, the second layer has a second surface facing away from the control structure. The second surface comprises or forms, for example, an outer surface of the second layer.

[0031] According to at least one embodiment of the method for manufacturing a component, the first surface and the second surface are at least approximately parts of an imaginary plane, for example, within the limits of manufacturing tolerances. In other words, the first surface and the second surface can be at the same vertical height. This means, for example, that the first surface and the second surface have the same vertical distance from the support. The imaginary plane can be parallel to the principal plane of extension of the support. For example, the first surface and / or the second surface run parallel to the principal plane of extension of the support.

[0032] In at least one embodiment, the method for manufacturing a component comprises providing at least one semiconductor body and one control structure on a 2023PF01465 19 August 2025 P2024 , 0132 WO N

[0033] 6

[0034] The substrate and the deposition of a first layer onto a side of the semiconductor body facing away from the substrate, and a second layer onto a side of the control structure facing away from the substrate. The second layer can only partially cover the side of the control structure facing away from the substrate. The first layer has a first surface facing away from the semiconductor body. The second layer has a second surface facing away from the control structure. The first surface and the second surface can be, at least approximately, parts of an imaginary common plane.

[0035] The method described here is based, among other things, on the idea of ​​producing at least one component that can be manufactured particularly efficiently. This component could be an LED, for example a thin-film LED.

[0036] It is also possible that the component is a micro-LED. Broadly speaking, a micro-LED could be any light-emitting diode or LED – generally not a laser – with a particularly small size. Typically – and this is a very important criterion besides size – a growth substrate may be removed in micro-LEDs, so that typical heights of such micro-LEDs are, for example, in the range of 1.5 pm to 10 pm.

[0037] In principle, a micro-LED does not necessarily have to have a rectangular emission surface. Generally, a micro-LED could, for example, have an emission surface where, viewed from above, each lateral extent of the emission surface is less than or equal to 2023PF01465 19 August 2025 P2024 , 0132 WO N

[0038] 7

[0039] 100 gm or less than or equal to 70 gm. For example, for rectangular micro-LEDs, an edge length of less than or equal to 70 gm or less than or equal to 50 gm is often cited as a criterion, especially when viewed from above the layers of the layer stack.

[0040] For example, such micro-LEDs can be provided on wafers with holding structures that can be removed without damaging the micro-LED.

[0041] Currently, the primary applications for micro-LEDs are displays. Micro-LEDs form pixels or subpixels and emit light of a defined color. Due to their small pixel size and high density with close spacing, micro-LEDs are suitable for small monolithic displays for AR applications, particularly smart glasses. Further applications are also being developed, especially in data communication and pixelated lighting applications.

[0042] In the literature you will find various spellings for micro-LED, e.g. gLED, g-LED, uLED or u-LED.

[0043] To manufacture components with a conversion layer, freestanding conversion plates, such as phosphor-in-glass or phosphor-ceramic converters, can be applied to the LED using a layer-attach process. The plates can be bonded to the chip using, for example, LRI (low refractive index) silicone. For this process, the LED wafer can be completely processed in the front end, and then the individual chips can be connected to the corresponding conversion element and completed in the back end. 2023PF01465 August 19, 2025

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[0045] - 8 -

[0046] If the layer, especially a conversion layer, is applied directly to the semiconductor body, the component can exhibit improved heat dissipation compared to components with bonded conversion layers or conversion plates. Furthermore, by directly applying the layer, for example, the conversion layer, to the semiconductor body, the lateral dimension of the layer can be particularly well adapted to a light-emitting area of ​​the semiconductor body. Additionally, the component height can be reduced by directly applying the layer or conversion layer. For example, the thickness of the conversion layer in a white-converted LED is between 10 and 50 pm. Such a small thickness is not achievable, for example, by bonding conversion layers or conversion plates. The component can, for example, exhibit increased brightness.

[0047] Such a layer or conversion layer can be applied, for example, in the front end, such as in front-end LED manufacturing. "Front end" can mean that the layer or conversion layer is applied within the wafer assembly. More specifically, "front end" can mean that such a layer or conversion layer is applied during the manufacturing of the semiconductor or LED chip before housing and / or packaging processes. This simplifies and streamlines the application of the layer.

[0048] According to at least one embodiment of the method for manufacturing a component, a first sum of the thickness of the semiconductor body and the thickness of the first layer deviates by a maximum of 20% from a second sum of the thickness of the 2023PF01465 19 August 2025

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[0050] - 9 -

[0051] The thickness of the control structure and the second layer varies. For example, the first layer may deviate by a maximum of 10%, 5%, or 2% from the second layer. An advantage of this design is that during re-taping or relamination, the semiconductor bodies and the control structure(s) can be reliably and easily bonded to a tape, film, or other substrate using the respective first layer, second layer, or layer, without potential damage.

[0052] According to at least one embodiment of the process for manufacturing a component, the first and second layers consist of the same material. For example, the first and second layers consist of a conversion material. The first and second layers can be applied in a single process step. This can mean that the first and second layers are applied simultaneously. For example, the first and second layers are sub-regions of a single layer. The layer, or the first and second layers, can thus be applied or arranged more easily. The material similarity of the first and second layers can have a positive effect in subsequent processes. For example, the material of the layer, for instance, the first and second layers, does not outgas or at least does so in approximately the same way.Furthermore, the isolation of the components and / or control structures can be simplified or improved by the material similarity of the first layer and the second layer.

[0053] According to at least one embodiment, the side of the semiconductor body facing away from the support has a light-emitting surface. 2023PF01465 19 August 2025 P2024 , 0132 WO N

[0054] 10

[0055] Surface area. For example, the semiconductor body is a main body of the component. The component can be a surface-emitting semiconductor chip, or the component can have a surface-emitting semiconductor chip.

[0056] According to at least one implementation form, the control structure is set up for orientation in production facilities.

[0057] According to at least one embodiment of the method for manufacturing a component, a photoresist is applied to the substrate, the semiconductor body and / or the control structure before the first layer and the second layer are applied.

[0058] According to at least one embodiment of the process, the photoresist is structured before the application of the first and second layers. For example, the photoresist is structured such that a light-emitting area of ​​the semiconductor body is free of the photoresist. The side of the control structure facing away from the substrate, for example, is only partially covered by the photoresist.

[0059] According to at least one embodiment, the control structure, for example in the form of a marker, has a machine-readable area. The machine-readable area of ​​the control structure may be covered by the photoresist. The machine-readable area is, for example, the inner area of ​​the control structure, or the inner area of ​​the control structure contains the machine-readable area of ​​the control structure. Because the machine-readable area of ​​the control structure is covered by the photoresist 2023PF01465 19 August 2025 P2024 , 0132 WO N

[0060] If layer 11 is covered, it can be easily and efficiently prevented that the second layer, or the layer on the machine-readable area of ​​the control structure, is located. This ensures that the machine-readable area can be detected or read.

[0061] According to at least one implementation method, cavities are formed during the structuring of the photoresist. The first and second layers, or layers, can each be applied to at least one of the cavities. For example, the first and / or second layer can be applied to the respective cavities by means of a doctor blade or by pouring. If the first and / or second layer is applied by means of a doctor blade, subsequent sanding is not necessary. The first and / or second layer can then, for example, be flush with the photoresist in the vertical direction.

[0062] According to at least one embodiment of the method for manufacturing a component, the first layer and the second layer are arranged such that the first layer and the second layer extend beyond the photoresist on the side of the photoresist facing away from the substrate.

[0063] According to at least one embodiment, the process includes grinding the first surface and / or the second surface. A top surface comprising the first surface, the second surface, and / or the side of the photoresist facing away from the substrate can thereby be planarized.

[0064] According to at least one implementation form, the method for manufacturing a plurality of components is established. 2023PF01465 19 August 2025

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[0066] 12

[0067] For example, the process involves providing a wafer array with a plurality of semiconductor bodies and a plurality of control structures on the substrate. The process may include a step of singulating the wafer array into a plurality of components and control structures. The wafer array may, for example, have fewer control structures than semiconductor bodies.

[0068] According to at least one implementation, singulating the wafer assembly includes cutting or singulating the carrier into a plurality of chip carriers. Each component and / or control structure can be assigned a chip carrier. The fact that each component and / or control structure can be assigned a chip carrier can mean that each component and / or control structure has a chip carrier. For example, each component and / or control structure is uniquely assigned a chip carrier. It is possible that, after singulating the wafer assembly into a plurality of components and control structures, no component with a control structure is arranged on a common carrier. For example, after singulating the wafer assembly into a plurality of components and control structures, no component with a control structure is arranged on a common chip carrier.For example, the support is thinned before being cut. The method for manufacturing a plurality of components may include arranging the components and / or control structures on an auxiliary support. It is possible for the components and control structures to be spaced apart from each other on the auxiliary support. 2023PF01465 19 August 2025 P2024 , 0132 WO N.

[0069] 13

[0070] The support structure can, for example, be continuous. The support structure can be designed so that the components can be detached from it, in particular without damage or destruction. The support structure can have a film or itself be a mechanically stable film.

[0071] Furthermore, an arrangement, for example of components, is specified. The arrangement is preferably producible using a method described herein, or the arrangement is, in particular, an intermediate product of the method described herein. In other words, all features of the method for producing a component are also of the arrangement and vice versa.

[0072] According to at least one embodiment, the arrangement includes a support, for example, a common support. The support can be a growth substrate. Alternatively, the support can be different from a growth substrate.

[0073] According to at least one embodiment, the arrangement comprises one or more semiconductor bodies. The semiconductor body or bodies are, for example, arranged on the substrate and / or grown onto the substrate. The semiconductor bodies on the substrate can have a similar structure and / or identical assembly structures.

[0074] According to at least one implementation form, the arrangement comprises a control structure or a plurality of control structures. The control structure or plurality of control structures is, for example, on carrier 2023PF01465, dated August 19, 2025.

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[0076] - 14 - arranged. In particular, the control structure and the semiconductor body can be arranged on the same side of the support. For example, the arrangement has fewer control structures than semiconductor bodies. This can mean that in the arrangement the number of control structures is smaller than the number of semiconductor bodies.

[0077] According to at least one embodiment, the arrangement comprises a first layer. The first layer can be located on the side of the semiconductor body facing away from the support. The first layer has a first surface facing away from the semiconductor body.

[0078] According to at least one embodiment, the arrangement comprises a second layer. The second layer can be arranged on the side of the control structure facing away from the support. For example, the second layer covers the side of the control structure facing away from the support only partially, for instance, only partially. The second layer has a second surface facing away from the control structure.

[0079] According to at least one embodiment of the arrangement, the first surface and the second surface are at least approximately subsurfaces of an imaginary common plane. This can mean that a first sum of the thickness of the semiconductor body and a second thickness of the first layer deviates by a maximum of 20% from a second sum of the thickness of the control structure and a thickness of the second layer.

[0080] In at least one embodiment of an arrangement, the arrangement comprises a support, a semiconductor body on the 2023PF01465 19 August 2025 P2024 , 0132 WO N

[0081] 15

[0082] The semiconductor consists of a substrate, a control structure on the substrate, a first layer, and a second layer. The first layer can be located on the side of the semiconductor body facing away from the substrate. For example, the second layer is located on the side of the control structure facing away from the substrate. The second layer can partially cover the side of the control structure facing away from the substrate. For example, the first layer has a first surface facing away from the semiconductor body. For example, the second layer has a second surface facing away from the control structure. The first surface and the second surface can be part of a common plane.

[0083] According to at least one embodiment of the arrangement, the first layer and the second layer have the same material, are formed from the same material, or consist of the same material.

[0084] According to at least one embodiment of the arrangement, the semiconductor bodies and the control structures are spaced apart in pairs. This allows the components to be simplified and separated without damage.

[0085] According to at least one embodiment of the arrangement, the arrangement comprises a plurality of semiconductor bodies and a plurality of control structures, for example, at least three control structures. The semiconductor bodies and the control structures are arranged, for example, at lattice points of a regular lattice.

[0086] According to at least one embodiment of the arrangement, the support has an auxiliary support that is different from a growth substrate. It is also possible that the support 2023PF01465 19 August 2025 P2024 , 0132 WO N

[0087] 16. An auxiliary support is present. A first chip support can be located between the semiconductor body and the auxiliary support. A second chip support can be located between the control structure and the auxiliary support. The first chip support and the second chip support are, for example, made of the same material. For example, the first chip support and / or the second chip support can be part of a growth substrate.

[0088] The following section explains in more detail the method for manufacturing a component and the arrangement described here, in conjunction with exemplary embodiments and the associated figures.

[0089] Figures 1A, 1B, IC, ID and IE show steps in a method for manufacturing a component according to an exemplary embodiment.

[0090] Figures 2, 3 and 4 show schematic top views of a control structure according to the examples shown.

[0091] Figures 5A, 5B, 5C and 5D show steps in a process for manufacturing a component according to a comparative example.

[0092] Identical, similar, or similarly effective elements are marked with the same reference symbols in the figures. The figures and the relative sizes of the elements depicted within them are not to be considered to scale. Rather, individual elements may be exaggerated for better representation and / or clarity. 2023PF01465 19 August 2025 P2024 , 0132 WO N

[0093] 17

[0094] Figure 1A shows a cross-sectional view of a process step in a method for fabricating a component 2. In this process, at least one semiconductor body 3 and a control structure 5 are provided on a support 6. The support 6 can be a growth substrate. This can mean that the semiconductor body 3 is grown on the support 6.

[0095] The control structure 5 is arranged laterally next to the at least one semiconductor body 3. For example, the control structure 5 and the at least one semiconductor body 3 are located on the same side of the support 6, for example on a top side of the support 6.

[0096] Control structure 5 can be set up for orientation in production facilities.

[0097] For example, control structure 5 is a marker, specifically an OCR marker. This can mean that the control structure is machine-readable. For example, an inner region 15 of control structure 5 is machine-readable. Therefore, control structure 5 can be detected and / or read by a production system, for example. In particular, the position of control structure 5, or the position of several control structures 5 in a wafer array, can be detected, for example, automatically detected, determined, and / or read. In order for a control structure 5 to be effectively detected and / or read, control structure 5, or at least the inner region 15 of control structure 5, should be visible. For example, the inner region 15 is not covered by a non-transparent layer, such as a conversion layer. 2023PF01465 19 August 2025 P2024, 0132 WO N

[0098] - 18 -

[0099] The semiconductor body 3 can have a light-emitting surface 13. For example, a side of the semiconductor body 3 facing away from the support 6 has the light-emitting surface 13. This can mean that the component 2 has a surface-emitting semiconductor chip or is a surface-emitting semiconductor chip.

[0100] It is possible to produce a plurality of components 2 using the method. In particular, the plurality or multiple of components 2 can be produced simultaneously. Then, for example, a wafer composite with a plurality of semiconductor bodies 3 and a plurality of control structures 5 is provided on the substrate 6.

[0101] At least one contact 4 can be arranged on the carrier 6. The contact 4 can be a contact, in particular an upper contact of the component 2. For example, the contact 4 is configured for electrical contacting the semiconductor body 3.

[0102] The control structure 5 is, for example, arranged at a distance from the semiconductor bodies 3. For instance, the control structure 5 is not in direct contact with a semiconductor body 3 and / or another control structure 5. Thus, in a subsequent process step, the wafer assembly with a plurality of semiconductor bodies 3 and control structures 5 can be simplified to be separated into components 2 and control structures 5.

[0103] Figure 1B shows one following Figure 1A

[0104] Process step in which a photoresist 7 is applied to the substrate 6, the semiconductor body 3 and / or the control structure 5 2023PF01465 19 August 2025

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[0106] - 19 - is applied. The photoresist 7 borders, for example, the semiconductor body 3 and / or the control structure 5 in a lateral direction x, y. This can mean that the photoresist 7 is at least partially in direct contact with the semiconductor body 3 and / or the control structure 5.

[0107] For example, the photoresist 7 is not arranged on the light-emitting surface 13 of the semiconductor body 3. In other words, the side of the semiconductor body 3 facing away from the support 6, for example the light-emitting surface 13, can be at least partially or completely free of the photoresist 7.

[0108] The control structure 5 can be partially covered by the photoresist 7, for example, only partially. This can mean that the photoresist 7 is located on the side of the control structure 5 facing away from the support 6. As shown here, the photoresist 7 can cover an inner area of ​​the control structure 5. In a top view, the photoresist 7 can have a donut-shaped structure in the area of ​​the control structure 5.

[0109] For example, in a process step preceding Figure 1B, the photoresist 7 was applied as a continuous, continuous, and / or planar layer to the substrate 6, the at least one semiconductor body 3, and the at least one control structure 5. Subsequently, the photoresist 7 was, for example, structured. In particular, the photoresist 7 was structured such that a light-emitting area 13 of the semiconductor body 3 is free of the photoresist 7, and the side of the control structure facing away from the substrate is partially, for example, only 2023PF01465 19 August 2025

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[0111] 20 is partially covered by the photoresist 7. This allows cavities 14 to be formed, which, for example, are completely surrounded laterally by the photoresist 7.

[0112] For example, photoresist 7 can be a dry film photoresist, such as a negative dry film photoresist, or photoresist 7 can have a dry film photoresist.

[0113] Figure IC shows a sectional view of an arrangement 1 after further process steps. After the process step shown in Figure 1B of structuring the photoresist 7 to form cavities 14, a first layer 8 can be applied to a side of the semiconductor body 3 facing away from the support 6. For example, a second layer 9 is applied to a side of the control structure 5 facing away from the support 6. For example, the first layer 8 and the second layer 9 are each placed into at least one of the cavities 14. The first layer 8 and / or the second layer 9 can be formed simultaneously, i.e., in a common process step, for example by doctor blades or casting. The first layer 8 and the second layer 9 can be designed as laterally spaced sublayers of a common layer 10. For example, the first layer 8 can be spaced apart from the second layer 9.

[0114] It is possible that the first layer 8 and / or the second layer 9 protrudes beyond the photoresist 7 on the side of the photoresist 7 facing away from the substrate 6, or at least is located partially on the side of the photoresist 7 facing away from the substrate 6. Alternatively, the first layer 8, the second layer 9 and / or the layer 10 can be located on the side of the photoresist 7 facing away from the substrate 6. 2023PF01465 19 August 2025

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[0116] - 21 - the opposite side is flush with the photoresist 7. It is also possible that the photoresist 7 extends beyond the first layer 8, the second layer 9 and / or the layer 10 in a direction away from the substrate 6.

[0117] The first layer 8 and the second layer 9 can be made of the same material. This can mean that a material of the first layer 8 and a material of the second layer 9 are at least approximately identical. For example, the first layer 8 and the second layer 9 are applied in a common process step, particularly simultaneously. This can mean that the first layer 8 and the second layer 9 form a common layer 10 or are encompassed by layer 10.

[0118] To proceed from the process step shown in Figure 1B to the arrangement shown in Figure IC, the photoresist 7 can be further removed, for example, using a stripping medium. It is possible to expose the photoresist 7 before removal, for example, by sanding. This can mean that the first layer 8, the second layer 9, and / or the layer 10 are removed from the side of the photoresist 7 facing away from the substrate 6, for example, by sanding, in order to expose the photoresist 7. During sanding, a portion of the photoresist 7 can also be removed or abraded. For example, during sanding, a top surface of the arrangement 1 comprising the first layer 8, the second layer 9, the layer 10, and / or the photoresist 7 is planarized. This can mean that the top surface of the arrangement 1 has or forms a plane. The top surface of the arrangement 1 can run parallel to a principal extension plane of the support 6.2023PF01465 19 August 2025.

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[0120] - 22 -

[0121] The second layer 9 partially covers the side of the control structure 5 facing away from the support 6, as shown here. The first layer 8 covers the light-emitting surface 13 of the semiconductor body 3, for example, completely. The first layer 8 has a first surface 11 facing away from the semiconductor body 3. The second layer 9 has a second surface 12 facing away from the control structure 5. A first sum D1 of the thickness of the semiconductor body 3 and the thickness of the first layer 8 can differ by a maximum of 20% from a second sum D2 of the thickness of the control structure 5 and the thickness of the second layer 9. This can mean that the first surface 11 and the second surface 12 are at least approximately parts of an imaginary common plane.

[0122] Figure ID shows a further process step in a method for manufacturing a component 2 or an arrangement 1 according to an exemplary embodiment. Following the process step shown in Figure IC, the carrier 6 is thinned, for example. It is also possible that a metallization, for example another contact (not shown), is applied to the side of the carrier 6 facing away from the semiconductor body 3. Shown here, the carrier 6 is cut to separate the components 2 of the wafer assembly, comprising the semiconductor bodies 3 and control structures 5. The carrier 6 is thereby separated, for example, into chip carriers 61.

[0123] Figure IE shows a further process step in a method for manufacturing a component 2 or an arrangement 1 according to a further embodiment. The arrangement 1 shown in Figure IE differs from that shown in 2023PF01465, dated August 19, 2025.

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[0125] - 23 - in the arrangement 1 shown in Figure ID, for example, in that the individual components 2 and / or control structures 5 are arranged on a common auxiliary carrier 17. The auxiliary carrier 17 is, for example, in direct contact with the carrier 6 or with the individual chip carriers 61.

[0126] The support carrier 17 can be different from a growth substrate. For example, a first chip carrier 61 is arranged between the semiconductor body 3 and the support carrier 17. Alternatively or additionally, a second chip carrier 61 can be arranged between the control structure 5 and the support carrier 17. The chip carriers 61 can be spaced apart from each other on the support carrier 17. For example, the first chip carrier 61 and the second chip carrier 61 are formed from the same material. In particular, the first chip carrier 61 and the second chip carrier 61 can be parts of the carrier 6. In other words, the first chip carrier 61 and the second chip carrier 61 are, for example, formed from the carrier 6.

[0127] Figure 2 shows a schematic top view of an arrangement 1 or a control structure 5 according to an exemplary embodiment. The second layer 9 or layer 10 is structured in an annular, frame-like, or donut-shaped manner. The second layer 9 has a web width. The web width is an uninterrupted extension of the second layer along the lateral directions x, y. The web width is, for example, sufficiently large to ensure adequate mechanical stability during re-taping or relamination. The inner region 15 of the control structure 5 is free of layer 9 or layer 10. An edge region 16 of the

[0128] Control structure 5 is at least partially free from the 2023PF01465 19 August 2025 P2024 , 0132 WO N

[0129] 24 second layer 9 or from layer 10. The boundary region 16 of the control structure 5 surrounds the inner region 15 of the control structure 5 in lateral directions x, y at least partially, and in particular completely. For example, an outline of the region of the control structure 5 covered by layer 9 or layer 10 corresponds to an outline of the light-emitting surface 13 of a semiconductor body 3.

[0130] The arrangement 1 comprises a plurality of semiconductor bodies 3 and, for example, at least three, in particular a plurality of, control structures 5. For example, the semiconductor bodies 3 and control structures 5 are arranged at lattice points of a regular lattice. It is possible that the semiconductor bodies 3 and the control structures 5 are spaced apart from each other in pairs.

[0131] Figure 3 shows a schematic top view of an arrangement 1 or a control structure 5 according to a further embodiment. The control structure 5 is partially free of the second layer 9 and / or the layer 10 in the edge region 16. For example, the control structure 5 is not covered by the second layer 9 and / or the layer 10 at at least one corner, for example at two corners, as shown here. It is possible that the control structure 5 can be easily identified, recognized and / or determined in the production plant.

[0132] Figure 4 shows a schematic top view of a control structure 5 according to a further embodiment. Compared to the views of the arrangement 1 or the control structure 5 shown in Figures 2 and 3, the control structure 5 shown here has an edge region 16 which is free of the second layer 9 and / or the layer 10. 2023PF01465 19 August 2025

[0133] P2024 , 0132 WO N

[0134] - 25 - and completely surrounds laterally the area of ​​the control structure 5 covered by the second layer 9 or by layer 10 .

[0135] Figures 5A, 5B, 5C, and 5D show steps in a method for fabricating a component 2 according to a comparative example. The method shown here differs from the method shown in Figures 1A to 1ID in that, in the process step shown in Figure 5B, the photoresist 7, for example after structuring the photoresist 7, completely covers the control structure 5 on the side facing away from the support 6. In other words, no cavity 14 is arranged in the area of ​​the control structure 5. Therefore, in the further process for fabricating a component 2, the arrangement 1 is free of a second layer 9 and / or layer 10 in the area of ​​the control structure 5. This means that the arrangement 1 has only the first layer 8, which is arranged on the light-emitting surface 13 of the semiconductor body 3.

[0136] The first surface 11 of the first layer 8 and / or layer 10 is thus located in a plane that is different from a plane of the side of the control structure 5 facing away from the support. During re-taping or relamination of the semiconductor bodies 3 and the control structure(s) 5, the control structure(s) 5 are not connected to a tape or auxiliary support via the second layer 9 or layer 10. If, in this case, the support 6 is cut to separate the components 2, the control structure 5 can fall out of the arrangement 1. In other words, a position of the control structure 5 within the arrangement 1 cannot be maintained, for example. Thus, the control structure 5 2023PF01465 August 19, 2025 P2024, 0132 WO N

[0137] - 26 - subsequently, for example, they can no longer be used for orientation in production facilities.

[0138] The invention is not limited to the description provided by means of the exemplary embodiments. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes every combination of features in the claims, even if that feature or combination itself is not explicitly stated in the claims or exemplary embodiments.

[0139] This patent application claims priority over German patent application 10 2024 124 018.0, the disclosure content of which is hereby incorporated by reference.

[0140] 2023PF01465 19 . August 2025 P2024 , 0132 WO N

[0141] - 27 -

[0142] Reference character list

[0143] 1. Arrangement

[0144] 2 Component

[0145] 3 Semiconductor bodies

[0146] 4 Contact

[0147] 5 Control structure

[0148] 6 carriers

[0149] 61 chip carriers

[0150] 7 Photoresist

[0151] 8 first shift

[0152] 9 second shift

[0153] 10 shifts

[0154] 11 first surface

[0155] 12 second surface

[0156] 13 light-emitting surfaces

[0157] 14 Cavity

[0158] 15 inner area of ​​the control structure

[0159] 16. Periphery of the control structure

[0160] 17 aid workers

[0161] First sum

[0162] D2 second sum x lateral direction y lateral direction z vertical direction

Claims

2023PF01465 August 19, 2025 P2024, 0132 WO N 28 Patent claims 1. Method for manufacturing a component (2) , comprising the following steps: - Providing at least one semiconductor body (3) and one control structure (5) on a support (6) , - Depositing a first layer (8) onto a side of the semiconductor body (3) facing away from the support (6) and a second layer (9) onto a side of the control structure (5) facing away from the support (6) , wherein - the second layer (9) partially covers the side of the control structure (5) facing away from the carrier (6), - the first layer (8) has a first surface (11) facing away from the semiconductor body, - the second layer (9) has a second surface (12) facing away from the control structure (5), and - the first surface (11) and the second surface (12) are at least approximately subsurfaces of an imaginary common plane, wherein - the control structure (5) is a marker with a machine-readable area and is set up for orientation in production facilities.

2. Method for manufacturing a component (2) according to the preceding claim, wherein a first sum of a thickness of the semiconductor body (3) and a thickness of the first layer (8) deviates by a maximum of 20% from a second sum of a thickness of the control structure (5) and a thickness of the second layer (9).

3. Method according to any of the preceding claims, wherein the first layer (8) and the second layer (9) have the same 2023PF01465 August 19, 2025 P2024, 0132 WO N 29 The material must be present and applied in a single process step.

4. Method according to one of the preceding claims, wherein the side of the semiconductor body (3) facing away from the support (6) has a light-emitting surface (13).

5. Method according to any of the preceding claims, wherein the support (6) is a growth substrate.

6. Method according to one of the preceding claims, wherein a photoresist (7) is applied to the substrate (6), the semiconductor body (3) and / or the control structure (5) prior to the application of the first layer (8) and the second layer (9).

7. Method according to the previous claim, wherein the photoresist (7) is structured before the application of the first layer (8) and the second layer (9) such that a light-emitting area (13) of the semiconductor body (3) is free of the photoresist (7), and the side of the control structure (5) facing away from the support (6) is only partially covered by the photoresist (7).

8. Method according to claim 6, wherein cavities (14) are formed when structuring the photoresist (7), and the first layer (8) and the second layer (9) are each introduced into at least one of the cavities (14).

9. Method according to the previous claim, wherein the first layer (8) and the second layer (9) are arranged such that the first layer (8) and the second layer (9) extend beyond the photoresist (7) on the side of the photoresist (7) facing away from the support (6). 2023PF01465 August 19, 2025 P2024, 0132 WO N - 30 - 10. Method according to one of claims 7 to 8, wherein the method comprises grinding the first surface (11) and / or the second surface (12), wherein a top surface comprising the first layer (8), the second layer (9) and / or the photoresist (7) is planarized.

11. Method according to one of the preceding claims for producing a plurality of components (2) , wherein a wafer composite with a plurality of semiconductor bodies (3) and a plurality of control structures (5) is provided on the support (6), and the method comprises a step of singulating the wafer composite into a plurality of components (2) and control structures (5).

12. Method according to the previous claim, wherein the singulation of the wafer assembly comprises cutting the carrier (6) into a plurality of chip carriers (61), wherein - each component (2) and each control structure (5) is assigned a chip carrier (61), and the method further comprises arranging the components (2) and control structures (5) on an auxiliary carrier (17), wherein the components (2) and control structures (5) are spaced apart from each other on the auxiliary carrier (17).

13. Method according to the previous claim, wherein a chip carrier (61) is uniquely assigned to each component (2) and each control structure (5).

14. Order (1) , comprising - a carrier (6) , - a semiconductor body (3) on the support (6) , - a control structure (5) on the carrier (6) , 2023PF01465 August 19, 2025 P2024, 0132 WO N 31 - a first layer (8) , and - a second layer (9) , wherein - the first layer (8) is arranged on a side of the semiconductor body (3) facing away from the support (6), - the second layer (9) is arranged on a side of the control structure (5) facing away from the support (6), - the second layer (9) partially covers the side of the control structure (5) facing away from the carrier (6), - the first layer (8) has a first surface (11) facing away from the semiconductor body (3), - the second layer (9) has a second surface (12) facing away from the control structure (5), and - the first surface (11) and the second surface (12) are at least approximately subsurfaces of an imaginary common plane, wherein - the control structure (5) is a marker with a machine-readable area and is set up for orientation in production facilities.

15. Arrangement (1) according to the preceding claim, wherein the first layer (8) and the second layer (9) are formed from the same material.

16. Arrangement (1) according to one of claims 14 to 15, wherein the semiconductor bodies (3) and the control structures (5) are spaced apart from each other in pairs.

17. Arrangement (1) according to any one of claims 14 to 16, wherein the arrangement (1) comprises a plurality of semiconductor bodies (3) and at least three control structures (5), and wherein the semiconductor bodies (3) and control structures (5) are arranged at lattice points of a regular lattice. 2023PF01465 August 19, 2025 P2024, 0132 WO N - 32 - 18. Arrangement (1) according to any one of claims 14 to 17, wherein - the support (6) has an auxiliary support (17) which is different from a growth substrate, - a first chip carrier (61) is arranged between the semiconductor body (3) and the auxiliary carrier (17), - a second chip carrier (61) between the control structure (5) and the auxiliary carrier (17), and - the first chip carrier (61) and the second chip carrier (61) are made of the same material.

19. Arrangement (1) according to any one of claims 14 to 18, wherein the first layer (8) and the second layer (9) are spaced apart from each other.

20. Arrangement (1) according to any one of claims 14 to 19, wherein an edge region (16) of the control structure (5) is free from the second layer (9).

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